1 /*
2 * QEMU ARM TCG CPUs.
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This code is licensed under the GNU GPL v2 or later.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include "qemu/osdep.h"
12 #include "cpu.h"
13 #include "internals.h"
14
15 /* CPU models. These are not needed for the AArch64 linux-user build. */
16 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
17
arm_v7m_cpu_exec_interrupt(CPUState * cs,int interrupt_request)18 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
19 {
20 CPUClass *cc = CPU_GET_CLASS(cs);
21 ARMCPU *cpu = ARM_CPU(cs);
22 CPUARMState *env = &cpu->env;
23 bool ret = false;
24
25 /*
26 * ARMv7-M interrupt masking works differently than -A or -R.
27 * There is no FIQ/IRQ distinction. Instead of I and F bits
28 * masking FIQ and IRQ interrupts, an exception is taken only
29 * if it is higher priority than the current execution priority
30 * (which depends on state like BASEPRI, FAULTMASK and the
31 * currently active exception).
32 */
33 if (interrupt_request & CPU_INTERRUPT_HARD
34 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
35 cs->exception_index = EXCP_IRQ;
36 cc->do_interrupt(cs);
37 ret = true;
38 }
39 return ret;
40 }
41
arm926_initfn(Object * obj)42 static void arm926_initfn(Object *obj)
43 {
44 ARMCPU *cpu = ARM_CPU(obj);
45
46 cpu->dtb_compatible = "arm,arm926";
47 set_feature(&cpu->env, ARM_FEATURE_V5);
48 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
49 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
50 cpu->midr = 0x41069265;
51 cpu->reset_fpsid = 0x41011090;
52 cpu->ctr = 0x1dd20d2;
53 cpu->reset_sctlr = 0x00090078;
54
55 /*
56 * ARMv5 does not have the ID_ISAR registers, but we can still
57 * set the field to indicate Jazelle support within QEMU.
58 */
59 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
60 /*
61 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
62 * support even though ARMv5 doesn't have this register.
63 */
64 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
65 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
66 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
67 }
68
arm946_initfn(Object * obj)69 static void arm946_initfn(Object *obj)
70 {
71 ARMCPU *cpu = ARM_CPU(obj);
72
73 cpu->dtb_compatible = "arm,arm946";
74 set_feature(&cpu->env, ARM_FEATURE_V5);
75 set_feature(&cpu->env, ARM_FEATURE_PMSA);
76 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
77 cpu->midr = 0x41059461;
78 cpu->ctr = 0x0f004006;
79 cpu->reset_sctlr = 0x00000078;
80 }
81
arm1026_initfn(Object * obj)82 static void arm1026_initfn(Object *obj)
83 {
84 ARMCPU *cpu = ARM_CPU(obj);
85
86 cpu->dtb_compatible = "arm,arm1026";
87 set_feature(&cpu->env, ARM_FEATURE_V5);
88 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
89 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
90 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
91 cpu->midr = 0x4106a262;
92 cpu->reset_fpsid = 0x410110a0;
93 cpu->ctr = 0x1dd20d2;
94 cpu->reset_sctlr = 0x00090078;
95 cpu->reset_auxcr = 1;
96
97 /*
98 * ARMv5 does not have the ID_ISAR registers, but we can still
99 * set the field to indicate Jazelle support within QEMU.
100 */
101 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
102 /*
103 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
104 * support even though ARMv5 doesn't have this register.
105 */
106 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
107 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
108 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
109
110 {
111 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
112 ARMCPRegInfo ifar = {
113 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
114 .access = PL1_RW,
115 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
116 .resetvalue = 0
117 };
118 define_one_arm_cp_reg(cpu, &ifar);
119 }
120 }
121
arm1136_r2_initfn(Object * obj)122 static void arm1136_r2_initfn(Object *obj)
123 {
124 ARMCPU *cpu = ARM_CPU(obj);
125 /*
126 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
127 * older core than plain "arm1136". In particular this does not
128 * have the v6K features.
129 * These ID register values are correct for 1136 but may be wrong
130 * for 1136_r2 (in particular r0p2 does not actually implement most
131 * of the ID registers).
132 */
133
134 cpu->dtb_compatible = "arm,arm1136";
135 set_feature(&cpu->env, ARM_FEATURE_V6);
136 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
137 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
138 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
139 cpu->midr = 0x4107b362;
140 cpu->reset_fpsid = 0x410120b4;
141 cpu->isar.mvfr0 = 0x11111111;
142 cpu->isar.mvfr1 = 0x00000000;
143 cpu->ctr = 0x1dd20d2;
144 cpu->reset_sctlr = 0x00050078;
145 cpu->isar.id_pfr0 = 0x111;
146 cpu->isar.id_pfr1 = 0x1;
147 cpu->isar.id_dfr0 = 0x2;
148 cpu->id_afr0 = 0x3;
149 cpu->isar.id_mmfr0 = 0x01130003;
150 cpu->isar.id_mmfr1 = 0x10030302;
151 cpu->isar.id_mmfr2 = 0x01222110;
152 cpu->isar.id_isar0 = 0x00140011;
153 cpu->isar.id_isar1 = 0x12002111;
154 cpu->isar.id_isar2 = 0x11231111;
155 cpu->isar.id_isar3 = 0x01102131;
156 cpu->isar.id_isar4 = 0x141;
157 cpu->reset_auxcr = 7;
158 }
159
arm1136_initfn(Object * obj)160 static void arm1136_initfn(Object *obj)
161 {
162 ARMCPU *cpu = ARM_CPU(obj);
163
164 cpu->dtb_compatible = "arm,arm1136";
165 set_feature(&cpu->env, ARM_FEATURE_V6K);
166 set_feature(&cpu->env, ARM_FEATURE_V6);
167 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
168 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
169 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
170 cpu->midr = 0x4117b363;
171 cpu->reset_fpsid = 0x410120b4;
172 cpu->isar.mvfr0 = 0x11111111;
173 cpu->isar.mvfr1 = 0x00000000;
174 cpu->ctr = 0x1dd20d2;
175 cpu->reset_sctlr = 0x00050078;
176 cpu->isar.id_pfr0 = 0x111;
177 cpu->isar.id_pfr1 = 0x1;
178 cpu->isar.id_dfr0 = 0x2;
179 cpu->id_afr0 = 0x3;
180 cpu->isar.id_mmfr0 = 0x01130003;
181 cpu->isar.id_mmfr1 = 0x10030302;
182 cpu->isar.id_mmfr2 = 0x01222110;
183 cpu->isar.id_isar0 = 0x00140011;
184 cpu->isar.id_isar1 = 0x12002111;
185 cpu->isar.id_isar2 = 0x11231111;
186 cpu->isar.id_isar3 = 0x01102131;
187 cpu->isar.id_isar4 = 0x141;
188 cpu->reset_auxcr = 7;
189 }
190
arm1176_initfn(Object * obj)191 static void arm1176_initfn(Object *obj)
192 {
193 ARMCPU *cpu = ARM_CPU(obj);
194
195 cpu->dtb_compatible = "arm,arm1176";
196 set_feature(&cpu->env, ARM_FEATURE_V6K);
197 set_feature(&cpu->env, ARM_FEATURE_VAPA);
198 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
199 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
200 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
201 set_feature(&cpu->env, ARM_FEATURE_EL3);
202 cpu->midr = 0x410fb767;
203 cpu->reset_fpsid = 0x410120b5;
204 cpu->isar.mvfr0 = 0x11111111;
205 cpu->isar.mvfr1 = 0x00000000;
206 cpu->ctr = 0x1dd20d2;
207 cpu->reset_sctlr = 0x00050078;
208 cpu->isar.id_pfr0 = 0x111;
209 cpu->isar.id_pfr1 = 0x11;
210 cpu->isar.id_dfr0 = 0x33;
211 cpu->id_afr0 = 0;
212 cpu->isar.id_mmfr0 = 0x01130003;
213 cpu->isar.id_mmfr1 = 0x10030302;
214 cpu->isar.id_mmfr2 = 0x01222100;
215 cpu->isar.id_isar0 = 0x0140011;
216 cpu->isar.id_isar1 = 0x12002111;
217 cpu->isar.id_isar2 = 0x11231121;
218 cpu->isar.id_isar3 = 0x01102131;
219 cpu->isar.id_isar4 = 0x01141;
220 cpu->reset_auxcr = 7;
221 }
222
arm11mpcore_initfn(Object * obj)223 static void arm11mpcore_initfn(Object *obj)
224 {
225 ARMCPU *cpu = ARM_CPU(obj);
226
227 cpu->dtb_compatible = "arm,arm11mpcore";
228 set_feature(&cpu->env, ARM_FEATURE_V6K);
229 set_feature(&cpu->env, ARM_FEATURE_VAPA);
230 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
231 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
232 cpu->midr = 0x410fb022;
233 cpu->reset_fpsid = 0x410120b4;
234 cpu->isar.mvfr0 = 0x11111111;
235 cpu->isar.mvfr1 = 0x00000000;
236 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
237 cpu->isar.id_pfr0 = 0x111;
238 cpu->isar.id_pfr1 = 0x1;
239 cpu->isar.id_dfr0 = 0;
240 cpu->id_afr0 = 0x2;
241 cpu->isar.id_mmfr0 = 0x01100103;
242 cpu->isar.id_mmfr1 = 0x10020302;
243 cpu->isar.id_mmfr2 = 0x01222000;
244 cpu->isar.id_isar0 = 0x00100011;
245 cpu->isar.id_isar1 = 0x12002111;
246 cpu->isar.id_isar2 = 0x11221011;
247 cpu->isar.id_isar3 = 0x01102131;
248 cpu->isar.id_isar4 = 0x141;
249 cpu->reset_auxcr = 1;
250 }
251
cortex_m0_initfn(Object * obj)252 static void cortex_m0_initfn(Object *obj)
253 {
254 ARMCPU *cpu = ARM_CPU(obj);
255 set_feature(&cpu->env, ARM_FEATURE_V6);
256 set_feature(&cpu->env, ARM_FEATURE_M);
257
258 cpu->midr = 0x410cc200;
259
260 /*
261 * These ID register values are not guest visible, because
262 * we do not implement the Main Extension. They must be set
263 * to values corresponding to the Cortex-M0's implemented
264 * features, because QEMU generally controls its emulation
265 * by looking at ID register fields. We use the same values as
266 * for the M3.
267 */
268 cpu->isar.id_pfr0 = 0x00000030;
269 cpu->isar.id_pfr1 = 0x00000200;
270 cpu->isar.id_dfr0 = 0x00100000;
271 cpu->id_afr0 = 0x00000000;
272 cpu->isar.id_mmfr0 = 0x00000030;
273 cpu->isar.id_mmfr1 = 0x00000000;
274 cpu->isar.id_mmfr2 = 0x00000000;
275 cpu->isar.id_mmfr3 = 0x00000000;
276 cpu->isar.id_isar0 = 0x01141110;
277 cpu->isar.id_isar1 = 0x02111000;
278 cpu->isar.id_isar2 = 0x21112231;
279 cpu->isar.id_isar3 = 0x01111110;
280 cpu->isar.id_isar4 = 0x01310102;
281 cpu->isar.id_isar5 = 0x00000000;
282 cpu->isar.id_isar6 = 0x00000000;
283 }
284
cortex_m3_initfn(Object * obj)285 static void cortex_m3_initfn(Object *obj)
286 {
287 ARMCPU *cpu = ARM_CPU(obj);
288 set_feature(&cpu->env, ARM_FEATURE_V7);
289 set_feature(&cpu->env, ARM_FEATURE_M);
290 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
291 cpu->midr = 0x410fc231;
292 cpu->pmsav7_dregion = 8;
293 cpu->isar.id_pfr0 = 0x00000030;
294 cpu->isar.id_pfr1 = 0x00000200;
295 cpu->isar.id_dfr0 = 0x00100000;
296 cpu->id_afr0 = 0x00000000;
297 cpu->isar.id_mmfr0 = 0x00000030;
298 cpu->isar.id_mmfr1 = 0x00000000;
299 cpu->isar.id_mmfr2 = 0x00000000;
300 cpu->isar.id_mmfr3 = 0x00000000;
301 cpu->isar.id_isar0 = 0x01141110;
302 cpu->isar.id_isar1 = 0x02111000;
303 cpu->isar.id_isar2 = 0x21112231;
304 cpu->isar.id_isar3 = 0x01111110;
305 cpu->isar.id_isar4 = 0x01310102;
306 cpu->isar.id_isar5 = 0x00000000;
307 cpu->isar.id_isar6 = 0x00000000;
308 }
309
cortex_m4_initfn(Object * obj)310 static void cortex_m4_initfn(Object *obj)
311 {
312 ARMCPU *cpu = ARM_CPU(obj);
313
314 set_feature(&cpu->env, ARM_FEATURE_V7);
315 set_feature(&cpu->env, ARM_FEATURE_M);
316 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
317 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
318 cpu->midr = 0x410fc240; /* r0p0 */
319 cpu->pmsav7_dregion = 8;
320 cpu->isar.mvfr0 = 0x10110021;
321 cpu->isar.mvfr1 = 0x11000011;
322 cpu->isar.mvfr2 = 0x00000000;
323 cpu->isar.id_pfr0 = 0x00000030;
324 cpu->isar.id_pfr1 = 0x00000200;
325 cpu->isar.id_dfr0 = 0x00100000;
326 cpu->id_afr0 = 0x00000000;
327 cpu->isar.id_mmfr0 = 0x00000030;
328 cpu->isar.id_mmfr1 = 0x00000000;
329 cpu->isar.id_mmfr2 = 0x00000000;
330 cpu->isar.id_mmfr3 = 0x00000000;
331 cpu->isar.id_isar0 = 0x01141110;
332 cpu->isar.id_isar1 = 0x02111000;
333 cpu->isar.id_isar2 = 0x21112231;
334 cpu->isar.id_isar3 = 0x01111110;
335 cpu->isar.id_isar4 = 0x01310102;
336 cpu->isar.id_isar5 = 0x00000000;
337 cpu->isar.id_isar6 = 0x00000000;
338 }
339
cortex_m7_initfn(Object * obj)340 static void cortex_m7_initfn(Object *obj)
341 {
342 ARMCPU *cpu = ARM_CPU(obj);
343
344 set_feature(&cpu->env, ARM_FEATURE_V7);
345 set_feature(&cpu->env, ARM_FEATURE_M);
346 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
347 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
348 cpu->midr = 0x411fc272; /* r1p2 */
349 cpu->pmsav7_dregion = 8;
350 cpu->isar.mvfr0 = 0x10110221;
351 cpu->isar.mvfr1 = 0x12000011;
352 cpu->isar.mvfr2 = 0x00000040;
353 cpu->isar.id_pfr0 = 0x00000030;
354 cpu->isar.id_pfr1 = 0x00000200;
355 cpu->isar.id_dfr0 = 0x00100000;
356 cpu->id_afr0 = 0x00000000;
357 cpu->isar.id_mmfr0 = 0x00100030;
358 cpu->isar.id_mmfr1 = 0x00000000;
359 cpu->isar.id_mmfr2 = 0x01000000;
360 cpu->isar.id_mmfr3 = 0x00000000;
361 cpu->isar.id_isar0 = 0x01101110;
362 cpu->isar.id_isar1 = 0x02112000;
363 cpu->isar.id_isar2 = 0x20232231;
364 cpu->isar.id_isar3 = 0x01111131;
365 cpu->isar.id_isar4 = 0x01310132;
366 cpu->isar.id_isar5 = 0x00000000;
367 cpu->isar.id_isar6 = 0x00000000;
368 }
369
cortex_m33_initfn(Object * obj)370 static void cortex_m33_initfn(Object *obj)
371 {
372 ARMCPU *cpu = ARM_CPU(obj);
373
374 set_feature(&cpu->env, ARM_FEATURE_V8);
375 set_feature(&cpu->env, ARM_FEATURE_M);
376 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
377 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
378 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
379 cpu->midr = 0x410fd213; /* r0p3 */
380 cpu->pmsav7_dregion = 16;
381 cpu->sau_sregion = 8;
382 cpu->isar.mvfr0 = 0x10110021;
383 cpu->isar.mvfr1 = 0x11000011;
384 cpu->isar.mvfr2 = 0x00000040;
385 cpu->isar.id_pfr0 = 0x00000030;
386 cpu->isar.id_pfr1 = 0x00000210;
387 cpu->isar.id_dfr0 = 0x00200000;
388 cpu->id_afr0 = 0x00000000;
389 cpu->isar.id_mmfr0 = 0x00101F40;
390 cpu->isar.id_mmfr1 = 0x00000000;
391 cpu->isar.id_mmfr2 = 0x01000000;
392 cpu->isar.id_mmfr3 = 0x00000000;
393 cpu->isar.id_isar0 = 0x01101110;
394 cpu->isar.id_isar1 = 0x02212000;
395 cpu->isar.id_isar2 = 0x20232232;
396 cpu->isar.id_isar3 = 0x01111131;
397 cpu->isar.id_isar4 = 0x01310132;
398 cpu->isar.id_isar5 = 0x00000000;
399 cpu->isar.id_isar6 = 0x00000000;
400 cpu->clidr = 0x00000000;
401 cpu->ctr = 0x8000c000;
402 }
403
404 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
405 /* Dummy the TCM region regs for the moment */
406 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
407 .access = PL1_RW, .type = ARM_CP_CONST },
408 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
409 .access = PL1_RW, .type = ARM_CP_CONST },
410 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
411 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
412 REGINFO_SENTINEL
413 };
414
cortex_r5_initfn(Object * obj)415 static void cortex_r5_initfn(Object *obj)
416 {
417 ARMCPU *cpu = ARM_CPU(obj);
418
419 set_feature(&cpu->env, ARM_FEATURE_V7);
420 set_feature(&cpu->env, ARM_FEATURE_V7MP);
421 set_feature(&cpu->env, ARM_FEATURE_PMSA);
422 set_feature(&cpu->env, ARM_FEATURE_PMU);
423 cpu->midr = 0x411fc153; /* r1p3 */
424 cpu->isar.id_pfr0 = 0x0131;
425 cpu->isar.id_pfr1 = 0x001;
426 cpu->isar.id_dfr0 = 0x010400;
427 cpu->id_afr0 = 0x0;
428 cpu->isar.id_mmfr0 = 0x0210030;
429 cpu->isar.id_mmfr1 = 0x00000000;
430 cpu->isar.id_mmfr2 = 0x01200000;
431 cpu->isar.id_mmfr3 = 0x0211;
432 cpu->isar.id_isar0 = 0x02101111;
433 cpu->isar.id_isar1 = 0x13112111;
434 cpu->isar.id_isar2 = 0x21232141;
435 cpu->isar.id_isar3 = 0x01112131;
436 cpu->isar.id_isar4 = 0x0010142;
437 cpu->isar.id_isar5 = 0x0;
438 cpu->isar.id_isar6 = 0x0;
439 cpu->mp_is_up = true;
440 cpu->pmsav7_dregion = 16;
441 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
442 }
443
cortex_r5f_initfn(Object * obj)444 static void cortex_r5f_initfn(Object *obj)
445 {
446 ARMCPU *cpu = ARM_CPU(obj);
447
448 cortex_r5_initfn(obj);
449 cpu->isar.mvfr0 = 0x10110221;
450 cpu->isar.mvfr1 = 0x00000011;
451 }
452
ti925t_initfn(Object * obj)453 static void ti925t_initfn(Object *obj)
454 {
455 ARMCPU *cpu = ARM_CPU(obj);
456 set_feature(&cpu->env, ARM_FEATURE_V4T);
457 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
458 cpu->midr = ARM_CPUID_TI925T;
459 cpu->ctr = 0x5109149;
460 cpu->reset_sctlr = 0x00000070;
461 }
462
sa1100_initfn(Object * obj)463 static void sa1100_initfn(Object *obj)
464 {
465 ARMCPU *cpu = ARM_CPU(obj);
466
467 cpu->dtb_compatible = "intel,sa1100";
468 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
469 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
470 cpu->midr = 0x4401A11B;
471 cpu->reset_sctlr = 0x00000070;
472 }
473
sa1110_initfn(Object * obj)474 static void sa1110_initfn(Object *obj)
475 {
476 ARMCPU *cpu = ARM_CPU(obj);
477 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
478 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
479 cpu->midr = 0x6901B119;
480 cpu->reset_sctlr = 0x00000070;
481 }
482
pxa250_initfn(Object * obj)483 static void pxa250_initfn(Object *obj)
484 {
485 ARMCPU *cpu = ARM_CPU(obj);
486
487 cpu->dtb_compatible = "marvell,xscale";
488 set_feature(&cpu->env, ARM_FEATURE_V5);
489 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
490 cpu->midr = 0x69052100;
491 cpu->ctr = 0xd172172;
492 cpu->reset_sctlr = 0x00000078;
493 }
494
pxa255_initfn(Object * obj)495 static void pxa255_initfn(Object *obj)
496 {
497 ARMCPU *cpu = ARM_CPU(obj);
498
499 cpu->dtb_compatible = "marvell,xscale";
500 set_feature(&cpu->env, ARM_FEATURE_V5);
501 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
502 cpu->midr = 0x69052d00;
503 cpu->ctr = 0xd172172;
504 cpu->reset_sctlr = 0x00000078;
505 }
506
pxa260_initfn(Object * obj)507 static void pxa260_initfn(Object *obj)
508 {
509 ARMCPU *cpu = ARM_CPU(obj);
510
511 cpu->dtb_compatible = "marvell,xscale";
512 set_feature(&cpu->env, ARM_FEATURE_V5);
513 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
514 cpu->midr = 0x69052903;
515 cpu->ctr = 0xd172172;
516 cpu->reset_sctlr = 0x00000078;
517 }
518
pxa261_initfn(Object * obj)519 static void pxa261_initfn(Object *obj)
520 {
521 ARMCPU *cpu = ARM_CPU(obj);
522
523 cpu->dtb_compatible = "marvell,xscale";
524 set_feature(&cpu->env, ARM_FEATURE_V5);
525 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
526 cpu->midr = 0x69052d05;
527 cpu->ctr = 0xd172172;
528 cpu->reset_sctlr = 0x00000078;
529 }
530
pxa262_initfn(Object * obj)531 static void pxa262_initfn(Object *obj)
532 {
533 ARMCPU *cpu = ARM_CPU(obj);
534
535 cpu->dtb_compatible = "marvell,xscale";
536 set_feature(&cpu->env, ARM_FEATURE_V5);
537 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
538 cpu->midr = 0x69052d06;
539 cpu->ctr = 0xd172172;
540 cpu->reset_sctlr = 0x00000078;
541 }
542
pxa270a0_initfn(Object * obj)543 static void pxa270a0_initfn(Object *obj)
544 {
545 ARMCPU *cpu = ARM_CPU(obj);
546
547 cpu->dtb_compatible = "marvell,xscale";
548 set_feature(&cpu->env, ARM_FEATURE_V5);
549 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
550 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
551 cpu->midr = 0x69054110;
552 cpu->ctr = 0xd172172;
553 cpu->reset_sctlr = 0x00000078;
554 }
555
pxa270a1_initfn(Object * obj)556 static void pxa270a1_initfn(Object *obj)
557 {
558 ARMCPU *cpu = ARM_CPU(obj);
559
560 cpu->dtb_compatible = "marvell,xscale";
561 set_feature(&cpu->env, ARM_FEATURE_V5);
562 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
563 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
564 cpu->midr = 0x69054111;
565 cpu->ctr = 0xd172172;
566 cpu->reset_sctlr = 0x00000078;
567 }
568
pxa270b0_initfn(Object * obj)569 static void pxa270b0_initfn(Object *obj)
570 {
571 ARMCPU *cpu = ARM_CPU(obj);
572
573 cpu->dtb_compatible = "marvell,xscale";
574 set_feature(&cpu->env, ARM_FEATURE_V5);
575 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
576 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
577 cpu->midr = 0x69054112;
578 cpu->ctr = 0xd172172;
579 cpu->reset_sctlr = 0x00000078;
580 }
581
pxa270b1_initfn(Object * obj)582 static void pxa270b1_initfn(Object *obj)
583 {
584 ARMCPU *cpu = ARM_CPU(obj);
585
586 cpu->dtb_compatible = "marvell,xscale";
587 set_feature(&cpu->env, ARM_FEATURE_V5);
588 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
589 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
590 cpu->midr = 0x69054113;
591 cpu->ctr = 0xd172172;
592 cpu->reset_sctlr = 0x00000078;
593 }
594
pxa270c0_initfn(Object * obj)595 static void pxa270c0_initfn(Object *obj)
596 {
597 ARMCPU *cpu = ARM_CPU(obj);
598
599 cpu->dtb_compatible = "marvell,xscale";
600 set_feature(&cpu->env, ARM_FEATURE_V5);
601 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
602 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
603 cpu->midr = 0x69054114;
604 cpu->ctr = 0xd172172;
605 cpu->reset_sctlr = 0x00000078;
606 }
607
pxa270c5_initfn(Object * obj)608 static void pxa270c5_initfn(Object *obj)
609 {
610 ARMCPU *cpu = ARM_CPU(obj);
611
612 cpu->dtb_compatible = "marvell,xscale";
613 set_feature(&cpu->env, ARM_FEATURE_V5);
614 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
615 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
616 cpu->midr = 0x69054117;
617 cpu->ctr = 0xd172172;
618 cpu->reset_sctlr = 0x00000078;
619 }
620
arm_v7m_class_init(ObjectClass * oc,void * data)621 static void arm_v7m_class_init(ObjectClass *oc, void *data)
622 {
623 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
624 CPUClass *cc = CPU_CLASS(oc);
625
626 acc->info = data;
627 #ifndef CONFIG_USER_ONLY
628 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
629 #endif
630
631 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
632 cc->gdb_core_xml_file = "arm-m-profile.xml";
633 }
634
635 static const ARMCPUInfo arm_tcg_cpus[] = {
636 { .name = "arm926", .initfn = arm926_initfn },
637 { .name = "arm946", .initfn = arm946_initfn },
638 { .name = "arm1026", .initfn = arm1026_initfn },
639 /*
640 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
641 * older core than plain "arm1136". In particular this does not
642 * have the v6K features.
643 */
644 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
645 { .name = "arm1136", .initfn = arm1136_initfn },
646 { .name = "arm1176", .initfn = arm1176_initfn },
647 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
648 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
649 .class_init = arm_v7m_class_init },
650 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
651 .class_init = arm_v7m_class_init },
652 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
653 .class_init = arm_v7m_class_init },
654 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
655 .class_init = arm_v7m_class_init },
656 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
657 .class_init = arm_v7m_class_init },
658 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
659 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
660 { .name = "ti925t", .initfn = ti925t_initfn },
661 { .name = "sa1100", .initfn = sa1100_initfn },
662 { .name = "sa1110", .initfn = sa1110_initfn },
663 { .name = "pxa250", .initfn = pxa250_initfn },
664 { .name = "pxa255", .initfn = pxa255_initfn },
665 { .name = "pxa260", .initfn = pxa260_initfn },
666 { .name = "pxa261", .initfn = pxa261_initfn },
667 { .name = "pxa262", .initfn = pxa262_initfn },
668 /* "pxa270" is an alias for "pxa270-a0" */
669 { .name = "pxa270", .initfn = pxa270a0_initfn },
670 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
671 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
672 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
673 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
674 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
675 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
676 };
677
arm_tcg_cpu_register_types(void)678 static void arm_tcg_cpu_register_types(void)
679 {
680 size_t i;
681
682 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
683 arm_cpu_register(&arm_tcg_cpus[i]);
684 }
685 }
686
687 type_init(arm_tcg_cpu_register_types)
688
689 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
690