1 /*
2 * TILE-Gx virtual CPU header
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef TILEGX_CPU_H
21 #define TILEGX_CPU_H
22
23 #include "exec/cpu-defs.h"
24 #include "qom/object.h"
25
26 /* TILE-Gx common register alias */
27 #define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
28 #define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */
29 #define TILEGX_R_NR 10 /* 10 register, for syscall number */
30 #define TILEGX_R_BP 52 /* 52 register, optional frame pointer */
31 #define TILEGX_R_TP 53 /* TP register, thread local storage data */
32 #define TILEGX_R_SP 54 /* SP register, stack pointer */
33 #define TILEGX_R_LR 55 /* LR register, may save pc, but it is not pc */
34 #define TILEGX_R_COUNT 56 /* Only 56 registers are really useful */
35 #define TILEGX_R_SN 56 /* SN register, obsoleted, it likes zero register */
36 #define TILEGX_R_IDN0 57 /* IDN0 register, cause IDN_ACCESS exception */
37 #define TILEGX_R_IDN1 58 /* IDN1 register, cause IDN_ACCESS exception */
38 #define TILEGX_R_UDN0 59 /* UDN0 register, cause UDN_ACCESS exception */
39 #define TILEGX_R_UDN1 60 /* UDN1 register, cause UDN_ACCESS exception */
40 #define TILEGX_R_UDN2 61 /* UDN2 register, cause UDN_ACCESS exception */
41 #define TILEGX_R_UDN3 62 /* UDN3 register, cause UDN_ACCESS exception */
42 #define TILEGX_R_ZERO 63 /* Zero register, always zero */
43 #define TILEGX_R_NOREG 255 /* Invalid register value */
44
45 /* TILE-Gx special registers used by outside */
46 enum {
47 TILEGX_SPR_CMPEXCH = 0,
48 TILEGX_SPR_CRITICAL_SEC = 1,
49 TILEGX_SPR_SIM_CONTROL = 2,
50 TILEGX_SPR_EX_CONTEXT_0_0 = 3,
51 TILEGX_SPR_EX_CONTEXT_0_1 = 4,
52 TILEGX_SPR_COUNT
53 };
54
55 /* Exception numbers */
56 typedef enum {
57 TILEGX_EXCP_NONE = 0,
58 TILEGX_EXCP_SYSCALL = 1,
59 TILEGX_EXCP_SIGNAL = 2,
60 TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
61 TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
62 TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
63 TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
64 TILEGX_EXCP_OPCODE_EXCH = 0x105,
65 TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
66 TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
67 TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
68 TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
69 TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
70 TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
71 TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
72 TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
73 TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
74 TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
75 TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
76 TILEGX_EXCP_UNALIGNMENT = 0x201,
77 TILEGX_EXCP_DBUG_BREAK = 0x301
78 } TileExcp;
79
80 typedef struct CPUTLGState {
81 uint64_t regs[TILEGX_R_COUNT]; /* Common used registers by outside */
82 uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
83 uint64_t pc; /* Current pc */
84
85 #if defined(CONFIG_USER_ONLY)
86 uint64_t excaddr; /* exception address */
87 uint64_t atomic_srca; /* Arguments to atomic "exceptions" */
88 uint64_t atomic_srcb;
89 uint32_t atomic_dstr;
90 uint32_t signo; /* Signal number */
91 uint32_t sigcode; /* Signal code */
92 #endif
93
94 /* Fields up to this point are cleared by a CPU reset */
95 struct {} end_reset_fields;
96 } CPUTLGState;
97
98 #include "hw/core/cpu.h"
99
100 #define TYPE_TILEGX_CPU "tilegx-cpu"
101
102 OBJECT_DECLARE_TYPE(TileGXCPU, TileGXCPUClass,
103 TILEGX_CPU)
104
105 /**
106 * TileGXCPUClass:
107 * @parent_realize: The parent class' realize handler.
108 * @parent_reset: The parent class' reset handler.
109 *
110 * A Tile-Gx CPU model.
111 */
112 struct TileGXCPUClass {
113 /*< private >*/
114 CPUClass parent_class;
115 /*< public >*/
116
117 DeviceRealize parent_realize;
118 DeviceReset parent_reset;
119 };
120
121 /**
122 * TileGXCPU:
123 * @env: #CPUTLGState
124 *
125 * A Tile-GX CPU.
126 */
127 struct TileGXCPU {
128 /*< private >*/
129 CPUState parent_obj;
130 /*< public >*/
131
132 CPUNegativeOffsetState neg;
133 CPUTLGState env;
134 };
135
136
137 /* TILE-Gx memory attributes */
138 #define MMU_USER_IDX 0 /* Current memory operation is in user mode */
139
140 typedef CPUTLGState CPUArchState;
141 typedef TileGXCPU ArchCPU;
142
143 #include "exec/cpu-all.h"
144
145 void tilegx_tcg_init(void);
146 int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
147
148 #define CPU_RESOLVING_TYPE TYPE_TILEGX_CPU
149
150 #define cpu_signal_handler cpu_tilegx_signal_handler
151
cpu_get_tb_cpu_state(CPUTLGState * env,target_ulong * pc,target_ulong * cs_base,uint32_t * flags)152 static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
153 target_ulong *cs_base, uint32_t *flags)
154 {
155 *pc = env->pc;
156 *cs_base = 0;
157 *flags = 0;
158 }
159
160 #endif
161