1 #ifndef CAPSTONE_ARM_H 2 #define CAPSTONE_ARM_H 3 4 /* Capstone Disassembly Engine */ 5 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ 6 7 #ifdef __cplusplus 8 extern "C" { 9 #endif 10 11 #include "platform.h" 12 13 #ifdef _MSC_VER 14 #pragma warning(disable:4201) 15 #endif 16 17 /// ARM shift type 18 typedef enum arm_shifter { 19 ARM_SFT_INVALID = 0, 20 ARM_SFT_ASR, ///< shift with immediate const 21 ARM_SFT_LSL, ///< shift with immediate const 22 ARM_SFT_LSR, ///< shift with immediate const 23 ARM_SFT_ROR, ///< shift with immediate const 24 ARM_SFT_RRX, ///< shift with immediate const 25 ARM_SFT_ASR_REG, ///< shift with register 26 ARM_SFT_LSL_REG, ///< shift with register 27 ARM_SFT_LSR_REG, ///< shift with register 28 ARM_SFT_ROR_REG, ///< shift with register 29 ARM_SFT_RRX_REG, ///< shift with register 30 } arm_shifter; 31 32 /// ARM condition code 33 typedef enum arm_cc { 34 ARM_CC_INVALID = 0, 35 ARM_CC_EQ, ///< Equal Equal 36 ARM_CC_NE, ///< Not equal Not equal, or unordered 37 ARM_CC_HS, ///< Carry set >, ==, or unordered 38 ARM_CC_LO, ///< Carry clear Less than 39 ARM_CC_MI, ///< Minus, negative Less than 40 ARM_CC_PL, ///< Plus, positive or zero >, ==, or unordered 41 ARM_CC_VS, ///< Overflow Unordered 42 ARM_CC_VC, ///< No overflow Not unordered 43 ARM_CC_HI, ///< Unsigned higher Greater than, or unordered 44 ARM_CC_LS, ///< Unsigned lower or same Less than or equal 45 ARM_CC_GE, ///< Greater than or equal Greater than or equal 46 ARM_CC_LT, ///< Less than Less than, or unordered 47 ARM_CC_GT, ///< Greater than Greater than 48 ARM_CC_LE, ///< Less than or equal <, ==, or unordered 49 ARM_CC_AL ///< Always (unconditional) Always (unconditional) 50 } arm_cc; 51 52 typedef enum arm_sysreg { 53 /// Special registers for MSR 54 ARM_SYSREG_INVALID = 0, 55 56 // SPSR* registers can be OR combined 57 ARM_SYSREG_SPSR_C = 1, 58 ARM_SYSREG_SPSR_X = 2, 59 ARM_SYSREG_SPSR_S = 4, 60 ARM_SYSREG_SPSR_F = 8, 61 62 // CPSR* registers can be OR combined 63 ARM_SYSREG_CPSR_C = 16, 64 ARM_SYSREG_CPSR_X = 32, 65 ARM_SYSREG_CPSR_S = 64, 66 ARM_SYSREG_CPSR_F = 128, 67 68 // independent registers 69 ARM_SYSREG_APSR = 256, 70 ARM_SYSREG_APSR_G, 71 ARM_SYSREG_APSR_NZCVQ, 72 ARM_SYSREG_APSR_NZCVQG, 73 74 ARM_SYSREG_IAPSR, 75 ARM_SYSREG_IAPSR_G, 76 ARM_SYSREG_IAPSR_NZCVQG, 77 ARM_SYSREG_IAPSR_NZCVQ, 78 79 ARM_SYSREG_EAPSR, 80 ARM_SYSREG_EAPSR_G, 81 ARM_SYSREG_EAPSR_NZCVQG, 82 ARM_SYSREG_EAPSR_NZCVQ, 83 84 ARM_SYSREG_XPSR, 85 ARM_SYSREG_XPSR_G, 86 ARM_SYSREG_XPSR_NZCVQG, 87 ARM_SYSREG_XPSR_NZCVQ, 88 89 ARM_SYSREG_IPSR, 90 ARM_SYSREG_EPSR, 91 ARM_SYSREG_IEPSR, 92 93 ARM_SYSREG_MSP, 94 ARM_SYSREG_PSP, 95 ARM_SYSREG_PRIMASK, 96 ARM_SYSREG_BASEPRI, 97 ARM_SYSREG_BASEPRI_MAX, 98 ARM_SYSREG_FAULTMASK, 99 ARM_SYSREG_CONTROL, 100 ARM_SYSREG_MSPLIM, 101 ARM_SYSREG_PSPLIM, 102 ARM_SYSREG_MSP_NS, 103 ARM_SYSREG_PSP_NS, 104 ARM_SYSREG_MSPLIM_NS, 105 ARM_SYSREG_PSPLIM_NS, 106 ARM_SYSREG_PRIMASK_NS, 107 ARM_SYSREG_BASEPRI_NS, 108 ARM_SYSREG_FAULTMASK_NS, 109 ARM_SYSREG_CONTROL_NS, 110 ARM_SYSREG_SP_NS, 111 112 // Banked Registers 113 ARM_SYSREG_R8_USR, 114 ARM_SYSREG_R9_USR, 115 ARM_SYSREG_R10_USR, 116 ARM_SYSREG_R11_USR, 117 ARM_SYSREG_R12_USR, 118 ARM_SYSREG_SP_USR, 119 ARM_SYSREG_LR_USR, 120 ARM_SYSREG_R8_FIQ, 121 ARM_SYSREG_R9_FIQ, 122 ARM_SYSREG_R10_FIQ, 123 ARM_SYSREG_R11_FIQ, 124 ARM_SYSREG_R12_FIQ, 125 ARM_SYSREG_SP_FIQ, 126 ARM_SYSREG_LR_FIQ, 127 ARM_SYSREG_LR_IRQ, 128 ARM_SYSREG_SP_IRQ, 129 ARM_SYSREG_LR_SVC, 130 ARM_SYSREG_SP_SVC, 131 ARM_SYSREG_LR_ABT, 132 ARM_SYSREG_SP_ABT, 133 ARM_SYSREG_LR_UND, 134 ARM_SYSREG_SP_UND, 135 ARM_SYSREG_LR_MON, 136 ARM_SYSREG_SP_MON, 137 ARM_SYSREG_ELR_HYP, 138 ARM_SYSREG_SP_HYP, 139 140 ARM_SYSREG_SPSR_FIQ, 141 ARM_SYSREG_SPSR_IRQ, 142 ARM_SYSREG_SPSR_SVC, 143 ARM_SYSREG_SPSR_ABT, 144 ARM_SYSREG_SPSR_UND, 145 ARM_SYSREG_SPSR_MON, 146 ARM_SYSREG_SPSR_HYP, 147 } arm_sysreg; 148 149 /// The memory barrier constants map directly to the 4-bit encoding of 150 /// the option field for Memory Barrier operations. 151 typedef enum arm_mem_barrier { 152 ARM_MB_INVALID = 0, 153 ARM_MB_RESERVED_0, 154 ARM_MB_OSHLD, 155 ARM_MB_OSHST, 156 ARM_MB_OSH, 157 ARM_MB_RESERVED_4, 158 ARM_MB_NSHLD, 159 ARM_MB_NSHST, 160 ARM_MB_NSH, 161 ARM_MB_RESERVED_8, 162 ARM_MB_ISHLD, 163 ARM_MB_ISHST, 164 ARM_MB_ISH, 165 ARM_MB_RESERVED_12, 166 ARM_MB_LD, 167 ARM_MB_ST, 168 ARM_MB_SY, 169 } arm_mem_barrier; 170 171 /// Operand type for instruction's operands 172 typedef enum arm_op_type { 173 ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized). 174 ARM_OP_REG, ///< = CS_OP_REG (Register operand). 175 ARM_OP_IMM, ///< = CS_OP_IMM (Immediate operand). 176 ARM_OP_MEM, ///< = CS_OP_MEM (Memory operand). 177 ARM_OP_FP, ///< = CS_OP_FP (Floating-Point operand). 178 ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers) 179 ARM_OP_PIMM, ///< P-Immediate (coprocessor registers) 180 ARM_OP_SETEND, ///< operand for SETEND instruction 181 ARM_OP_SYSREG, ///< MSR/MRS special register operand 182 } arm_op_type; 183 184 /// Operand type for SETEND instruction 185 typedef enum arm_setend_type { 186 ARM_SETEND_INVALID = 0, ///< Uninitialized. 187 ARM_SETEND_BE, ///< BE operand. 188 ARM_SETEND_LE, ///< LE operand 189 } arm_setend_type; 190 191 typedef enum arm_cpsmode_type { 192 ARM_CPSMODE_INVALID = 0, 193 ARM_CPSMODE_IE = 2, 194 ARM_CPSMODE_ID = 3 195 } arm_cpsmode_type; 196 197 /// Operand type for SETEND instruction 198 typedef enum arm_cpsflag_type { 199 ARM_CPSFLAG_INVALID = 0, 200 ARM_CPSFLAG_F = 1, 201 ARM_CPSFLAG_I = 2, 202 ARM_CPSFLAG_A = 4, 203 ARM_CPSFLAG_NONE = 16, ///< no flag 204 } arm_cpsflag_type; 205 206 /// Data type for elements of vector instructions. 207 typedef enum arm_vectordata_type { 208 ARM_VECTORDATA_INVALID = 0, 209 210 // Integer type 211 ARM_VECTORDATA_I8, 212 ARM_VECTORDATA_I16, 213 ARM_VECTORDATA_I32, 214 ARM_VECTORDATA_I64, 215 216 // Signed integer type 217 ARM_VECTORDATA_S8, 218 ARM_VECTORDATA_S16, 219 ARM_VECTORDATA_S32, 220 ARM_VECTORDATA_S64, 221 222 // Unsigned integer type 223 ARM_VECTORDATA_U8, 224 ARM_VECTORDATA_U16, 225 ARM_VECTORDATA_U32, 226 ARM_VECTORDATA_U64, 227 228 // Data type for VMUL/VMULL 229 ARM_VECTORDATA_P8, 230 231 // Floating type 232 ARM_VECTORDATA_F16, 233 ARM_VECTORDATA_F32, 234 ARM_VECTORDATA_F64, 235 236 // Convert float <-> float 237 ARM_VECTORDATA_F16F64, // f16.f64 238 ARM_VECTORDATA_F64F16, // f64.f16 239 ARM_VECTORDATA_F32F16, // f32.f16 240 ARM_VECTORDATA_F16F32, // f32.f16 241 ARM_VECTORDATA_F64F32, // f64.f32 242 ARM_VECTORDATA_F32F64, // f32.f64 243 244 // Convert integer <-> float 245 ARM_VECTORDATA_S32F32, // s32.f32 246 ARM_VECTORDATA_U32F32, // u32.f32 247 ARM_VECTORDATA_F32S32, // f32.s32 248 ARM_VECTORDATA_F32U32, // f32.u32 249 ARM_VECTORDATA_F64S16, // f64.s16 250 ARM_VECTORDATA_F32S16, // f32.s16 251 ARM_VECTORDATA_F64S32, // f64.s32 252 ARM_VECTORDATA_S16F64, // s16.f64 253 ARM_VECTORDATA_S16F32, // s16.f64 254 ARM_VECTORDATA_S32F64, // s32.f64 255 ARM_VECTORDATA_U16F64, // u16.f64 256 ARM_VECTORDATA_U16F32, // u16.f32 257 ARM_VECTORDATA_U32F64, // u32.f64 258 ARM_VECTORDATA_F64U16, // f64.u16 259 ARM_VECTORDATA_F32U16, // f32.u16 260 ARM_VECTORDATA_F64U32, // f64.u32 261 ARM_VECTORDATA_F16U16, // f16.u16 262 ARM_VECTORDATA_U16F16, // u16.f16 263 ARM_VECTORDATA_F16U32, // f16.u32 264 ARM_VECTORDATA_U32F16, // u32.f16 265 } arm_vectordata_type; 266 267 /// ARM registers 268 typedef enum arm_reg { 269 ARM_REG_INVALID = 0, 270 ARM_REG_APSR, 271 ARM_REG_APSR_NZCV, 272 ARM_REG_CPSR, 273 ARM_REG_FPEXC, 274 ARM_REG_FPINST, 275 ARM_REG_FPSCR, 276 ARM_REG_FPSCR_NZCV, 277 ARM_REG_FPSID, 278 ARM_REG_ITSTATE, 279 ARM_REG_LR, 280 ARM_REG_PC, 281 ARM_REG_SP, 282 ARM_REG_SPSR, 283 ARM_REG_D0, 284 ARM_REG_D1, 285 ARM_REG_D2, 286 ARM_REG_D3, 287 ARM_REG_D4, 288 ARM_REG_D5, 289 ARM_REG_D6, 290 ARM_REG_D7, 291 ARM_REG_D8, 292 ARM_REG_D9, 293 ARM_REG_D10, 294 ARM_REG_D11, 295 ARM_REG_D12, 296 ARM_REG_D13, 297 ARM_REG_D14, 298 ARM_REG_D15, 299 ARM_REG_D16, 300 ARM_REG_D17, 301 ARM_REG_D18, 302 ARM_REG_D19, 303 ARM_REG_D20, 304 ARM_REG_D21, 305 ARM_REG_D22, 306 ARM_REG_D23, 307 ARM_REG_D24, 308 ARM_REG_D25, 309 ARM_REG_D26, 310 ARM_REG_D27, 311 ARM_REG_D28, 312 ARM_REG_D29, 313 ARM_REG_D30, 314 ARM_REG_D31, 315 ARM_REG_FPINST2, 316 ARM_REG_MVFR0, 317 ARM_REG_MVFR1, 318 ARM_REG_MVFR2, 319 ARM_REG_Q0, 320 ARM_REG_Q1, 321 ARM_REG_Q2, 322 ARM_REG_Q3, 323 ARM_REG_Q4, 324 ARM_REG_Q5, 325 ARM_REG_Q6, 326 ARM_REG_Q7, 327 ARM_REG_Q8, 328 ARM_REG_Q9, 329 ARM_REG_Q10, 330 ARM_REG_Q11, 331 ARM_REG_Q12, 332 ARM_REG_Q13, 333 ARM_REG_Q14, 334 ARM_REG_Q15, 335 ARM_REG_R0, 336 ARM_REG_R1, 337 ARM_REG_R2, 338 ARM_REG_R3, 339 ARM_REG_R4, 340 ARM_REG_R5, 341 ARM_REG_R6, 342 ARM_REG_R7, 343 ARM_REG_R8, 344 ARM_REG_R9, 345 ARM_REG_R10, 346 ARM_REG_R11, 347 ARM_REG_R12, 348 ARM_REG_S0, 349 ARM_REG_S1, 350 ARM_REG_S2, 351 ARM_REG_S3, 352 ARM_REG_S4, 353 ARM_REG_S5, 354 ARM_REG_S6, 355 ARM_REG_S7, 356 ARM_REG_S8, 357 ARM_REG_S9, 358 ARM_REG_S10, 359 ARM_REG_S11, 360 ARM_REG_S12, 361 ARM_REG_S13, 362 ARM_REG_S14, 363 ARM_REG_S15, 364 ARM_REG_S16, 365 ARM_REG_S17, 366 ARM_REG_S18, 367 ARM_REG_S19, 368 ARM_REG_S20, 369 ARM_REG_S21, 370 ARM_REG_S22, 371 ARM_REG_S23, 372 ARM_REG_S24, 373 ARM_REG_S25, 374 ARM_REG_S26, 375 ARM_REG_S27, 376 ARM_REG_S28, 377 ARM_REG_S29, 378 ARM_REG_S30, 379 ARM_REG_S31, 380 381 ARM_REG_ENDING, // <-- mark the end of the list or registers 382 383 // alias registers 384 ARM_REG_R13 = ARM_REG_SP, 385 ARM_REG_R14 = ARM_REG_LR, 386 ARM_REG_R15 = ARM_REG_PC, 387 388 ARM_REG_SB = ARM_REG_R9, 389 ARM_REG_SL = ARM_REG_R10, 390 ARM_REG_FP = ARM_REG_R11, 391 ARM_REG_IP = ARM_REG_R12, 392 } arm_reg; 393 394 /// Instruction's operand referring to memory 395 /// This is associated with ARM_OP_MEM operand type above 396 typedef struct arm_op_mem { 397 arm_reg base; ///< base register 398 arm_reg index; ///< index register 399 int scale; ///< scale for index register (can be 1, or -1) 400 int disp; ///< displacement/offset value 401 /// left-shift on index register, or 0 if irrelevant 402 /// NOTE: this value can also be fetched via operand.shift.value 403 int lshift; 404 } arm_op_mem; 405 406 /// Instruction operand 407 typedef struct cs_arm_op { 408 int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) 409 410 struct { 411 arm_shifter type; 412 unsigned int value; 413 } shift; 414 415 arm_op_type type; ///< operand type 416 417 union { 418 int reg; ///< register value for REG/SYSREG operand 419 int32_t imm; ///< immediate value for C-IMM, P-IMM or IMM operand 420 double fp; ///< floating point value for FP operand 421 arm_op_mem mem; ///< base/index/scale/disp value for MEM operand 422 arm_setend_type setend; ///< SETEND instruction's operand type 423 }; 424 425 /// in some instructions, an operand can be subtracted or added to 426 /// the base register, 427 /// if TRUE, this operand is subtracted. otherwise, it is added. 428 bool subtracted; 429 430 /// How is this operand accessed? (READ, WRITE or READ|WRITE) 431 /// This field is combined of cs_ac_type. 432 /// NOTE: this field is irrelevant if engine is compiled in DIET mode. 433 uint8_t access; 434 435 /// Neon lane index for NEON instructions (or -1 if irrelevant) 436 int8_t neon_lane; 437 } cs_arm_op; 438 439 /// Instruction structure 440 typedef struct cs_arm { 441 bool usermode; ///< User-mode registers to be loaded (for LDM/STM instructions) 442 int vector_size; ///< Scalar size for vector instructions 443 arm_vectordata_type vector_data; ///< Data type for elements of vector instructions 444 arm_cpsmode_type cps_mode; ///< CPS mode for CPS instruction 445 arm_cpsflag_type cps_flag; ///< CPS mode for CPS instruction 446 arm_cc cc; ///< conditional code for this insn 447 bool update_flags; ///< does this insn update flags? 448 bool writeback; ///< does this insn write-back? 449 arm_mem_barrier mem_barrier; ///< Option for some memory barrier instructions 450 451 /// Number of operands of this instruction, 452 /// or 0 when instruction has no operand. 453 uint8_t op_count; 454 455 cs_arm_op operands[36]; ///< operands for this instruction. 456 } cs_arm; 457 458 /// ARM instruction 459 typedef enum arm_insn { 460 ARM_INS_INVALID = 0, 461 462 ARM_INS_ADC, 463 ARM_INS_ADD, 464 ARM_INS_ADDW, 465 ARM_INS_ADR, 466 ARM_INS_AESD, 467 ARM_INS_AESE, 468 ARM_INS_AESIMC, 469 ARM_INS_AESMC, 470 ARM_INS_AND, 471 ARM_INS_ASR, 472 ARM_INS_B, 473 ARM_INS_BFC, 474 ARM_INS_BFI, 475 ARM_INS_BIC, 476 ARM_INS_BKPT, 477 ARM_INS_BL, 478 ARM_INS_BLX, 479 ARM_INS_BLXNS, 480 ARM_INS_BX, 481 ARM_INS_BXJ, 482 ARM_INS_BXNS, 483 ARM_INS_CBNZ, 484 ARM_INS_CBZ, 485 ARM_INS_CDP, 486 ARM_INS_CDP2, 487 ARM_INS_CLREX, 488 ARM_INS_CLZ, 489 ARM_INS_CMN, 490 ARM_INS_CMP, 491 ARM_INS_CPS, 492 ARM_INS_CRC32B, 493 ARM_INS_CRC32CB, 494 ARM_INS_CRC32CH, 495 ARM_INS_CRC32CW, 496 ARM_INS_CRC32H, 497 ARM_INS_CRC32W, 498 ARM_INS_CSDB, 499 ARM_INS_DBG, 500 ARM_INS_DCPS1, 501 ARM_INS_DCPS2, 502 ARM_INS_DCPS3, 503 ARM_INS_DFB, 504 ARM_INS_DMB, 505 ARM_INS_DSB, 506 ARM_INS_EOR, 507 ARM_INS_ERET, 508 ARM_INS_ESB, 509 ARM_INS_FADDD, 510 ARM_INS_FADDS, 511 ARM_INS_FCMPZD, 512 ARM_INS_FCMPZS, 513 ARM_INS_FCONSTD, 514 ARM_INS_FCONSTS, 515 ARM_INS_FLDMDBX, 516 ARM_INS_FLDMIAX, 517 ARM_INS_FMDHR, 518 ARM_INS_FMDLR, 519 ARM_INS_FMSTAT, 520 ARM_INS_FSTMDBX, 521 ARM_INS_FSTMIAX, 522 ARM_INS_FSUBD, 523 ARM_INS_FSUBS, 524 ARM_INS_HINT, 525 ARM_INS_HLT, 526 ARM_INS_HVC, 527 ARM_INS_ISB, 528 ARM_INS_IT, 529 ARM_INS_LDA, 530 ARM_INS_LDAB, 531 ARM_INS_LDAEX, 532 ARM_INS_LDAEXB, 533 ARM_INS_LDAEXD, 534 ARM_INS_LDAEXH, 535 ARM_INS_LDAH, 536 ARM_INS_LDC, 537 ARM_INS_LDC2, 538 ARM_INS_LDC2L, 539 ARM_INS_LDCL, 540 ARM_INS_LDM, 541 ARM_INS_LDMDA, 542 ARM_INS_LDMDB, 543 ARM_INS_LDMIB, 544 ARM_INS_LDR, 545 ARM_INS_LDRB, 546 ARM_INS_LDRBT, 547 ARM_INS_LDRD, 548 ARM_INS_LDREX, 549 ARM_INS_LDREXB, 550 ARM_INS_LDREXD, 551 ARM_INS_LDREXH, 552 ARM_INS_LDRH, 553 ARM_INS_LDRHT, 554 ARM_INS_LDRSB, 555 ARM_INS_LDRSBT, 556 ARM_INS_LDRSH, 557 ARM_INS_LDRSHT, 558 ARM_INS_LDRT, 559 ARM_INS_LSL, 560 ARM_INS_LSR, 561 ARM_INS_MCR, 562 ARM_INS_MCR2, 563 ARM_INS_MCRR, 564 ARM_INS_MCRR2, 565 ARM_INS_MLA, 566 ARM_INS_MLS, 567 ARM_INS_MOV, 568 ARM_INS_MOVS, 569 ARM_INS_MOVT, 570 ARM_INS_MOVW, 571 ARM_INS_MRC, 572 ARM_INS_MRC2, 573 ARM_INS_MRRC, 574 ARM_INS_MRRC2, 575 ARM_INS_MRS, 576 ARM_INS_MSR, 577 ARM_INS_MUL, 578 ARM_INS_MVN, 579 ARM_INS_NEG, 580 ARM_INS_NOP, 581 ARM_INS_ORN, 582 ARM_INS_ORR, 583 ARM_INS_PKHBT, 584 ARM_INS_PKHTB, 585 ARM_INS_PLD, 586 ARM_INS_PLDW, 587 ARM_INS_PLI, 588 ARM_INS_POP, 589 ARM_INS_PUSH, 590 ARM_INS_QADD, 591 ARM_INS_QADD16, 592 ARM_INS_QADD8, 593 ARM_INS_QASX, 594 ARM_INS_QDADD, 595 ARM_INS_QDSUB, 596 ARM_INS_QSAX, 597 ARM_INS_QSUB, 598 ARM_INS_QSUB16, 599 ARM_INS_QSUB8, 600 ARM_INS_RBIT, 601 ARM_INS_REV, 602 ARM_INS_REV16, 603 ARM_INS_REVSH, 604 ARM_INS_RFEDA, 605 ARM_INS_RFEDB, 606 ARM_INS_RFEIA, 607 ARM_INS_RFEIB, 608 ARM_INS_ROR, 609 ARM_INS_RRX, 610 ARM_INS_RSB, 611 ARM_INS_RSC, 612 ARM_INS_SADD16, 613 ARM_INS_SADD8, 614 ARM_INS_SASX, 615 ARM_INS_SBC, 616 ARM_INS_SBFX, 617 ARM_INS_SDIV, 618 ARM_INS_SEL, 619 ARM_INS_SETEND, 620 ARM_INS_SETPAN, 621 ARM_INS_SEV, 622 ARM_INS_SEVL, 623 ARM_INS_SG, 624 ARM_INS_SHA1C, 625 ARM_INS_SHA1H, 626 ARM_INS_SHA1M, 627 ARM_INS_SHA1P, 628 ARM_INS_SHA1SU0, 629 ARM_INS_SHA1SU1, 630 ARM_INS_SHA256H, 631 ARM_INS_SHA256H2, 632 ARM_INS_SHA256SU0, 633 ARM_INS_SHA256SU1, 634 ARM_INS_SHADD16, 635 ARM_INS_SHADD8, 636 ARM_INS_SHASX, 637 ARM_INS_SHSAX, 638 ARM_INS_SHSUB16, 639 ARM_INS_SHSUB8, 640 ARM_INS_SMC, 641 ARM_INS_SMLABB, 642 ARM_INS_SMLABT, 643 ARM_INS_SMLAD, 644 ARM_INS_SMLADX, 645 ARM_INS_SMLAL, 646 ARM_INS_SMLALBB, 647 ARM_INS_SMLALBT, 648 ARM_INS_SMLALD, 649 ARM_INS_SMLALDX, 650 ARM_INS_SMLALTB, 651 ARM_INS_SMLALTT, 652 ARM_INS_SMLATB, 653 ARM_INS_SMLATT, 654 ARM_INS_SMLAWB, 655 ARM_INS_SMLAWT, 656 ARM_INS_SMLSD, 657 ARM_INS_SMLSDX, 658 ARM_INS_SMLSLD, 659 ARM_INS_SMLSLDX, 660 ARM_INS_SMMLA, 661 ARM_INS_SMMLAR, 662 ARM_INS_SMMLS, 663 ARM_INS_SMMLSR, 664 ARM_INS_SMMUL, 665 ARM_INS_SMMULR, 666 ARM_INS_SMUAD, 667 ARM_INS_SMUADX, 668 ARM_INS_SMULBB, 669 ARM_INS_SMULBT, 670 ARM_INS_SMULL, 671 ARM_INS_SMULTB, 672 ARM_INS_SMULTT, 673 ARM_INS_SMULWB, 674 ARM_INS_SMULWT, 675 ARM_INS_SMUSD, 676 ARM_INS_SMUSDX, 677 ARM_INS_SRSDA, 678 ARM_INS_SRSDB, 679 ARM_INS_SRSIA, 680 ARM_INS_SRSIB, 681 ARM_INS_SSAT, 682 ARM_INS_SSAT16, 683 ARM_INS_SSAX, 684 ARM_INS_SSUB16, 685 ARM_INS_SSUB8, 686 ARM_INS_STC, 687 ARM_INS_STC2, 688 ARM_INS_STC2L, 689 ARM_INS_STCL, 690 ARM_INS_STL, 691 ARM_INS_STLB, 692 ARM_INS_STLEX, 693 ARM_INS_STLEXB, 694 ARM_INS_STLEXD, 695 ARM_INS_STLEXH, 696 ARM_INS_STLH, 697 ARM_INS_STM, 698 ARM_INS_STMDA, 699 ARM_INS_STMDB, 700 ARM_INS_STMIB, 701 ARM_INS_STR, 702 ARM_INS_STRB, 703 ARM_INS_STRBT, 704 ARM_INS_STRD, 705 ARM_INS_STREX, 706 ARM_INS_STREXB, 707 ARM_INS_STREXD, 708 ARM_INS_STREXH, 709 ARM_INS_STRH, 710 ARM_INS_STRHT, 711 ARM_INS_STRT, 712 ARM_INS_SUB, 713 ARM_INS_SUBS, 714 ARM_INS_SUBW, 715 ARM_INS_SVC, 716 ARM_INS_SWP, 717 ARM_INS_SWPB, 718 ARM_INS_SXTAB, 719 ARM_INS_SXTAB16, 720 ARM_INS_SXTAH, 721 ARM_INS_SXTB, 722 ARM_INS_SXTB16, 723 ARM_INS_SXTH, 724 ARM_INS_TBB, 725 ARM_INS_TBH, 726 ARM_INS_TEQ, 727 ARM_INS_TRAP, 728 ARM_INS_TSB, 729 ARM_INS_TST, 730 ARM_INS_TT, 731 ARM_INS_TTA, 732 ARM_INS_TTAT, 733 ARM_INS_TTT, 734 ARM_INS_UADD16, 735 ARM_INS_UADD8, 736 ARM_INS_UASX, 737 ARM_INS_UBFX, 738 ARM_INS_UDF, 739 ARM_INS_UDIV, 740 ARM_INS_UHADD16, 741 ARM_INS_UHADD8, 742 ARM_INS_UHASX, 743 ARM_INS_UHSAX, 744 ARM_INS_UHSUB16, 745 ARM_INS_UHSUB8, 746 ARM_INS_UMAAL, 747 ARM_INS_UMLAL, 748 ARM_INS_UMULL, 749 ARM_INS_UQADD16, 750 ARM_INS_UQADD8, 751 ARM_INS_UQASX, 752 ARM_INS_UQSAX, 753 ARM_INS_UQSUB16, 754 ARM_INS_UQSUB8, 755 ARM_INS_USAD8, 756 ARM_INS_USADA8, 757 ARM_INS_USAT, 758 ARM_INS_USAT16, 759 ARM_INS_USAX, 760 ARM_INS_USUB16, 761 ARM_INS_USUB8, 762 ARM_INS_UXTAB, 763 ARM_INS_UXTAB16, 764 ARM_INS_UXTAH, 765 ARM_INS_UXTB, 766 ARM_INS_UXTB16, 767 ARM_INS_UXTH, 768 ARM_INS_VABA, 769 ARM_INS_VABAL, 770 ARM_INS_VABD, 771 ARM_INS_VABDL, 772 ARM_INS_VABS, 773 ARM_INS_VACGE, 774 ARM_INS_VACGT, 775 ARM_INS_VACLE, 776 ARM_INS_VACLT, 777 ARM_INS_VADD, 778 ARM_INS_VADDHN, 779 ARM_INS_VADDL, 780 ARM_INS_VADDW, 781 ARM_INS_VAND, 782 ARM_INS_VBIC, 783 ARM_INS_VBIF, 784 ARM_INS_VBIT, 785 ARM_INS_VBSL, 786 ARM_INS_VCADD, 787 ARM_INS_VCEQ, 788 ARM_INS_VCGE, 789 ARM_INS_VCGT, 790 ARM_INS_VCLE, 791 ARM_INS_VCLS, 792 ARM_INS_VCLT, 793 ARM_INS_VCLZ, 794 ARM_INS_VCMLA, 795 ARM_INS_VCMP, 796 ARM_INS_VCMPE, 797 ARM_INS_VCNT, 798 ARM_INS_VCVT, 799 ARM_INS_VCVTA, 800 ARM_INS_VCVTB, 801 ARM_INS_VCVTM, 802 ARM_INS_VCVTN, 803 ARM_INS_VCVTP, 804 ARM_INS_VCVTR, 805 ARM_INS_VCVTT, 806 ARM_INS_VDIV, 807 ARM_INS_VDUP, 808 ARM_INS_VEOR, 809 ARM_INS_VEXT, 810 ARM_INS_VFMA, 811 ARM_INS_VFMS, 812 ARM_INS_VFNMA, 813 ARM_INS_VFNMS, 814 ARM_INS_VHADD, 815 ARM_INS_VHSUB, 816 ARM_INS_VINS, 817 ARM_INS_VJCVT, 818 ARM_INS_VLD1, 819 ARM_INS_VLD2, 820 ARM_INS_VLD3, 821 ARM_INS_VLD4, 822 ARM_INS_VLDMDB, 823 ARM_INS_VLDMIA, 824 ARM_INS_VLDR, 825 ARM_INS_VLLDM, 826 ARM_INS_VLSTM, 827 ARM_INS_VMAX, 828 ARM_INS_VMAXNM, 829 ARM_INS_VMIN, 830 ARM_INS_VMINNM, 831 ARM_INS_VMLA, 832 ARM_INS_VMLAL, 833 ARM_INS_VMLS, 834 ARM_INS_VMLSL, 835 ARM_INS_VMOV, 836 ARM_INS_VMOVL, 837 ARM_INS_VMOVN, 838 ARM_INS_VMOVX, 839 ARM_INS_VMRS, 840 ARM_INS_VMSR, 841 ARM_INS_VMUL, 842 ARM_INS_VMULL, 843 ARM_INS_VMVN, 844 ARM_INS_VNEG, 845 ARM_INS_VNMLA, 846 ARM_INS_VNMLS, 847 ARM_INS_VNMUL, 848 ARM_INS_VORN, 849 ARM_INS_VORR, 850 ARM_INS_VPADAL, 851 ARM_INS_VPADD, 852 ARM_INS_VPADDL, 853 ARM_INS_VPMAX, 854 ARM_INS_VPMIN, 855 ARM_INS_VPOP, 856 ARM_INS_VPUSH, 857 ARM_INS_VQABS, 858 ARM_INS_VQADD, 859 ARM_INS_VQDMLAL, 860 ARM_INS_VQDMLSL, 861 ARM_INS_VQDMULH, 862 ARM_INS_VQDMULL, 863 ARM_INS_VQMOVN, 864 ARM_INS_VQMOVUN, 865 ARM_INS_VQNEG, 866 ARM_INS_VQRDMLAH, 867 ARM_INS_VQRDMLSH, 868 ARM_INS_VQRDMULH, 869 ARM_INS_VQRSHL, 870 ARM_INS_VQRSHRN, 871 ARM_INS_VQRSHRUN, 872 ARM_INS_VQSHL, 873 ARM_INS_VQSHLU, 874 ARM_INS_VQSHRN, 875 ARM_INS_VQSHRUN, 876 ARM_INS_VQSUB, 877 ARM_INS_VRADDHN, 878 ARM_INS_VRECPE, 879 ARM_INS_VRECPS, 880 ARM_INS_VREV16, 881 ARM_INS_VREV32, 882 ARM_INS_VREV64, 883 ARM_INS_VRHADD, 884 ARM_INS_VRINTA, 885 ARM_INS_VRINTM, 886 ARM_INS_VRINTN, 887 ARM_INS_VRINTP, 888 ARM_INS_VRINTR, 889 ARM_INS_VRINTX, 890 ARM_INS_VRINTZ, 891 ARM_INS_VRSHL, 892 ARM_INS_VRSHR, 893 ARM_INS_VRSHRN, 894 ARM_INS_VRSQRTE, 895 ARM_INS_VRSQRTS, 896 ARM_INS_VRSRA, 897 ARM_INS_VRSUBHN, 898 ARM_INS_VSDOT, 899 ARM_INS_VSELEQ, 900 ARM_INS_VSELGE, 901 ARM_INS_VSELGT, 902 ARM_INS_VSELVS, 903 ARM_INS_VSHL, 904 ARM_INS_VSHLL, 905 ARM_INS_VSHR, 906 ARM_INS_VSHRN, 907 ARM_INS_VSLI, 908 ARM_INS_VSQRT, 909 ARM_INS_VSRA, 910 ARM_INS_VSRI, 911 ARM_INS_VST1, 912 ARM_INS_VST2, 913 ARM_INS_VST3, 914 ARM_INS_VST4, 915 ARM_INS_VSTMDB, 916 ARM_INS_VSTMIA, 917 ARM_INS_VSTR, 918 ARM_INS_VSUB, 919 ARM_INS_VSUBHN, 920 ARM_INS_VSUBL, 921 ARM_INS_VSUBW, 922 ARM_INS_VSWP, 923 ARM_INS_VTBL, 924 ARM_INS_VTBX, 925 ARM_INS_VTRN, 926 ARM_INS_VTST, 927 ARM_INS_VUDOT, 928 ARM_INS_VUZP, 929 ARM_INS_VZIP, 930 ARM_INS_WFE, 931 ARM_INS_WFI, 932 ARM_INS_YIELD, 933 934 ARM_INS_ENDING, // <-- mark the end of the list of instructions 935 } arm_insn; 936 937 /// Group of ARM instructions 938 typedef enum arm_insn_group { 939 ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID 940 941 // Generic groups 942 // all jump instructions (conditional+direct+indirect jumps) 943 ARM_GRP_JUMP, ///< = CS_GRP_JUMP 944 ARM_GRP_CALL, ///< = CS_GRP_CALL 945 ARM_GRP_INT = 4, ///< = CS_GRP_INT 946 ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE 947 ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE 948 949 // Architecture-specific groups 950 ARM_GRP_CRYPTO = 128, 951 ARM_GRP_DATABARRIER, 952 ARM_GRP_DIVIDE, 953 ARM_GRP_FPARMV8, 954 ARM_GRP_MULTPRO, 955 ARM_GRP_NEON, 956 ARM_GRP_T2EXTRACTPACK, 957 ARM_GRP_THUMB2DSP, 958 ARM_GRP_TRUSTZONE, 959 ARM_GRP_V4T, 960 ARM_GRP_V5T, 961 ARM_GRP_V5TE, 962 ARM_GRP_V6, 963 ARM_GRP_V6T2, 964 ARM_GRP_V7, 965 ARM_GRP_V8, 966 ARM_GRP_VFP2, 967 ARM_GRP_VFP3, 968 ARM_GRP_VFP4, 969 ARM_GRP_ARM, 970 ARM_GRP_MCLASS, 971 ARM_GRP_NOTMCLASS, 972 ARM_GRP_THUMB, 973 ARM_GRP_THUMB1ONLY, 974 ARM_GRP_THUMB2, 975 ARM_GRP_PREV8, 976 ARM_GRP_FPVMLX, 977 ARM_GRP_MULOPS, 978 ARM_GRP_CRC, 979 ARM_GRP_DPVFP, 980 ARM_GRP_V6M, 981 ARM_GRP_VIRTUALIZATION, 982 983 ARM_GRP_ENDING, 984 } arm_insn_group; 985 986 #ifdef __cplusplus 987 } 988 #endif 989 990 #endif 991