1 /** @file 2 3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4 Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef __AARCH64_H__ 11 #define __AARCH64_H__ 12 13 #include <Chipset/AArch64Mmu.h> 14 15 // ARM Interrupt ID in Exception Table 16 #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ 17 18 // CPACR - Coprocessor Access Control Register definitions 19 #define CPACR_TTA_EN (1UL << 28) 20 #define CPACR_FPEN_EL1 (1UL << 20) 21 #define CPACR_FPEN_FULL (3UL << 20) 22 #define CPACR_CP_FULL_ACCESS 0x300000 23 24 // Coprocessor Trap Register (CPTR) 25 #define AARCH64_CPTR_TFP (1 << 10) 26 27 // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions 28 #define AARCH64_PFR0_FP (0xF << 16) 29 #define AARCH64_PFR0_GIC (0xF << 24) 30 31 // SCR - Secure Configuration Register definitions 32 #define SCR_NS (1 << 0) 33 #define SCR_IRQ (1 << 1) 34 #define SCR_FIQ (1 << 2) 35 #define SCR_EA (1 << 3) 36 #define SCR_FW (1 << 4) 37 #define SCR_AW (1 << 5) 38 39 // MIDR - Main ID Register definitions 40 #define ARM_CPU_TYPE_SHIFT 4 41 #define ARM_CPU_TYPE_MASK 0xFFF 42 #define ARM_CPU_TYPE_AEMv8 0xD0F 43 #define ARM_CPU_TYPE_A53 0xD03 44 #define ARM_CPU_TYPE_A57 0xD07 45 #define ARM_CPU_TYPE_A72 0xD08 46 #define ARM_CPU_TYPE_A15 0xC0F 47 #define ARM_CPU_TYPE_A9 0xC09 48 #define ARM_CPU_TYPE_A7 0xC07 49 #define ARM_CPU_TYPE_A5 0xC05 50 51 #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) ) 52 #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF)) 53 54 // Hypervisor Configuration Register 55 #define ARM_HCR_FMO BIT3 56 #define ARM_HCR_IMO BIT4 57 #define ARM_HCR_AMO BIT5 58 #define ARM_HCR_TSC BIT19 59 #define ARM_HCR_TGE BIT27 60 61 // Exception Syndrome Register 62 #define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr)) 63 #define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr)) 64 65 #define AARCH64_ESR_EC_SMC32 (0x13 << 26) 66 #define AARCH64_ESR_EC_SMC64 (0x17 << 26) 67 68 // AArch64 Exception Level 69 #define AARCH64_EL3 0xC 70 #define AARCH64_EL2 0x8 71 #define AARCH64_EL1 0x4 72 73 // Saved Program Status Register definitions 74 #define SPSR_A BIT8 75 #define SPSR_I BIT7 76 #define SPSR_F BIT6 77 78 #define SPSR_AARCH32 BIT4 79 80 #define SPSR_AARCH32_MODE_USER 0x0 81 #define SPSR_AARCH32_MODE_FIQ 0x1 82 #define SPSR_AARCH32_MODE_IRQ 0x2 83 #define SPSR_AARCH32_MODE_SVC 0x3 84 #define SPSR_AARCH32_MODE_ABORT 0x7 85 #define SPSR_AARCH32_MODE_UNDEF 0xB 86 #define SPSR_AARCH32_MODE_SYS 0xF 87 88 // Counter-timer Hypervisor Control register definitions 89 #define CNTHCTL_EL2_EL1PCTEN BIT0 90 #define CNTHCTL_EL2_EL1PCEN BIT1 91 92 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1) 93 94 // Vector table offset definitions 95 #define ARM_VECTOR_CUR_SP0_SYNC 0x000 96 #define ARM_VECTOR_CUR_SP0_IRQ 0x080 97 #define ARM_VECTOR_CUR_SP0_FIQ 0x100 98 #define ARM_VECTOR_CUR_SP0_SERR 0x180 99 100 #define ARM_VECTOR_CUR_SPx_SYNC 0x200 101 #define ARM_VECTOR_CUR_SPx_IRQ 0x280 102 #define ARM_VECTOR_CUR_SPx_FIQ 0x300 103 #define ARM_VECTOR_CUR_SPx_SERR 0x380 104 105 #define ARM_VECTOR_LOW_A64_SYNC 0x400 106 #define ARM_VECTOR_LOW_A64_IRQ 0x480 107 #define ARM_VECTOR_LOW_A64_FIQ 0x500 108 #define ARM_VECTOR_LOW_A64_SERR 0x580 109 110 #define ARM_VECTOR_LOW_A32_SYNC 0x600 111 #define ARM_VECTOR_LOW_A32_IRQ 0x680 112 #define ARM_VECTOR_LOW_A32_FIQ 0x700 113 #define ARM_VECTOR_LOW_A32_SERR 0x780 114 115 #define VECTOR_BASE(tbl) \ 116 .section .text.##tbl##,"ax"; \ 117 .align 11; \ 118 .org 0x0; \ 119 GCC_ASM_EXPORT(tbl); \ 120 ASM_PFX(tbl): \ 121 122 #define VECTOR_ENTRY(tbl, off) \ 123 .org off 124 125 #define VECTOR_END(tbl) \ 126 .org 0x800; \ 127 .previous 128 129 VOID 130 EFIAPI 131 ArmEnableSWPInstruction ( 132 VOID 133 ); 134 135 UINTN 136 EFIAPI 137 ArmReadCbar ( 138 VOID 139 ); 140 141 UINTN 142 EFIAPI 143 ArmReadTpidrurw ( 144 VOID 145 ); 146 147 VOID 148 EFIAPI 149 ArmWriteTpidrurw ( 150 UINTN Value 151 ); 152 153 UINTN 154 EFIAPI 155 ArmGetTCR ( 156 VOID 157 ); 158 159 VOID 160 EFIAPI 161 ArmSetTCR ( 162 UINTN Value 163 ); 164 165 UINTN 166 EFIAPI 167 ArmGetMAIR ( 168 VOID 169 ); 170 171 VOID 172 EFIAPI 173 ArmSetMAIR ( 174 UINTN Value 175 ); 176 177 VOID 178 EFIAPI 179 ArmDisableAlignmentCheck ( 180 VOID 181 ); 182 183 VOID 184 EFIAPI 185 ArmEnableAlignmentCheck ( 186 VOID 187 ); 188 189 VOID 190 EFIAPI 191 ArmDisableStackAlignmentCheck ( 192 VOID 193 ); 194 195 VOID 196 EFIAPI 197 ArmEnableStackAlignmentCheck ( 198 VOID 199 ); 200 201 VOID 202 EFIAPI 203 ArmDisableAllExceptions ( 204 VOID 205 ); 206 207 VOID 208 ArmWriteHcr ( 209 IN UINTN Hcr 210 ); 211 212 UINTN 213 ArmReadHcr ( 214 VOID 215 ); 216 217 UINTN 218 ArmReadCurrentEL ( 219 VOID 220 ); 221 222 UINTN 223 ArmWriteCptr ( 224 IN UINT64 Cptr 225 ); 226 227 UINT32 228 ArmReadCntHctl ( 229 VOID 230 ); 231 232 VOID 233 ArmWriteCntHctl ( 234 IN UINT32 CntHctl 235 ); 236 237 #endif // __AARCH64_H__ 238