1 #ifndef __AHCI_H 2 #define __AHCI_H 3 4 #include "block.h" // struct drive_s 5 #include "types.h" // u32 6 7 struct sata_cmd_fis { 8 u8 reg; 9 u8 pmp_type; 10 u8 command; 11 u8 feature; 12 13 u8 lba_low; 14 u8 lba_mid; 15 u8 lba_high; 16 u8 device; 17 18 u8 lba_low2; 19 u8 lba_mid2; 20 u8 lba_high2; 21 u8 feature2; 22 23 u8 sector_count; 24 u8 sector_count2; 25 u8 res_1; 26 u8 control; 27 28 u8 res_2[64 - 16]; 29 }; 30 31 struct ahci_ctrl_s { 32 struct pci_device *pci_tmp; 33 u8 irq; 34 void *iobase; 35 u32 caps; 36 u32 ports; 37 }; 38 39 struct ahci_cmd_s { 40 struct sata_cmd_fis fis; 41 u8 atapi[0x20]; 42 u8 res[0x20]; 43 struct { 44 u32 base; 45 u32 baseu; 46 u32 res; 47 u32 flags; 48 } prdt[]; 49 }; 50 51 /* command list */ 52 struct ahci_list_s { 53 u32 flags; 54 u32 bytes; 55 u32 base; 56 u32 baseu; 57 u32 res[4]; 58 }; 59 60 struct ahci_fis_s { 61 u8 dsfis[0x1c]; /* dma setup */ 62 u8 res_1[0x04]; 63 u8 psfis[0x14]; /* pio setup */ 64 u8 res_2[0x0c]; 65 u8 rfis[0x14]; /* d2h register */ 66 u8 res_3[0x04]; 67 u8 sdbfis[0x08]; /* set device bits */ 68 u8 ufis[0x40]; /* unknown */ 69 u8 res_4[0x60]; 70 }; 71 72 struct ahci_port_s { 73 struct drive_s drive; 74 struct ahci_ctrl_s *ctrl; 75 struct ahci_list_s *list; 76 struct ahci_fis_s *fis; 77 struct ahci_cmd_s *cmd; 78 u32 pnr; 79 u32 atapi; 80 char *desc; 81 int prio; 82 }; 83 84 void ahci_setup(void); 85 int ahci_process_op(struct disk_op_s *op); 86 int ahci_atapi_process_op(struct disk_op_s *op); 87 88 #define AHCI_IRQ_ON_SG (1 << 31) 89 #define AHCI_CMD_ATAPI (1 << 5) 90 #define AHCI_CMD_WRITE (1 << 6) 91 #define AHCI_CMD_PREFETCH (1 << 7) 92 #define AHCI_CMD_RESET (1 << 8) 93 #define AHCI_CMD_CLR_BUSY (1 << 10) 94 95 #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ 96 #define RX_FIS_SDB 0x58 /* offset of SDB FIS data */ 97 #define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */ 98 99 /* global controller registers */ 100 #define HOST_CAP 0x00 /* host capabilities */ 101 #define HOST_CTL 0x04 /* global host control */ 102 #define HOST_IRQ_STAT 0x08 /* interrupt status */ 103 #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ 104 #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ 105 106 /* HOST_CTL bits */ 107 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */ 108 #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */ 109 #define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ 110 111 /* HOST_CAP bits */ 112 #define HOST_CAP_SSC (1 << 14) /* Slumber capable */ 113 #define HOST_CAP_AHCI (1 << 18) /* AHCI only */ 114 #define HOST_CAP_CLO (1 << 24) /* Command List Override support */ 115 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */ 116 #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */ 117 #define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */ 118 119 /* registers for each SATA port */ 120 #define PORT_LST_ADDR 0x00 /* command list DMA addr */ 121 #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ 122 #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ 123 #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ 124 #define PORT_IRQ_STAT 0x10 /* interrupt status */ 125 #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ 126 #define PORT_CMD 0x18 /* port command */ 127 #define PORT_TFDATA 0x20 /* taskfile data */ 128 #define PORT_SIG 0x24 /* device TF signature */ 129 #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ 130 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ 131 #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ 132 #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ 133 #define PORT_CMD_ISSUE 0x38 /* command issue */ 134 #define PORT_RESERVED 0x3c /* reserved */ 135 136 /* PORT_IRQ_{STAT,MASK} bits */ 137 #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ 138 #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ 139 #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ 140 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ 141 #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ 142 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ 143 #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ 144 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ 145 146 #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ 147 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ 148 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ 149 #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ 150 #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ 151 #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ 152 #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ 153 #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ 154 #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ 155 156 #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \ 157 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \ 158 PORT_IRQ_UNK_FIS) 159 #define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \ 160 PORT_IRQ_HBUS_DATA_ERR) 161 #define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \ 162 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \ 163 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS) 164 165 /* PORT_CMD bits */ 166 #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ 167 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ 168 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ 169 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ 170 #define PORT_CMD_CLO (1 << 3) /* Command list override */ 171 #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ 172 #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ 173 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ 174 175 #define PORT_CMD_ICC_MASK (0xf << 28) /* i/f ICC state mask */ 176 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ 177 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ 178 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ 179 180 #define PORT_IRQ_STAT_DHRS (1 << 0) /* Device to Host Register FIS */ 181 #define PORT_IRQ_STAT_PSS (1 << 1) /* PIO Setup FIS */ 182 #define PORT_IRQ_STAT_DSS (1 << 2) /* DMA Setup FIS */ 183 #define PORT_IRQ_STAT_SDBS (1 << 3) /* Set Device Bits */ 184 #define PORT_IRQ_STAT_UFS (1 << 4) /* Unknown FIS */ 185 #define PORT_IRQ_STAT_DPS (1 << 5) /* Descriptor Processed */ 186 #define PORT_IRQ_STAT_PCS (1 << 6) /* Port Connect Change Status */ 187 #define PORT_IRQ_STAT_DMPS (1 << 7) /* Device Mechanical Presence 188 Status */ 189 #define PORT_IRQ_STAT_PRCS (1 << 22) /* File Ready Status */ 190 #define PORT_IRQ_STAT_IPMS (1 << 23) /* Incorrect Port Multiplier 191 Status */ 192 #define PORT_IRQ_STAT_OFS (1 << 24) /* Overflow Status */ 193 #define PORT_IRQ_STAT_INFS (1 << 26) /* Interface Non-Fatal Error 194 Status */ 195 #define PORT_IRQ_STAT_IFS (1 << 27) /* Interface Fatal Error */ 196 #define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */ 197 #define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */ 198 #define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */ 199 #define PORT_IRQ_STAT_CPDS (1 << 31) /* Code Port Detect Status */ 200 201 #endif // ahci.h 202