1 // Code for misc 16bit handlers and variables.
2 //
3 // Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
5 //
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
7
8 #include "biosvar.h" // GET_BDA
9 #include "bregs.h" // struct bregs
10 #include "hw/pic.h" // enable_hwirq
11 #include "output.h" // debug_enter
12 #include "stacks.h" // call16_int
13 #include "string.h" // memset
14
15 #define PORT_MATH_CLEAR 0x00f0
16
17 // Indicator if POST phase has been started (and if it has completed).
18 int HaveRunPost VARFSEG;
19
20 int
in_post(void)21 in_post(void)
22 {
23 return GET_GLOBAL(HaveRunPost) == 1;
24 }
25
26
27 /****************************************************************
28 * Misc 16bit ISRs
29 ****************************************************************/
30
31 // INT 12h Memory Size Service Entry Point
32 void VISIBLE16
handle_12(struct bregs * regs)33 handle_12(struct bregs *regs)
34 {
35 debug_enter(regs, DEBUG_HDL_12);
36 regs->ax = GET_BDA(mem_size_kb);
37 }
38
39 // INT 11h Equipment List Service Entry Point
40 void VISIBLE16
handle_11(struct bregs * regs)41 handle_11(struct bregs *regs)
42 {
43 debug_enter(regs, DEBUG_HDL_11);
44 regs->ax = GET_BDA(equipment_list_flags);
45 }
46
47 // INT 05h Print Screen Service Entry Point
48 void VISIBLE16
handle_05(struct bregs * regs)49 handle_05(struct bregs *regs)
50 {
51 debug_enter(regs, DEBUG_HDL_05);
52 }
53
54 // NMI handler
55 void VISIBLE16
handle_02(void)56 handle_02(void)
57 {
58 debug_isr(DEBUG_ISR_02);
59 }
60
61 void
mathcp_setup(void)62 mathcp_setup(void)
63 {
64 dprintf(3, "math cp init\n");
65 // 80x87 coprocessor installed
66 set_equipment_flags(0x02, 0x02);
67 enable_hwirq(13, FUNC16(entry_75));
68 }
69
70 // INT 75 - IRQ13 - MATH COPROCESSOR EXCEPTION
71 void VISIBLE16
handle_75(void)72 handle_75(void)
73 {
74 debug_isr(DEBUG_ISR_75);
75
76 // clear irq13
77 outb(0, PORT_MATH_CLEAR);
78 // clear interrupt
79 pic_eoi2();
80 // legacy nmi call
81 struct bregs br;
82 memset(&br, 0, sizeof(br));
83 br.flags = F_IF;
84 call16_int(0x02, &br);
85 }
86
87
88 /****************************************************************
89 * BIOS_CONFIG_TABLE
90 ****************************************************************/
91
92 // DMA channel 3 used by hard disk BIOS
93 #define CBT_F1_DMA3USED (1<<7)
94 // 2nd interrupt controller (8259) installed
95 #define CBT_F1_2NDPIC (1<<6)
96 // Real-Time Clock installed
97 #define CBT_F1_RTC (1<<5)
98 // INT 15/AH=4Fh called upon INT 09h
99 #define CBT_F1_INT154F (1<<4)
100 // wait for external event (INT 15/AH=41h) supported
101 #define CBT_F1_WAITEXT (1<<3)
102 // extended BIOS area allocated (usually at top of RAM)
103 #define CBT_F1_EBDA (1<<2)
104 // bus is Micro Channel instead of ISA
105 #define CBT_F1_MCA (1<<1)
106 // system has dual bus (Micro Channel + ISA)
107 #define CBT_F1_MCAISA (1<<0)
108
109 // INT 16/AH=09h (keyboard functionality) supported
110 #define CBT_F2_INT1609 (1<<6)
111
112 struct bios_config_table_s BIOS_CONFIG_TABLE VARFSEGFIXED(0xe6f5) = {
113 .size = sizeof(BIOS_CONFIG_TABLE) - 2,
114 .model = BUILD_MODEL_ID,
115 .submodel = BUILD_SUBMODEL_ID,
116 .biosrev = BUILD_BIOS_REVISION,
117 .feature1 = (
118 CBT_F1_2NDPIC | CBT_F1_RTC | CBT_F1_EBDA
119 | (CONFIG_KBD_CALL_INT15_4F ? CBT_F1_INT154F : 0)),
120 .feature2 = CBT_F2_INT1609,
121 .feature3 = 0,
122 .feature4 = 0,
123 .feature5 = 0,
124 };
125
126
127 /****************************************************************
128 * GDT and IDT tables
129 ****************************************************************/
130
131 // Real mode IDT descriptor
132 struct descloc_s rmode_IDT_info VARFSEG = {
133 .length = sizeof(struct rmode_IVT) - 1,
134 .addr = (u32)MAKE_FLATPTR(SEG_IVT, 0),
135 };
136
137 // Dummy IDT that forces a machine shutdown if an irq happens in
138 // protected mode.
139 u8 dummy_IDT VARFSEG;
140
141 // Protected mode IDT descriptor
142 struct descloc_s pmode_IDT_info VARFSEG = {
143 .length = sizeof(dummy_IDT) - 1,
144 .addr = (u32)&dummy_IDT,
145 };
146
147 // GDT
148 u64 rombios32_gdt[] VARFSEG __aligned(8) = {
149 // First entry can't be used.
150 0x0000000000000000LL,
151 // 32 bit flat code segment (SEG32_MODE32_CS)
152 GDT_GRANLIMIT(0xffffffff) | GDT_CODE | GDT_B,
153 // 32 bit flat data segment (SEG32_MODE32_DS)
154 GDT_GRANLIMIT(0xffffffff) | GDT_DATA | GDT_B,
155 // 16 bit code segment base=0xf0000 limit=0xffff (SEG32_MODE16_CS)
156 GDT_LIMIT(BUILD_BIOS_SIZE-1) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR),
157 // 16 bit data segment base=0x0 limit=0xffff (SEG32_MODE16_DS)
158 GDT_LIMIT(0x0ffff) | GDT_DATA,
159 // 16 bit code segment base=0xf0000 limit=0xffffffff (SEG32_MODE16BIG_CS)
160 GDT_GRANLIMIT(0xffffffff) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR),
161 // 16 bit data segment base=0 limit=0xffffffff (SEG32_MODE16BIG_DS)
162 GDT_GRANLIMIT(0xffffffff) | GDT_DATA,
163 };
164
165 // GDT descriptor
166 struct descloc_s rombios32_gdt_48 VARFSEG = {
167 .length = sizeof(rombios32_gdt) - 1,
168 .addr = (u32)rombios32_gdt,
169 };
170
171
172 /****************************************************************
173 * Misc fixed vars
174 ****************************************************************/
175
176 // BIOS build date
177 char BiosDate[] VARFSEGFIXED(0xfff5) = "06/23/99";
178
179 u8 BiosModelId VARFSEGFIXED(0xfffe) = BUILD_MODEL_ID;
180
181 u8 BiosChecksum VARFSEGFIXED(0xffff);
182
183 struct floppy_dbt_s diskette_param_table VARFSEGFIXED(0xefc7);
184
185 // Old Fixed Disk Parameter Table (newer tables are in the ebda).
186 struct fdpt_s OldFDPT VARFSEGFIXED(0xe401);
187
188 // XXX - Baud Rate Generator Table
189 u8 BaudTable[16] VARFSEGFIXED(0xe729);
190
191 // XXX - Initial Interrupt Vector Offsets Loaded by POST
192 u8 InitVectors[13] VARFSEGFIXED(0xfef3);
193
194 // XXX - INT 1D - SYSTEM DATA - VIDEO PARAMETER TABLES
195 u8 VideoParams[88] VARFSEGFIXED(0xf0a4);
196