1.. _skiboot-5.9.2: 2 3============= 4skiboot-5.9.2 5============= 6 7skiboot 5.9.2 was released on Thursday November 16th, 2017. It replaces 8:ref:`skiboot-5.9.1` as the current stable release in the 5.9.x series. 9 10Over :ref:`skiboot-5.9.1`, we have a few PHB4 (PCI) fixes, an i2c fix for 11POWER9 platforms to avoid conflicting with the OCC use and an important 12NPU2 (NVLink2) fix. 13 14- phb4: Fix lane equalisation setting 15 16 Fix cut and paste from phb3. The sizes have changes now we have GEN4, 17 so the check here needs to change also 18 19 Without this we end up with the default settings (all '7') rather 20 than what's in HDAT. 21 22- phb4: Fix PE mapping of M32 BAR 23 24 The M32 BAR is the PHB4 region used to map all the non-prefetchable 25 or 32-bit device BARs. It's supposed to have its segments remapped 26 via the MDT and Linux relies on that to assign them individual PE#. 27 28 However, we weren't configuring that properly and instead used the 29 mode where PE# == segment#, thus causing EEH to freeze the wrong 30 device or PE#. 31- phb4: Fix lost bit in PE number on config accesses 32 33 A PE number can be up to 9 bits, using a uint8_t won't fly.. 34 35 That was causing error on config accesses to freeze the 36 wrong PE. 37- phb4: Update inits 38 39 New init value from HW folks for the fence enable register. 40 41 This clears bit 17 (CFG Write Error CA or UR response) and bit 22 (MMIO Write 42 DAT_ERR Indication) and sets bit 21 (MMIO CFG Pending Error) 43- npu2: Move to new GPU memory map 44 45 There are three different ways we configure the MCD and memory map. 46 47 1) Old way (current way) 48 Skiboot configures the MCD and puts GPUs at 4TB and below 49 2) New way with MCD 50 Hostboot configures the MCD and skiboot puts GPU at 4TB and above 51 3) New way without MCD 52 No one configures the MCD and skiboot puts GPU at 4TB and below 53 54 The change keeps option 1 and adds options 2 and 3. 55 56 The different configurations are detected using certain scoms (see 57 patch). 58 59 Option 1 will go away eventually as it's a configuration that can 60 cause xstops or data integrity problems. We are keeping it around to 61 support existing hostboot. 62 63 Option 2 supports only 4 GPUs and 512GB of memory per socket. 64 65 Option 3 supports 6 GPUs and 4TB of memory but may have some 66 performance impact. 67 68- p8-i2c: Don't write the watermark register at init 69 70 On P9 the I2C master is shared with the OCC. Currently the watermark 71 values are set once at init time which is bad for two reasons: 72 73 a) We don't take the OCC master lock before setting it. Which 74 may cause issues if the OCC is currently using the master. 75 b) The OCC might change the watermark levels and we need to reset 76 them. 77 78 Change this so that we set the watermark value when a new transaction 79 is started rather than at init time. 80 81