1 /*
2 * (C) Copyright 2000-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * CPU specific code
26 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
32 */
33
34 #include <common.h>
35 #include <watchdog.h>
36 #include <command.h>
37 #include <asm/cache.h>
38 #include <ppc4xx.h>
39 #include <netdev.h>
40 #include <asm/io.h>
41
42 DECLARE_GLOBAL_DATA_PTR;
43
44 void board_reset(void);
45
46 /*
47 * To provide an interface to detect CPU number for boards that support
48 * more then one CPU, we implement the "weak" default functions here.
49 *
50 * Returns CPU number
51 */
__get_cpu_num(void)52 int __get_cpu_num(void)
53 {
54 return NA_OR_UNKNOWN_CPU;
55 }
56 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
57
58 #if defined(CONFIG_PCI)
59 #if defined(CONFIG_405GP) || \
60 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
61 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
62
63 #define PCI_ASYNC
64
pci_async_enabled(void)65 static int pci_async_enabled(void)
66 {
67 #if defined(CONFIG_405GP)
68 return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
69 #endif
70
71 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
72 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
73 defined(CONFIG_460EX) || defined(CONFIG_460GT)
74 unsigned long val;
75
76 mfsdr(SDR0_SDSTP1, val);
77 return (val & SDR0_SDSTP1_PAME_MASK);
78 #endif
79 }
80 #endif
81 #endif /* CONFIG_PCI */
82
83 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
84 !defined(CONFIG_405) && !defined(CONFIG_405EX)
pci_arbiter_enabled(void)85 int pci_arbiter_enabled(void)
86 {
87 #if defined(CONFIG_405GP)
88 return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
89 #endif
90
91 #if defined(CONFIG_405EP)
92 return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
93 #endif
94
95 #if defined(CONFIG_440GP)
96 return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
97 #endif
98
99 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
100 unsigned long val;
101
102 mfsdr(SDR0_XCR, val);
103 return (val & 0x80000000);
104 #endif
105 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
106 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
107 defined(CONFIG_460EX) || defined(CONFIG_460GT)
108 unsigned long val;
109
110 mfsdr(SDR0_PCI0, val);
111 return (val & 0x80000000);
112 #endif
113 }
114 #endif
115
116 #if defined(CONFIG_405EP)
117 #define I2C_BOOTROM
118
i2c_bootrom_enabled(void)119 static int i2c_bootrom_enabled(void)
120 {
121 #if defined(CONFIG_405EP)
122 return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
123 #else
124 unsigned long val;
125
126 mfsdr(SDR0_SDCS0, val);
127 return (val & SDR0_SDCS_SDD);
128 #endif
129 }
130 #endif
131
132 #if defined(CONFIG_440GX)
133 #define SDR0_PINSTP_SHIFT 29
134 static char *bootstrap_str[] = {
135 "EBC (16 bits)",
136 "EBC (8 bits)",
137 "EBC (32 bits)",
138 "EBC (8 bits)",
139 "PCI",
140 "I2C (Addr 0x54)",
141 "Reserved",
142 "I2C (Addr 0x50)",
143 };
144 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
145 #endif
146
147 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
148 #define SDR0_PINSTP_SHIFT 30
149 static char *bootstrap_str[] = {
150 "EBC (8 bits)",
151 "PCI",
152 "I2C (Addr 0x54)",
153 "I2C (Addr 0x50)",
154 };
155 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
156 #endif
157
158 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
159 #define SDR0_PINSTP_SHIFT 29
160 static char *bootstrap_str[] = {
161 "EBC (8 bits)",
162 "PCI",
163 "NAND (8 bits)",
164 "EBC (16 bits)",
165 "EBC (16 bits)",
166 "I2C (Addr 0x54)",
167 "PCI",
168 "I2C (Addr 0x52)",
169 };
170 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
171 #endif
172
173 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
174 #define SDR0_PINSTP_SHIFT 29
175 static char *bootstrap_str[] = {
176 "EBC (8 bits)",
177 "EBC (16 bits)",
178 "EBC (16 bits)",
179 "NAND (8 bits)",
180 "PCI",
181 "I2C (Addr 0x54)",
182 "PCI",
183 "I2C (Addr 0x52)",
184 };
185 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
186 #endif
187
188 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
189 #define SDR0_PINSTP_SHIFT 29
190 static char *bootstrap_str[] = {
191 "EBC (8 bits)",
192 "EBC (16 bits)",
193 "PCI",
194 "PCI",
195 "EBC (16 bits)",
196 "NAND (8 bits)",
197 "I2C (Addr 0x54)", /* A8 */
198 "I2C (Addr 0x52)", /* A4 */
199 };
200 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
201 #endif
202
203 #if defined(CONFIG_460SX)
204 #define SDR0_PINSTP_SHIFT 29
205 static char *bootstrap_str[] = {
206 "EBC (8 bits)",
207 "EBC (16 bits)",
208 "EBC (32 bits)",
209 "NAND (8 bits)",
210 "I2C (Addr 0x54)", /* A8 */
211 "I2C (Addr 0x52)", /* A4 */
212 };
213 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
214 #endif
215
216 #if defined(CONFIG_405EZ)
217 #define SDR0_PINSTP_SHIFT 28
218 static char *bootstrap_str[] = {
219 "EBC (8 bits)",
220 "SPI (fast)",
221 "NAND (512 page, 4 addr cycle)",
222 "I2C (Addr 0x50)",
223 "EBC (32 bits)",
224 "I2C (Addr 0x50)",
225 "NAND (2K page, 5 addr cycle)",
226 "I2C (Addr 0x50)",
227 "EBC (16 bits)",
228 "Reserved",
229 "NAND (2K page, 4 addr cycle)",
230 "I2C (Addr 0x50)",
231 "NAND (512 page, 3 addr cycle)",
232 "I2C (Addr 0x50)",
233 "SPI (slow)",
234 "I2C (Addr 0x50)",
235 };
236 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
237 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
238 #endif
239
240 #if defined(CONFIG_405EX)
241 #define SDR0_PINSTP_SHIFT 29
242 static char *bootstrap_str[] = {
243 "EBC (8 bits)",
244 "EBC (16 bits)",
245 "EBC (16 bits)",
246 "NAND (8 bits)",
247 "NAND (8 bits)",
248 "I2C (Addr 0x54)",
249 "EBC (8 bits)",
250 "I2C (Addr 0x52)",
251 };
252 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
253 #endif
254
255 #if defined(SDR0_PINSTP_SHIFT)
bootstrap_option(void)256 static int bootstrap_option(void)
257 {
258 unsigned long val;
259
260 mfsdr(SDR0_PINSTP, val);
261 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
262 }
263 #endif /* SDR0_PINSTP_SHIFT */
264
265
266 #if defined(CONFIG_440)
do_chip_reset(unsigned long sys0,unsigned long sys1)267 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
268 {
269 /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
270 * reset.
271 */
272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */
273 mtdcr (CPC0_SYS0, sys0);
274 mtdcr (CPC0_SYS1, sys1);
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
276 mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
277
278 return 1;
279 }
280 #endif
281
282
checkcpu(void)283 int checkcpu (void)
284 {
285 #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
286 uint pvr = get_pvr();
287 ulong clock = gd->cpu_clk;
288 char buf[32];
289 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
290 u32 reg;
291 #endif
292
293 #if !defined(CONFIG_IOP480)
294 char addstr[64] = "";
295 sys_info_t sys_info;
296 int cpu_num;
297
298 cpu_num = get_cpu_num();
299 if (cpu_num >= 0)
300 printf("CPU%d: ", cpu_num);
301 else
302 puts("CPU: ");
303
304 get_sys_info(&sys_info);
305
306 #if defined(CONFIG_XILINX_440)
307 puts("IBM PowerPC 4");
308 #else
309 puts("AMCC PowerPC 4");
310 #endif
311
312 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
313 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
314 defined(CONFIG_405EX)
315 puts("05");
316 #endif
317 #if defined(CONFIG_440)
318 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
319 puts("60");
320 #else
321 puts("40");
322 #endif
323 #endif
324
325 switch (pvr) {
326 case PVR_405GP_RB:
327 puts("GP Rev. B");
328 break;
329
330 case PVR_405GP_RC:
331 puts("GP Rev. C");
332 break;
333
334 case PVR_405GP_RD:
335 puts("GP Rev. D");
336 break;
337
338 #ifdef CONFIG_405GP
339 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
340 puts("GP Rev. E");
341 break;
342 #endif
343
344 case PVR_405CR_RA:
345 puts("CR Rev. A");
346 break;
347
348 case PVR_405CR_RB:
349 puts("CR Rev. B");
350 break;
351
352 #ifdef CONFIG_405CR
353 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
354 puts("CR Rev. C");
355 break;
356 #endif
357
358 case PVR_405GPR_RB:
359 puts("GPr Rev. B");
360 break;
361
362 case PVR_405EP_RB:
363 puts("EP Rev. B");
364 break;
365
366 case PVR_405EZ_RA:
367 puts("EZ Rev. A");
368 break;
369
370 case PVR_405EX1_RA:
371 puts("EX Rev. A");
372 strcpy(addstr, "Security support");
373 break;
374
375 case PVR_405EXR2_RA:
376 puts("EXr Rev. A");
377 strcpy(addstr, "No Security support");
378 break;
379
380 case PVR_405EX1_RC:
381 puts("EX Rev. C");
382 strcpy(addstr, "Security support");
383 break;
384
385 case PVR_405EX2_RC:
386 puts("EX Rev. C");
387 strcpy(addstr, "No Security support");
388 break;
389
390 case PVR_405EXR1_RC:
391 puts("EXr Rev. C");
392 strcpy(addstr, "Security support");
393 break;
394
395 case PVR_405EXR2_RC:
396 puts("EXr Rev. C");
397 strcpy(addstr, "No Security support");
398 break;
399
400 case PVR_405EX1_RD:
401 puts("EX Rev. D");
402 strcpy(addstr, "Security support");
403 break;
404
405 case PVR_405EX2_RD:
406 puts("EX Rev. D");
407 strcpy(addstr, "No Security support");
408 break;
409
410 case PVR_405EXR1_RD:
411 puts("EXr Rev. D");
412 strcpy(addstr, "Security support");
413 break;
414
415 case PVR_405EXR2_RD:
416 puts("EXr Rev. D");
417 strcpy(addstr, "No Security support");
418 break;
419
420 #if defined(CONFIG_440)
421 case PVR_440GP_RB:
422 puts("GP Rev. B");
423 /* See errata 1.12: CHIP_4 */
424 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
425 (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
426 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
427 "Resetting chip ...\n");
428 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
429 do_chip_reset ( mfdcr(CPC0_STRP0),
430 mfdcr(CPC0_STRP1) );
431 }
432 break;
433
434 case PVR_440GP_RC:
435 puts("GP Rev. C");
436 break;
437
438 case PVR_440GX_RA:
439 puts("GX Rev. A");
440 break;
441
442 case PVR_440GX_RB:
443 puts("GX Rev. B");
444 break;
445
446 case PVR_440GX_RC:
447 puts("GX Rev. C");
448 break;
449
450 case PVR_440GX_RF:
451 puts("GX Rev. F");
452 break;
453
454 case PVR_440EP_RA:
455 puts("EP Rev. A");
456 break;
457
458 #ifdef CONFIG_440EP
459 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
460 puts("EP Rev. B");
461 break;
462
463 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
464 puts("EP Rev. C");
465 break;
466 #endif /* CONFIG_440EP */
467
468 #ifdef CONFIG_440GR
469 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
470 puts("GR Rev. A");
471 break;
472
473 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
474 puts("GR Rev. B");
475 break;
476 #endif /* CONFIG_440GR */
477 #endif /* CONFIG_440 */
478
479 #ifdef CONFIG_440EPX
480 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
481 puts("EPx Rev. A");
482 strcpy(addstr, "Security/Kasumi support");
483 break;
484
485 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
486 puts("EPx Rev. A");
487 strcpy(addstr, "No Security/Kasumi support");
488 break;
489 #endif /* CONFIG_440EPX */
490
491 #ifdef CONFIG_440GRX
492 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
493 puts("GRx Rev. A");
494 strcpy(addstr, "Security/Kasumi support");
495 break;
496
497 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
498 puts("GRx Rev. A");
499 strcpy(addstr, "No Security/Kasumi support");
500 break;
501 #endif /* CONFIG_440GRX */
502
503 case PVR_440SP_6_RAB:
504 puts("SP Rev. A/B");
505 strcpy(addstr, "RAID 6 support");
506 break;
507
508 case PVR_440SP_RAB:
509 puts("SP Rev. A/B");
510 strcpy(addstr, "No RAID 6 support");
511 break;
512
513 case PVR_440SP_6_RC:
514 puts("SP Rev. C");
515 strcpy(addstr, "RAID 6 support");
516 break;
517
518 case PVR_440SP_RC:
519 puts("SP Rev. C");
520 strcpy(addstr, "No RAID 6 support");
521 break;
522
523 case PVR_440SPe_6_RA:
524 puts("SPe Rev. A");
525 strcpy(addstr, "RAID 6 support");
526 break;
527
528 case PVR_440SPe_RA:
529 puts("SPe Rev. A");
530 strcpy(addstr, "No RAID 6 support");
531 break;
532
533 case PVR_440SPe_6_RB:
534 puts("SPe Rev. B");
535 strcpy(addstr, "RAID 6 support");
536 break;
537
538 case PVR_440SPe_RB:
539 puts("SPe Rev. B");
540 strcpy(addstr, "No RAID 6 support");
541 break;
542
543 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
544 case PVR_460EX_RA:
545 puts("EX Rev. A");
546 strcpy(addstr, "No Security/Kasumi support");
547 break;
548
549 case PVR_460EX_SE_RA:
550 puts("EX Rev. A");
551 strcpy(addstr, "Security/Kasumi support");
552 break;
553
554 case PVR_460EX_RB:
555 puts("EX Rev. B");
556 mfsdr(SDR0_ECID3, reg);
557 if (reg & 0x00100000)
558 strcpy(addstr, "No Security/Kasumi support");
559 else
560 strcpy(addstr, "Security/Kasumi support");
561 break;
562
563 case PVR_460GT_RA:
564 puts("GT Rev. A");
565 strcpy(addstr, "No Security/Kasumi support");
566 break;
567
568 case PVR_460GT_SE_RA:
569 puts("GT Rev. A");
570 strcpy(addstr, "Security/Kasumi support");
571 break;
572
573 case PVR_460GT_RB:
574 puts("GT Rev. B");
575 mfsdr(SDR0_ECID3, reg);
576 if (reg & 0x00100000)
577 strcpy(addstr, "No Security/Kasumi support");
578 else
579 strcpy(addstr, "Security/Kasumi support");
580 break;
581 #endif
582
583 case PVR_460SX_RA:
584 puts("SX Rev. A");
585 strcpy(addstr, "Security support");
586 break;
587
588 case PVR_460SX_RA_V1:
589 puts("SX Rev. A");
590 strcpy(addstr, "No Security support");
591 break;
592
593 case PVR_460GX_RA:
594 puts("GX Rev. A");
595 strcpy(addstr, "Security support");
596 break;
597
598 case PVR_460GX_RA_V1:
599 puts("GX Rev. A");
600 strcpy(addstr, "No Security support");
601 break;
602
603 case PVR_VIRTEX5:
604 puts("x5 VIRTEX5");
605 break;
606
607 default:
608 printf (" UNKNOWN (PVR=%08x)", pvr);
609 break;
610 }
611
612 printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
613 strmhz(buf, clock),
614 sys_info.freqPLB / 1000000,
615 get_OPB_freq() / 1000000,
616 sys_info.freqEBC / 1000000);
617 #if defined(CONFIG_PCI) && \
618 (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
619 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
620 printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
621 #endif
622 printf(")\n");
623
624 if (addstr[0] != 0)
625 printf(" %s\n", addstr);
626
627 #if defined(I2C_BOOTROM)
628 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
629 #endif /* I2C_BOOTROM */
630 #if defined(SDR0_PINSTP_SHIFT)
631 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
632 printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
633 #ifdef CONFIG_NAND_U_BOOT
634 puts(", booting from NAND");
635 #endif /* CONFIG_NAND_U_BOOT */
636 putc('\n');
637 #endif /* SDR0_PINSTP_SHIFT */
638
639 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
640 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
641 #endif
642
643 #if defined(CONFIG_PCI) && defined(PCI_ASYNC)
644 if (pci_async_enabled()) {
645 printf (", PCI async ext clock used");
646 } else {
647 printf (", PCI sync clock at %lu MHz",
648 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
649 }
650 #endif
651
652 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
653 putc('\n');
654 #endif
655
656 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
657 printf (" 16 kB I-Cache 16 kB D-Cache");
658 #elif defined(CONFIG_440)
659 printf (" 32 kB I-Cache 32 kB D-Cache");
660 #else
661 printf (" 16 kB I-Cache %d kB D-Cache",
662 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
663 #endif
664 #endif /* !defined(CONFIG_IOP480) */
665
666 #if defined(CONFIG_IOP480)
667 printf ("PLX IOP480 (PVR=%08x)", pvr);
668 printf (" at %s MHz:", strmhz(buf, clock));
669 printf (" %u kB I-Cache", 4);
670 printf (" %u kB D-Cache", 2);
671 #endif
672
673 #endif /* !defined(CONFIG_405) */
674
675 putc ('\n');
676
677 return 0;
678 }
679
ppc440spe_revB()680 int ppc440spe_revB() {
681 unsigned int pvr;
682
683 pvr = get_pvr();
684 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
685 return 1;
686 else
687 return 0;
688 }
689
690 /* ------------------------------------------------------------------------- */
691
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * argv[])692 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
693 {
694 #if defined(CONFIG_SAM460EX)
695 usb_stop();
696
697 u16 fpga_val = 0;
698 fpga_val = in_be16((void *)CONFIG_SYS_FPGA_BASE + 0x30);
699 fpga_val &= 0xFFEB;
700 out_be16((void *)CONFIG_SYS_FPGA_BASE + 0x30, fpga_val);
701 udelay(100);
702 #endif
703 #if defined(CONFIG_BOARD_RESET)
704 board_reset();
705 #else
706 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
707 mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
708 #else
709 /*
710 * Initiate system reset in debug control register DBCR
711 */
712 mtspr(SPRN_DBCR0, 0x30000000);
713 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
714 #endif /* defined(CONFIG_BOARD_RESET) */
715
716 return 1;
717 }
718
719
720 /*
721 * Get timebase clock frequency
722 */
get_tbclk(void)723 unsigned long get_tbclk (void)
724 {
725 #if !defined(CONFIG_IOP480)
726 sys_info_t sys_info;
727
728 get_sys_info(&sys_info);
729 return (sys_info.freqProcessor);
730 #else
731 return (66000000);
732 #endif
733
734 }
735
736
737 #if defined(CONFIG_WATCHDOG)
watchdog_reset(void)738 void watchdog_reset(void)
739 {
740 int re_enable = disable_interrupts();
741 reset_4xx_watchdog();
742 if (re_enable) enable_interrupts();
743 }
744
reset_4xx_watchdog(void)745 void reset_4xx_watchdog(void)
746 {
747 /*
748 * Clear TSR(WIS) bit
749 */
750 mtspr(SPRN_TSR, 0x40000000);
751 }
752 #endif /* CONFIG_WATCHDOG */
753
754 /*
755 * Initializes on-chip ethernet controllers.
756 * to override, implement board_eth_init()
757 */
cpu_eth_init(bd_t * bis)758 int cpu_eth_init(bd_t *bis)
759 {
760 #if defined(CONFIG_PPC4xx_EMAC)
761 ppc_4xx_eth_initialize(bis);
762 #endif
763 return 0;
764 }
765