1 /* Core.h - Basic core logic functions and definitions */ 2 3 /* Copyright Galileo Technology. */ 4 5 /* 6 DESCRIPTION 7 This header file contains simple read/write macros for addressing 8 the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address 9 space). The macros take care of Big/Little endian conversions. 10 */ 11 12 #ifndef __INCcoreh 13 #define __INCcoreh 14 15 /* includes */ 16 #include "gt64260R.h" 17 18 extern unsigned int INTERNAL_REG_BASE_ADDR; 19 20 /* 21 * GT-6426x variants 22 */ 23 #define GT_64260 0 /* includes both 64260A and 64260B */ 24 #define GT_64261 1 25 26 #if (CONFIG_SYS_GT_6426x == GT_64260) 27 #ifdef CONFIG_ETHER_PORT_MII 28 #define GAL_ETH_DEVS 2 29 #else 30 #define GAL_ETH_DEVS 3 31 #endif 32 #elif (CONFIG_SYS_GT_6426x == GT_64261) 33 #define GAL_ETH_DEVS 2 34 #else 35 #define GAL_ETH_DEVS 3 /* default to a 64260 */ 36 #endif 37 38 /****************************************/ 39 /* GENERAL Definitions */ 40 /****************************************/ 41 42 #define NO_BIT 0x00000000 43 #define BIT0 0x00000001 44 #define BIT1 0x00000002 45 #define BIT2 0x00000004 46 #define BIT3 0x00000008 47 #define BIT4 0x00000010 48 #define BIT5 0x00000020 49 #define BIT6 0x00000040 50 #define BIT7 0x00000080 51 #define BIT8 0x00000100 52 #define BIT9 0x00000200 53 #define BIT10 0x00000400 54 #define BIT11 0x00000800 55 #define BIT12 0x00001000 56 #define BIT13 0x00002000 57 #define BIT14 0x00004000 58 #define BIT15 0x00008000 59 #define BIT16 0x00010000 60 #define BIT17 0x00020000 61 #define BIT18 0x00040000 62 #define BIT19 0x00080000 63 #define BIT20 0x00100000 64 #define BIT21 0x00200000 65 #define BIT22 0x00400000 66 #define BIT23 0x00800000 67 #define BIT24 0x01000000 68 #define BIT25 0x02000000 69 #define BIT26 0x04000000 70 #define BIT27 0x08000000 71 #define BIT28 0x10000000 72 #define BIT29 0x20000000 73 #define BIT30 0x40000000 74 #define BIT31 0x80000000 75 76 #define _1K 0x00000400 77 #define _2K 0x00000800 78 #define _4K 0x00001000 79 #define _8K 0x00002000 80 #define _16K 0x00004000 81 #define _32K 0x00008000 82 #define _64K 0x00010000 83 #define _128K 0x00020000 84 #define _256K 0x00040000 85 #define _512K 0x00080000 86 87 #define _1M 0x00100000 88 #define _2M 0x00200000 89 #define _3M 0x00300000 90 #define _4M 0x00400000 91 #define _5M 0x00500000 92 #define _6M 0x00600000 93 #define _7M 0x00700000 94 #define _8M 0x00800000 95 #define _9M 0x00900000 96 #define _10M 0x00a00000 97 #define _11M 0x00b00000 98 #define _12M 0x00c00000 99 #define _13M 0x00d00000 100 #define _14M 0x00e00000 101 #define _15M 0x00f00000 102 #define _16M 0x01000000 103 104 #define _32M 0x02000000 105 #define _64M 0x04000000 106 #define _128M 0x08000000 107 #define _256M 0x10000000 108 #define _512M 0x20000000 109 110 #define _1G 0x40000000 111 #define _2G 0x80000000 112 113 #ifndef BOOL_WAS_DEFINED 114 #define BOOL_WAS_DEFINED 115 typedef enum _bool{false,true} bool; 116 #endif 117 118 /* Little to Big endian conversion macros */ 119 120 #ifdef LE /* Little Endian */ 121 #define SHORT_SWAP(X) (X) 122 #define WORD_SWAP(X) (X) 123 #define LONG_SWAP(X) ((l64)(X)) 124 125 #else /* Big Endian */ 126 #define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) 127 128 #define WORD_SWAP(X) (((X)&0xff)<<24)+ \ 129 (((X)&0xff00)<<8)+ \ 130 (((X)&0xff0000)>>8)+ \ 131 (((X)&0xff000000)>>24) 132 133 #define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ 134 (((X)&0xff00ULL)<<40)+ \ 135 (((X)&0xff0000ULL)<<24)+ \ 136 (((X)&0xff000000ULL)<<8)+ \ 137 (((X)&0xff00000000ULL)>>8)+ \ 138 (((X)&0xff0000000000ULL)>>24)+ \ 139 (((X)&0xff000000000000ULL)>>40)+ \ 140 (((X)&0xff00000000000000ULL)>>56)) 141 142 #endif 143 144 #ifndef NULL 145 #define NULL 0 146 #endif 147 148 /* Those two definitions were defined to be compatible with MIPS */ 149 #define NONE_CACHEABLE 0x00000000 150 #define CACHEABLE 0x00000000 151 152 /* 750 cache line */ 153 #define CACHE_LINE_SIZE 32 154 #define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1) 155 #define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS) 156 157 /* Read/Write to/from GT`s internal registers */ 158 #define GT_REG_READ(offset, pData) \ 159 *pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ 160 INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ 161 *pData = WORD_SWAP(*pData) 162 163 #define GTREGREAD(offset) \ 164 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ 165 INTERNAL_REG_BASE_ADDR | (offset))) )) 166 167 #define GT_REG_WRITE(offset, data) \ 168 *((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \ 169 WORD_SWAP(data) 170 171 /* Write 32/16/8 bit */ 172 #define WRITE_CHAR(address, data) \ 173 *((unsigned char *)(address)) = data 174 #define WRITE_SHORT(address, data) \ 175 *((unsigned short *)(address)) = data 176 #define WRITE_WORD(address, data) \ 177 *((unsigned int *)(address)) = data 178 179 /* Read 32/16/8 bits - returns data in variable. */ 180 #define READ_CHAR(address, pData) \ 181 *pData = *((volatile unsigned char *)(address)) 182 183 #define READ_SHORT(address, pData) \ 184 *pData = *((volatile unsigned short *)(address)) 185 186 #define READ_WORD(address, pData) \ 187 *pData = *((volatile unsigned int *)(address)) 188 189 /* Read 32/16/8 bit - returns data direct. */ 190 #define READCHAR(address) \ 191 *((volatile unsigned char *)((address) | NONE_CACHEABLE)) 192 193 #define READSHORT(address) \ 194 *((volatile unsigned short *)((address) | NONE_CACHEABLE)) 195 196 #define READWORD(address) \ 197 *((volatile unsigned int *)((address) | NONE_CACHEABLE)) 198 199 /* Those two Macros were defined to be compatible with MIPS */ 200 #define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff) 201 #define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE) 202 203 /* SET_REG_BITS(regOffset,bits) - 204 gets register offset and bits: a 32bit value. It set to logic '1' in the 205 internal register the bits which given as an input example: 206 SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic 207 '1' in register 0x840 while the other bits stays as is. */ 208 #define SET_REG_BITS(regOffset,bits) \ 209 *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ 210 regOffset) |= (unsigned int)WORD_SWAP(bits) 211 212 /* RESET_REG_BITS(regOffset,bits) - 213 gets register offset and bits: a 32bit value. It set to logic '0' in the 214 internal register the bits which given as an input example: 215 RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic 216 '0' in register 0x840 while the other bits stays as is. */ 217 #define RESET_REG_BITS(regOffset,bits) \ 218 *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ 219 | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) 220 221 #endif /* __INCcoreh */ 222