1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * (C) 2018 Theobroma Systems Design und Consulting GmbH
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <syscon.h>
11 #include <asm/io.h>
12 #include <asm/arch/grf_rk3399.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/periph.h>
15 #include <asm/arch/clock.h>
16 #include <dm/pinctrl.h>
17
18 #if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
19 static const u32 RK_GRF_P_PULLUP = 1;
20 static const u32 RK_GRF_P_PULLDOWN = 2;
21 #endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
22
23 struct rk3399_pinctrl_priv {
24 struct rk3399_grf_regs *grf;
25 struct rk3399_pmugrf_regs *pmugrf;
26 struct rockchip_pin_bank *banks;
27 };
28
29 #if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
30 /* Location of pinctrl/pinconf registers. */
31 enum rk_grf_location {
32 RK_GRF,
33 RK_PMUGRF,
34 };
35
36 /**
37 * @nr_pins: number of pins in this bank
38 * @grf_location: location of pinctrl/pinconf registers
39 * @bank_num: number of the bank, to account for holes
40 * @iomux: array describing the 4 iomux sources of the bank
41 */
42 struct rockchip_pin_bank {
43 u8 nr_pins;
44 enum rk_grf_location grf_location;
45 size_t iomux_offset;
46 size_t pupd_offset;
47 };
48
49 #define PIN_BANK(pins, grf, iomux, pupd) \
50 { \
51 .nr_pins = pins, \
52 .grf_location = grf, \
53 .iomux_offset = iomux, \
54 .pupd_offset = pupd, \
55 }
56
57 static struct rockchip_pin_bank rk3399_pin_banks[] = {
58 PIN_BANK(16, RK_PMUGRF,
59 offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
60 offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
61 PIN_BANK(32, RK_PMUGRF,
62 offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
63 offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
64 PIN_BANK(32, RK_GRF,
65 offsetof(struct rk3399_grf_regs, gpio2a_iomux),
66 offsetof(struct rk3399_grf_regs, gpio2_p)),
67 PIN_BANK(32, RK_GRF,
68 offsetof(struct rk3399_grf_regs, gpio3a_iomux),
69 offsetof(struct rk3399_grf_regs, gpio3_p)),
70 PIN_BANK(32, RK_GRF,
71 offsetof(struct rk3399_grf_regs, gpio4a_iomux),
72 offsetof(struct rk3399_grf_regs, gpio4_p)),
73 };
74
rk_pinctrl_get_info(uintptr_t base,u32 index,uintptr_t * addr,u32 * shift,u32 * mask)75 static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr,
76 u32 *shift, u32 *mask)
77 {
78 /*
79 * In general we four subsequent 32-bit configuration registers
80 * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
81 * The configuration for each pin has two bits.
82 *
83 * @base...contains the address to the first register.
84 * @index...defines the pin within the bank (0..31).
85 * @addr...will be the address of the actual register to use
86 * @shift...will be the bit position in the configuration register
87 * @mask...will be the (unshifted) mask
88 */
89
90 const u32 pins_per_register = 8;
91 const u32 config_bits_per_pin = 2;
92
93 /* Get the address of the configuration register. */
94 *addr = base + (index / pins_per_register) * sizeof(u32);
95
96 /* Get the bit offset within the configuration register. */
97 *shift = (index & (pins_per_register - 1)) * config_bits_per_pin;
98
99 /* Get the (unshifted) mask for the configuration pins. */
100 *mask = ((1 << config_bits_per_pin) - 1);
101
102 pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n",
103 __func__, *addr, *mask, *shift);
104 }
105
rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr,struct rockchip_pin_bank * bank,u32 index,u32 muxval)106 static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr,
107 struct rockchip_pin_bank *bank,
108 u32 index, u32 muxval)
109 {
110 uintptr_t iomux_base, addr;
111 u32 shift, mask;
112
113 iomux_base = grf_addr + bank->iomux_offset;
114 rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask);
115
116 /* Set pinmux register */
117 rk_clrsetreg(addr, mask << shift, muxval << shift);
118 }
119
rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr,struct rockchip_pin_bank * bank,u32 index,int pinconfig)120 static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr,
121 struct rockchip_pin_bank *bank,
122 u32 index, int pinconfig)
123 {
124 uintptr_t pupd_base, addr;
125 u32 shift, mask, pupdval;
126
127 /* Fast path in case there's nothing to do. */
128 if (!pinconfig)
129 return;
130
131 if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP))
132 pupdval = RK_GRF_P_PULLUP;
133 else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) {
134 pupdval = RK_GRF_P_PULLDOWN;
135 } else {
136 /* Flag not supported. */
137 pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__,
138 pinconfig);
139 return;
140 }
141
142 pupd_base = grf_addr + (uintptr_t)bank->pupd_offset;
143 rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask);
144
145 /* Set pull-up/pull-down regisrer */
146 rk_clrsetreg(addr, mask << shift, pupdval << shift);
147 }
148
rk3399_pinctrl_set_pin(struct udevice * dev,u32 banknum,u32 index,u32 muxval,int pinconfig)149 static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index,
150 u32 muxval, int pinconfig)
151 {
152 struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
153 struct rockchip_pin_bank *bank = &priv->banks[banknum];
154 uintptr_t grf_addr;
155
156 pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval,
157 pinconfig);
158
159 if (bank->grf_location == RK_GRF)
160 grf_addr = (uintptr_t)priv->grf;
161 else if (bank->grf_location == RK_PMUGRF)
162 grf_addr = (uintptr_t)priv->pmugrf;
163 else
164 return -EINVAL;
165
166 rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval);
167
168 rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig);
169 return 0;
170 }
171
rk3399_pinctrl_set_state(struct udevice * dev,struct udevice * config)172 static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config)
173 {
174 /*
175 * The order of the fields in this struct must match the order of
176 * the fields in the "rockchip,pins" property.
177 */
178 struct rk_pin {
179 u32 banknum;
180 u32 index;
181 u32 muxval;
182 u32 phandle;
183 } __packed;
184
185 u32 *fields = NULL;
186 const int fields_per_pin = 4;
187 int num_fields, num_pins;
188 int ret;
189 int size;
190 int i;
191 struct rk_pin *pin;
192
193 pr_debug("%s: %s\n", __func__, config->name);
194
195 size = dev_read_size(config, "rockchip,pins");
196 if (size < 0)
197 return -EINVAL;
198
199 num_fields = size / sizeof(u32);
200 num_pins = num_fields / fields_per_pin;
201
202 if (num_fields * sizeof(u32) != size ||
203 num_pins * fields_per_pin != num_fields) {
204 pr_warn("Invalid number of rockchip,pins fields.\n");
205 return -EINVAL;
206 }
207
208 fields = calloc(num_fields, sizeof(u32));
209 if (!fields)
210 return -ENOMEM;
211
212 ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields);
213 if (ret) {
214 pr_warn("%s: Failed to read rockchip,pins fields.\n",
215 config->name);
216 goto end;
217 }
218
219 pin = (struct rk_pin *)fields;
220 for (i = 0; i < num_pins; i++, pin++) {
221 struct udevice *dev_pinconfig;
222 int pinconfig;
223
224 ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG,
225 pin->phandle,
226 &dev_pinconfig);
227 if (ret) {
228 pr_debug("Could not get pinconfig device\n");
229 goto end;
230 }
231
232 pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig);
233 if (pinconfig < 0) {
234 pr_warn("Could not parse pinconfig\n");
235 goto end;
236 }
237
238 ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index,
239 pin->muxval, pinconfig);
240 if (ret) {
241 pr_warn("Could not set pinctrl settings\n");
242 goto end;
243 }
244 }
245
246 end:
247 free(fields);
248 return ret;
249 }
250
251 #endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
252
pinctrl_rk3399_pwm_config(struct rk3399_grf_regs * grf,struct rk3399_pmugrf_regs * pmugrf,int pwm_id)253 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
254 struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
255 {
256 switch (pwm_id) {
257 case PERIPH_ID_PWM0:
258 rk_clrsetreg(&grf->gpio4c_iomux,
259 GRF_GPIO4C2_SEL_MASK,
260 GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
261 break;
262 case PERIPH_ID_PWM1:
263 rk_clrsetreg(&grf->gpio4c_iomux,
264 GRF_GPIO4C6_SEL_MASK,
265 GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
266 break;
267 case PERIPH_ID_PWM2:
268 rk_clrsetreg(&pmugrf->gpio1c_iomux,
269 PMUGRF_GPIO1C3_SEL_MASK,
270 PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
271 break;
272 case PERIPH_ID_PWM3:
273 if (readl(&pmugrf->soc_con0) & (1 << 5))
274 rk_clrsetreg(&pmugrf->gpio1b_iomux,
275 PMUGRF_GPIO1B6_SEL_MASK,
276 PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
277 else
278 rk_clrsetreg(&pmugrf->gpio0a_iomux,
279 PMUGRF_GPIO0A6_SEL_MASK,
280 PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
281 break;
282 default:
283 debug("pwm id = %d iomux error!\n", pwm_id);
284 break;
285 }
286 }
287
pinctrl_rk3399_i2c_config(struct rk3399_grf_regs * grf,struct rk3399_pmugrf_regs * pmugrf,int i2c_id)288 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
289 struct rk3399_pmugrf_regs *pmugrf,
290 int i2c_id)
291 {
292 switch (i2c_id) {
293 case PERIPH_ID_I2C0:
294 rk_clrsetreg(&pmugrf->gpio1b_iomux,
295 PMUGRF_GPIO1B7_SEL_MASK,
296 PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
297 rk_clrsetreg(&pmugrf->gpio1c_iomux,
298 PMUGRF_GPIO1C0_SEL_MASK,
299 PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
300 break;
301
302 case PERIPH_ID_I2C1:
303 rk_clrsetreg(&grf->gpio4a_iomux,
304 GRF_GPIO4A1_SEL_MASK,
305 GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT);
306 rk_clrsetreg(&grf->gpio4a_iomux,
307 GRF_GPIO4A2_SEL_MASK,
308 GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT);
309 break;
310
311 case PERIPH_ID_I2C2:
312 rk_clrsetreg(&grf->gpio2a_iomux,
313 GRF_GPIO2A0_SEL_MASK,
314 GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT);
315 rk_clrsetreg(&grf->gpio2a_iomux,
316 GRF_GPIO2A1_SEL_MASK,
317 GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT);
318 break;
319 case PERIPH_ID_I2C3:
320 rk_clrsetreg(&grf->gpio4c_iomux,
321 GRF_GPIO4C0_SEL_MASK,
322 GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT);
323 rk_clrsetreg(&grf->gpio4c_iomux,
324 GRF_GPIO4C1_SEL_MASK,
325 GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT);
326 break;
327
328 case PERIPH_ID_I2C4:
329 rk_clrsetreg(&pmugrf->gpio1b_iomux,
330 PMUGRF_GPIO1B3_SEL_MASK,
331 PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT);
332 rk_clrsetreg(&pmugrf->gpio1b_iomux,
333 PMUGRF_GPIO1B4_SEL_MASK,
334 PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT);
335 break;
336
337 case PERIPH_ID_I2C7:
338 rk_clrsetreg(&grf->gpio2a_iomux,
339 GRF_GPIO2A7_SEL_MASK,
340 GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT);
341 rk_clrsetreg(&grf->gpio2b_iomux,
342 GRF_GPIO2B0_SEL_MASK,
343 GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT);
344 break;
345
346 case PERIPH_ID_I2C6:
347 rk_clrsetreg(&grf->gpio2b_iomux,
348 GRF_GPIO2B1_SEL_MASK,
349 GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT);
350 rk_clrsetreg(&grf->gpio2b_iomux,
351 GRF_GPIO2B2_SEL_MASK,
352 GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT);
353 break;
354
355 case PERIPH_ID_I2C8:
356 rk_clrsetreg(&pmugrf->gpio1c_iomux,
357 PMUGRF_GPIO1C4_SEL_MASK,
358 PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT);
359 rk_clrsetreg(&pmugrf->gpio1c_iomux,
360 PMUGRF_GPIO1C5_SEL_MASK,
361 PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
362 break;
363
364 case PERIPH_ID_I2C5:
365 default:
366 debug("i2c id = %d iomux error!\n", i2c_id);
367 break;
368 }
369 }
370
pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs * grf,int lcd_id)371 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
372 {
373 switch (lcd_id) {
374 case PERIPH_ID_LCDC0:
375 break;
376 default:
377 debug("lcdc id = %d iomux error!\n", lcd_id);
378 break;
379 }
380 }
381
pinctrl_rk3399_spi_config(struct rk3399_grf_regs * grf,struct rk3399_pmugrf_regs * pmugrf,enum periph_id spi_id,int cs)382 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
383 struct rk3399_pmugrf_regs *pmugrf,
384 enum periph_id spi_id, int cs)
385 {
386 switch (spi_id) {
387 case PERIPH_ID_SPI0:
388 switch (cs) {
389 case 0:
390 rk_clrsetreg(&grf->gpio3a_iomux,
391 GRF_GPIO3A7_SEL_MASK,
392 GRF_SPI0NORCODEC_CSN0
393 << GRF_GPIO3A7_SEL_SHIFT);
394 break;
395 case 1:
396 rk_clrsetreg(&grf->gpio3b_iomux,
397 GRF_GPIO3B0_SEL_MASK,
398 GRF_SPI0NORCODEC_CSN1
399 << GRF_GPIO3B0_SEL_SHIFT);
400 break;
401 default:
402 goto err;
403 }
404 rk_clrsetreg(&grf->gpio3a_iomux,
405 GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
406 | GRF_GPIO3A6_SEL_SHIFT,
407 GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
408 | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
409 | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
410 break;
411 case PERIPH_ID_SPI1:
412 if (cs != 0)
413 goto err;
414 rk_clrsetreg(&pmugrf->gpio1a_iomux,
415 PMUGRF_GPIO1A7_SEL_MASK,
416 PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
417 rk_clrsetreg(&pmugrf->gpio1b_iomux,
418 PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
419 | PMUGRF_GPIO1B2_SEL_MASK,
420 PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
421 | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
422 | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
423 break;
424 case PERIPH_ID_SPI2:
425 if (cs != 0)
426 goto err;
427 rk_clrsetreg(&grf->gpio2b_iomux,
428 GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
429 | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
430 GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
431 | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
432 | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
433 | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
434 break;
435 case PERIPH_ID_SPI5:
436 if (cs != 0)
437 goto err;
438 rk_clrsetreg(&grf->gpio2c_iomux,
439 GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
440 | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
441 GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
442 | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
443 | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
444 | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
445 break;
446 default:
447 printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
448 goto err;
449 }
450
451 return 0;
452 err:
453 debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
454 return -ENOENT;
455 }
456
pinctrl_rk3399_uart_config(struct rk3399_grf_regs * grf,struct rk3399_pmugrf_regs * pmugrf,int uart_id)457 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
458 struct rk3399_pmugrf_regs *pmugrf,
459 int uart_id)
460 {
461 switch (uart_id) {
462 case PERIPH_ID_UART2:
463 /* Using channel-C by default */
464 rk_clrsetreg(&grf->gpio4c_iomux,
465 GRF_GPIO4C3_SEL_MASK,
466 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
467 rk_clrsetreg(&grf->gpio4c_iomux,
468 GRF_GPIO4C4_SEL_MASK,
469 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
470 break;
471 case PERIPH_ID_UART0:
472 case PERIPH_ID_UART1:
473 case PERIPH_ID_UART3:
474 case PERIPH_ID_UART4:
475 default:
476 debug("uart id = %d iomux error!\n", uart_id);
477 break;
478 }
479 }
480
pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs * grf,int mmc_id)481 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
482 {
483 switch (mmc_id) {
484 case PERIPH_ID_EMMC:
485 break;
486 case PERIPH_ID_SDCARD:
487 rk_clrsetreg(&grf->gpio4b_iomux,
488 GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
489 | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
490 | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
491 GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
492 | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
493 | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
494 | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
495 | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
496 | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
497 break;
498 default:
499 debug("mmc id = %d iomux error!\n", mmc_id);
500 break;
501 }
502 }
503
504 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
pinctrl_rk3399_gmac_config(struct rk3399_grf_regs * grf,int mmc_id)505 static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
506 {
507 rk_clrsetreg(&grf->gpio3a_iomux,
508 GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
509 GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
510 GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
511 GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
512 GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
513 GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
514 GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
515 GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
516 GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
517 GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
518 GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
519 GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
520 rk_clrsetreg(&grf->gpio3b_iomux,
521 GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
522 GRF_GPIO3B3_SEL_MASK |
523 GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
524 GRF_GPIO3B6_SEL_MASK,
525 GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
526 GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
527 GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
528 GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
529 GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
530 GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
531 rk_clrsetreg(&grf->gpio3c_iomux,
532 GRF_GPIO3C1_SEL_MASK,
533 GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
534
535 /* Set drive strength for GMAC tx io, value 3 means 13mA */
536 rk_clrsetreg(&grf->gpio3_e[0],
537 GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK |
538 GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK,
539 3 << GRF_GPIO3A0_E_SHIFT |
540 3 << GRF_GPIO3A1_E_SHIFT |
541 3 << GRF_GPIO3A4_E_SHIFT |
542 1 << GRF_GPIO3A5_E0_SHIFT);
543 rk_clrsetreg(&grf->gpio3_e[1],
544 GRF_GPIO3A5_E12_MASK,
545 1 << GRF_GPIO3A5_E12_SHIFT);
546 rk_clrsetreg(&grf->gpio3_e[2],
547 GRF_GPIO3B4_E_MASK,
548 3 << GRF_GPIO3B4_E_SHIFT);
549 rk_clrsetreg(&grf->gpio3_e[4],
550 GRF_GPIO3C1_E_MASK,
551 3 << GRF_GPIO3C1_E_SHIFT);
552 }
553 #endif
554
555 #if !defined(CONFIG_SPL_BUILD)
pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs * grf,int hdmi_id)556 static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id)
557 {
558 switch (hdmi_id) {
559 case PERIPH_ID_HDMI:
560 rk_clrsetreg(&grf->gpio4c_iomux,
561 GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK,
562 (GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) |
563 (GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT));
564 break;
565 default:
566 debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id);
567 break;
568 }
569 }
570 #endif
571
rk3399_pinctrl_request(struct udevice * dev,int func,int flags)572 static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
573 {
574 struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
575
576 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
577 switch (func) {
578 case PERIPH_ID_PWM0:
579 case PERIPH_ID_PWM1:
580 case PERIPH_ID_PWM2:
581 case PERIPH_ID_PWM3:
582 case PERIPH_ID_PWM4:
583 pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
584 break;
585 case PERIPH_ID_I2C0:
586 case PERIPH_ID_I2C1:
587 case PERIPH_ID_I2C2:
588 case PERIPH_ID_I2C3:
589 case PERIPH_ID_I2C4:
590 case PERIPH_ID_I2C5:
591 case PERIPH_ID_I2C6:
592 case PERIPH_ID_I2C7:
593 case PERIPH_ID_I2C8:
594 pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
595 break;
596 case PERIPH_ID_SPI0:
597 case PERIPH_ID_SPI1:
598 case PERIPH_ID_SPI2:
599 case PERIPH_ID_SPI3:
600 case PERIPH_ID_SPI4:
601 case PERIPH_ID_SPI5:
602 pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
603 break;
604 case PERIPH_ID_UART0:
605 case PERIPH_ID_UART1:
606 case PERIPH_ID_UART2:
607 case PERIPH_ID_UART3:
608 case PERIPH_ID_UART4:
609 pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
610 break;
611 case PERIPH_ID_LCDC0:
612 case PERIPH_ID_LCDC1:
613 pinctrl_rk3399_lcdc_config(priv->grf, func);
614 break;
615 case PERIPH_ID_SDMMC0:
616 case PERIPH_ID_SDMMC1:
617 pinctrl_rk3399_sdmmc_config(priv->grf, func);
618 break;
619 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
620 case PERIPH_ID_GMAC:
621 pinctrl_rk3399_gmac_config(priv->grf, func);
622 break;
623 #endif
624 #if !defined(CONFIG_SPL_BUILD)
625 case PERIPH_ID_HDMI:
626 pinctrl_rk3399_hdmi_config(priv->grf, func);
627 break;
628 #endif
629 default:
630 return -EINVAL;
631 }
632
633 return 0;
634 }
635
rk3399_pinctrl_get_periph_id(struct udevice * dev,struct udevice * periph)636 static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
637 struct udevice *periph)
638 {
639 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
640 u32 cell[3];
641 int ret;
642
643 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
644 if (ret < 0)
645 return -EINVAL;
646
647 switch (cell[1]) {
648 case 68:
649 return PERIPH_ID_SPI0;
650 case 53:
651 return PERIPH_ID_SPI1;
652 case 52:
653 return PERIPH_ID_SPI2;
654 case 132:
655 return PERIPH_ID_SPI5;
656 case 57:
657 return PERIPH_ID_I2C0;
658 case 59: /* Note strange order */
659 return PERIPH_ID_I2C1;
660 case 35:
661 return PERIPH_ID_I2C2;
662 case 34:
663 return PERIPH_ID_I2C3;
664 case 56:
665 return PERIPH_ID_I2C4;
666 case 38:
667 return PERIPH_ID_I2C5;
668 case 37:
669 return PERIPH_ID_I2C6;
670 case 36:
671 return PERIPH_ID_I2C7;
672 case 58:
673 return PERIPH_ID_I2C8;
674 case 65:
675 return PERIPH_ID_SDMMC1;
676 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
677 case 12:
678 return PERIPH_ID_GMAC;
679 #endif
680 #if !defined(CONFIG_SPL_BUILD)
681 case 23:
682 return PERIPH_ID_HDMI;
683 #endif
684 }
685 #endif
686 return -ENOENT;
687 }
688
rk3399_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)689 static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
690 struct udevice *periph)
691 {
692 int func;
693
694 func = rk3399_pinctrl_get_periph_id(dev, periph);
695 if (func < 0)
696 return func;
697
698 return rk3399_pinctrl_request(dev, func, 0);
699 }
700
701 static struct pinctrl_ops rk3399_pinctrl_ops = {
702 #if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
703 .set_state = rk3399_pinctrl_set_state,
704 #endif
705 .set_state_simple = rk3399_pinctrl_set_state_simple,
706 .request = rk3399_pinctrl_request,
707 .get_periph_id = rk3399_pinctrl_get_periph_id,
708 };
709
rk3399_pinctrl_probe(struct udevice * dev)710 static int rk3399_pinctrl_probe(struct udevice *dev)
711 {
712 struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
713 int ret = 0;
714
715 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
716 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
717 debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
718 #if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
719 priv->banks = rk3399_pin_banks;
720 #endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
721
722 return ret;
723 }
724
725 static const struct udevice_id rk3399_pinctrl_ids[] = {
726 { .compatible = "rockchip,rk3399-pinctrl" },
727 { }
728 };
729
730 U_BOOT_DRIVER(pinctrl_rk3399) = {
731 .name = "rockchip_rk3399_pinctrl",
732 .id = UCLASS_PINCTRL,
733 .of_match = rk3399_pinctrl_ids,
734 .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
735 .ops = &rk3399_pinctrl_ops,
736 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
737 .bind = dm_scan_fdt_dev,
738 #endif
739 .probe = rk3399_pinctrl_probe,
740 };
741