1 /*
2 * OpenRISC translation
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "disas/disas.h"
25 #include "tcg/tcg-op.h"
26 #include "qemu/log.h"
27 #include "qemu/bitops.h"
28 #include "qemu/qemu-print.h"
29 #include "exec/cpu_ldst.h"
30 #include "exec/translator.h"
31
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34 #include "exec/gen-icount.h"
35
36 #include "trace-tcg.h"
37 #include "exec/log.h"
38
39 /* is_jmp field values */
40 #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */
41 #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */
42
43 typedef struct DisasContext {
44 DisasContextBase base;
45 uint32_t mem_idx;
46 uint32_t tb_flags;
47 uint32_t delayed_branch;
48 uint32_t cpucfgr;
49 uint32_t avr;
50
51 /* If not -1, jmp_pc contains this value and so is a direct jump. */
52 target_ulong jmp_pc_imm;
53
54 /* The temporary corresponding to register 0 for this compilation. */
55 TCGv R0;
56 } DisasContext;
57
is_user(DisasContext * dc)58 static inline bool is_user(DisasContext *dc)
59 {
60 #ifdef CONFIG_USER_ONLY
61 return true;
62 #else
63 return !(dc->tb_flags & TB_FLAGS_SM);
64 #endif
65 }
66
67 /* Include the auto-generated decoder. */
68 #include "decode-insns.c.inc"
69
70 static TCGv cpu_sr;
71 static TCGv cpu_regs[32];
72 static TCGv cpu_pc;
73 static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
74 static TCGv cpu_ppc;
75 static TCGv cpu_sr_f; /* bf/bnf, F flag taken */
76 static TCGv cpu_sr_cy; /* carry (unsigned overflow) */
77 static TCGv cpu_sr_ov; /* signed overflow */
78 static TCGv cpu_lock_addr;
79 static TCGv cpu_lock_value;
80 static TCGv_i32 fpcsr;
81 static TCGv_i64 cpu_mac; /* MACHI:MACLO */
82 static TCGv_i32 cpu_dflag;
83
openrisc_translate_init(void)84 void openrisc_translate_init(void)
85 {
86 static const char * const regnames[] = {
87 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
88 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
89 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
90 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
91 };
92 int i;
93
94 cpu_sr = tcg_global_mem_new(cpu_env,
95 offsetof(CPUOpenRISCState, sr), "sr");
96 cpu_dflag = tcg_global_mem_new_i32(cpu_env,
97 offsetof(CPUOpenRISCState, dflag),
98 "dflag");
99 cpu_pc = tcg_global_mem_new(cpu_env,
100 offsetof(CPUOpenRISCState, pc), "pc");
101 cpu_ppc = tcg_global_mem_new(cpu_env,
102 offsetof(CPUOpenRISCState, ppc), "ppc");
103 jmp_pc = tcg_global_mem_new(cpu_env,
104 offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
105 cpu_sr_f = tcg_global_mem_new(cpu_env,
106 offsetof(CPUOpenRISCState, sr_f), "sr_f");
107 cpu_sr_cy = tcg_global_mem_new(cpu_env,
108 offsetof(CPUOpenRISCState, sr_cy), "sr_cy");
109 cpu_sr_ov = tcg_global_mem_new(cpu_env,
110 offsetof(CPUOpenRISCState, sr_ov), "sr_ov");
111 cpu_lock_addr = tcg_global_mem_new(cpu_env,
112 offsetof(CPUOpenRISCState, lock_addr),
113 "lock_addr");
114 cpu_lock_value = tcg_global_mem_new(cpu_env,
115 offsetof(CPUOpenRISCState, lock_value),
116 "lock_value");
117 fpcsr = tcg_global_mem_new_i32(cpu_env,
118 offsetof(CPUOpenRISCState, fpcsr),
119 "fpcsr");
120 cpu_mac = tcg_global_mem_new_i64(cpu_env,
121 offsetof(CPUOpenRISCState, mac),
122 "mac");
123 for (i = 0; i < 32; i++) {
124 cpu_regs[i] = tcg_global_mem_new(cpu_env,
125 offsetof(CPUOpenRISCState,
126 shadow_gpr[0][i]),
127 regnames[i]);
128 }
129 }
130
gen_exception(DisasContext * dc,unsigned int excp)131 static void gen_exception(DisasContext *dc, unsigned int excp)
132 {
133 TCGv_i32 tmp = tcg_const_i32(excp);
134 gen_helper_exception(cpu_env, tmp);
135 tcg_temp_free_i32(tmp);
136 }
137
gen_illegal_exception(DisasContext * dc)138 static void gen_illegal_exception(DisasContext *dc)
139 {
140 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
141 gen_exception(dc, EXCP_ILLEGAL);
142 dc->base.is_jmp = DISAS_NORETURN;
143 }
144
check_v1_3(DisasContext * dc)145 static bool check_v1_3(DisasContext *dc)
146 {
147 return dc->avr >= 0x01030000;
148 }
149
check_of32s(DisasContext * dc)150 static bool check_of32s(DisasContext *dc)
151 {
152 return dc->cpucfgr & CPUCFGR_OF32S;
153 }
154
check_of64a32s(DisasContext * dc)155 static bool check_of64a32s(DisasContext *dc)
156 {
157 return dc->cpucfgr & CPUCFGR_OF64A32S;
158 }
159
cpu_R(DisasContext * dc,int reg)160 static TCGv cpu_R(DisasContext *dc, int reg)
161 {
162 if (reg == 0) {
163 return dc->R0;
164 } else {
165 return cpu_regs[reg];
166 }
167 }
168
169 /*
170 * We're about to write to REG. On the off-chance that the user is
171 * writing to R0, re-instate the architectural register.
172 */
check_r0_write(DisasContext * dc,int reg)173 static void check_r0_write(DisasContext *dc, int reg)
174 {
175 if (unlikely(reg == 0)) {
176 dc->R0 = cpu_regs[0];
177 }
178 }
179
gen_ove_cy(DisasContext * dc)180 static void gen_ove_cy(DisasContext *dc)
181 {
182 if (dc->tb_flags & SR_OVE) {
183 gen_helper_ove_cy(cpu_env);
184 }
185 }
186
gen_ove_ov(DisasContext * dc)187 static void gen_ove_ov(DisasContext *dc)
188 {
189 if (dc->tb_flags & SR_OVE) {
190 gen_helper_ove_ov(cpu_env);
191 }
192 }
193
gen_ove_cyov(DisasContext * dc)194 static void gen_ove_cyov(DisasContext *dc)
195 {
196 if (dc->tb_flags & SR_OVE) {
197 gen_helper_ove_cyov(cpu_env);
198 }
199 }
200
gen_add(DisasContext * dc,TCGv dest,TCGv srca,TCGv srcb)201 static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
202 {
203 TCGv t0 = tcg_const_tl(0);
204 TCGv res = tcg_temp_new();
205
206 tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0);
207 tcg_gen_xor_tl(cpu_sr_ov, srca, srcb);
208 tcg_gen_xor_tl(t0, res, srcb);
209 tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov);
210 tcg_temp_free(t0);
211
212 tcg_gen_mov_tl(dest, res);
213 tcg_temp_free(res);
214
215 gen_ove_cyov(dc);
216 }
217
gen_addc(DisasContext * dc,TCGv dest,TCGv srca,TCGv srcb)218 static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
219 {
220 TCGv t0 = tcg_const_tl(0);
221 TCGv res = tcg_temp_new();
222
223 tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0);
224 tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0);
225 tcg_gen_xor_tl(cpu_sr_ov, srca, srcb);
226 tcg_gen_xor_tl(t0, res, srcb);
227 tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov);
228 tcg_temp_free(t0);
229
230 tcg_gen_mov_tl(dest, res);
231 tcg_temp_free(res);
232
233 gen_ove_cyov(dc);
234 }
235
gen_sub(DisasContext * dc,TCGv dest,TCGv srca,TCGv srcb)236 static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
237 {
238 TCGv res = tcg_temp_new();
239
240 tcg_gen_sub_tl(res, srca, srcb);
241 tcg_gen_xor_tl(cpu_sr_cy, srca, srcb);
242 tcg_gen_xor_tl(cpu_sr_ov, res, srcb);
243 tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy);
244 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb);
245
246 tcg_gen_mov_tl(dest, res);
247 tcg_temp_free(res);
248
249 gen_ove_cyov(dc);
250 }
251
gen_mul(DisasContext * dc,TCGv dest,TCGv srca,TCGv srcb)252 static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
253 {
254 TCGv t0 = tcg_temp_new();
255
256 tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb);
257 tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1);
258 tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0);
259 tcg_temp_free(t0);
260
261 tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);
262 gen_ove_ov(dc);
263 }
264
gen_mulu(DisasContext * dc,TCGv dest,TCGv srca,TCGv srcb)265 static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
266 {
267 tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb);
268 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0);
269
270 gen_ove_cy(dc);
271 }
272
gen_div(DisasContext * dc,TCGv dest,TCGv srca,TCGv srcb)273 static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
274 {
275 TCGv t0 = tcg_temp_new();
276
277 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0);
278 /* The result of divide-by-zero is undefined.
279 Supress the host-side exception by dividing by 1. */
280 tcg_gen_or_tl(t0, srcb, cpu_sr_ov);
281 tcg_gen_div_tl(dest, srca, t0);
282 tcg_temp_free(t0);
283
284 tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);
285 gen_ove_ov(dc);
286 }
287
gen_divu(DisasContext * dc,TCGv dest,TCGv srca,TCGv srcb)288 static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
289 {
290 TCGv t0 = tcg_temp_new();
291
292 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0);
293 /* The result of divide-by-zero is undefined.
294 Supress the host-side exception by dividing by 1. */
295 tcg_gen_or_tl(t0, srcb, cpu_sr_cy);
296 tcg_gen_divu_tl(dest, srca, t0);
297 tcg_temp_free(t0);
298
299 gen_ove_cy(dc);
300 }
301
gen_muld(DisasContext * dc,TCGv srca,TCGv srcb)302 static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb)
303 {
304 TCGv_i64 t1 = tcg_temp_new_i64();
305 TCGv_i64 t2 = tcg_temp_new_i64();
306
307 tcg_gen_ext_tl_i64(t1, srca);
308 tcg_gen_ext_tl_i64(t2, srcb);
309 if (TARGET_LONG_BITS == 32) {
310 tcg_gen_mul_i64(cpu_mac, t1, t2);
311 tcg_gen_movi_tl(cpu_sr_ov, 0);
312 } else {
313 TCGv_i64 high = tcg_temp_new_i64();
314
315 tcg_gen_muls2_i64(cpu_mac, high, t1, t2);
316 tcg_gen_sari_i64(t1, cpu_mac, 63);
317 tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high);
318 tcg_temp_free_i64(high);
319 tcg_gen_trunc_i64_tl(cpu_sr_ov, t1);
320 tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);
321
322 gen_ove_ov(dc);
323 }
324 tcg_temp_free_i64(t1);
325 tcg_temp_free_i64(t2);
326 }
327
gen_muldu(DisasContext * dc,TCGv srca,TCGv srcb)328 static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb)
329 {
330 TCGv_i64 t1 = tcg_temp_new_i64();
331 TCGv_i64 t2 = tcg_temp_new_i64();
332
333 tcg_gen_extu_tl_i64(t1, srca);
334 tcg_gen_extu_tl_i64(t2, srcb);
335 if (TARGET_LONG_BITS == 32) {
336 tcg_gen_mul_i64(cpu_mac, t1, t2);
337 tcg_gen_movi_tl(cpu_sr_cy, 0);
338 } else {
339 TCGv_i64 high = tcg_temp_new_i64();
340
341 tcg_gen_mulu2_i64(cpu_mac, high, t1, t2);
342 tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0);
343 tcg_gen_trunc_i64_tl(cpu_sr_cy, high);
344 tcg_temp_free_i64(high);
345
346 gen_ove_cy(dc);
347 }
348 tcg_temp_free_i64(t1);
349 tcg_temp_free_i64(t2);
350 }
351
gen_mac(DisasContext * dc,TCGv srca,TCGv srcb)352 static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb)
353 {
354 TCGv_i64 t1 = tcg_temp_new_i64();
355 TCGv_i64 t2 = tcg_temp_new_i64();
356
357 tcg_gen_ext_tl_i64(t1, srca);
358 tcg_gen_ext_tl_i64(t2, srcb);
359 tcg_gen_mul_i64(t1, t1, t2);
360
361 /* Note that overflow is only computed during addition stage. */
362 tcg_gen_xor_i64(t2, cpu_mac, t1);
363 tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
364 tcg_gen_xor_i64(t1, t1, cpu_mac);
365 tcg_gen_andc_i64(t1, t1, t2);
366 tcg_temp_free_i64(t2);
367
368 #if TARGET_LONG_BITS == 32
369 tcg_gen_extrh_i64_i32(cpu_sr_ov, t1);
370 #else
371 tcg_gen_mov_i64(cpu_sr_ov, t1);
372 #endif
373 tcg_temp_free_i64(t1);
374
375 gen_ove_ov(dc);
376 }
377
gen_macu(DisasContext * dc,TCGv srca,TCGv srcb)378 static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb)
379 {
380 TCGv_i64 t1 = tcg_temp_new_i64();
381 TCGv_i64 t2 = tcg_temp_new_i64();
382
383 tcg_gen_extu_tl_i64(t1, srca);
384 tcg_gen_extu_tl_i64(t2, srcb);
385 tcg_gen_mul_i64(t1, t1, t2);
386 tcg_temp_free_i64(t2);
387
388 /* Note that overflow is only computed during addition stage. */
389 tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
390 tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1);
391 tcg_gen_trunc_i64_tl(cpu_sr_cy, t1);
392 tcg_temp_free_i64(t1);
393
394 gen_ove_cy(dc);
395 }
396
gen_msb(DisasContext * dc,TCGv srca,TCGv srcb)397 static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb)
398 {
399 TCGv_i64 t1 = tcg_temp_new_i64();
400 TCGv_i64 t2 = tcg_temp_new_i64();
401
402 tcg_gen_ext_tl_i64(t1, srca);
403 tcg_gen_ext_tl_i64(t2, srcb);
404 tcg_gen_mul_i64(t1, t1, t2);
405
406 /* Note that overflow is only computed during subtraction stage. */
407 tcg_gen_xor_i64(t2, cpu_mac, t1);
408 tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
409 tcg_gen_xor_i64(t1, t1, cpu_mac);
410 tcg_gen_and_i64(t1, t1, t2);
411 tcg_temp_free_i64(t2);
412
413 #if TARGET_LONG_BITS == 32
414 tcg_gen_extrh_i64_i32(cpu_sr_ov, t1);
415 #else
416 tcg_gen_mov_i64(cpu_sr_ov, t1);
417 #endif
418 tcg_temp_free_i64(t1);
419
420 gen_ove_ov(dc);
421 }
422
gen_msbu(DisasContext * dc,TCGv srca,TCGv srcb)423 static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb)
424 {
425 TCGv_i64 t1 = tcg_temp_new_i64();
426 TCGv_i64 t2 = tcg_temp_new_i64();
427
428 tcg_gen_extu_tl_i64(t1, srca);
429 tcg_gen_extu_tl_i64(t2, srcb);
430 tcg_gen_mul_i64(t1, t1, t2);
431
432 /* Note that overflow is only computed during subtraction stage. */
433 tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1);
434 tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
435 tcg_gen_trunc_i64_tl(cpu_sr_cy, t2);
436 tcg_temp_free_i64(t2);
437 tcg_temp_free_i64(t1);
438
439 gen_ove_cy(dc);
440 }
441
trans_l_add(DisasContext * dc,arg_dab * a)442 static bool trans_l_add(DisasContext *dc, arg_dab *a)
443 {
444 check_r0_write(dc, a->d);
445 gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
446 return true;
447 }
448
trans_l_addc(DisasContext * dc,arg_dab * a)449 static bool trans_l_addc(DisasContext *dc, arg_dab *a)
450 {
451 check_r0_write(dc, a->d);
452 gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
453 return true;
454 }
455
trans_l_sub(DisasContext * dc,arg_dab * a)456 static bool trans_l_sub(DisasContext *dc, arg_dab *a)
457 {
458 check_r0_write(dc, a->d);
459 gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
460 return true;
461 }
462
trans_l_and(DisasContext * dc,arg_dab * a)463 static bool trans_l_and(DisasContext *dc, arg_dab *a)
464 {
465 check_r0_write(dc, a->d);
466 tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
467 return true;
468 }
469
trans_l_or(DisasContext * dc,arg_dab * a)470 static bool trans_l_or(DisasContext *dc, arg_dab *a)
471 {
472 check_r0_write(dc, a->d);
473 tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
474 return true;
475 }
476
trans_l_xor(DisasContext * dc,arg_dab * a)477 static bool trans_l_xor(DisasContext *dc, arg_dab *a)
478 {
479 check_r0_write(dc, a->d);
480 tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
481 return true;
482 }
483
trans_l_sll(DisasContext * dc,arg_dab * a)484 static bool trans_l_sll(DisasContext *dc, arg_dab *a)
485 {
486 check_r0_write(dc, a->d);
487 tcg_gen_shl_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
488 return true;
489 }
490
trans_l_srl(DisasContext * dc,arg_dab * a)491 static bool trans_l_srl(DisasContext *dc, arg_dab *a)
492 {
493 check_r0_write(dc, a->d);
494 tcg_gen_shr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
495 return true;
496 }
497
trans_l_sra(DisasContext * dc,arg_dab * a)498 static bool trans_l_sra(DisasContext *dc, arg_dab *a)
499 {
500 check_r0_write(dc, a->d);
501 tcg_gen_sar_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
502 return true;
503 }
504
trans_l_ror(DisasContext * dc,arg_dab * a)505 static bool trans_l_ror(DisasContext *dc, arg_dab *a)
506 {
507 check_r0_write(dc, a->d);
508 tcg_gen_rotr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
509 return true;
510 }
511
trans_l_exths(DisasContext * dc,arg_da * a)512 static bool trans_l_exths(DisasContext *dc, arg_da *a)
513 {
514 check_r0_write(dc, a->d);
515 tcg_gen_ext16s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a));
516 return true;
517 }
518
trans_l_extbs(DisasContext * dc,arg_da * a)519 static bool trans_l_extbs(DisasContext *dc, arg_da *a)
520 {
521 check_r0_write(dc, a->d);
522 tcg_gen_ext8s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a));
523 return true;
524 }
525
trans_l_exthz(DisasContext * dc,arg_da * a)526 static bool trans_l_exthz(DisasContext *dc, arg_da *a)
527 {
528 check_r0_write(dc, a->d);
529 tcg_gen_ext16u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a));
530 return true;
531 }
532
trans_l_extbz(DisasContext * dc,arg_da * a)533 static bool trans_l_extbz(DisasContext *dc, arg_da *a)
534 {
535 check_r0_write(dc, a->d);
536 tcg_gen_ext8u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a));
537 return true;
538 }
539
trans_l_cmov(DisasContext * dc,arg_dab * a)540 static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
541 {
542 TCGv zero;
543
544 check_r0_write(dc, a->d);
545 zero = tcg_const_tl(0);
546 tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero,
547 cpu_R(dc, a->a), cpu_R(dc, a->b));
548 tcg_temp_free(zero);
549 return true;
550 }
551
trans_l_ff1(DisasContext * dc,arg_da * a)552 static bool trans_l_ff1(DisasContext *dc, arg_da *a)
553 {
554 check_r0_write(dc, a->d);
555 tcg_gen_ctzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), -1);
556 tcg_gen_addi_tl(cpu_R(dc, a->d), cpu_R(dc, a->d), 1);
557 return true;
558 }
559
trans_l_fl1(DisasContext * dc,arg_da * a)560 static bool trans_l_fl1(DisasContext *dc, arg_da *a)
561 {
562 check_r0_write(dc, a->d);
563 tcg_gen_clzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), TARGET_LONG_BITS);
564 tcg_gen_subfi_tl(cpu_R(dc, a->d), TARGET_LONG_BITS, cpu_R(dc, a->d));
565 return true;
566 }
567
trans_l_mul(DisasContext * dc,arg_dab * a)568 static bool trans_l_mul(DisasContext *dc, arg_dab *a)
569 {
570 check_r0_write(dc, a->d);
571 gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
572 return true;
573 }
574
trans_l_mulu(DisasContext * dc,arg_dab * a)575 static bool trans_l_mulu(DisasContext *dc, arg_dab *a)
576 {
577 check_r0_write(dc, a->d);
578 gen_mulu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
579 return true;
580 }
581
trans_l_div(DisasContext * dc,arg_dab * a)582 static bool trans_l_div(DisasContext *dc, arg_dab *a)
583 {
584 check_r0_write(dc, a->d);
585 gen_div(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
586 return true;
587 }
588
trans_l_divu(DisasContext * dc,arg_dab * a)589 static bool trans_l_divu(DisasContext *dc, arg_dab *a)
590 {
591 check_r0_write(dc, a->d);
592 gen_divu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
593 return true;
594 }
595
trans_l_muld(DisasContext * dc,arg_ab * a)596 static bool trans_l_muld(DisasContext *dc, arg_ab *a)
597 {
598 gen_muld(dc, cpu_R(dc, a->a), cpu_R(dc, a->b));
599 return true;
600 }
601
trans_l_muldu(DisasContext * dc,arg_ab * a)602 static bool trans_l_muldu(DisasContext *dc, arg_ab *a)
603 {
604 gen_muldu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b));
605 return true;
606 }
607
trans_l_j(DisasContext * dc,arg_l_j * a)608 static bool trans_l_j(DisasContext *dc, arg_l_j *a)
609 {
610 target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
611
612 tcg_gen_movi_tl(jmp_pc, tmp_pc);
613 dc->jmp_pc_imm = tmp_pc;
614 dc->delayed_branch = 2;
615 return true;
616 }
617
trans_l_jal(DisasContext * dc,arg_l_jal * a)618 static bool trans_l_jal(DisasContext *dc, arg_l_jal *a)
619 {
620 target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
621 target_ulong ret_pc = dc->base.pc_next + 8;
622
623 tcg_gen_movi_tl(cpu_regs[9], ret_pc);
624 /* Optimize jal being used to load the PC for PIC. */
625 if (tmp_pc != ret_pc) {
626 tcg_gen_movi_tl(jmp_pc, tmp_pc);
627 dc->jmp_pc_imm = tmp_pc;
628 dc->delayed_branch = 2;
629 }
630 return true;
631 }
632
do_bf(DisasContext * dc,arg_l_bf * a,TCGCond cond)633 static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond)
634 {
635 target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
636 TCGv t_next = tcg_const_tl(dc->base.pc_next + 8);
637 TCGv t_true = tcg_const_tl(tmp_pc);
638 TCGv t_zero = tcg_const_tl(0);
639
640 tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next);
641
642 tcg_temp_free(t_next);
643 tcg_temp_free(t_true);
644 tcg_temp_free(t_zero);
645 dc->delayed_branch = 2;
646 }
647
trans_l_bf(DisasContext * dc,arg_l_bf * a)648 static bool trans_l_bf(DisasContext *dc, arg_l_bf *a)
649 {
650 do_bf(dc, a, TCG_COND_NE);
651 return true;
652 }
653
trans_l_bnf(DisasContext * dc,arg_l_bf * a)654 static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a)
655 {
656 do_bf(dc, a, TCG_COND_EQ);
657 return true;
658 }
659
trans_l_jr(DisasContext * dc,arg_l_jr * a)660 static bool trans_l_jr(DisasContext *dc, arg_l_jr *a)
661 {
662 tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b));
663 dc->delayed_branch = 2;
664 return true;
665 }
666
trans_l_jalr(DisasContext * dc,arg_l_jalr * a)667 static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a)
668 {
669 tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b));
670 tcg_gen_movi_tl(cpu_regs[9], dc->base.pc_next + 8);
671 dc->delayed_branch = 2;
672 return true;
673 }
674
trans_l_lwa(DisasContext * dc,arg_load * a)675 static bool trans_l_lwa(DisasContext *dc, arg_load *a)
676 {
677 TCGv ea;
678
679 check_r0_write(dc, a->d);
680 ea = tcg_temp_new();
681 tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i);
682 tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL);
683 tcg_gen_mov_tl(cpu_lock_addr, ea);
684 tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d));
685 tcg_temp_free(ea);
686 return true;
687 }
688
do_load(DisasContext * dc,arg_load * a,MemOp mop)689 static void do_load(DisasContext *dc, arg_load *a, MemOp mop)
690 {
691 TCGv ea;
692
693 check_r0_write(dc, a->d);
694 ea = tcg_temp_new();
695 tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i);
696 tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop);
697 tcg_temp_free(ea);
698 }
699
trans_l_lwz(DisasContext * dc,arg_load * a)700 static bool trans_l_lwz(DisasContext *dc, arg_load *a)
701 {
702 do_load(dc, a, MO_TEUL);
703 return true;
704 }
705
trans_l_lws(DisasContext * dc,arg_load * a)706 static bool trans_l_lws(DisasContext *dc, arg_load *a)
707 {
708 do_load(dc, a, MO_TESL);
709 return true;
710 }
711
trans_l_lbz(DisasContext * dc,arg_load * a)712 static bool trans_l_lbz(DisasContext *dc, arg_load *a)
713 {
714 do_load(dc, a, MO_UB);
715 return true;
716 }
717
trans_l_lbs(DisasContext * dc,arg_load * a)718 static bool trans_l_lbs(DisasContext *dc, arg_load *a)
719 {
720 do_load(dc, a, MO_SB);
721 return true;
722 }
723
trans_l_lhz(DisasContext * dc,arg_load * a)724 static bool trans_l_lhz(DisasContext *dc, arg_load *a)
725 {
726 do_load(dc, a, MO_TEUW);
727 return true;
728 }
729
trans_l_lhs(DisasContext * dc,arg_load * a)730 static bool trans_l_lhs(DisasContext *dc, arg_load *a)
731 {
732 do_load(dc, a, MO_TESW);
733 return true;
734 }
735
trans_l_swa(DisasContext * dc,arg_store * a)736 static bool trans_l_swa(DisasContext *dc, arg_store *a)
737 {
738 TCGv ea, val;
739 TCGLabel *lab_fail, *lab_done;
740
741 ea = tcg_temp_new();
742 tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i);
743
744 /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned
745 to cpu_regs[0]. Since l.swa is quite often immediately followed by a
746 branch, don't bother reallocating; finish the TB using the "real" R0.
747 This also takes care of RB input across the branch. */
748 dc->R0 = cpu_regs[0];
749
750 lab_fail = gen_new_label();
751 lab_done = gen_new_label();
752 tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail);
753 tcg_temp_free(ea);
754
755 val = tcg_temp_new();
756 tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value,
757 cpu_regs[a->b], dc->mem_idx, MO_TEUL);
758 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value);
759 tcg_temp_free(val);
760
761 tcg_gen_br(lab_done);
762
763 gen_set_label(lab_fail);
764 tcg_gen_movi_tl(cpu_sr_f, 0);
765
766 gen_set_label(lab_done);
767 tcg_gen_movi_tl(cpu_lock_addr, -1);
768 return true;
769 }
770
do_store(DisasContext * dc,arg_store * a,MemOp mop)771 static void do_store(DisasContext *dc, arg_store *a, MemOp mop)
772 {
773 TCGv t0 = tcg_temp_new();
774 tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i);
775 tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop);
776 tcg_temp_free(t0);
777 }
778
trans_l_sw(DisasContext * dc,arg_store * a)779 static bool trans_l_sw(DisasContext *dc, arg_store *a)
780 {
781 do_store(dc, a, MO_TEUL);
782 return true;
783 }
784
trans_l_sb(DisasContext * dc,arg_store * a)785 static bool trans_l_sb(DisasContext *dc, arg_store *a)
786 {
787 do_store(dc, a, MO_UB);
788 return true;
789 }
790
trans_l_sh(DisasContext * dc,arg_store * a)791 static bool trans_l_sh(DisasContext *dc, arg_store *a)
792 {
793 do_store(dc, a, MO_TEUW);
794 return true;
795 }
796
trans_l_nop(DisasContext * dc,arg_l_nop * a)797 static bool trans_l_nop(DisasContext *dc, arg_l_nop *a)
798 {
799 return true;
800 }
801
trans_l_adrp(DisasContext * dc,arg_l_adrp * a)802 static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a)
803 {
804 if (!check_v1_3(dc)) {
805 return false;
806 }
807 check_r0_write(dc, a->d);
808
809 tcg_gen_movi_i32(cpu_R(dc, a->d),
810 (dc->base.pc_next & TARGET_PAGE_MASK) +
811 ((target_long)a->i << TARGET_PAGE_BITS));
812 return true;
813 }
814
trans_l_addi(DisasContext * dc,arg_rri * a)815 static bool trans_l_addi(DisasContext *dc, arg_rri *a)
816 {
817 TCGv t0;
818
819 check_r0_write(dc, a->d);
820 t0 = tcg_const_tl(a->i);
821 gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0);
822 tcg_temp_free(t0);
823 return true;
824 }
825
trans_l_addic(DisasContext * dc,arg_rri * a)826 static bool trans_l_addic(DisasContext *dc, arg_rri *a)
827 {
828 TCGv t0;
829
830 check_r0_write(dc, a->d);
831 t0 = tcg_const_tl(a->i);
832 gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0);
833 tcg_temp_free(t0);
834 return true;
835 }
836
trans_l_muli(DisasContext * dc,arg_rri * a)837 static bool trans_l_muli(DisasContext *dc, arg_rri *a)
838 {
839 TCGv t0;
840
841 check_r0_write(dc, a->d);
842 t0 = tcg_const_tl(a->i);
843 gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0);
844 tcg_temp_free(t0);
845 return true;
846 }
847
trans_l_maci(DisasContext * dc,arg_l_maci * a)848 static bool trans_l_maci(DisasContext *dc, arg_l_maci *a)
849 {
850 TCGv t0;
851
852 t0 = tcg_const_tl(a->i);
853 gen_mac(dc, cpu_R(dc, a->a), t0);
854 tcg_temp_free(t0);
855 return true;
856 }
857
trans_l_andi(DisasContext * dc,arg_rrk * a)858 static bool trans_l_andi(DisasContext *dc, arg_rrk *a)
859 {
860 check_r0_write(dc, a->d);
861 tcg_gen_andi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k);
862 return true;
863 }
864
trans_l_ori(DisasContext * dc,arg_rrk * a)865 static bool trans_l_ori(DisasContext *dc, arg_rrk *a)
866 {
867 check_r0_write(dc, a->d);
868 tcg_gen_ori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k);
869 return true;
870 }
871
trans_l_xori(DisasContext * dc,arg_rri * a)872 static bool trans_l_xori(DisasContext *dc, arg_rri *a)
873 {
874 check_r0_write(dc, a->d);
875 tcg_gen_xori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->i);
876 return true;
877 }
878
trans_l_mfspr(DisasContext * dc,arg_l_mfspr * a)879 static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a)
880 {
881 check_r0_write(dc, a->d);
882
883 if (is_user(dc)) {
884 gen_illegal_exception(dc);
885 } else {
886 TCGv spr = tcg_temp_new();
887
888 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
889 gen_io_start();
890 if (dc->delayed_branch) {
891 tcg_gen_mov_tl(cpu_pc, jmp_pc);
892 tcg_gen_discard_tl(jmp_pc);
893 } else {
894 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
895 }
896 dc->base.is_jmp = DISAS_EXIT;
897 }
898
899 tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
900 gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr);
901 tcg_temp_free(spr);
902 }
903 return true;
904 }
905
trans_l_mtspr(DisasContext * dc,arg_l_mtspr * a)906 static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
907 {
908 if (is_user(dc)) {
909 gen_illegal_exception(dc);
910 } else {
911 TCGv spr;
912
913 if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
914 gen_io_start();
915 }
916 /* For SR, we will need to exit the TB to recognize the new
917 * exception state. For NPC, in theory this counts as a branch
918 * (although the SPR only exists for use by an ICE). Save all
919 * of the cpu state first, allowing it to be overwritten.
920 */
921 if (dc->delayed_branch) {
922 tcg_gen_mov_tl(cpu_pc, jmp_pc);
923 tcg_gen_discard_tl(jmp_pc);
924 } else {
925 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
926 }
927 dc->base.is_jmp = DISAS_EXIT;
928
929 spr = tcg_temp_new();
930 tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
931 gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b));
932 tcg_temp_free(spr);
933 }
934 return true;
935 }
936
trans_l_mac(DisasContext * dc,arg_ab * a)937 static bool trans_l_mac(DisasContext *dc, arg_ab *a)
938 {
939 gen_mac(dc, cpu_R(dc, a->a), cpu_R(dc, a->b));
940 return true;
941 }
942
trans_l_msb(DisasContext * dc,arg_ab * a)943 static bool trans_l_msb(DisasContext *dc, arg_ab *a)
944 {
945 gen_msb(dc, cpu_R(dc, a->a), cpu_R(dc, a->b));
946 return true;
947 }
948
trans_l_macu(DisasContext * dc,arg_ab * a)949 static bool trans_l_macu(DisasContext *dc, arg_ab *a)
950 {
951 gen_macu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b));
952 return true;
953 }
954
trans_l_msbu(DisasContext * dc,arg_ab * a)955 static bool trans_l_msbu(DisasContext *dc, arg_ab *a)
956 {
957 gen_msbu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b));
958 return true;
959 }
960
trans_l_slli(DisasContext * dc,arg_dal * a)961 static bool trans_l_slli(DisasContext *dc, arg_dal *a)
962 {
963 check_r0_write(dc, a->d);
964 tcg_gen_shli_tl(cpu_R(dc, a->d), cpu_R(dc, a->a),
965 a->l & (TARGET_LONG_BITS - 1));
966 return true;
967 }
968
trans_l_srli(DisasContext * dc,arg_dal * a)969 static bool trans_l_srli(DisasContext *dc, arg_dal *a)
970 {
971 check_r0_write(dc, a->d);
972 tcg_gen_shri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a),
973 a->l & (TARGET_LONG_BITS - 1));
974 return true;
975 }
976
trans_l_srai(DisasContext * dc,arg_dal * a)977 static bool trans_l_srai(DisasContext *dc, arg_dal *a)
978 {
979 check_r0_write(dc, a->d);
980 tcg_gen_sari_tl(cpu_R(dc, a->d), cpu_R(dc, a->a),
981 a->l & (TARGET_LONG_BITS - 1));
982 return true;
983 }
984
trans_l_rori(DisasContext * dc,arg_dal * a)985 static bool trans_l_rori(DisasContext *dc, arg_dal *a)
986 {
987 check_r0_write(dc, a->d);
988 tcg_gen_rotri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a),
989 a->l & (TARGET_LONG_BITS - 1));
990 return true;
991 }
992
trans_l_movhi(DisasContext * dc,arg_l_movhi * a)993 static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a)
994 {
995 check_r0_write(dc, a->d);
996 tcg_gen_movi_tl(cpu_R(dc, a->d), a->k << 16);
997 return true;
998 }
999
trans_l_macrc(DisasContext * dc,arg_l_macrc * a)1000 static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a)
1001 {
1002 check_r0_write(dc, a->d);
1003 tcg_gen_trunc_i64_tl(cpu_R(dc, a->d), cpu_mac);
1004 tcg_gen_movi_i64(cpu_mac, 0);
1005 return true;
1006 }
1007
trans_l_sfeq(DisasContext * dc,arg_ab * a)1008 static bool trans_l_sfeq(DisasContext *dc, arg_ab *a)
1009 {
1010 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f,
1011 cpu_R(dc, a->a), cpu_R(dc, a->b));
1012 return true;
1013 }
1014
trans_l_sfne(DisasContext * dc,arg_ab * a)1015 static bool trans_l_sfne(DisasContext *dc, arg_ab *a)
1016 {
1017 tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f,
1018 cpu_R(dc, a->a), cpu_R(dc, a->b));
1019 return true;
1020 }
1021
trans_l_sfgtu(DisasContext * dc,arg_ab * a)1022 static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a)
1023 {
1024 tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f,
1025 cpu_R(dc, a->a), cpu_R(dc, a->b));
1026 return true;
1027 }
1028
trans_l_sfgeu(DisasContext * dc,arg_ab * a)1029 static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a)
1030 {
1031 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f,
1032 cpu_R(dc, a->a), cpu_R(dc, a->b));
1033 return true;
1034 }
1035
trans_l_sfltu(DisasContext * dc,arg_ab * a)1036 static bool trans_l_sfltu(DisasContext *dc, arg_ab *a)
1037 {
1038 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f,
1039 cpu_R(dc, a->a), cpu_R(dc, a->b));
1040 return true;
1041 }
1042
trans_l_sfleu(DisasContext * dc,arg_ab * a)1043 static bool trans_l_sfleu(DisasContext *dc, arg_ab *a)
1044 {
1045 tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f,
1046 cpu_R(dc, a->a), cpu_R(dc, a->b));
1047 return true;
1048 }
1049
trans_l_sfgts(DisasContext * dc,arg_ab * a)1050 static bool trans_l_sfgts(DisasContext *dc, arg_ab *a)
1051 {
1052 tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f,
1053 cpu_R(dc, a->a), cpu_R(dc, a->b));
1054 return true;
1055 }
1056
trans_l_sfges(DisasContext * dc,arg_ab * a)1057 static bool trans_l_sfges(DisasContext *dc, arg_ab *a)
1058 {
1059 tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f,
1060 cpu_R(dc, a->a), cpu_R(dc, a->b));
1061 return true;
1062 }
1063
trans_l_sflts(DisasContext * dc,arg_ab * a)1064 static bool trans_l_sflts(DisasContext *dc, arg_ab *a)
1065 {
1066 tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f,
1067 cpu_R(dc, a->a), cpu_R(dc, a->b));
1068 return true;
1069 }
1070
trans_l_sfles(DisasContext * dc,arg_ab * a)1071 static bool trans_l_sfles(DisasContext *dc, arg_ab *a)
1072 {
1073 tcg_gen_setcond_tl(TCG_COND_LE,
1074 cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b));
1075 return true;
1076 }
1077
trans_l_sfeqi(DisasContext * dc,arg_ai * a)1078 static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a)
1079 {
1080 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), a->i);
1081 return true;
1082 }
1083
trans_l_sfnei(DisasContext * dc,arg_ai * a)1084 static bool trans_l_sfnei(DisasContext *dc, arg_ai *a)
1085 {
1086 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R(dc, a->a), a->i);
1087 return true;
1088 }
1089
trans_l_sfgtui(DisasContext * dc,arg_ai * a)1090 static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a)
1091 {
1092 tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), a->i);
1093 return true;
1094 }
1095
trans_l_sfgeui(DisasContext * dc,arg_ai * a)1096 static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a)
1097 {
1098 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), a->i);
1099 return true;
1100 }
1101
trans_l_sfltui(DisasContext * dc,arg_ai * a)1102 static bool trans_l_sfltui(DisasContext *dc, arg_ai *a)
1103 {
1104 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i);
1105 return true;
1106 }
1107
trans_l_sfleui(DisasContext * dc,arg_ai * a)1108 static bool trans_l_sfleui(DisasContext *dc, arg_ai *a)
1109 {
1110 tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R(dc, a->a), a->i);
1111 return true;
1112 }
1113
trans_l_sfgtsi(DisasContext * dc,arg_ai * a)1114 static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a)
1115 {
1116 tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), a->i);
1117 return true;
1118 }
1119
trans_l_sfgesi(DisasContext * dc,arg_ai * a)1120 static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a)
1121 {
1122 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), a->i);
1123 return true;
1124 }
1125
trans_l_sfltsi(DisasContext * dc,arg_ai * a)1126 static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a)
1127 {
1128 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R(dc, a->a), a->i);
1129 return true;
1130 }
1131
trans_l_sflesi(DisasContext * dc,arg_ai * a)1132 static bool trans_l_sflesi(DisasContext *dc, arg_ai *a)
1133 {
1134 tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R(dc, a->a), a->i);
1135 return true;
1136 }
1137
trans_l_sys(DisasContext * dc,arg_l_sys * a)1138 static bool trans_l_sys(DisasContext *dc, arg_l_sys *a)
1139 {
1140 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
1141 gen_exception(dc, EXCP_SYSCALL);
1142 dc->base.is_jmp = DISAS_NORETURN;
1143 return true;
1144 }
1145
trans_l_trap(DisasContext * dc,arg_l_trap * a)1146 static bool trans_l_trap(DisasContext *dc, arg_l_trap *a)
1147 {
1148 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
1149 gen_exception(dc, EXCP_TRAP);
1150 dc->base.is_jmp = DISAS_NORETURN;
1151 return true;
1152 }
1153
trans_l_msync(DisasContext * dc,arg_l_msync * a)1154 static bool trans_l_msync(DisasContext *dc, arg_l_msync *a)
1155 {
1156 tcg_gen_mb(TCG_MO_ALL);
1157 return true;
1158 }
1159
trans_l_psync(DisasContext * dc,arg_l_psync * a)1160 static bool trans_l_psync(DisasContext *dc, arg_l_psync *a)
1161 {
1162 return true;
1163 }
1164
trans_l_csync(DisasContext * dc,arg_l_csync * a)1165 static bool trans_l_csync(DisasContext *dc, arg_l_csync *a)
1166 {
1167 return true;
1168 }
1169
trans_l_rfe(DisasContext * dc,arg_l_rfe * a)1170 static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a)
1171 {
1172 if (is_user(dc)) {
1173 gen_illegal_exception(dc);
1174 } else {
1175 gen_helper_rfe(cpu_env);
1176 dc->base.is_jmp = DISAS_EXIT;
1177 }
1178 return true;
1179 }
1180
do_fp2(DisasContext * dc,arg_da * a,void (* fn)(TCGv,TCGv_env,TCGv))1181 static bool do_fp2(DisasContext *dc, arg_da *a,
1182 void (*fn)(TCGv, TCGv_env, TCGv))
1183 {
1184 if (!check_of32s(dc)) {
1185 return false;
1186 }
1187 check_r0_write(dc, a->d);
1188 fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a));
1189 gen_helper_update_fpcsr(cpu_env);
1190 return true;
1191 }
1192
do_fp3(DisasContext * dc,arg_dab * a,void (* fn)(TCGv,TCGv_env,TCGv,TCGv))1193 static bool do_fp3(DisasContext *dc, arg_dab *a,
1194 void (*fn)(TCGv, TCGv_env, TCGv, TCGv))
1195 {
1196 if (!check_of32s(dc)) {
1197 return false;
1198 }
1199 check_r0_write(dc, a->d);
1200 fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
1201 gen_helper_update_fpcsr(cpu_env);
1202 return true;
1203 }
1204
do_fpcmp(DisasContext * dc,arg_ab * a,void (* fn)(TCGv,TCGv_env,TCGv,TCGv),bool inv,bool swap)1205 static bool do_fpcmp(DisasContext *dc, arg_ab *a,
1206 void (*fn)(TCGv, TCGv_env, TCGv, TCGv),
1207 bool inv, bool swap)
1208 {
1209 if (!check_of32s(dc)) {
1210 return false;
1211 }
1212 if (swap) {
1213 fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a));
1214 } else {
1215 fn(cpu_sr_f, cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
1216 }
1217 if (inv) {
1218 tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
1219 }
1220 gen_helper_update_fpcsr(cpu_env);
1221 return true;
1222 }
1223
trans_lf_add_s(DisasContext * dc,arg_dab * a)1224 static bool trans_lf_add_s(DisasContext *dc, arg_dab *a)
1225 {
1226 return do_fp3(dc, a, gen_helper_float_add_s);
1227 }
1228
trans_lf_sub_s(DisasContext * dc,arg_dab * a)1229 static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a)
1230 {
1231 return do_fp3(dc, a, gen_helper_float_sub_s);
1232 }
1233
trans_lf_mul_s(DisasContext * dc,arg_dab * a)1234 static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a)
1235 {
1236 return do_fp3(dc, a, gen_helper_float_mul_s);
1237 }
1238
trans_lf_div_s(DisasContext * dc,arg_dab * a)1239 static bool trans_lf_div_s(DisasContext *dc, arg_dab *a)
1240 {
1241 return do_fp3(dc, a, gen_helper_float_div_s);
1242 }
1243
trans_lf_rem_s(DisasContext * dc,arg_dab * a)1244 static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a)
1245 {
1246 return do_fp3(dc, a, gen_helper_float_rem_s);
1247 return true;
1248 }
1249
trans_lf_itof_s(DisasContext * dc,arg_da * a)1250 static bool trans_lf_itof_s(DisasContext *dc, arg_da *a)
1251 {
1252 return do_fp2(dc, a, gen_helper_itofs);
1253 }
1254
trans_lf_ftoi_s(DisasContext * dc,arg_da * a)1255 static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a)
1256 {
1257 return do_fp2(dc, a, gen_helper_ftois);
1258 }
1259
trans_lf_madd_s(DisasContext * dc,arg_dab * a)1260 static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a)
1261 {
1262 if (!check_of32s(dc)) {
1263 return false;
1264 }
1265 check_r0_write(dc, a->d);
1266 gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d),
1267 cpu_R(dc, a->a), cpu_R(dc, a->b));
1268 gen_helper_update_fpcsr(cpu_env);
1269 return true;
1270 }
1271
trans_lf_sfeq_s(DisasContext * dc,arg_ab * a)1272 static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a)
1273 {
1274 return do_fpcmp(dc, a, gen_helper_float_eq_s, false, false);
1275 }
1276
trans_lf_sfne_s(DisasContext * dc,arg_ab * a)1277 static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a)
1278 {
1279 return do_fpcmp(dc, a, gen_helper_float_eq_s, true, false);
1280 }
1281
trans_lf_sfgt_s(DisasContext * dc,arg_ab * a)1282 static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a)
1283 {
1284 return do_fpcmp(dc, a, gen_helper_float_lt_s, false, true);
1285 }
1286
trans_lf_sfge_s(DisasContext * dc,arg_ab * a)1287 static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a)
1288 {
1289 return do_fpcmp(dc, a, gen_helper_float_le_s, false, true);
1290 }
1291
trans_lf_sflt_s(DisasContext * dc,arg_ab * a)1292 static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a)
1293 {
1294 return do_fpcmp(dc, a, gen_helper_float_lt_s, false, false);
1295 }
1296
trans_lf_sfle_s(DisasContext * dc,arg_ab * a)1297 static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a)
1298 {
1299 return do_fpcmp(dc, a, gen_helper_float_le_s, false, false);
1300 }
1301
trans_lf_sfueq_s(DisasContext * dc,arg_ab * a)1302 static bool trans_lf_sfueq_s(DisasContext *dc, arg_ab *a)
1303 {
1304 if (!check_v1_3(dc)) {
1305 return false;
1306 }
1307 return do_fpcmp(dc, a, gen_helper_float_ueq_s, false, false);
1308 }
1309
trans_lf_sfult_s(DisasContext * dc,arg_ab * a)1310 static bool trans_lf_sfult_s(DisasContext *dc, arg_ab *a)
1311 {
1312 if (!check_v1_3(dc)) {
1313 return false;
1314 }
1315 return do_fpcmp(dc, a, gen_helper_float_ult_s, false, false);
1316 }
1317
trans_lf_sfugt_s(DisasContext * dc,arg_ab * a)1318 static bool trans_lf_sfugt_s(DisasContext *dc, arg_ab *a)
1319 {
1320 if (!check_v1_3(dc)) {
1321 return false;
1322 }
1323 return do_fpcmp(dc, a, gen_helper_float_ult_s, false, true);
1324 }
1325
trans_lf_sfule_s(DisasContext * dc,arg_ab * a)1326 static bool trans_lf_sfule_s(DisasContext *dc, arg_ab *a)
1327 {
1328 if (!check_v1_3(dc)) {
1329 return false;
1330 }
1331 return do_fpcmp(dc, a, gen_helper_float_ule_s, false, false);
1332 }
1333
trans_lf_sfuge_s(DisasContext * dc,arg_ab * a)1334 static bool trans_lf_sfuge_s(DisasContext *dc, arg_ab *a)
1335 {
1336 if (!check_v1_3(dc)) {
1337 return false;
1338 }
1339 return do_fpcmp(dc, a, gen_helper_float_ule_s, false, true);
1340 }
1341
trans_lf_sfun_s(DisasContext * dc,arg_ab * a)1342 static bool trans_lf_sfun_s(DisasContext *dc, arg_ab *a)
1343 {
1344 if (!check_v1_3(dc)) {
1345 return false;
1346 }
1347 return do_fpcmp(dc, a, gen_helper_float_un_s, false, false);
1348 }
1349
check_pair(DisasContext * dc,int r,int p)1350 static bool check_pair(DisasContext *dc, int r, int p)
1351 {
1352 return r + 1 + p < 32;
1353 }
1354
load_pair(DisasContext * dc,TCGv_i64 t,int r,int p)1355 static void load_pair(DisasContext *dc, TCGv_i64 t, int r, int p)
1356 {
1357 tcg_gen_concat_i32_i64(t, cpu_R(dc, r + 1 + p), cpu_R(dc, r));
1358 }
1359
save_pair(DisasContext * dc,TCGv_i64 t,int r,int p)1360 static void save_pair(DisasContext *dc, TCGv_i64 t, int r, int p)
1361 {
1362 tcg_gen_extr_i64_i32(cpu_R(dc, r + 1 + p), cpu_R(dc, r), t);
1363 }
1364
do_dp3(DisasContext * dc,arg_dab_pair * a,void (* fn)(TCGv_i64,TCGv_env,TCGv_i64,TCGv_i64))1365 static bool do_dp3(DisasContext *dc, arg_dab_pair *a,
1366 void (*fn)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64))
1367 {
1368 TCGv_i64 t0, t1;
1369
1370 if (!check_of64a32s(dc) ||
1371 !check_pair(dc, a->a, a->ap) ||
1372 !check_pair(dc, a->b, a->bp) ||
1373 !check_pair(dc, a->d, a->dp)) {
1374 return false;
1375 }
1376 check_r0_write(dc, a->d);
1377
1378 t0 = tcg_temp_new_i64();
1379 t1 = tcg_temp_new_i64();
1380 load_pair(dc, t0, a->a, a->ap);
1381 load_pair(dc, t1, a->b, a->bp);
1382 fn(t0, cpu_env, t0, t1);
1383 save_pair(dc, t0, a->d, a->dp);
1384 tcg_temp_free_i64(t0);
1385 tcg_temp_free_i64(t1);
1386
1387 gen_helper_update_fpcsr(cpu_env);
1388 return true;
1389 }
1390
do_dp2(DisasContext * dc,arg_da_pair * a,void (* fn)(TCGv_i64,TCGv_env,TCGv_i64))1391 static bool do_dp2(DisasContext *dc, arg_da_pair *a,
1392 void (*fn)(TCGv_i64, TCGv_env, TCGv_i64))
1393 {
1394 TCGv_i64 t0;
1395
1396 if (!check_of64a32s(dc) ||
1397 !check_pair(dc, a->a, a->ap) ||
1398 !check_pair(dc, a->d, a->dp)) {
1399 return false;
1400 }
1401 check_r0_write(dc, a->d);
1402
1403 t0 = tcg_temp_new_i64();
1404 load_pair(dc, t0, a->a, a->ap);
1405 fn(t0, cpu_env, t0);
1406 save_pair(dc, t0, a->d, a->dp);
1407 tcg_temp_free_i64(t0);
1408
1409 gen_helper_update_fpcsr(cpu_env);
1410 return true;
1411 }
1412
do_dpcmp(DisasContext * dc,arg_ab_pair * a,void (* fn)(TCGv,TCGv_env,TCGv_i64,TCGv_i64),bool inv,bool swap)1413 static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a,
1414 void (*fn)(TCGv, TCGv_env, TCGv_i64, TCGv_i64),
1415 bool inv, bool swap)
1416 {
1417 TCGv_i64 t0, t1;
1418
1419 if (!check_of64a32s(dc) ||
1420 !check_pair(dc, a->a, a->ap) ||
1421 !check_pair(dc, a->b, a->bp)) {
1422 return false;
1423 }
1424
1425 t0 = tcg_temp_new_i64();
1426 t1 = tcg_temp_new_i64();
1427 load_pair(dc, t0, a->a, a->ap);
1428 load_pair(dc, t1, a->b, a->bp);
1429 if (swap) {
1430 fn(cpu_sr_f, cpu_env, t1, t0);
1431 } else {
1432 fn(cpu_sr_f, cpu_env, t0, t1);
1433 }
1434 tcg_temp_free_i64(t0);
1435 tcg_temp_free_i64(t1);
1436
1437 if (inv) {
1438 tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
1439 }
1440 gen_helper_update_fpcsr(cpu_env);
1441 return true;
1442 }
1443
trans_lf_add_d(DisasContext * dc,arg_dab_pair * a)1444 static bool trans_lf_add_d(DisasContext *dc, arg_dab_pair *a)
1445 {
1446 return do_dp3(dc, a, gen_helper_float_add_d);
1447 }
1448
trans_lf_sub_d(DisasContext * dc,arg_dab_pair * a)1449 static bool trans_lf_sub_d(DisasContext *dc, arg_dab_pair *a)
1450 {
1451 return do_dp3(dc, a, gen_helper_float_sub_d);
1452 }
1453
trans_lf_mul_d(DisasContext * dc,arg_dab_pair * a)1454 static bool trans_lf_mul_d(DisasContext *dc, arg_dab_pair *a)
1455 {
1456 return do_dp3(dc, a, gen_helper_float_mul_d);
1457 }
1458
trans_lf_div_d(DisasContext * dc,arg_dab_pair * a)1459 static bool trans_lf_div_d(DisasContext *dc, arg_dab_pair *a)
1460 {
1461 return do_dp3(dc, a, gen_helper_float_div_d);
1462 }
1463
trans_lf_rem_d(DisasContext * dc,arg_dab_pair * a)1464 static bool trans_lf_rem_d(DisasContext *dc, arg_dab_pair *a)
1465 {
1466 return do_dp3(dc, a, gen_helper_float_rem_d);
1467 }
1468
trans_lf_itof_d(DisasContext * dc,arg_da_pair * a)1469 static bool trans_lf_itof_d(DisasContext *dc, arg_da_pair *a)
1470 {
1471 return do_dp2(dc, a, gen_helper_itofd);
1472 }
1473
trans_lf_ftoi_d(DisasContext * dc,arg_da_pair * a)1474 static bool trans_lf_ftoi_d(DisasContext *dc, arg_da_pair *a)
1475 {
1476 return do_dp2(dc, a, gen_helper_ftoid);
1477 }
1478
trans_lf_stod_d(DisasContext * dc,arg_lf_stod_d * a)1479 static bool trans_lf_stod_d(DisasContext *dc, arg_lf_stod_d *a)
1480 {
1481 TCGv_i64 t0;
1482
1483 if (!check_of64a32s(dc) ||
1484 !check_pair(dc, a->d, a->dp)) {
1485 return false;
1486 }
1487 check_r0_write(dc, a->d);
1488
1489 t0 = tcg_temp_new_i64();
1490 gen_helper_stod(t0, cpu_env, cpu_R(dc, a->a));
1491 save_pair(dc, t0, a->d, a->dp);
1492 tcg_temp_free_i64(t0);
1493
1494 gen_helper_update_fpcsr(cpu_env);
1495 return true;
1496 }
1497
trans_lf_dtos_d(DisasContext * dc,arg_lf_dtos_d * a)1498 static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_dtos_d *a)
1499 {
1500 TCGv_i64 t0;
1501
1502 if (!check_of64a32s(dc) ||
1503 !check_pair(dc, a->a, a->ap)) {
1504 return false;
1505 }
1506 check_r0_write(dc, a->d);
1507
1508 t0 = tcg_temp_new_i64();
1509 load_pair(dc, t0, a->a, a->ap);
1510 gen_helper_dtos(cpu_R(dc, a->d), cpu_env, t0);
1511 tcg_temp_free_i64(t0);
1512
1513 gen_helper_update_fpcsr(cpu_env);
1514 return true;
1515 }
1516
trans_lf_madd_d(DisasContext * dc,arg_dab_pair * a)1517 static bool trans_lf_madd_d(DisasContext *dc, arg_dab_pair *a)
1518 {
1519 TCGv_i64 t0, t1, t2;
1520
1521 if (!check_of64a32s(dc) ||
1522 !check_pair(dc, a->a, a->ap) ||
1523 !check_pair(dc, a->b, a->bp) ||
1524 !check_pair(dc, a->d, a->dp)) {
1525 return false;
1526 }
1527 check_r0_write(dc, a->d);
1528
1529 t0 = tcg_temp_new_i64();
1530 t1 = tcg_temp_new_i64();
1531 t2 = tcg_temp_new_i64();
1532 load_pair(dc, t0, a->d, a->dp);
1533 load_pair(dc, t1, a->a, a->ap);
1534 load_pair(dc, t2, a->b, a->bp);
1535 gen_helper_float_madd_d(t0, cpu_env, t0, t1, t2);
1536 save_pair(dc, t0, a->d, a->dp);
1537 tcg_temp_free_i64(t0);
1538 tcg_temp_free_i64(t1);
1539 tcg_temp_free_i64(t2);
1540
1541 gen_helper_update_fpcsr(cpu_env);
1542 return true;
1543 }
1544
trans_lf_sfeq_d(DisasContext * dc,arg_ab_pair * a)1545 static bool trans_lf_sfeq_d(DisasContext *dc, arg_ab_pair *a)
1546 {
1547 return do_dpcmp(dc, a, gen_helper_float_eq_d, false, false);
1548 }
1549
trans_lf_sfne_d(DisasContext * dc,arg_ab_pair * a)1550 static bool trans_lf_sfne_d(DisasContext *dc, arg_ab_pair *a)
1551 {
1552 return do_dpcmp(dc, a, gen_helper_float_eq_d, true, false);
1553 }
1554
trans_lf_sfgt_d(DisasContext * dc,arg_ab_pair * a)1555 static bool trans_lf_sfgt_d(DisasContext *dc, arg_ab_pair *a)
1556 {
1557 return do_dpcmp(dc, a, gen_helper_float_lt_d, false, true);
1558 }
1559
trans_lf_sfge_d(DisasContext * dc,arg_ab_pair * a)1560 static bool trans_lf_sfge_d(DisasContext *dc, arg_ab_pair *a)
1561 {
1562 return do_dpcmp(dc, a, gen_helper_float_le_d, false, true);
1563 }
1564
trans_lf_sflt_d(DisasContext * dc,arg_ab_pair * a)1565 static bool trans_lf_sflt_d(DisasContext *dc, arg_ab_pair *a)
1566 {
1567 return do_dpcmp(dc, a, gen_helper_float_lt_d, false, false);
1568 }
1569
trans_lf_sfle_d(DisasContext * dc,arg_ab_pair * a)1570 static bool trans_lf_sfle_d(DisasContext *dc, arg_ab_pair *a)
1571 {
1572 return do_dpcmp(dc, a, gen_helper_float_le_d, false, false);
1573 }
1574
trans_lf_sfueq_d(DisasContext * dc,arg_ab_pair * a)1575 static bool trans_lf_sfueq_d(DisasContext *dc, arg_ab_pair *a)
1576 {
1577 return do_dpcmp(dc, a, gen_helper_float_ueq_d, false, false);
1578 }
1579
trans_lf_sfule_d(DisasContext * dc,arg_ab_pair * a)1580 static bool trans_lf_sfule_d(DisasContext *dc, arg_ab_pair *a)
1581 {
1582 return do_dpcmp(dc, a, gen_helper_float_ule_d, false, false);
1583 }
1584
trans_lf_sfuge_d(DisasContext * dc,arg_ab_pair * a)1585 static bool trans_lf_sfuge_d(DisasContext *dc, arg_ab_pair *a)
1586 {
1587 return do_dpcmp(dc, a, gen_helper_float_ule_d, false, true);
1588 }
1589
trans_lf_sfult_d(DisasContext * dc,arg_ab_pair * a)1590 static bool trans_lf_sfult_d(DisasContext *dc, arg_ab_pair *a)
1591 {
1592 return do_dpcmp(dc, a, gen_helper_float_ult_d, false, false);
1593 }
1594
trans_lf_sfugt_d(DisasContext * dc,arg_ab_pair * a)1595 static bool trans_lf_sfugt_d(DisasContext *dc, arg_ab_pair *a)
1596 {
1597 return do_dpcmp(dc, a, gen_helper_float_ult_d, false, true);
1598 }
1599
trans_lf_sfun_d(DisasContext * dc,arg_ab_pair * a)1600 static bool trans_lf_sfun_d(DisasContext *dc, arg_ab_pair *a)
1601 {
1602 return do_dpcmp(dc, a, gen_helper_float_un_d, false, false);
1603 }
1604
openrisc_tr_init_disas_context(DisasContextBase * dcb,CPUState * cs)1605 static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
1606 {
1607 DisasContext *dc = container_of(dcb, DisasContext, base);
1608 CPUOpenRISCState *env = cs->env_ptr;
1609 int bound;
1610
1611 dc->mem_idx = cpu_mmu_index(env, false);
1612 dc->tb_flags = dc->base.tb->flags;
1613 dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
1614 dc->cpucfgr = env->cpucfgr;
1615 dc->avr = env->avr;
1616 dc->jmp_pc_imm = -1;
1617
1618 bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
1619 dc->base.max_insns = MIN(dc->base.max_insns, bound);
1620 }
1621
openrisc_tr_tb_start(DisasContextBase * db,CPUState * cs)1622 static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs)
1623 {
1624 DisasContext *dc = container_of(db, DisasContext, base);
1625
1626 /* Allow the TCG optimizer to see that R0 == 0,
1627 when it's true, which is the common case. */
1628 if (dc->tb_flags & TB_FLAGS_R0_0) {
1629 dc->R0 = tcg_const_tl(0);
1630 } else {
1631 dc->R0 = cpu_regs[0];
1632 }
1633 }
1634
openrisc_tr_insn_start(DisasContextBase * dcbase,CPUState * cs)1635 static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
1636 {
1637 DisasContext *dc = container_of(dcbase, DisasContext, base);
1638
1639 tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
1640 | (dc->base.num_insns > 1 ? 2 : 0));
1641 }
1642
openrisc_tr_breakpoint_check(DisasContextBase * dcbase,CPUState * cs,const CPUBreakpoint * bp)1643 static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
1644 const CPUBreakpoint *bp)
1645 {
1646 DisasContext *dc = container_of(dcbase, DisasContext, base);
1647
1648 tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
1649 gen_exception(dc, EXCP_DEBUG);
1650 dc->base.is_jmp = DISAS_NORETURN;
1651 /* The address covered by the breakpoint must be included in
1652 [tb->pc, tb->pc + tb->size) in order to for it to be
1653 properly cleared -- thus we increment the PC here so that
1654 the logic setting tb->size below does the right thing. */
1655 dc->base.pc_next += 4;
1656 return true;
1657 }
1658
openrisc_tr_translate_insn(DisasContextBase * dcbase,CPUState * cs)1659 static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
1660 {
1661 DisasContext *dc = container_of(dcbase, DisasContext, base);
1662 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
1663 uint32_t insn = translator_ldl(&cpu->env, dc->base.pc_next);
1664
1665 if (!decode(dc, insn)) {
1666 gen_illegal_exception(dc);
1667 }
1668 dc->base.pc_next += 4;
1669
1670 /* When exiting the delay slot normally, exit via jmp_pc.
1671 * For DISAS_NORETURN, we have raised an exception and already exited.
1672 * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing
1673 * in the manual saying this is illegal, but it surely it should.
1674 * At least or1ksim overrides pcnext and ignores the branch.
1675 */
1676 if (dc->delayed_branch
1677 && --dc->delayed_branch == 0
1678 && dc->base.is_jmp == DISAS_NEXT) {
1679 dc->base.is_jmp = DISAS_JUMP;
1680 }
1681 }
1682
openrisc_tr_tb_stop(DisasContextBase * dcbase,CPUState * cs)1683 static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
1684 {
1685 DisasContext *dc = container_of(dcbase, DisasContext, base);
1686 target_ulong jmp_dest;
1687
1688 /* If we have already exited the TB, nothing following has effect. */
1689 if (dc->base.is_jmp == DISAS_NORETURN) {
1690 return;
1691 }
1692
1693 /* Adjust the delayed branch state for the next TB. */
1694 if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
1695 tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
1696 }
1697
1698 /* For DISAS_TOO_MANY, jump to the next insn. */
1699 jmp_dest = dc->base.pc_next;
1700 tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4);
1701
1702 switch (dc->base.is_jmp) {
1703 case DISAS_JUMP:
1704 jmp_dest = dc->jmp_pc_imm;
1705 if (jmp_dest == -1) {
1706 /* The jump destination is indirect/computed; use jmp_pc. */
1707 tcg_gen_mov_tl(cpu_pc, jmp_pc);
1708 tcg_gen_discard_tl(jmp_pc);
1709 if (unlikely(dc->base.singlestep_enabled)) {
1710 gen_exception(dc, EXCP_DEBUG);
1711 } else {
1712 tcg_gen_lookup_and_goto_ptr();
1713 }
1714 break;
1715 }
1716 /* The jump destination is direct; use jmp_pc_imm.
1717 However, we will have stored into jmp_pc as well;
1718 we know now that it wasn't needed. */
1719 tcg_gen_discard_tl(jmp_pc);
1720 /* fallthru */
1721
1722 case DISAS_TOO_MANY:
1723 if (unlikely(dc->base.singlestep_enabled)) {
1724 tcg_gen_movi_tl(cpu_pc, jmp_dest);
1725 gen_exception(dc, EXCP_DEBUG);
1726 } else if ((dc->base.pc_first ^ jmp_dest) & TARGET_PAGE_MASK) {
1727 tcg_gen_movi_tl(cpu_pc, jmp_dest);
1728 tcg_gen_lookup_and_goto_ptr();
1729 } else {
1730 tcg_gen_goto_tb(0);
1731 tcg_gen_movi_tl(cpu_pc, jmp_dest);
1732 tcg_gen_exit_tb(dc->base.tb, 0);
1733 }
1734 break;
1735
1736 case DISAS_EXIT:
1737 if (unlikely(dc->base.singlestep_enabled)) {
1738 gen_exception(dc, EXCP_DEBUG);
1739 } else {
1740 tcg_gen_exit_tb(NULL, 0);
1741 }
1742 break;
1743 default:
1744 g_assert_not_reached();
1745 }
1746 }
1747
openrisc_tr_disas_log(const DisasContextBase * dcbase,CPUState * cs)1748 static void openrisc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
1749 {
1750 DisasContext *s = container_of(dcbase, DisasContext, base);
1751
1752 qemu_log("IN: %s\n", lookup_symbol(s->base.pc_first));
1753 log_target_disas(cs, s->base.pc_first, s->base.tb->size);
1754 }
1755
1756 static const TranslatorOps openrisc_tr_ops = {
1757 .init_disas_context = openrisc_tr_init_disas_context,
1758 .tb_start = openrisc_tr_tb_start,
1759 .insn_start = openrisc_tr_insn_start,
1760 .breakpoint_check = openrisc_tr_breakpoint_check,
1761 .translate_insn = openrisc_tr_translate_insn,
1762 .tb_stop = openrisc_tr_tb_stop,
1763 .disas_log = openrisc_tr_disas_log,
1764 };
1765
gen_intermediate_code(CPUState * cs,TranslationBlock * tb,int max_insns)1766 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
1767 {
1768 DisasContext ctx;
1769
1770 translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb, max_insns);
1771 }
1772
openrisc_cpu_dump_state(CPUState * cs,FILE * f,int flags)1773 void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1774 {
1775 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
1776 CPUOpenRISCState *env = &cpu->env;
1777 int i;
1778
1779 qemu_fprintf(f, "PC=%08x\n", env->pc);
1780 for (i = 0; i < 32; ++i) {
1781 qemu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i),
1782 (i % 4) == 3 ? '\n' : ' ');
1783 }
1784 }
1785
restore_state_to_opc(CPUOpenRISCState * env,TranslationBlock * tb,target_ulong * data)1786 void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb,
1787 target_ulong *data)
1788 {
1789 env->pc = data[0];
1790 env->dflag = data[1] & 1;
1791 if (data[1] & 2) {
1792 env->ppc = env->pc - 4;
1793 }
1794 }
1795