1 /* hp3000_cpu.h: HP 3000 CPU declarations 2 3 Copyright (c) 2016-2019, J. David Bryan 4 5 Permission is hereby granted, free of charge, to any person obtaining a copy 6 of this software and associated documentation files (the "Software"), to deal 7 in the Software without restriction, including without limitation the rights 8 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 copies of the Software, and to permit persons to whom the Software is 10 furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included in 13 all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 19 ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 20 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22 Except as contained in this notice, the name of the author shall not be used 23 in advertising or otherwise to promote the sale, use or other dealings in 24 this Software without prior written authorization from the author. 25 26 18-Feb-19 JDB Added SS_PAUSE_RESUMED simulation stop condition 27 25-Jul-18 JDB Fixed typo in "cpu_setup_code_segment" declaration 28 07-Nov-16 JDB Added SETR and SETR_X for SETR executor use; 29 renamed cpu_byte_to_word_ea to cpu_byte_ea 30 03-Nov-16 JDB Added LABEL_LOCAL for PARC/XBR/ENDP executor use 31 01-Nov-16 JDB Added debug flag for per-instruction trace capability 32 22-Oct-16 JDB Added "cpu_interrupt_pending" global from cpu_base.c 33 07-Oct-16 JDB Added "cpu_dev" external so executors can trace instructions 34 28-Sep-16 JDB Added CIS definitions 35 22-Sep-16 JDB Added cpu_byte_to_word_ea, STATUS_CS macro 36 21-Sep-16 JDB Added STATUS_CCI, UNIT_CIS, and the CIS dispatcher 37 12-Sep-16 JDB Added the PCN_SERIES_II and PCN_SERIES_III constants 38 02-Sep-16 JDB Added the POWER_STATE enumeration type, the UNIT_PFARS 39 flag, and the "cpu_power_state" external declaration 40 24-Aug-16 JDB Fixed the UNIT_CPU_MODEL test macro 41 23-Aug-16 JDB Added the MOD (module control) register 42 12-Jul-16 JDB Renamed "loading" EXEC_STATE to "waiting" 43 21-Mar-16 JDB Changed cpu_ccb_table type from uint16 to HP_WORD 44 14-Feb-16 JDB First release version 45 11-Dec-12 JDB Created 46 47 48 This file provides the declarations for interoperation between the CPU and 49 its supporting modules. It provides the symbols that allow direct 50 manipulation of the CPU registers and determination of currently installed 51 features. 52 */ 53 54 55 56 #include <setjmp.h> 57 58 59 60 /* Supported breakpoint switches */ 61 62 #define BP_EXEC (SWMASK ('E')) /* an execution breakpoint */ 63 #define BP_SUPPORTED (BP_EXEC) /* the list of supported breakpoint types */ 64 65 66 /* Unit flags and accessors */ 67 68 #define UNIT_MODEL_SHIFT (UNIT_V_UF + 0) /* the CPU model (1 bit) */ 69 #define UNIT_EIS_SHIFT (UNIT_V_UF + 1) /* the Extended Instruction Set firmware option */ 70 #define UNIT_CALTIME_SHIFT (UNIT_V_UF + 2) /* the process clock timing mode */ 71 #define UNIT_PFARS_SHIFT (UNIT_V_UF + 3) /* the power-fail auto-restart mode */ 72 #define UNIT_CIS_SHIFT (UNIT_V_UF + 4) /* the COBOL II Extended Instruction Set firmware option */ 73 74 #define UNIT_MODEL_MASK 0000001u /* model ID mask */ 75 76 #define UNIT_MODEL (UNIT_MODEL_MASK << UNIT_MODEL_SHIFT) 77 78 #define UNIT_SERIES_III (0u << UNIT_MODEL_SHIFT) /* the CPU is a Series III */ 79 #define UNIT_SERIES_II (1u << UNIT_MODEL_SHIFT) /* the CPU is a Series II */ 80 #define UNIT_EIS (1u << UNIT_EIS_SHIFT) /* the Extended Instruction Set is installed */ 81 #define UNIT_CALTIME (1u << UNIT_CALTIME_SHIFT) /* the process clock is calibrated to wall time */ 82 #define UNIT_PFARS (1u << UNIT_PFARS_SHIFT) /* the system will auto-restart after a power failure */ 83 #define UNIT_CIS (1u << UNIT_CIS_SHIFT) /* the COBOL II Extended Instruction Set is installed */ 84 85 #define UNIT_CPU_MODEL (cpu_unit [0].flags & UNIT_MODEL) 86 87 #define CPU_MODEL(f) ((f) >> UNIT_MODEL_SHIFT & UNIT_MODEL_MASK) 88 89 #define MEMSIZE (cpu_unit [0].capac) /* the current memory size in 16-bit words */ 90 91 92 /* CPU debug flags */ 93 94 #define DEB_ALL ~0u /* trace everything */ 95 96 #define DEB_INSTR (1u << 0) /* trace instructions */ 97 #define DEB_REG (1u << 1) /* trace register values */ 98 #define DEB_PSERV (1u << 2) /* trace PCLK service events */ 99 #define DEB_EXEC (1u << 3) /* trace matched instruction executions */ 100 101 #define BOV_FORMAT "%02o.%06o %06o " /* bank-offset-value trace format string */ 102 103 104 /* CPU stop flags */ 105 106 #define SS_LOOP (1u << 0) /* stop on infinite loop */ 107 #define SS_PAUSE (1u << 1) /* stop on PAUS instruction */ 108 #define SS_UNDEF (1u << 2) /* stop on undefined instruction */ 109 #define SS_UNIMPL (1u << 3) /* stop on unimplemented instruction */ 110 111 #define SS_PAUSE_RESUMED (1u << 30) /* stop resumes into a PAUS instruction */ 112 #define SS_BYPASSED (1u << 31) /* stops are bypassed for this instruction */ 113 114 115 /* Memory access macros */ 116 117 #define cpu_read_memory(c,o,v) mem_read (&cpu_dev, c, o, v) 118 #define cpu_write_memory(c,o,v) mem_write (&cpu_dev, c, o, v) 119 120 121 122 /* System power state. 123 124 The HP 3000 power supply uses two signals to indicate its state: PON (power 125 on) and PFW (power-fail warning). PON is asserted when the DC power levels 126 are within their operating ranges. PFW is asserted when AC power is lost. 127 When a power failure occurs, PFW will be asserted at least three milliseconds 128 before PON is denied. When power is restored, PFW denies immediately, but 129 PON does not assert until the DC output voltages have stabilized, and the 130 machine is ready to resume execution. 131 132 In simulation, the four states of these two signals are modeled with 133 enumeration constants, as follows: 134 135 PON PFW State Simulator Action 136 --- --- --------------- ---------------------------- 137 1 0 power on executing normally 138 1 1 power failing executing with cpx1_PFINTR 139 0 1 power off will not execute 140 0 0 power returning executing with trap_Power_On 141 */ 142 143 typedef enum { 144 power_on, 145 power_failing, 146 power_off, 147 power_returning 148 } POWER_STATE; 149 150 151 /* Micromachine execution state */ 152 153 typedef enum { 154 running, /* the micromachine is running */ 155 paused, /* a PAUS instruction has been executed */ 156 waiting, /* a cold load or dump is in progress */ 157 halted /* a programmed or front panel HALT has been executed */ 158 } EXEC_STATE; 159 160 161 /* CPX register flags. 162 163 The CPX1 register contains flags that designate the run-time interrupts. The 164 CPX2 register contains flags for halt-time interrupts. 165 166 167 Implementation notes: 168 169 1. These are implemented as enumeration types to allow the "gdb" debugger to 170 display the CPX register values as bit sets. 171 */ 172 173 typedef enum { 174 cpx1_INTOVFL = 0100000u, /* integer overflow */ 175 cpx1_BNDVIOL = 0040000u, /* bounds violation */ 176 cpx1_ILLADDR = 0020000u, /* illegal address */ 177 cpx1_CPUTIMER = 0010000u, /* CPU timer */ 178 cpx1_SYSPAR = 0004000u, /* system parity error */ 179 cpx1_ADDRPAR = 0002000u, /* address parity error */ 180 cpx1_DATAPAR = 0001000u, /* data parity error */ 181 cpx1_MODINTR = 0000400u, /* module interrupt */ 182 cpx1_EXTINTR = 0000200u, /* external interrupt */ 183 cpx1_PFINTR = 0000100u, /* power fail interrupt */ 184 /* cpx1_UNUSED = 0000040u, unused, always 0 */ 185 cpx1_ICSFLAG = 0000020u, /* ICS flag */ 186 cpx1_DISPFLAG = 0000010u, /* dispatcher-is-active flag */ 187 cpx1_EMULATOR = 0000004u, /* emulator-in-use flag */ 188 cpx1_IOTIMER = 0000002u, /* I/O timeout */ 189 cpx1_OPTION = 0000001u /* option present */ 190 } CPX1FLAG; 191 192 #define CPX1_IRQ_SET (cpx1_INTOVFL | cpx1_BNDVIOL | \ 193 cpx1_ILLADDR | cpx1_CPUTIMER | \ 194 cpx1_SYSPAR | cpx1_ADDRPAR | \ 195 cpx1_DATAPAR | cpx1_MODINTR | \ 196 cpx1_EXTINTR | cpx1_PFINTR) /* the set of CPX1 interrupt requests */ 197 198 typedef enum { 199 cpx2_RUNSWCH = 0100000u, /* RUN switch */ 200 cpx2_DUMPSWCH = 0040000u, /* DUMP switch */ 201 cpx2_LOADSWCH = 0020000u, /* LOAD switch */ 202 cpx2_LOADREG = 0010000u, /* load register */ 203 cpx2_LOADADDR = 0004000u, /* load address */ 204 cpx2_LOADMEM = 0002000u, /* load memory */ 205 cpx2_DISPMEM = 0001000u, /* display memory */ 206 cpx2_SNGLINST = 0000400u, /* single instruction */ 207 cpx2_EXECSWCH = 0000200u, /* EXECUTE switch */ 208 cpx2_INCRADDR = 0000100u, /* increment address */ 209 cpx2_DECRADDR = 0000040u, /* decrement address */ 210 /* cpx2_UNUSED = 0000020u, unused, always 0 */ 211 /* cpx2_UNUSED = 0000010u, unused, always 0 */ 212 cpx2_INHPFARS = 0000004u, /* inhibit power-fail auto-restart */ 213 cpx2_SYSHALT = 0000002u, /* system halt */ 214 cpx2_RUN = 0000001u /* run flip-flop */ 215 } CPX2FLAG; 216 217 #define CPX2_IRQ_SET (cpx2_RUNSWCH | cpx2_DUMPSWCH | \ 218 cpx2_LOADSWCH | cpx2_LOADREG | \ 219 cpx2_LOADADDR | cpx2_LOADMEM | \ 220 cpx2_DISPMEM | cpx2_SNGLINST | \ 221 cpx2_EXECSWCH) /* the set of CPX2 interrupt requests */ 222 223 224 /* Interrupt classifications. 225 226 Interrupts are generated by setting CPX1 bits, by microcode aborts (traps), 227 or by the DISP or IXIT instructions to run the OS dispatcher or in response 228 to an external interrupt. Each interrupt source is serviced by a procedure 229 in the Segment Transfer Table of segment 1, and the classification values are 230 chosen to match the STT numbers. 231 232 233 Implementation notes: 234 235 1. The STT numbers are relevant only for interrupts that come from setting 236 the CPX1 bits (except for bit 8). The enumeration values for external, 237 trap, DISP, and IXIT interrupts are not significant. 238 */ 239 240 typedef enum { 241 /* identifier STT Source Description */ 242 /* ----------------------- --- ------ ------------------------- */ 243 irq_Integer_Overflow = 000, /* CPX1.0 Integer Overflow */ 244 irq_Bounds_Violation = 001, /* CPX1.1 Bounds Violation */ 245 irq_Illegal_Address = 002, /* CPX1.2 Illegal Memory Address */ 246 irq_Timeout = 003, /* CPX1.3 Non-Responding Module */ 247 irq_System_Parity = 004, /* CPX1.4 System Parity Error */ 248 irq_Address_Parity = 005, /* CPX1.5 Address Parity Error */ 249 irq_Data_Parity = 006, /* CPX1.6 Data Parity Error */ 250 irq_Module = 007, /* CPX1.7 Module Interrupt */ 251 irq_External = 010, /* CPX1.8 External Interrupt */ 252 irq_Power_Fail = 011, /* CPX1.9 Power Fail Interrupt */ 253 irq_Trap = 012, /* uABORT System or user trap */ 254 irq_Dispatch = 013, /* DISP Run the dispatcher */ 255 irq_IXIT = 014 /* IXIT External interrupt */ 256 } IRQ_CLASS; 257 258 259 /* Trap classifications. 260 261 Except for the power-on trap, all traps result from microcode aborts. In 262 hardware, these result in microcode jumps to the appropriate trap handlers. 263 In simulation, a MICRO_ABORT executes a "longjmp" to the trap handler just 264 before the main instruction loop. As with interrupts, each trap is serviced 265 by a procedure in the Segment Transfer Table of segment 1, and the 266 classification values are chosen to match the STT numbers. 267 268 Traps are invoked by the MICRO_ABORT macro, which takes as its parameter a 269 trap classification value. Some traps require an additional parameter and 270 must be invoked by the MICRO_ABORTP macro, which takes a trap classification 271 value and a trap-specific value as parameters. 272 273 Accessors are provided to separate the TRAP_CLASS and the parameter from the 274 combined longjmp value. 275 276 277 Implementation notes: 278 279 1. Trap classifications must be > 0 for longjmp compatibility. 280 281 2. A System Halt trap does not call an OS procedure but instead stops the 282 simulator. The parameter number indicates the reason for the halt. 283 284 3. The User trap is subdivided into traps for a number of arithmetic 285 conditions. These are indicated by their corresponding parameter numbers 286 in the upper words of the longjmp values. 287 */ 288 289 typedef enum { 290 /* identifier STT Source Description */ 291 /* ------------------------ --- ------ ------------------------- */ 292 trap_None = 000, /* -- (none) */ 293 trap_Bounds_Violation = 001, /* ucode Bounds Violation */ 294 trap_Unimplemented = 020, /* ucode Unimplemented Instruction */ 295 trap_STT_Violation = 021, /* ucode STT Violation */ 296 trap_CST_Violation = 022, /* ucode CST Violation */ 297 trap_DST_Violation = 023, /* ucode DST Violation */ 298 trap_Stack_Underflow = 024, /* ucode Stack Underflow */ 299 trap_Privilege_Violation = 025, /* ucode Privileged Mode Violation */ 300 trap_Stack_Overflow = 030, /* ucode Stack Overflow */ 301 trap_User = 031, /* ucode User Trap */ 302 trap_CS_Absent = 037, /* ucode Absent Code Segment */ 303 trap_Trace = 040, /* ucode Trace */ 304 trap_Uncallable = 041, /* ucode STT Entry Uncallable */ 305 trap_DS_Absent = 042, /* ucode Absent Data Segment */ 306 trap_Power_On = 043, /* hdwe Power On */ 307 trap_Cold_Load = 044, /* ucode Cold Load */ 308 trap_System_Halt = 045 /* ucode System Halt */ 309 } TRAP_CLASS; 310 311 #define trap_Integer_Overflow TO_DWORD (001, trap_User) 312 #define trap_Float_Overflow TO_DWORD (002, trap_User) 313 #define trap_Float_Underflow TO_DWORD (003, trap_User) 314 #define trap_Integer_Zero_Divide TO_DWORD (004, trap_User) 315 #define trap_Float_Zero_Divide TO_DWORD (005, trap_User) 316 #define trap_Ext_Float_Overflow TO_DWORD (010, trap_User) 317 #define trap_Ext_Float_Underflow TO_DWORD (011, trap_User) 318 #define trap_Ext_Float_Zero_Divide TO_DWORD (012, trap_User) 319 #define trap_Decimal_Overflow TO_DWORD (013, trap_User) 320 #define trap_Invalid_ASCII_Digit TO_DWORD (014, trap_User) 321 #define trap_Invalid_Decimal_Digit TO_DWORD (015, trap_User) 322 #define trap_Invalid_Word_Count TO_DWORD (016, trap_User) 323 #define trap_Word_Count_Overflow TO_DWORD (017, trap_User) 324 #define trap_Decimal_Zero_Divide TO_DWORD (020, trap_User) 325 326 #define trap_SysHalt_STTV_1 TO_DWORD ( 1, trap_System_Halt) 327 #define trap_SysHalt_Absent_ICS TO_DWORD ( 2, trap_System_Halt) 328 #define trap_SysHalt_Absent_1 TO_DWORD ( 3, trap_System_Halt) 329 #define trap_SysHalt_Overflow_ICS TO_DWORD ( 4, trap_System_Halt) 330 #define trap_SysHalt_IO_Timeout TO_DWORD ( 6, trap_System_Halt) 331 #define trap_SysHalt_PSEB_Enabled TO_DWORD ( 9, trap_System_Halt) 332 #define trap_SysHalt_CSTV_1 TO_DWORD (13, trap_System_Halt) 333 #define trap_SysHalt_LOCK_EI TO_DWORD (23, trap_System_Halt) 334 #define trap_SysHalt_Trace_1 TO_DWORD (33, trap_System_Halt) 335 336 #define PARAM(i) (uint32) UPPER_WORD (i) 337 #define TRAP(i) (TRAP_CLASS) LOWER_WORD (i) 338 339 #define MICRO_ABORT(t) longjmp (cpu_save_env, (t)) 340 #define MICRO_ABORTP(t,p) longjmp (cpu_save_env, TO_DWORD ((p),(t))) 341 342 343 /* Central Data Bus module definitions */ 344 345 #define MODULE_MEMORY_LOWER 0 /* lower memory MCL address */ 346 #define MODULE_MEMORY_UPPER 2 /* upper memory MCL address */ 347 #define MODULE_MEMORY 3 /* upper bound of MCL addresses */ 348 #define MODULE_PORT_CNTLR 4 /* selector channel port controller address */ 349 #define MODULE_CPU 5 /* CPU MCU address */ 350 #define MODULE_UNDEFINED 6 /* addresses 6-7 are unused */ 351 352 #define MOP_NOP 0 /* module operation 00 = no operation */ 353 #define MOP_WRITE 1 /* module operation 01 = write */ 354 #define MOP_READ 2 /* module operation 10 = read */ 355 #define MOP_READ_WRITE_ONES 3 /* module operation 11 = read/write ones */ 356 357 358 /* Module control register accessors. 359 360 The module control register, MOD, has this format: 361 362 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 363 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 364 | 0 0 | MOP | 0 | FROM | 0 0 0 0 | B | A | 0 0 | 365 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 366 367 Where: 368 369 MOP = module operation 370 FROM = source module address 371 B = this CPU is CPU #2 372 A = this CPU is CPU #1 373 */ 374 375 #define MOD_MOP_MASK 0030000u /* MOD register MOP field mask */ 376 #define MOD_FROM_MASK 0003400u /* MOD register FROM field mask */ 377 #define MOD_CPU_2 0000010u /* CPU number 2 MCU */ 378 #define MOD_CPU_1 0000004u /* CPU number 1 MCU */ 379 380 #define MOD_MOP_SHIFT 12 /* MOD register MOP field alignment shift */ 381 #define MOD_FROM_SHIFT 8 /* MOD register FROM field alignment shift */ 382 383 #define TO_MOD_MOP(v) ((v) << MOD_MOP_SHIFT & MOD_MOP_MASK) 384 #define TO_MOD_FROM(v) ((v) << MOD_FROM_SHIFT & MOD_FROM_MASK) 385 386 387 /* Status register accessors. 388 389 The CPU status register, STA, has this format: 390 391 0 | 1 2 3 | 4 5 6 | 7 8 9 |10 11 12 |13 14 15 392 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 393 | M | I | T | R | O | C | ccode | current code segment number | 394 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 395 396 Where: 397 398 M = user mode/protected mode (0/1) 399 I = external interrupts are enabled 400 T = user traps are enabled 401 R = right-hand stack operation executes next 402 O = arithmetic overflow has occurred 403 C = arithmetic carry has occurred 404 405 Condition Code: 406 407 00 = CCG (greater than) 408 01 = CCL (less than) 409 10 = CCE (equal to) 410 11 = invalid 411 */ 412 413 #define STATUS_M 0100000u /* mode flag */ 414 #define STATUS_I 0040000u /* interrupt flag */ 415 #define STATUS_T 0020000u /* trap flag */ 416 #define STATUS_R 0010000u /* right-hand stack op flag */ 417 #define STATUS_O 0004000u /* overflow flag */ 418 #define STATUS_C 0002000u /* carry flag */ 419 420 #define STATUS_CCG 0000000u /* condition code greater than */ 421 #define STATUS_CCL 0000400u /* condition code less than */ 422 #define STATUS_CCE 0001000u /* condition code equal to */ 423 #define STATUS_CCI 0001400u /* condition code invalid */ 424 425 #define STATUS_CC_MASK 0001400u /* condition code mask */ 426 #define STATUS_CC_SHIFT 8 /* condition code alignment */ 427 428 #define STATUS_CS_MASK 0000377u /* code segment mask */ 429 #define STATUS_CS_SHIFT 0 /* code segment alignment */ 430 #define STATUS_CS_WIDTH 8 /* code segment mask width */ 431 432 #define STATUS_CS(s) (((s) & STATUS_CS_MASK) >> STATUS_CS_SHIFT) 433 434 435 #define STATUS_OVTRAP (STATUS_T | STATUS_O) 436 #define STATUS_NPRV (STATUS_T | STATUS_O | STATUS_C | STATUS_CC_MASK) 437 438 #define TO_CCN(s) (((s) & STATUS_CC_MASK) >> STATUS_CC_SHIFT) 439 440 441 /* Status register mode tests */ 442 443 #define PRIV (STA & STATUS_M) /* current mode is privileged */ 444 #define NPRV (!PRIV) /* current mode is non-privileged */ 445 446 447 /* Condition code flags. 448 449 Several instructions define "condition code flags" that specify condition 450 code tests to be performed. These flags are ANDed with the condition code 451 from the status register to establish whether the test passes. CCE and CCL 452 are encoded in the status register by bits 6 and 7, respectively, but CCG is 453 encoded as 00, causing a direct AND to fail. This is resolved in microcode 454 by the "CC" S-bus micro-order, which copies bits 6 and 7 to bits 8 and 9 of 455 the S-bus register and also sets bit 7 if bits 8 and 9 are zero (CCG). The 456 result is a single bit set for each condition code that may be ANDed with the 457 CCF field of the instruction. 458 459 The MVBW (Move Bytes While) instruction moves bytes from the source to the 460 destination while the bytes are alphabetic, numeric, or either, depending on 461 the A and N bits in the instruction. The CCB classification table is used to 462 determine the type of each byte moved. If both A and N bits are set, then a 463 table entry of either CCG or CCE will succeed. Matching via a single AND 464 operation is possible only if the encoding of all three conditions is 465 disjoint. 466 467 We implement this scheme without the two-bit right-shift, so that ANDing a 468 CCF with STATUS_CC_MASK will produce the correctly aligned status register 469 value. The TO_CCF macro converts the current condition code in the status 470 register to a condition code flag. 471 */ 472 473 #define CFL 0000400u /* condition code flag less than */ 474 #define CFE 0001000u /* condition code flag equal to */ 475 #define CFG 0002000u /* condition code flag greater than */ 476 477 #define TO_CCF(s) ((s) & STATUS_CC_MASK ? (s) & STATUS_CC_MASK : CFG) 478 479 480 /* Condition code patterns. 481 482 Machine instructions typically set the condition code field of the status 483 register to reflect the values of their operands, which may be on the top of 484 the stack, in the X register, or in memory. Each instruction that affects 485 the condition code field commonly uses one of the following patterns to set 486 the field: 487 488 CCA (arithmetic) sets CC to: 489 - CCG (00) if the operand is > 0 490 - CCL (01) if the operand is < 0 491 - CCE (10) if the operand is = 0 492 493 CCB (byte) sets CC to: 494 - CCG (00) if the operand is numeric (byte value is 060-071) 495 - CCL (01) if the operand is any other character 496 - CCE (10) if the operand is alphabetic (0101-0132 or 0141-0172) 497 498 CCC (comparison) sets CC to: 499 - CCG (00) if operand 1 is > operand 2 500 - CCL (01) if operand 1 is < operand 2 501 - CCE (10) if operand 1 is = operand 2 502 503 CCD (direct I/O) sets CC to: 504 - CCG (00) if the device is not ready 505 - CCL (01) if the device controller is not responding 506 - CCE (10) if the device is ready and controller is responding 507 508 The operand(s) may be a byte, word, double word, triple word, or quadruple 509 word, and may be signed (integer) or unsigned (logical). 510 511 Statement macros are provided to set the condition code explicitly, as well 512 as to set the code using patterns CCA, CCB, or CCC. The CCA macro takes two 513 parameters: an upper word and a lower word. The CCB macro takes a single 514 byte parameter. The CCC macro takes four parameters: an upper and lower word 515 for each of the two operands. 516 517 No macro is provided for pattern CCD, as that pattern reflects the 518 operational status of the target device and interface, rather than the 519 condition of an operand. The I/O instructions use the explicit macros to set 520 the codes for pattern D. 521 */ 522 523 #define SET_CCG STA = STA & ~STATUS_CC_MASK | STATUS_CCG 524 #define SET_CCL STA = STA & ~STATUS_CC_MASK | STATUS_CCL 525 #define SET_CCE STA = STA & ~STATUS_CC_MASK | STATUS_CCE 526 527 528 /* Condition code pattern CCA (arithmetic). 529 530 Semantics: 531 532 if operand > 0 533 then CCG 534 else if operand < 0 535 then CCL 536 else 537 CCE 538 539 Macro: 540 541 SET_CCA (upper, lower) 542 543 Implementation: 544 545 if upper = 0 or lower = 0 546 then CCE 547 else if upper.sign = 1 548 then CCL 549 else CCG 550 551 Usage: 552 553 SET_CCA (RA, 0) -- a 16-bit integer value 554 SET_CCA (0, RA) -- a 16-bit logical value 555 SET_CCA (RB, RA) -- a 32-bit integer value 556 SET_CCA (0, RB | RA) -- a 32-bit logical value 557 SET_CCA (RC, RB | RA) -- a 48-bit integer value 558 SET_CCA (RD, RC | RB | RA) -- a 64-bit integer value 559 560 561 Implementation notes: 562 563 1. When either "upper" or "lower" is 0, the corresponding test is optimized 564 away. 565 */ 566 567 #define SET_CCA(u,l) STA = STA & ~STATUS_CC_MASK | \ 568 (((u) | (l)) == 0 \ 569 ? STATUS_CCE \ 570 : (u) & D16_SIGN \ 571 ? STATUS_CCL \ 572 : STATUS_CCG) 573 574 575 /* Condition code pattern CCB (byte). 576 577 Semantics: 578 579 if operand in 060 .. 071 580 then CCG 581 else if operand in 0101 .. 0132 or operand in 0141 .. 0172 582 then CCE 583 else 584 CCL 585 586 Macro: 587 588 SET_CCB (byte) 589 590 Implementation: 591 592 CCx = ccb_lookup_table [byte] 593 594 Usage: 595 596 SET_CCB (RA) 597 598 599 Implementation notes: 600 601 1. The byte parameter is not masked before being used as an array index, so 602 the caller must ensure that the value is between 0 and 255. 603 604 2. The table value must be masked if it is to be stored in the status 605 register because CCG is returned as 100 (base 2) to ensure that all 606 values are disjoint for the MVBW and Bcc instructions. 607 */ 608 609 #define SET_CCB(b) STA = STA & ~STATUS_CC_MASK | \ 610 cpu_ccb_table [(b)] & STATUS_CC_MASK 611 612 613 /* Condition code pattern CCC (conditional). 614 615 Semantics: 616 617 if operand_1 > operand_2 618 then CCG 619 else if operand_1 < operand_2 620 then CCL 621 else 622 CCE 623 624 Macro: 625 626 SET_CCC (upper_1, lower_1, upper_2, lower_2) 627 628 Implementation: 629 630 if upper_1 = upper_2 631 then 632 if lower_1 = lower_2 633 then CCE 634 else if lower_1 < lower_2 635 then CCL 636 else CCG 637 else if |upper_1| < |upper_2| 638 then CCL 639 else CCG 640 641 Usage: 642 643 SET_CCC (RA, 0, RB, 0) -- 16-bit integer comparison 644 SET_CCC ( 0, RA, 0, RB) -- 16-bit logical comparison 645 SET_CCC (RB, RA, RD, RC) -- 32-bit integer comparison 646 647 648 Implementation notes: 649 650 1. When any of the parameters are 0, the corresponding tests are optimized 651 away. 652 653 2. Complementing the signs of the upper words allows an unsigned comparison 654 to substitute for a signed comparison. 655 */ 656 657 #define SET_CCC(u1,l1,u2,l2) STA = STA & ~STATUS_CC_MASK | \ 658 ((u1) == (u2) \ 659 ? ((l1) == (l2) \ 660 ? STATUS_CCE \ 661 : ((l1) < (l2) \ 662 ? STATUS_CCL \ 663 : STATUS_CCG)) \ 664 : (((u1) ^ D16_SIGN) < ((u2) ^ D16_SIGN) \ 665 ? STATUS_CCL \ 666 : STATUS_CCG)) 667 668 /* Set carry and overflow. 669 670 These macros are used by arithmetic operations to set the carry and overflow 671 bits in the status register. In addition to setting the overflow bit, if 672 user traps are enabled, the Integer Overflow bit in the CPX1 register is set, 673 which will cause an interrupt 674 */ 675 676 #define SET_CARRY(b) STA = ((b) ? STA | STATUS_C : STA & ~STATUS_C) 677 678 #define SET_OVERFLOW(b) if (b) { \ 679 STA |= STATUS_O; \ 680 if (STA & STATUS_T) \ 681 CPX1 |= cpx1_INTOVFL; \ 682 } \ 683 else \ 684 STA &= ~STATUS_O 685 686 /* SR preadjust. 687 688 The PREADJUST_SR macro is called to ensure that the correct number of TOS 689 registers are valid prior to instruction execution. 690 */ 691 692 #define PREADJUST_SR(n) if (SR < (n)) \ 693 cpu_adjust_sr (n) 694 695 696 /* Machine instruction bit-field accessors */ 697 698 #define BITS_0_3_MASK 0170000u /* bits 0-3 mask */ 699 #define BITS_0_3_SHIFT 12 /* bits 0-3 alignment shift */ 700 701 #define BITS_0_3(v) (((v) & BITS_0_3_MASK) >> BITS_0_3_SHIFT) 702 703 #define BITS_4_5_MASK 0006000u /* bits 4-5 mask */ 704 #define BITS_4_5_SHIFT 10 /* bits 4-5 alignment shift */ 705 706 #define BITS_4_5(v) (((v) & BITS_4_5_MASK) >> BITS_4_5_SHIFT) 707 708 #define BITS_4_7_MASK 0007400u /* bits 4-7 mask */ 709 #define BITS_4_7_SHIFT 8 /* bits 4-7 alignment shift */ 710 711 #define BITS_4_7(v) (((v) & BITS_4_7_MASK) >> BITS_4_7_SHIFT) 712 713 #define BITS_4_9_MASK 0007700u /* bits 4-9 mask */ 714 #define BITS_4_9_SHIFT 6 /* bits 4-9 alignment shift */ 715 716 #define BITS_4_9(v) (((v) & BITS_4_9_MASK) >> BITS_4_9_SHIFT) 717 718 #define BITS_5_9_MASK 0003700u /* bits 5-9 mask */ 719 #define BITS_5_9_SHIFT 6 /* bits 5-9 alignment shift */ 720 721 #define BITS_5_9(v) (((v) & BITS_5_9_MASK) >> BITS_5_9_SHIFT) 722 723 #define BITS_8_11_MASK 0000360u /* bits 8-11 mask */ 724 #define BITS_8_11_SHIFT 4 /* bits 8-11 alignment shift */ 725 726 #define BITS_8_11(v) (((v) & BITS_8_11_MASK) >> BITS_8_11_SHIFT) 727 728 #define BITS_8_12_MASK 0000370u /* bits 8-12 mask */ 729 #define BITS_8_12_SHIFT 3 /* bits 8-12 alignment shift */ 730 731 #define BITS_8_12(v) (((v) & BITS_8_12_MASK) >> BITS_8_12_SHIFT) 732 733 #define BITS_10_15_MASK 0000077u /* bits 10-15 mask */ 734 #define BITS_10_15_SHIFT 0 /* bits 10-15 alignment shift */ 735 736 #define BITS_10_15(v) (((v) & BITS_10_15_MASK) >> BITS_10_15_SHIFT) 737 738 #define BITS_12_15_MASK 0000017u /* bits 12-15 mask */ 739 #define BITS_12_15_SHIFT 0 /* bits 12-15 alignment shift */ 740 741 #define BITS_12_15(v) (((v) & BITS_12_15_MASK) >> BITS_12_15_SHIFT) 742 743 744 /* Instruction-class accessors */ 745 746 #define SUBOP_MASK BITS_0_3_MASK /* subopcode mask */ 747 #define SUBOP_SHIFT BITS_0_3_SHIFT /* subopcode alignment shift */ 748 #define SUBOP(v) BITS_0_3(v) /* subopcode accessor */ 749 750 #define STACKOP_A_MASK BITS_4_9_MASK /* stack operation A mask */ 751 #define STACKOP_A_SHIFT BITS_4_9_SHIFT /* stack operation A alignment shift */ 752 #define STACKOP_A(v) BITS_4_9(v) /* stack operation A accessor */ 753 754 #define STACKOP_B_MASK BITS_10_15_MASK /* stack operation B mask */ 755 #define STACKOP_B_SHIFT BITS_10_15_SHIFT /* stack operation B alignment shift */ 756 #define STACKOP_B(v) BITS_10_15(v) /* stack operation B accessor */ 757 758 #define SBBOP_MASK BITS_5_9_MASK /* shift/branch/bit operation mask */ 759 #define SBBOP_SHIFT BITS_5_9_SHIFT /* shift/branch/bit operation alignment shift */ 760 #define SBBOP(v) BITS_5_9(v) /* shift/branch/bit operation accessor */ 761 762 #define MSFIFROP_MASK BITS_4_7_MASK /* move/special/firmware/immediate/field/register operation mask */ 763 #define MSFIFROP_SHIFT BITS_4_7_SHIFT /* move/special/firmware/immediate/field/register operation alignment shift */ 764 #define MSFIFROP(v) BITS_4_7(v) /* move/special/firmware/immediate/field/register operation accessor */ 765 766 #define MSSUBOP_MASK BITS_8_12_MASK /* move/special suboperation mask */ 767 #define MSSUBOP_SHIFT BITS_8_12_SHIFT /* move/special suboperation alignment shift */ 768 #define MSSUBOP(v) BITS_8_12(v) /* move/special suboperation accessor */ 769 770 #define SPECOP_MASK BITS_12_15_MASK /* special operation mask */ 771 #define SPECOP_SHIFT BITS_12_15_SHIFT /* special operation alignment shift */ 772 #define SPECOP(v) BITS_12_15(v) /* special operation accessor */ 773 774 #define IOCPIMOP_MASK BITS_4_7_MASK /* I-O/control/program/immediate/memory operation mask */ 775 #define IOCPIMOP_SHIFT BITS_4_7_SHIFT /* I-O/control/program/immediate/memory operation alignment shift */ 776 #define IOCPIMOP(v) BITS_4_7(v) /* I-O/control/program/immediate/memory operation accessor */ 777 778 #define IOCSUBOP_MASK BITS_8_11_MASK /* I-O/control suboperation mask */ 779 #define IOCSUBOP_SHIFT BITS_8_11_SHIFT /* I-O/control suboperation alignment shift */ 780 #define IOCSUBOP(v) BITS_8_11(v) /* I-O/control suboperation accessor */ 781 782 #define CNTLOP_MASK BITS_12_15_MASK /* control operation mask */ 783 #define CNTLOP_SHIFT BITS_12_15_SHIFT /* control operation alignment shift */ 784 #define CNTLOP(v) BITS_12_15(v) /* control operation accessor */ 785 786 #define MLBOP_MASK BITS_0_3_MASK /* memory/loop/branch operation mask */ 787 #define MLBOP_SHIFT BITS_0_3_SHIFT /* memory/loop/branch operation alignment shift */ 788 #define MLBOP(v) BITS_0_3(v) /* memory/loop/branch operation accessor */ 789 790 #define FIRMEXTOP_MASK BITS_8_11_MASK /* firmware extension operation mask */ 791 #define FIRMEXTOP_SHIFT BITS_8_11_SHIFT /* firmware extension operation alignment shift */ 792 #define FIRMEXTOP(v) BITS_8_11(v) /* firmware extension operation accessor */ 793 794 #define FMEXSUBOP_MASK BITS_12_15_MASK /* firmware extension suboperation mask */ 795 #define FMEXSUBOP_SHIFT BITS_12_15_SHIFT /* firmware extension suboperation alignment shift */ 796 #define FMEXSUBOP(v) BITS_12_15(v) /* firmware extension suboperation accessor */ 797 798 799 /* General instruction accessors */ 800 801 #define IOOP_K_MASK 0000017u /* I/O K-field mask */ 802 #define IOOP_K_SHIFT 0000000u /* I/O K-field alignment shift */ 803 #define IO_K(v) (((v) & IOOP_K_MASK) >> IOOP_K_SHIFT) 804 805 #define X_FLAG 0004000u /* index flag in bit 4 */ 806 #define I_FLAG_BIT_4 0004000u /* indirect flag in bit 4 */ 807 #define I_FLAG_BIT_5 0002000u /* indirect flag in bit 5 */ 808 #define M_FLAG 0001000u /* memory subop flag in bit 6 */ 809 810 #define START_BIT_MASK 0000360u /* start bit mask for bit field instructions */ 811 #define START_BIT_SHIFT 4 /* start bit alignment shift */ 812 #define START_BIT(v) (((v) & START_BIT_MASK) >> START_BIT_SHIFT) 813 814 #define BIT_COUNT_MASK 0000017u /* bit count mask for bit field instructions */ 815 #define BIT_COUNT_SHIFT 0 /* bit count alignment shift */ 816 #define BIT_COUNT(v) (((v) & BIT_COUNT_MASK) >> BIT_COUNT_SHIFT) 817 818 #define BIT_POSITION_MASK 0000077u /* bit position mask for bit test instructions */ 819 #define BIT_POSITION_SHIFT 0 /* bit position alignment shift */ 820 #define BIT_POSITION(v) (((v) & BIT_POSITION_MASK) >> BIT_POSITION_SHIFT) 821 822 #define SHIFT_COUNT_MASK 0000077u /* shift count mask for shift instructions */ 823 #define SHIFT_COUNT_SHIFT 0 /* shift count alignment shift */ 824 #define SHIFT_COUNT(v) (((v) & SHIFT_COUNT_MASK) >> SHIFT_COUNT_SHIFT) 825 826 #define SHIFT_RIGHT_FLAG 0000100u /* shift instructions left/right (0/1) flag */ 827 828 #define MODE_DISP_MASK 0001777u /* memory-reference mode and displacement mask */ 829 #define MODE_MASK 0001700u /* memory-reference mode mask */ 830 #define MODE_SHIFT 6 /* memory-reference mode alignment shift */ 831 832 #define DISPL_31_SIGN 0000040u /* sign bit for 0-31 displacements */ 833 #define DISPL_255_SIGN 0000400u /* sign bit for 0-255 displacements */ 834 835 #define DISPL_31_MASK 0000037u /* mask for 0-31 displacements */ 836 #define DISPL_63_MASK 0000077u /* mask for 0-63 displacements */ 837 #define DISPL_127_MASK 0000177u /* mask for 0-127 displacements */ 838 #define DISPL_255_MASK 0000377u /* mask for 0-255 displacements */ 839 840 #define DISPL_P_FLAG 0001000u /* P-relative displacement flag */ 841 #define DISPL_DB_FLAG 0000400u /* DB-relative displacement flag */ 842 #define DISPL_QPOS_FLAG 0000200u /* positive Q-relative displacement flag */ 843 #define DISPL_QNEG_FLAG 0000100u /* negative Q-relative displacement flag */ 844 845 #define IMMED_MASK 0000377u /* mask for immediate values */ 846 847 #define SDEC2_MASK 0000003u /* two-bit S-decrement mask for move instructions */ 848 #define SDEC3_MASK 0000007u /* three-bit S-decrement mask for move instructions */ 849 #define SDEC_SHIFT 0 /* S-decrement alignment shift */ 850 #define SDEC2(v) (((v) & SDEC2_MASK) >> SDEC_SHIFT) 851 #define SDEC3(v) (((v) & SDEC3_MASK) >> SDEC_SHIFT) 852 853 #define DB_FLAG 0000020u /* base set PB/DB base register flag */ 854 #define CIS_DB_FLAG 0000001u /* CIS set PB/DB base register flag */ 855 856 857 /* Explicit instruction opcodes and accessors */ 858 859 #define NOP 0000000u /* no operation */ 860 #define QASR 0015700u /* quadruple arithmetic right shift */ 861 #define DMUL 0020570u /* double integer multiply */ 862 #define DDIV 0020571u /* double integer divide */ 863 #define SETR 0027400u /* set registers (none) */ 864 #define SETR_X 0027404u /* set registers (index) */ 865 #define SED_1 0030041u /* set enable interrupt */ 866 #define HALT_10 0030370u /* halt 10 */ 867 868 #define MTFDS_MASK 0177730u /* move to/from data segment mask */ 869 #define MTFDS 0020130u /* move to/from data segment */ 870 871 #define EXIT_MASK 0177400u /* exit procedure mask */ 872 #define EXIT 0031400u /* exit procedure */ 873 874 #define PAUS_MASK 0177760u /* pause mask */ 875 #define PAUS 0030020u /* pause */ 876 877 #define BR_MASK 0173000u /* conditional and unconditional branch mask */ 878 #define BR_DBQS_I 0143000u /* branch unconditionally DB/Q/S-relative indirect */ 879 #define BCC 0141000u /* branch conditionally */ 880 #define BCC_CCF_SHIFT 2 /* CCF alignment in BCC instruction */ 881 882 #define LSDX_MASK 0175000u /* load/store double-word indexed mask */ 883 #define LDD_X 0155000u /* load double-word indexed */ 884 #define STD_X 0165000u /* store double-word indexed */ 885 886 #define TBR_MASK 0177000u /* test and branch mask */ 887 #define TBA 0050000u /* test and branch, limit in A */ 888 #define MTBA 0052000u /* modify, test and branch, limit in A */ 889 #define TBX 0054000u /* test and branch, limit in X */ 890 #define MTBX 0056000u /* modify, test and branch, limit in X */ 891 892 #define CMD_TO_MASK 0000007u /* CMD command word TO field mask */ 893 #define CMD_MOP_MASK 0000060u /* CMD command word MOP field mask */ 894 895 #define CMD_TO_SHIFT 0 /* CMD command word TO field alignment shift */ 896 #define CMD_MOP_SHIFT 4 /* CMD command word MOP field alignment shift */ 897 898 #define CMD_TO(v) (((v) & CMD_TO_MASK) >> CMD_TO_SHIFT) 899 #define CMD_MOP(v) (((v) & CMD_MOP_MASK) >> CMD_MOP_SHIFT) 900 901 #define MVBW_CCF 0000030u /* MVBW condition code flags */ 902 #define MVBW_N_FLAG 0000020u /* MVBW numeric flag */ 903 #define MVBW_A_FLAG 0000010u /* MVBW alphabetic flag */ 904 #define MVBW_S_FLAG 0000004u /* MVBW upshift flag */ 905 #define MVBW_CCF_SHIFT 6 /* CCF alignment in MVBW instruction */ 906 907 #define NABS_FLAG 0000100u /* CVDA negative absolute value flag */ 908 #define ABS_FLAG 0000040u /* CVDA absolute value flag */ 909 910 #define CVND_SC_MASK 0000016u /* CVND sign-control mask */ 911 #define CVND_SC_SHIFT 1 /* CVND sign-control field alignment shift */ 912 913 #define EIS_SDEC_MASK 0000020u /* EIS S-decrement mask */ 914 #define EIS_SDEC_SHIFT 4 /* EIS S-decrement alignment shift */ 915 916 #define CIS_SDEC_MASK 0000001u /* CIS S-decrement mask */ 917 #define CIS_SDEC_SHIFT 0 /* CIS S-decrement alignment shift */ 918 919 #define TCCS_CCF_SHIFT 8 /* CIS TCCS instruction CCF alignment */ 920 921 922 /* PSHR/SETR instruction accessors */ 923 924 #define PSR_RL_MASK 0000001u /* PSHR/SETR register right-to-left mask */ 925 #define PSR_LR_MASK 0000200u /* PSHR/SETR register left-to-right mask */ 926 927 #define PSR_SBANK 0000200u /* Stack bank register */ 928 #define PSR_DB_DBANK 0000100u /* Data base and data bank registers */ 929 #define PSR_DL 0000040u /* Data limit register */ 930 #define PSR_Z 0000020u /* Stack limit register */ 931 #define PSR_STA 0000010u /* Status register */ 932 #define PSR_X 0000004u /* Index register */ 933 #define PSR_Q 0000002u /* Frame pointer */ 934 #define PSR_S 0000001u /* Stack pointer */ 935 936 #define PSR_PRIV (PSR_SBANK | PSR_DB_DBANK | PSR_DL | PSR_Z) 937 938 939 /* PCN instruction result values */ 940 941 #define PCN_SERIES_II 1 /* CPU number for the Series II */ 942 #define PCN_SERIES_III 2 /* CPU number for the Series III */ 943 944 945 /* EDIT instruction subprogram operation values */ 946 947 #define EDIT_SUFS 013 /* highest opcode with an extended immediate operand */ 948 #define EDIT_EXOP 017 /* extended opcode prefix */ 949 950 #define EDIT_TE (EDIT_EXOP + 000) /* first extended opcode with no operand */ 951 #define EDIT_MDWO (EDIT_EXOP + 004) /* last extended opcode with no operand */ 952 #define EDIT_DBNZ (EDIT_EXOP + 011) /* last extended opcode */ 953 954 955 /* Reserved memory addresses */ 956 957 #define CSTB_POINTER 0000000u /* code segment table base pointer */ 958 #define CSTX_POINTER 0000001u /* code segment table extension pointer */ 959 #define DST_POINTER 0000002u /* data segment table pointer */ 960 #define ICS_Q 0000005u /* interrupt control stack marker pointer (QI) */ 961 #define ICS_Z 0000006u /* interrupt control stack limit (ZI) */ 962 #define INTERRUPT_MASK 0000007u /* interrupt mask */ 963 #define SGT_POINTER 0001000u /* system global tables pointer */ 964 965 966 /* Code Segment Table accessors */ 967 968 #define CST_A_BIT 0100000u /* code segment is absent */ 969 #define CST_M_BIT 0040000u /* code segment is privileged */ 970 #define CST_R_BIT 0020000u /* code segment has been referenced flag */ 971 #define CST_T_BIT 0010000u /* code segment is to be traced */ 972 #define CST_SEGLEN_MASK 0007777u /* code segment length mask */ 973 #define CST_BANK_MASK 0000017u /* code segment bank mask */ 974 975 #define CST_RESERVED 0000300u /* number of CST entries reserved for the system */ 976 977 978 /* Data Segment Table accessors */ 979 980 #define DST_A_BIT 0100000u /* data segment is absent */ 981 #define DST_C_BIT 0040000u /* data segment is clean (not modified) */ 982 #define DST_R_BIT 0020000u /* data segment has been referenced */ 983 #define DST_SEGLEN_MASK 0017777u /* data segment length mask */ 984 #define DST_BANK_MASK 0000017u /* data segment bank mask */ 985 986 987 /* Segment Transfer Table accessors */ 988 989 #define STT_LENGTH_MASK 0000377u /* STT length mask */ 990 991 #define STT_LENGTH_SHIFT 0 /* STT length alignment shift */ 992 993 #define STT_LENGTH(l) (((l) & STT_LENGTH_MASK) >> STT_LENGTH_SHIFT) 994 995 996 /* Program label accessors */ 997 998 #define LABEL_EXTERNAL 0100000u /* external program label flag */ 999 #define LABEL_STTN_MASK 0077400u /* external program label STT number mask */ 1000 #define LABEL_SEGMENT_MASK 0000377u /* external program label segment mask */ 1001 1002 #define LABEL_STTN_SHIFT 8 /* STT number alignment shift */ 1003 #define LABEL_SEGMENT_SHIFT 0 /* segment number alignment shift */ 1004 1005 #define LABEL_LOCAL 0000000u /* local program label flag */ 1006 #define LABEL_UNCALLABLE 0040000u /* local program label uncallable flag */ 1007 #define LABEL_ADDRESS_MASK 0037777u /* local program label address mask */ 1008 1009 #define STT_NUMBER(l) (((l) & LABEL_STTN_MASK) >> LABEL_STTN_SHIFT) 1010 #define STT_SEGMENT(l) (((l) & LABEL_SEGMENT_MASK) >> LABEL_SEGMENT_SHIFT) 1011 1012 #define ISR_SEGMENT 1 /* segment number containing interrupt service routines */ 1013 1014 #define LABEL_IRQ (LABEL_EXTERNAL | ISR_SEGMENT) /* label for interrupt requests */ 1015 #define LABEL_STTN_MAX (LABEL_STTN_MASK >> LABEL_STTN_SHIFT) /* STT number maximum value */ 1016 1017 #define TO_LABEL(s,n) ((s) | (n) << LABEL_STTN_SHIFT) /* s = segment number, n = STT number */ 1018 1019 1020 /* Stack marker accessors */ 1021 1022 #define STMK_D 0100000u /* dispatcher flag */ 1023 #define STMK_T 0100000u /* trace flag */ 1024 #define STMK_M 0040000u /* mapped flag */ 1025 #define STMK_RTN_ADDR 0037777u /* PB-relative return address */ 1026 1027 1028 /* CPU registers */ 1029 1030 extern HP_WORD CIR; /* Current Instruction Register */ 1031 extern HP_WORD NIR; /* Next Instruction Register */ 1032 extern HP_WORD PB; /* Program Base Register */ 1033 extern HP_WORD P; /* Program Counter */ 1034 extern HP_WORD PL; /* Program Limit Register */ 1035 extern HP_WORD PBANK; /* Program Segment Bank Register */ 1036 extern HP_WORD DL; /* Data Limit Register */ 1037 extern HP_WORD DB; /* Data Base Register */ 1038 extern HP_WORD DBANK; /* Data Segment Bank Register */ 1039 extern HP_WORD Q; /* Stack Marker Register */ 1040 extern HP_WORD SM; /* Stack Memory Register */ 1041 extern HP_WORD SR; /* Stack Register Counter */ 1042 extern HP_WORD Z; /* Stack Limit Register */ 1043 extern HP_WORD SBANK; /* Stack Segment Bank Register */ 1044 extern HP_WORD TR [4]; /* Top of Stack Registers */ 1045 extern HP_WORD X; /* Index Register */ 1046 extern HP_WORD STA; /* Status Register */ 1047 extern HP_WORD SWCH; /* Switch Register */ 1048 extern HP_WORD CPX1; /* Run-Mode Interrupt Flags Register */ 1049 extern HP_WORD CPX2; /* Halt-Mode Interrupt Flags Register */ 1050 extern HP_WORD MOD; /* Module Control Register */ 1051 extern HP_WORD PCLK; /* Process Clock Register */ 1052 extern HP_WORD CNTR; /* Microcode Counter */ 1053 1054 1055 /* Top of stack register names */ 1056 1057 #define RA TR [0] 1058 #define RB TR [1] 1059 #define RC TR [2] 1060 #define RD TR [3] 1061 1062 1063 /* CPU device */ 1064 1065 extern DEVICE cpu_dev; /* Central Processing Unit */ 1066 1067 1068 /* CPU state */ 1069 1070 extern jmp_buf cpu_save_env; /* saved environment for microcode aborts */ 1071 extern POWER_STATE cpu_power_state; /* power supply state */ 1072 extern EXEC_STATE cpu_micro_state; /* micromachine execution state */ 1073 extern uint32 cpu_stop_flags; /* set of simulation stop flags */ 1074 extern t_bool cpu_base_changed; /* TRUE if any base register has been changed */ 1075 extern UNIT cpu_unit []; /* CPU unit array (needed for memory size) */ 1076 1077 1078 /* Condition Code B mapping table */ 1079 1080 extern const HP_WORD cpu_ccb_table [256]; /* byte-value to condition-code map */ 1081 1082 1083 /* Global CPU functions */ 1084 1085 extern void cpu_push (void); 1086 extern void cpu_pop (void); 1087 extern void cpu_queue_up (void); 1088 extern void cpu_queue_down (void); 1089 extern void cpu_flush (void); 1090 extern void cpu_adjust_sr (uint32 target); 1091 extern void cpu_mark_stack (void); 1092 1093 extern void cpu_ea (HP_WORD mode_disp, ACCESS_CLASS *class, HP_WORD *offset, BYTE_SELECTOR *selector); 1094 extern uint32 cpu_byte_ea (ACCESS_CLASS class, uint32 byte_offset, uint32 block_length); 1095 1096 extern void cpu_setup_irq_handler (IRQ_CLASS class, HP_WORD parameter); 1097 extern void cpu_setup_ics_irq (IRQ_CLASS class, TRAP_CLASS trap); 1098 extern void cpu_run_mode_interrupt (HP_WORD device_number); 1099 extern void cpu_setup_code_segment (HP_WORD label, HP_WORD *status, HP_WORD *entry_0); 1100 extern void cpu_setup_data_segment (HP_WORD segment_number, HP_WORD *bank, HP_WORD *address); 1101 extern void cpu_call_procedure (HP_WORD label, HP_WORD offset); 1102 extern void cpu_exit_procedure (HP_WORD new_q, HP_WORD new_sm, HP_WORD parameter); 1103 extern void cpu_start_dispatcher (void); 1104 extern void cpu_update_pclk (void); 1105 1106 1107 /* Global CPU instruction execution routines */ 1108 1109 extern t_bool cpu_interrupt_pending (t_stat *status); 1110 extern t_stat cpu_branch_short (t_bool check_loop); 1111 1112 extern HP_WORD cpu_add_16 (HP_WORD augend, HP_WORD addend); 1113 extern HP_WORD cpu_sub_16 (HP_WORD minuend, HP_WORD subtrahend); 1114 extern HP_WORD cpu_mpy_16 (HP_WORD multiplicand, HP_WORD multiplier); 1115 1116 extern t_stat cpu_stack_op (void); 1117 extern t_stat cpu_shift_branch_bit_op (void); 1118 extern t_stat cpu_move_spec_fw_imm_field_reg_op (void); 1119 extern t_stat cpu_io_cntl_prog_imm_mem_op (void); 1120 extern t_stat cpu_cis_op (void); 1121