1 /*
2  * QEMU AArch64 CPU
3  *
4  * Copyright (c) 2013 Linaro Ltd
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version 2
9  * of the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, see
18  * <http://www.gnu.org/licenses/gpl-2.0.html>
19  */
20 
21 #include "cpu.h"
22 #include "qemu-common.h"
23 #include "hw/arm/arm.h"
24 #include "sysemu/sysemu.h"
25 
set_feature(CPUARMState * env,int feature)26 static inline void set_feature(CPUARMState *env, int feature)
27 {
28     env->features |= 1ULL << feature;
29 }
30 
31 #ifndef CONFIG_USER_ONLY
a57_l2ctlr_read(CPUARMState * env,const ARMCPRegInfo * ri)32 static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
33 {
34     /* Number of processors is in [25:24]; otherwise we RAZ */
35     return (smp_cpus - 1) << 24;
36 }
37 #endif
38 
39 static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
40 #ifndef CONFIG_USER_ONLY
41     { "L2CTLR_EL1", 0,11,0, 3,1,2, ARM_CP_STATE_AA64,
42       0, PL1_RW, NULL, 0, 0,
43       NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
44     { "L2CTLR", 15,9,0, 0,1,2, 0,
45       0, PL1_RW, NULL, 0, 0,
46       NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
47 #endif
48     { "L2ECTLR_EL1", 0,11,0, 3,1,3, ARM_CP_STATE_AA64,
49       ARM_CP_CONST, PL1_RW, NULL, 0, },
50     { "L2ECTLR", 15,9,0, 0,1,3, 0,
51       ARM_CP_CONST, PL1_RW, NULL, 0, },
52     { "L2ACTLR", 0,15,0, 3,1,0, ARM_CP_STATE_BOTH,
53       ARM_CP_CONST, PL1_RW, NULL, 0 },
54     { "CPUACTLR_EL1", 0,15,2, 3,1,0, ARM_CP_STATE_AA64,
55       ARM_CP_CONST, PL1_RW, NULL, 0 },
56     { "CPUACTLR", 15,0,15, 0,0,0, 0,
57       ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, },
58     { "CPUECTLR_EL1", 0,15,2, 3,1,1, ARM_CP_STATE_AA64,
59       ARM_CP_CONST, PL1_RW, NULL, 0, },
60     { "CPUECTLR", 15,0,15, 0,1,0, 0,
61       ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, },
62     { "CPUMERRSR_EL1", 0,15,2, 3,1,2, ARM_CP_STATE_AA64,
63       ARM_CP_CONST, PL1_RW, NULL, 0 },
64     { "CPUMERRSR", 15,0,15, 0,2,0, 0,
65       ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0 },
66     { "L2MERRSR_EL1", 0,15,2, 3,1,3, ARM_CP_STATE_AA64,
67       ARM_CP_CONST, PL1_RW, NULL, 0 },
68     { "L2MERRSR", 15,0,15, 0,3,0, 0,
69       ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0 },
70     REGINFO_SENTINEL
71 };
72 
aarch64_a57_initfn(struct uc_struct * uc,Object * obj,void * opaque)73 static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
74 {
75     ARMCPU *cpu = ARM_CPU(uc, obj);
76 
77     set_feature(&cpu->env, ARM_FEATURE_V8);
78     set_feature(&cpu->env, ARM_FEATURE_VFP4);
79     set_feature(&cpu->env, ARM_FEATURE_NEON);
80     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
81     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
82     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
83     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
84     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
85     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
86     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
87     set_feature(&cpu->env, ARM_FEATURE_CRC);
88     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
89     cpu->midr = 0x411fd070;
90     cpu->reset_fpsid = 0x41034070;
91     cpu->mvfr0 = 0x10110222;
92     cpu->mvfr1 = 0x12111111;
93     cpu->mvfr2 = 0x00000043;
94     cpu->ctr = 0x8444c004;
95     cpu->reset_sctlr = 0x00c50838;
96     cpu->id_pfr0 = 0x00000131;
97     cpu->id_pfr1 = 0x00011011;
98     cpu->id_dfr0 = 0x03010066;
99     cpu->id_afr0 = 0x00000000;
100     cpu->id_mmfr0 = 0x10101105;
101     cpu->id_mmfr1 = 0x40000000;
102     cpu->id_mmfr2 = 0x01260000;
103     cpu->id_mmfr3 = 0x02102211;
104     cpu->id_isar0 = 0x02101110;
105     cpu->id_isar1 = 0x13112111;
106     cpu->id_isar2 = 0x21232042;
107     cpu->id_isar3 = 0x01112131;
108     cpu->id_isar4 = 0x00011142;
109     cpu->id_isar5 = 0x00011121;
110     cpu->id_aa64pfr0 = 0x00002222;
111     cpu->id_aa64dfr0 = 0x10305106;
112     cpu->id_aa64isar0 = 0x00011120;
113     cpu->id_aa64mmfr0 = 0x00001124;
114     cpu->dbgdidr = 0x3516d000;
115     cpu->clidr = 0x0a200023;
116     cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
117     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
118     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
119     cpu->dcz_blocksize = 4; /* 64 bytes */
120     define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
121 }
122 
123 #ifdef CONFIG_USER_ONLY
aarch64_any_initfn(struct uc_struct * uc,Object * obj,void * opaque)124 static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque)
125 {
126     ARMCPU *cpu = ARM_CPU(uc, obj);
127 
128     set_feature(&cpu->env, ARM_FEATURE_V8);
129     set_feature(&cpu->env, ARM_FEATURE_VFP4);
130     set_feature(&cpu->env, ARM_FEATURE_NEON);
131     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
132     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
133     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
134     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
135     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
136     set_feature(&cpu->env, ARM_FEATURE_CRC);
137     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
138     cpu->dcz_blocksize = 7; /*  512 bytes */
139 }
140 #endif
141 
142 typedef struct ARMCPUInfo {
143     const char *name;
144     void (*initfn)(struct uc_struct *uc, Object *obj, void *opaque);
145     void (*class_init)(struct uc_struct *uc, ObjectClass *oc, void *data);
146 } ARMCPUInfo;
147 
148 static const ARMCPUInfo aarch64_cpus[] = {
149     { "cortex-a57",  aarch64_a57_initfn },
150 #ifdef CONFIG_USER_ONLY
151     { "any",         aarch64_any_initfn },
152 #endif
153     { NULL }
154 };
155 
aarch64_cpu_initfn(struct uc_struct * uc,Object * obj,void * opaque)156 static void aarch64_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
157 {
158 }
159 
aarch64_cpu_finalizefn(struct uc_struct * uc,Object * obj,void * opaque)160 static void aarch64_cpu_finalizefn(struct uc_struct *uc, Object *obj, void *opaque)
161 {
162 }
163 
aarch64_cpu_set_pc(CPUState * cs,vaddr value)164 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
165 {
166     //CPUARMState *env = cs->env_ptr;
167     ARMCPU *cpu = ARM_CPU(NULL, cs);
168     /* It's OK to look at env for the current mode here, because it's
169      * never possible for an AArch64 TB to chain to an AArch32 TB.
170      * (Otherwise we would need to use synchronize_from_tb instead.)
171      */
172     if (is_a64(&cpu->env)) {
173         cpu->env.pc = value;
174     } else {
175         cpu->env.regs[15] = value;
176     }
177 }
178 
aarch64_cpu_class_init(struct uc_struct * uc,ObjectClass * oc,void * data)179 static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
180 {
181     CPUClass *cc = CPU_CLASS(uc, oc);
182 
183 #if !defined(CONFIG_USER_ONLY)
184     cc->do_interrupt = aarch64_cpu_do_interrupt;
185 #endif
186     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
187     cc->set_pc = aarch64_cpu_set_pc;
188 }
189 
aarch64_cpu_register(struct uc_struct * uc,const ARMCPUInfo * info)190 static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
191 {
192     TypeInfo type_info = { 0 };
193     type_info.parent = TYPE_AARCH64_CPU;
194     type_info.instance_size = sizeof(ARMCPU);
195     type_info.instance_init = info->initfn;
196     type_info.class_size = sizeof(ARMCPUClass);
197     type_info.class_init = info->class_init;
198 
199     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
200     type_register(uc, &type_info);
201     g_free((void *)type_info.name);
202 }
203 
aarch64_cpu_register_types(void * opaque)204 void aarch64_cpu_register_types(void *opaque)
205 {
206     const ARMCPUInfo *info = aarch64_cpus;
207 
208     static TypeInfo aarch64_cpu_type_info = { 0 };
209     aarch64_cpu_type_info.name = TYPE_AARCH64_CPU;
210     aarch64_cpu_type_info.parent = TYPE_ARM_CPU;
211     aarch64_cpu_type_info.instance_size = sizeof(ARMCPU);
212     aarch64_cpu_type_info.instance_init = aarch64_cpu_initfn;
213     aarch64_cpu_type_info.instance_finalize = aarch64_cpu_finalizefn;
214     aarch64_cpu_type_info.abstract = true;
215     aarch64_cpu_type_info.class_size = sizeof(AArch64CPUClass);
216     aarch64_cpu_type_info.class_init = aarch64_cpu_class_init;
217 
218     type_register_static(opaque, &aarch64_cpu_type_info);
219 
220     while (info->name) {
221         aarch64_cpu_register(opaque, info);
222         info++;
223     }
224 }
225