1 /* Definitions to support the system control coprocessor. 2 Copyright 2001, 2003 Brian R. Gaeke. 3 4 This file is part of VMIPS. 5 6 VMIPS is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the 8 Free Software Foundation; either version 2 of the License, or (at your 9 option) any later version. 10 11 VMIPS is distributed in the hope that it will be useful, but 12 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License along 17 with VMIPS; if not, write to the Free Software Foundation, Inc., 18 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ 19 20 #ifndef _CPZERO_H_ 21 #define _CPZERO_H_ 22 23 #include "tlbentry.h" 24 #include <cstdio> 25 class CPU; 26 class DeviceExc; 27 class IntCtrl; 28 29 #define TLB_ENTRIES 64 30 31 class CPZero 32 { 33 TLBEntry tlb[TLB_ENTRIES]; 34 uint32 reg[32]; 35 CPU *cpu; 36 IntCtrl *intc; 37 38 // Return TRUE if interrupts are enabled, FALSE otherwise. 39 bool interrupts_enabled(void) const; 40 41 // Return TRUE if the cpu is running in kernel mode, FALSE otherwise. 42 bool kernel_mode(void) const; 43 44 // Return the currently pending interrupts. 45 uint32 getIP(void); 46 47 void mfc0_emulate(uint32 instr, uint32 pc); 48 void mtc0_emulate(uint32 instr, uint32 pc); 49 void bc0x_emulate(uint32 instr, uint32 pc); 50 void tlbr_emulate(uint32 instr, uint32 pc); 51 void tlbwi_emulate(uint32 instr, uint32 pc); 52 void tlbwr_emulate(uint32 instr, uint32 pc); 53 void tlbp_emulate(uint32 instr, uint32 pc); 54 void rfe_emulate(uint32 instr, uint32 pc); 55 void load_addr_trans_excp_info(uint32 va, uint32 vpn, TLBEntry *match); 56 int find_matching_tlb_entry(uint32 vpn, uint32 asid); 57 uint32 tlb_translate(uint32 seg, uint32 vaddr, int mode, 58 bool *cacheable, DeviceExc *client); 59 60 public: 61 bool tlb_miss_user; 62 63 // Write TLB entry number INDEX with the contents of the EntryHi 64 // and EntryLo registers. 65 void tlb_write(unsigned index); 66 67 // Return the contents of the readable bits of register REG. 68 uint32 read_reg(const uint16 regno); 69 70 // Change the contents of the writable bits of register REG to NEW_DATA. 71 void write_reg(const uint16 regno, const uint32 new_data); 72 73 /* Convention says that CP0's condition is TRUE if the memory 74 write-back buffer is empty. Because memory writes are fast as far 75 as the emulation is concerned, the write buffer is always empty 76 for CP0. */ cpCond()77 bool cpCond() const { return true; } 78 CPZero(CPU * m,IntCtrl * i)79 CPZero(CPU *m, IntCtrl *i) : cpu (m), intc (i) { } 80 void reset(void); 81 82 /* Request to translate virtual address VADDR, while the processor is 83 in mode MODE to a physical address. CLIENT is the entity that will 84 recieve any interrupts generated by the attempted translation. On 85 return CACHEABLE will be set to TRUE if the returned address is 86 cacheable, it will be set to FALSE otherwise. Returns the physical 87 address corresponding to VADDR if such a translation is possible, 88 otherwise an interrupt is raised with CLIENT and the return value 89 is undefined. */ 90 uint32 address_trans(uint32 vaddr, int mode, bool *cacheable, 91 DeviceExc *client); 92 93 void enter_exception(uint32 pc, uint32 excCode, uint32 ce, bool dly); 94 bool use_boot_excp_address(void); 95 bool caches_isolated(void); 96 97 /* Return TRUE if the instruction and data caches are swapped, 98 FALSE otherwise. */ 99 bool caches_swapped(void); 100 101 bool cop_usable (int coprocno); 102 void cpzero_emulate(uint32 instr, uint32 pc); 103 104 // Write the state of the CP0 registers to stream F. 105 void dump_regs(FILE *f); 106 107 // Write the state of the TLB to stream F. 108 void dump_tlb(FILE *f); 109 110 // Write the state of the CP0 registers and the TLB to stream F. 111 void dump_regs_and_tlb(FILE *f); 112 113 /* Change the CP0 random register after an instruction step. */ 114 void adjust_random(void); 115 116 /* Return TRUE if there is an interrupt which should be handled 117 at the next available opportunity, FALSE otherwise. */ 118 bool interrupt_pending(void); 119 120 void read_debug_info(uint32 *status, uint32 *bad, uint32 *cause); 121 void write_debug_info(uint32 status, uint32 bad, uint32 cause); 122 123 /* TLB translate VADDR without exceptions. Returns true if a valid 124 TLB mapping is found, false otherwise. If VADDR has no valid 125 mapping, PADDR is written with 0xffffffff, otherwise it is written 126 with the translation. */ 127 bool debug_tlb_translate(uint32 vaddr, uint32 *paddr); 128 }; 129 130 #endif /* _CPZERO_H_ */ 131