1 /* Useful constants for system control coprocessor registers. 2 Copyright 2001, 2002 Brian R. Gaeke. 3 4 This file is part of VMIPS. 5 6 VMIPS is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the 8 Free Software Foundation; either version 2 of the License, or (at your 9 option) any later version. 10 11 VMIPS is distributed in the hope that it will be useful, but 12 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License along 17 with VMIPS; if not, write to the Free Software Foundation, Inc., 18 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ 19 20 #ifndef _CPZEROREG_H_ 21 #define _CPZEROREG_H_ 22 23 /* Constants for virtual address translation. 24 * 25 * Some of these are used as masks and some are used as constant 26 * translations (i.e., the address of something is the address of 27 * something else plus or minus a translation). The desired effect is 28 * to reduce the number of random "magic numbers" floating around... 29 */ 30 31 #define KSEG_SELECT_MASK 0xe0000000 /* bits of address which determine seg. */ 32 #define KUSEG 0 /* not really a mask, but user space begins here */ 33 #define KERNEL_SPACE_MASK 0x80000000 /* beginning of kernel space */ 34 #define KSEG0 0x80000000 /* beginning of unmapped cached kernel segment */ 35 #define KSEG0_CONST_TRANSLATION 0x80000000 /* kseg0 v->p address difference */ 36 #define KSEG1 0xa0000000 /* beginning of unmapped uncached kernel segment */ 37 #define KSEG1_CONST_TRANSLATION 0xa0000000 /* kseg1 v->p address difference */ 38 #define KSEG2 0xc0000000 /* beginning of mapped cached kernel segment */ 39 #define KSEG2_top 0xe0000000 /* 2nd half of mapped cached kernel segment */ 40 41 /* CP0 register names and masks 42 * 43 * A table of names for CP0's registers follows. After that follow a 44 * series of masks by which fields of these registers can be isolated. 45 * The masks are convenient for Boolean flags but are slightly less so 46 * for numbers being extracted from the middle of a word because they 47 * still need to be shifted. At least, it makes clear which field is 48 * being accessed, and the bit numbers are clearly indicated in every mask 49 * below. The naming convention is as follows: Mumble is the name of some 50 * CP0 register, Mumble_MASK is the bit mask which controls reading and 51 * writing of the register (0 -> bit is always zero and ignores writes, 52 * 1 -> normal read/write) and Mumble_Field_MASK is the mask used to 53 * access the "Field" portion of register Mumble. For more information 54 * on these fields consult "MIPS RISC Architecture", chapters 4 and 6. 55 */ 56 57 #define Index 0 /* selects TLB entry for r/w ops & shows probe success */ 58 #define Random 1 /* continuously decrementing number (range 8..63) */ 59 #define EntryLo 2 /* low word of a TLB entry */ 60 #define EntryLo0 2 /* R4k uses this for even-numbered virtual pages */ 61 #define EntryLo1 3 /* R4k uses this for odd-numbered virtual pages */ 62 #define Context 4 /* TLB refill handler's kernel PTE entry pointer */ 63 #define PageMask 5 /* R4k page number bit mask (impl. variable page sizes) */ 64 #define Wired 6 /* R4k lower bnd for Random (controls randomness of TLB) */ 65 #define Error 7 /* R6k status/control register for parity checking */ 66 #define BadVAddr 8 /* "bad" virt. addr (VA of last failed v->p translation) */ 67 #define Count 9 /* R4k r/w reg - continuously incrementing counter */ 68 #define EntryHi 10 /* High word of a TLB entry */ 69 #define ASID 10 /* R6k uses this to store the ASID (only) */ 70 #define Compare 11 /* R4k traps when this register equals Count */ 71 #define Status 12 /* Kernel/User mode, interrupt enb., & diagnostic states */ 72 #define Cause 13 /* Cause of last exception */ 73 #define EPC 14 /* Address to return to after processing this exception */ 74 #define PRId 15 /* Processor revision identifier */ 75 #define Config 16 /* R4k config options for caches, etc. */ 76 #define LLAdr 17 /* R4k last instruction read by a Load Linked */ 77 #define LLAddr 17 /* Inconsistencies in naming... sigh. */ 78 #define WatchLo 18 /* R4k hardware watchpoint data */ 79 #define WatchHi 19 /* R4k hardware watchpoint data */ 80 /* 20-25 - reserved */ 81 #define ECC 26 /* R4k cache Error Correction Code */ 82 #define CacheErr 27 /* R4k read-only cache error codes */ 83 #define TagLo 28 /* R4k primary or secondary cache tag and parity */ 84 #define TagHi 29 /* R4k primary or secondary cache tag and parity */ 85 #define ErrorEPC 30 /* R4k cache error EPC */ 86 /* 31 - reserved */ 87 88 /* (0) Index fields */ 89 #define Index_P_MASK 0x80000000 /* Last TLB Probe instr failed (31) */ 90 #define Index_Index_MASK 0x00003f00 /* TLB entry to read/write next (13-8) */ 91 #define Index_MASK 0x80003f00 92 93 /* (1) Random fields */ 94 #define Random_Random_MASK 0x00003f00 /* TLB entry to replace next (13-8) */ 95 #define Random_MASK 0x00003f00 96 /* Random register upper and lower bounds (R3000) */ 97 #define Random_UPPER_BOUND 63 98 #define Random_LOWER_BOUND 8 99 100 /* (2) EntryLo fields */ 101 #define EntryLo_PFN_MASK 0xfffff000 /* Page frame number (31-12) */ 102 #define EntryLo_N_MASK 0x00000800 /* Noncacheable (11) */ 103 #define EntryLo_D_MASK 0x00000400 /* Dirty (10) */ 104 #define EntryLo_V_MASK 0x00000200 /* Valid (9) */ 105 #define EntryLo_G_MASK 0x00000100 /* Global (8) */ 106 #define EntryLo_MASK 0xffffff00 107 108 /* (4) Context fields */ 109 #define Context_PTEBase_MASK 0xffe00000 /* Page Table Base (31-21) */ 110 #define Context_BadVPN_MASK 0x001ffffc /* Bad Virtual Page num. (20-2) */ 111 #define Context_MASK 0xfffffffc 112 113 /* (5) PageMask is only on the R4k */ 114 #define PageMask_MASK 0x00000000 115 116 /* (6) Wired is only on the R4k */ 117 #define Wired_MASK 0x00000000 118 119 /* (7) Error is only on the R6k */ 120 #define Error_MASK 0x00000000 121 122 /* (8) BadVAddr has only one field */ 123 #define BadVAddr_MASK 0xffffffff 124 125 /* (9) Count is only on the R4k */ 126 #define Count_MASK 0x00000000 127 128 /* (10) EntryHi fields */ 129 #define EntryHi_VPN_MASK 0xfffff000 /* Virtual page no. (31-12) */ 130 #define EntryHi_ASID_MASK 0x00000fc0 /* Current ASID (11-6) */ 131 #define EntryHi_MASK 0xffffffc0 132 133 /* (11) Compare is only on the R4k */ 134 #define Compare_MASK 0x00000000 135 136 /* (12) Status fields */ 137 #define Status_CU_MASK 0xf0000000 /* Coprocessor (3..0) Usable (31-28) */ 138 #define Status_CU3_MASK 0x80000000 /* Coprocessor 3 Usable (31) */ 139 #define Status_CU2_MASK 0x40000000 /* Coprocessor 2 Usable (30) */ 140 #define Status_CU1_MASK 0x20000000 /* Coprocessor 1 Usable (29) */ 141 #define Status_CU0_MASK 0x10000000 /* Coprocessor 0 Usable (28) */ 142 #define Status_RE_MASK 0x02000000 /* Reverse Endian (R3000A/R6000) (25) */ 143 #define Status_DS_MASK 0x01ff0000 /* Diagnostic Status (24-16) */ 144 #define Status_DS_BEV_MASK 0x00400000 /* Bootstrap Exception Vector (22) */ 145 #define Status_DS_TS_MASK 0x00200000 /* TLB Shutdown (21) */ 146 #define Status_DS_PE_MASK 0x00100000 /* Cache Parity Error (20) */ 147 #define Status_DS_CM_MASK 0x00080000 /* Cache miss (19) */ 148 #define Status_DS_PZ_MASK 0x00040000 /* Cache parity forced to zero (18) */ 149 #define Status_DS_SwC_MASK 0x00020000 /* Data/Inst cache switched (17) */ 150 #define Status_DS_IsC_MASK 0x00010000 /* Cache isolated (16) */ 151 #define Status_IM_MASK 0x0000ff00 /* Interrupt Mask (15-8) */ 152 #define Status_IM_Ext_MASK 0x0000fc00 /* Extrn. (HW) Interrupt Mask (15-10) */ 153 #define Status_IM_SW_MASK 0x00000300 /* Software Interrupt Mask (9-8) */ 154 #define Status_KU_IE_MASK 0x0000003f /* Kernel/User & Int Enable bits (5-0) */ 155 #define Status_KUo_MASK 0x00000020 /* Old Kernel/User status (5) */ 156 #define Status_IEo_MASK 0x00000010 /* Old Interrupt Enable status (4) */ 157 #define Status_KUp_MASK 0x00000008 /* Previous Kernel/User status (3) */ 158 #define Status_IEp_MASK 0x00000004 /* Previous Interrupt Enable status (2) */ 159 #define Status_KUc_MASK 0x00000002 /* Current Kernel/User status (1) */ 160 #define Status_IEc_MASK 0x00000001 /* Current Interrupt Enable status (0) */ 161 #define Status_MASK 0xf27fff3f 162 163 /* (13) Cause fields */ 164 #define Cause_BD_MASK 0x80000000 /* Branch Delay (31) */ 165 #define Cause_CE_MASK 0x30000000 /* Coprocessor Error (29-28) */ 166 #define Cause_IP_MASK 0x0000ff00 /* Interrupt Pending (15-8) */ 167 #define Cause_IP_Ext_MASK 0x0000fc00 /* External (HW) ints IP(7-2) (15-10) */ 168 #define Cause_IP_SW_MASK 0x00000300 /* Software ints IP(1-0) (9-8) */ 169 #define Cause_ExcCode_MASK 0x0000007c /* Exception Code (6-2) */ 170 #define Cause_MASK 0xb000ff7c 171 172 /* (14) EPC has only one field */ 173 #define EPC_MASK 0xffffffff 174 175 /* (15) PRId fields */ 176 #define PRId_Imp_MASK 0x0000ff00 /* Implementation (15-8) */ 177 #define PRId_Rev_MASK 0x000000ff /* Revision (7-0) */ 178 #define PRId_MASK 0x0000ffff 179 180 /* (16) Config is only on the R4k */ 181 #define Config_MASK 0x00000000 182 183 /* (17) LLAddr is only on the R4k */ 184 #define LLAddr_MASK 0x00000000 185 186 /* (18) WatchLo is only on the R4k */ 187 #define WatchLo_MASK 0x00000000 188 189 /* (19) WatchHi is only on the R4k */ 190 #define WatchHi_MASK 0x00000000 191 192 /* (20-25) reserved */ 193 194 /* (26) ECC is only on the R4k */ 195 #define ECC_MASK 0x00000000 196 197 /* (27) CacheErr is only on the R4k */ 198 #define CacheErr_MASK 0x00000000 199 200 /* (28) TagLo is only on the R4k */ 201 #define TagLo_MASK 0x00000000 202 203 /* (29) TagHi is only on the R4k */ 204 #define TagHi_MASK 0x00000000 205 206 /* (30) ErrorEPC is only on the R4k */ 207 #define ErrorEPC_MASK 0x00000000 208 209 /* (31) reserved */ 210 211 #endif /* _CPZEROREG_H_ */ 212