1 /*
2 must fix:
3 callm
4 chk
5 */
6 /* ======================================================================== */
7 /* ========================= LICENSING & COPYRIGHT ======================== */
8 /* ======================================================================== */
9 /*
10 * MUSASHI
11 * Version 3.31
12 *
13 * A portable Motorola M680x0 processor emulation engine.
14 * Copyright 1998-2007 Karl Stenerud. All rights reserved.
15 *
16 * This code may be freely used for non-commercial purposes as long as this
17 * copyright notice remains unaltered in the source code and any binary files
18 * containing this code in compiled form.
19 *
20 * All other lisencing terms must be negotiated with the author
21 * (Karl Stenerud).
22 *
23 * The latest version of this code can be obtained at:
24 * http://kstenerud.cjb.net
25 */
26
27 /* Special thanks to Bart Trzynadlowski for his insight into the
28 * undocumented features of this chip:
29 *
30 * http://dynarec.com/~bart/files/68knotes.txt
31 */
32
33
34 /* Input file for m68kmake
35 * -----------------------
36 *
37 * All sections begin with 80 X's in a row followed by an end-of-line
38 * sequence.
39 * After this, m68kmake will expect to find one of the following section
40 * identifiers:
41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
45 * M68KMAKE_TABLE_BODY - the table itself
46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
49 *
50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
51 * M68KMAKE_TABLE_BODY must be second last in the file.
52 *
53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
54 * primitives themselves. Each opcode handler begins with:
55 * M68KMAKE_OP(A, B, C, D)
56 *
57 * where A is the opcode handler name, B is the size of the operation,
58 * C denotes any special processing mode, and D denotes a specific
59 * addressing mode.
60 * For C and D where nothing is specified, use "."
61 *
62 * Example:
63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
66 *
67 * All opcode handler primitives end with a closing curly brace "}" at column 1
68 *
69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
70 * and do not put a closing curly brace at column 1 unless it is
71 * marking the end of the handler!
72 *
73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
75 * opcode handlers to handle variations in the opcode handler.
76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
78 * be interpreted on instructions where the corresponding table entry
79 * specifies multiple effective addressing modes.
80 * Example:
81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
82 *
83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
86 */
87
88 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
89 M68KMAKE_PROTOTYPE_HEADER
90
91 #ifndef M68KOPS__HEADER
92 #define M68KOPS__HEADER
93
94 /* ======================================================================== */
95 /* ============================ OPCODE HANDLERS =========================== */
96 /* ======================================================================== */
97
98
99
100 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
101 M68KMAKE_PROTOTYPE_FOOTER
102
103
104 /* Build the opcode handler table */
105 void m68ki_build_opcode_table(void);
106
107 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
108 extern unsigned char m68ki_cycles[][0x10000];
109
110
111 /* ======================================================================== */
112 /* ============================== END OF FILE ============================= */
113 /* ======================================================================== */
114
115 #endif /* M68KOPS__HEADER */
116
117
118
119 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
120 M68KMAKE_TABLE_HEADER
121
122 /* ======================================================================== */
123 /* ========================= OPCODE TABLE BUILDER ========================= */
124 /* ======================================================================== */
125
126 #include "m68kops.h"
127
128 #define NUM_CPU_TYPES 4
129
130 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
131 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
132
133 /* This is used to generate the opcode handler jump table */
134 typedef struct
135 {
136 void (*opcode_handler)(void); /* handler function */
137 unsigned int mask; /* mask on opcode */
138 unsigned int match; /* what to match after masking */
139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
140 } opcode_handler_struct;
141
142
143 /* Opcode handler table */
144 static opcode_handler_struct m68k_opcode_handler_table[] =
145 {
146 /* function mask match 000 010 020 040 */
147
148
149
150 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
151 M68KMAKE_TABLE_FOOTER
152
153 {0, 0, 0, {0, 0, 0, 0}}
154 };
155
156
157 /* Build the opcode handler jump table */
m68ki_build_opcode_table(void)158 void m68ki_build_opcode_table(void)
159 {
160 opcode_handler_struct *ostruct;
161 int instr;
162 int i;
163 int j;
164 int k;
165
166 for(i = 0; i < 0x10000; i++)
167 {
168 /* default to illegal */
169 m68ki_instruction_jump_table[i] = m68k_op_illegal;
170 for(k=0;k<NUM_CPU_TYPES;k++)
171 m68ki_cycles[k][i] = 0;
172 }
173
174 ostruct = m68k_opcode_handler_table;
175 while(ostruct->mask != 0xff00)
176 {
177 for(i = 0;i < 0x10000;i++)
178 {
179 if((i & ostruct->mask) == ostruct->match)
180 {
181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
182 for(k=0;k<NUM_CPU_TYPES;k++)
183 m68ki_cycles[k][i] = ostruct->cycles[k];
184 }
185 }
186 ostruct++;
187 }
188 while(ostruct->mask == 0xff00)
189 {
190 for(i = 0;i <= 0xff;i++)
191 {
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
193 for(k=0;k<NUM_CPU_TYPES;k++)
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
195 }
196 ostruct++;
197 }
198 while(ostruct->mask == 0xf1f8)
199 {
200 for(i = 0;i < 8;i++)
201 {
202 for(j = 0;j < 8;j++)
203 {
204 instr = ostruct->match | (i << 9) | j;
205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
206 for(k=0;k<NUM_CPU_TYPES;k++)
207 m68ki_cycles[k][instr] = ostruct->cycles[k];
208 }
209 }
210 ostruct++;
211 }
212 while(ostruct->mask == 0xfff0)
213 {
214 for(i = 0;i <= 0x0f;i++)
215 {
216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
217 for(k=0;k<NUM_CPU_TYPES;k++)
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
219 }
220 ostruct++;
221 }
222 while(ostruct->mask == 0xf1ff)
223 {
224 for(i = 0;i <= 0x07;i++)
225 {
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
227 for(k=0;k<NUM_CPU_TYPES;k++)
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
229 }
230 ostruct++;
231 }
232 while(ostruct->mask == 0xfff8)
233 {
234 for(i = 0;i <= 0x07;i++)
235 {
236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
237 for(k=0;k<NUM_CPU_TYPES;k++)
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
239 }
240 ostruct++;
241 }
242 while(ostruct->mask == 0xffff)
243 {
244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
245 for(k=0;k<NUM_CPU_TYPES;k++)
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
247 ostruct++;
248 }
249 }
250
251
252 /* ======================================================================== */
253 /* ============================== END OF FILE ============================= */
254 /* ======================================================================== */
255
256
257
258 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
259 M68KMAKE_OPCODE_HANDLER_HEADER
260
261 #include "m68kcpu.h"
262 extern void m68040_fpu_op0(void);
263 extern void m68040_fpu_op1(void);
264
265 /* ======================================================================== */
266 /* ========================= INSTRUCTION HANDLERS ========================= */
267 /* ======================================================================== */
268
269
270
271 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
272 M68KMAKE_OPCODE_HANDLER_FOOTER
273
274 /* ======================================================================== */
275 /* ============================== END OF FILE ============================= */
276 /* ======================================================================== */
277
278
279
280 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
281 M68KMAKE_TABLE_BODY
282
283 The following table is arranged as follows:
284
285 name: Opcode mnemonic
286
287 size: Operation size
288
289 spec proc: Special processing mode:
290 .: normal
291 s: static operand
292 r: register operand
293 rr: register to register
294 mm: memory to memory
295 er: effective address to register
296 re: register to effective address
297 dd: data register to data register
298 da: data register to address register
299 aa: address register to address register
300 cr: control register to register
301 rc: register to control register
302 toc: to condition code register
303 tos: to status register
304 tou: to user stack pointer
305 frc: from condition code register
306 frs: from status register
307 fru: from user stack pointer
308 * for move.x, the special processing mode is a specific
309 destination effective addressing mode.
310
311 spec ea: Specific effective addressing mode:
312 .: normal
313 i: immediate
314 d: data register
315 a: address register
316 ai: address register indirect
317 pi: address register indirect with postincrement
318 pd: address register indirect with predecrement
319 di: address register indirect with displacement
320 ix: address register indirect with index
321 aw: absolute word address
322 al: absolute long address
323 pcdi: program counter relative with displacement
324 pcix: program counter relative with index
325 a7: register specified in instruction is A7
326 ax7: register field X of instruction is A7
327 ay7: register field Y of instruction is A7
328 axy7: register fields X and Y of instruction are A7
329
330 bit pattern: Pattern to recognize this opcode. "." means don't care.
331
332 allowed ea: List of allowed addressing modes:
333 .: not present
334 A: address register indirect
335 +: ARI (address register indirect) with postincrement
336 -: ARI with predecrement
337 D: ARI with displacement
338 X: ARI with index
339 W: absolute word address
340 L: absolute long address
341 d: program counter indirect with displacement
342 x: program counter indirect with index
343 I: immediate
344 mode: CPU operating mode for each cpu type. U = user or supervisor,
345 S = supervisor only, "." = opcode not present.
346
347 cpu cycles: Base number of cycles required to execute this opcode on the
348 specified CPU type.
349 Use "." if CPU does not have this opcode.
350
351
352
353 spec spec allowed ea mode cpu cycles
354 name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments
355 ====== ==== ==== ==== ================ ========== = = = = === === === === =============
356 M68KMAKE_TABLE_START
357 1010 0 . . 1010............ .......... U U U U 4 4 4 4
358 1111 0 . . 1111............ .......... U U U U 4 4 4 4
359 040fpu0 32 . . 11110010........ .......... . . . U . . . 0
360 040fpu1 32 . . 11110011........ .......... . . . U . . . 0
361 abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4
362 abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16
363 abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16
364 abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16
365 abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16
366 add 8 er d 1101...000000... .......... U U U U 4 4 2 2
367 add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2
368 add 16 er d 1101...001000... .......... U U U U 4 4 2 2
369 add 16 er a 1101...001001... .......... U U U U 4 4 2 2
370 add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2
371 add 32 er d 1101...010000... .......... U U U U 6 6 2 2
372 add 32 er a 1101...010001... .......... U U U U 6 6 2 2
373 add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2
374 add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4
375 add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4
376 add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4
377 adda 16 . d 1101...011000... .......... U U U U 8 8 2 2
378 adda 16 . a 1101...011001... .......... U U U U 8 8 2 2
379 adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2
380 adda 32 . d 1101...111000... .......... U U U U 6 6 2 2
381 adda 32 . a 1101...111001... .......... U U U U 6 6 2 2
382 adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2
383 addi 8 . d 0000011000000... .......... U U U U 8 8 2 2
384 addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4
385 addi 16 . d 0000011001000... .......... U U U U 8 8 2 2
386 addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4
387 addi 32 . d 0000011010000... .......... U U U U 16 14 2 2
388 addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4
389 addq 8 . d 0101...000000... .......... U U U U 4 4 2 2
390 addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4
391 addq 16 . d 0101...001000... .......... U U U U 4 4 2 2
392 addq 16 . a 0101...001001... .......... U U U U 4 4 2 2
393 addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4
394 addq 32 . d 0101...010000... .......... U U U U 8 8 2 2
395 addq 32 . a 0101...010001... .......... U U U U 8 8 2 2
396 addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4
397 addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2
398 addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2
399 addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2
400 addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12
401 addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12
402 addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12
403 addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12
404 addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12
405 addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12
406 and 8 er d 1100...000000... .......... U U U U 4 4 2 2
407 and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2
408 and 16 er d 1100...001000... .......... U U U U 4 4 2 2
409 and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2
410 and 32 er d 1100...010000... .......... U U U U 6 6 2 2
411 and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2
412 and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4
413 and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4
414 and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4
415 andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12
416 andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12
417 andi 8 . d 0000001000000... .......... U U U U 8 8 2 2
418 andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4
419 andi 16 . d 0000001001000... .......... U U U U 8 8 2 2
420 andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4
421 andi 32 . d 0000001010000... .......... U U U U 14 14 2 2
422 andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4
423 asr 8 s . 1110...000000... .......... U U U U 6 6 6 6
424 asr 16 s . 1110...001000... .......... U U U U 6 6 6 6
425 asr 32 s . 1110...010000... .......... U U U U 8 8 6 6
426 asr 8 r . 1110...000100... .......... U U U U 6 6 6 6
427 asr 16 r . 1110...001100... .......... U U U U 6 6 6 6
428 asr 32 r . 1110...010100... .......... U U U U 8 8 6 6
429 asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5
430 asl 8 s . 1110...100000... .......... U U U U 6 6 8 8
431 asl 16 s . 1110...101000... .......... U U U U 6 6 8 8
432 asl 32 s . 1110...110000... .......... U U U U 8 8 8 8
433 asl 8 r . 1110...100100... .......... U U U U 6 6 8 8
434 asl 16 r . 1110...101100... .......... U U U U 6 6 8 8
435 asl 32 r . 1110...110100... .......... U U U U 8 8 8 8
436 asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6
437 bcc 8 . . 0110............ .......... U U U U 10 10 6 6
438 bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6
439 bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6
440 bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4
441 bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4
442 bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4
443 bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4
444 bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4
445 bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4
446 bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4
447 bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4
448 bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct
449 bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20
450 bfclr 32 . d 1110110011000... .......... . . U U . . 12 12
451 bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20
452 bfexts 32 . d 1110101111000... .......... . . U U . . 8 8
453 bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15
454 bfextu 32 . d 1110100111000... .......... . . U U . . 8 8
455 bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15
456 bfffo 32 . d 1110110111000... .......... . . U U . . 18 18
457 bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28
458 bfins 32 . d 1110111111000... .......... . . U U . . 10 10
459 bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17
460 bfset 32 . d 1110111011000... .......... . . U U . . 12 12
461 bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20
462 bftst 32 . d 1110100011000... .......... . . U U . . 6 6
463 bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13
464 bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10
465 bra 8 . . 01100000........ .......... U U U U 10 10 10 10
466 bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10
467 bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10
468 bset 32 r d 0000...111000... .......... U U U U 8 8 4 4
469 bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4
470 bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4
471 bset 32 s d 0000100011000... .......... U U U U 12 12 4 4
472 bsr 8 . . 01100001........ .......... U U U U 18 18 7 7
473 bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7
474 bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7
475 btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4
476 btst 32 r d 0000...100000... .......... U U U U 6 6 4 4
477 btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4
478 btst 32 s d 0000100000000... .......... U U U U 10 10 4 4
479 callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated
480 cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12
481 cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12
482 cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12
483 cas2 16 . . 0000110011111100 .......... . . U U . . 12 12
484 cas2 32 . . 0000111011111100 .......... . . U U . . 12 12
485 chk 16 . d 0100...110000... .......... U U U U 10 8 8 8
486 chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8
487 chk 32 . d 0100...100000... .......... . . U U . . 8 8
488 chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8
489 chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23
490 chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23
491 chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18
492 chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23
493 chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23
494 chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18
495 chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
496 chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
497 chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
498 clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
499 clr 8 . . 0100001000...... A+-DXWL... U U U U 8 4 4 4
500 clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
501 clr 16 . . 0100001001...... A+-DXWL... U U U U 8 4 4 4
502 clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
503 clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
504 cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
505 cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2
506 cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2
507 cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2
508 cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2
509 cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2
510 cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2
511 cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2
512 cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4
513 cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4
514 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4
515 cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4
516 cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4
517 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4
518 cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2
519 cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2
520 cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7
521 cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9
522 cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2
523 cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2
524 cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7
525 cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9
526 cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2
527 cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2
528 cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7
529 cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9
530 cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9
531 cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9
532 cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9
533 cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9
534 cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9
535 cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9
536 cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated
537 cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated
538 cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated
539 cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated
540 cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated
541 dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6
542 dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6
543 dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6
544 divs 16 . d 1000...111000... .......... U U U U 158 122 56 56
545 divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56
546 divu 16 . d 1000...011000... .......... U U U U 140 108 44 44
547 divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44
548 divl 32 . d 0100110001000... .......... . . U U . . 84 84
549 divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84
550 eor 8 . d 1011...100000... .......... U U U U 4 4 2 2
551 eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4
552 eor 16 . d 1011...101000... .......... U U U U 4 4 2 2
553 eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4
554 eor 32 . d 1011...110000... .......... U U U U 8 6 2 2
555 eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4
556 eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12
557 eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12
558 eori 8 . d 0000101000000... .......... U U U U 8 8 2 2
559 eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4
560 eori 16 . d 0000101001000... .......... U U U U 8 8 2 2
561 eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4
562 eori 32 . d 0000101010000... .......... U U U U 16 14 2 2
563 eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4
564 exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2
565 exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2
566 exg 32 da . 1100...110001... .......... U U U U 6 6 2 2
567 ext 16 . . 0100100010000... .......... U U U U 4 4 4 4
568 ext 32 . . 0100100011000... .......... U U U U 4 4 4 4
569 extb 32 . . 0100100111000... .......... . . U U . . 4 4
570 illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4
571 jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0
572 jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0
573 lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2
574 link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5
575 link 16 . . 0100111001010... .......... U U U U 16 16 5 5
576 link 32 . a7 0100100000001111 .......... . . U U . . 6 6
577 link 32 . . 0100100000001... .......... . . U U . . 6 6
578 lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4
579 lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4
580 lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4
581 lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6
582 lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6
583 lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6
584 lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5
585 lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4
586 lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4
587 lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4
588 lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6
589 lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6
590 lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6
591 lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5
592 move 8 d d 0001...000000... .......... U U U U 4 4 2 2
593 move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2
594 move 8 ai d 0001...010000... .......... U U U U 8 8 4 4
595 move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4
596 move 8 pi d 0001...011000... .......... U U U U 8 8 4 4
597 move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4
598 move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4
599 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4
600 move 8 pd d 0001...100000... .......... U U U U 8 8 5 5
601 move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5
602 move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5
603 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5
604 move 8 di d 0001...101000... .......... U U U U 12 12 5 5
605 move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5
606 move 8 ix d 0001...110000... .......... U U U U 14 14 7 7
607 move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7
608 move 8 aw d 0001000111000... .......... U U U U 12 12 4 4
609 move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4
610 move 8 al d 0001001111000... .......... U U U U 16 16 6 6
611 move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6
612 move 16 d d 0011...000000... .......... U U U U 4 4 2 2
613 move 16 d a 0011...000001... .......... U U U U 4 4 2 2
614 move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2
615 move 16 ai d 0011...010000... .......... U U U U 8 8 4 4
616 move 16 ai a 0011...010001... .......... U U U U 8 8 4 4
617 move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4
618 move 16 pi d 0011...011000... .......... U U U U 8 8 4 4
619 move 16 pi a 0011...011001... .......... U U U U 8 8 4 4
620 move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4
621 move 16 pd d 0011...100000... .......... U U U U 8 8 5 5
622 move 16 pd a 0011...100001... .......... U U U U 8 8 5 5
623 move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5
624 move 16 di d 0011...101000... .......... U U U U 12 12 5 5
625 move 16 di a 0011...101001... .......... U U U U 12 12 5 5
626 move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5
627 move 16 ix d 0011...110000... .......... U U U U 14 14 7 7
628 move 16 ix a 0011...110001... .......... U U U U 14 14 7 7
629 move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7
630 move 16 aw d 0011000111000... .......... U U U U 12 12 4 4
631 move 16 aw a 0011000111001... .......... U U U U 12 12 4 4
632 move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4
633 move 16 al d 0011001111000... .......... U U U U 16 16 6 6
634 move 16 al a 0011001111001... .......... U U U U 16 16 6 6
635 move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6
636 move 32 d d 0010...000000... .......... U U U U 4 4 2 2
637 move 32 d a 0010...000001... .......... U U U U 4 4 2 2
638 move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2
639 move 32 ai d 0010...010000... .......... U U U U 12 12 4 4
640 move 32 ai a 0010...010001... .......... U U U U 12 12 4 4
641 move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4
642 move 32 pi d 0010...011000... .......... U U U U 12 12 4 4
643 move 32 pi a 0010...011001... .......... U U U U 12 12 4 4
644 move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4
645 move 32 pd d 0010...100000... .......... U U U U 12 14 5 5
646 move 32 pd a 0010...100001... .......... U U U U 12 14 5 5
647 move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5
648 move 32 di d 0010...101000... .......... U U U U 16 16 5 5
649 move 32 di a 0010...101001... .......... U U U U 16 16 5 5
650 move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5
651 move 32 ix d 0010...110000... .......... U U U U 18 18 7 7
652 move 32 ix a 0010...110001... .......... U U U U 18 18 7 7
653 move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7
654 move 32 aw d 0010000111000... .......... U U U U 16 16 4 4
655 move 32 aw a 0010000111001... .......... U U U U 16 16 4 4
656 move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4
657 move 32 al d 0010001111000... .......... U U U U 20 20 6 6
658 move 32 al a 0010001111001... .......... U U U U 20 20 6 6
659 move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6
660 movea 16 . d 0011...001000... .......... U U U U 4 4 2 2
661 movea 16 . a 0011...001001... .......... U U U U 4 4 2 2
662 movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2
663 movea 32 . d 0010...001000... .......... U U U U 4 4 2 2
664 movea 32 . a 0010...001001... .......... U U U U 4 4 2 2
665 movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2
666 move 16 frc d 0100001011000... .......... . U U U . 4 4 4
667 move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4
668 move 16 toc d 0100010011000... .......... U U U U 12 12 4 4
669 move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4
670 move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000
671 move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000
672 move 16 tos d 0100011011000... .......... S S S S 12 12 8 8
673 move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8
674 move 32 fru . 0100111001101... .......... S S S S 4 6 2 2
675 move 32 tou . 0100111001100... .......... S S S S 4 6 2 2
676 movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6
677 movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12
678 movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4
679 movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4
680 movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4
681 movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4
682 movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8
683 movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9
684 movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11
685 movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8
686 movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8
687 movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9
688 movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11
689 movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8
690 movep 16 er . 0000...100001... .......... U U U U 16 16 12 12
691 movep 32 er . 0000...101001... .......... U U U U 24 24 18 18
692 movep 16 re . 0000...110001... .......... U U U U 16 16 11 11
693 movep 32 re . 0000...111001... .......... U U U U 24 24 17 17
694 moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2
695 moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5
696 moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5
697 moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5
698 move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing
699 muls 16 . d 1100...111000... .......... U U U U 54 32 27 27
700 muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27
701 mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27
702 mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27
703 mull 32 . d 0100110000000... .......... . . U U . . 43 43
704 mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43
705 nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6
706 nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6
707 neg 8 . d 0100010000000... .......... U U U U 4 4 2 2
708 neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4
709 neg 16 . d 0100010001000... .......... U U U U 4 4 2 2
710 neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4
711 neg 32 . d 0100010010000... .......... U U U U 6 6 2 2
712 neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4
713 negx 8 . d 0100000000000... .......... U U U U 4 4 2 2
714 negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4
715 negx 16 . d 0100000001000... .......... U U U U 4 4 2 2
716 negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4
717 negx 32 . d 0100000010000... .......... U U U U 6 6 2 2
718 negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4
719 nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2
720 not 8 . d 0100011000000... .......... U U U U 4 4 2 2
721 not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4
722 not 16 . d 0100011001000... .......... U U U U 4 4 2 2
723 not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4
724 not 32 . d 0100011010000... .......... U U U U 6 6 2 2
725 not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4
726 or 8 er d 1000...000000... .......... U U U U 4 4 2 2
727 or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2
728 or 16 er d 1000...001000... .......... U U U U 4 4 2 2
729 or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2
730 or 32 er d 1000...010000... .......... U U U U 6 6 2 2
731 or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2
732 or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4
733 or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4
734 or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4
735 ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12
736 ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12
737 ori 8 . d 0000000000000... .......... U U U U 8 8 2 2
738 ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4
739 ori 16 . d 0000000001000... .......... U U U U 8 8 2 2
740 ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4
741 ori 32 . d 0000000010000... .......... U U U U 16 14 2 2
742 ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4
743 pack 16 rr . 1000...101000... .......... . . U U . . 6 6
744 pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13
745 pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13
746 pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13
747 pack 16 mm . 1000...101001... .......... . . U U . . 13 13
748 pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5
749 pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing
750 reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0
751 ror 8 s . 1110...000011... .......... U U U U 6 6 8 8
752 ror 16 s . 1110...001011... .......... U U U U 6 6 8 8
753 ror 32 s . 1110...010011... .......... U U U U 8 8 8 8
754 ror 8 r . 1110...000111... .......... U U U U 6 6 8 8
755 ror 16 r . 1110...001111... .......... U U U U 6 6 8 8
756 ror 32 r . 1110...010111... .......... U U U U 8 8 8 8
757 ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7
758 rol 8 s . 1110...100011... .......... U U U U 6 6 8 8
759 rol 16 s . 1110...101011... .......... U U U U 6 6 8 8
760 rol 32 s . 1110...110011... .......... U U U U 8 8 8 8
761 rol 8 r . 1110...100111... .......... U U U U 6 6 8 8
762 rol 16 r . 1110...101111... .......... U U U U 6 6 8 8
763 rol 32 r . 1110...110111... .......... U U U U 8 8 8 8
764 rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7
765 roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12
766 roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12
767 roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12
768 roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12
769 roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12
770 roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12
771 roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5
772 roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12
773 roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12
774 roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12
775 roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12
776 roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12
777 roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12
778 roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5
779 rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10
780 rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated
781 rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated
782 rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14
783 rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10
784 sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4
785 sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16
786 sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16
787 sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16
788 sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16
789 st 8 . d 0101000011000... .......... U U U U 6 4 4 4
790 st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6
791 sf 8 . d 0101000111000... .......... U U U U 4 4 4 4
792 sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6
793 scc 8 . d 0101....11000... .......... U U U U 4 4 4 4
794 scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6
795 stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8
796 sub 8 er d 1001...000000... .......... U U U U 4 4 2 2
797 sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2
798 sub 16 er d 1001...001000... .......... U U U U 4 4 2 2
799 sub 16 er a 1001...001001... .......... U U U U 4 4 2 2
800 sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2
801 sub 32 er d 1001...010000... .......... U U U U 6 6 2 2
802 sub 32 er a 1001...010001... .......... U U U U 6 6 2 2
803 sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2
804 sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4
805 sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4
806 sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4
807 suba 16 . d 1001...011000... .......... U U U U 8 8 2 2
808 suba 16 . a 1001...011001... .......... U U U U 8 8 2 2
809 suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2
810 suba 32 . d 1001...111000... .......... U U U U 6 6 2 2
811 suba 32 . a 1001...111001... .......... U U U U 6 6 2 2
812 suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2
813 subi 8 . d 0000010000000... .......... U U U U 8 8 2 2
814 subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4
815 subi 16 . d 0000010001000... .......... U U U U 8 8 2 2
816 subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4
817 subi 32 . d 0000010010000... .......... U U U U 16 14 2 2
818 subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4
819 subq 8 . d 0101...100000... .......... U U U U 4 4 2 2
820 subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4
821 subq 16 . d 0101...101000... .......... U U U U 4 4 2 2
822 subq 16 . a 0101...101001... .......... U U U U 8 4 2 2
823 subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4
824 subq 32 . d 0101...110000... .......... U U U U 8 8 2 2
825 subq 32 . a 0101...110001... .......... U U U U 8 8 2 2
826 subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4
827 subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2
828 subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2
829 subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2
830 subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12
831 subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12
832 subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12
833 subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12
834 subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12
835 subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12
836 swap 32 . . 0100100001000... .......... U U U U 4 4 4 4
837 tas 8 . d 0100101011000... .......... U U U U 4 4 4 4
838 tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12
839 trap 0 . . 010011100100.... .......... U U U U 4 4 4 4
840 trapt 0 . . 0101000011111100 .......... . . U U . . 4 4
841 trapt 16 . . 0101000011111010 .......... . . U U . . 6 6
842 trapt 32 . . 0101000011111011 .......... . . U U . . 8 8
843 trapf 0 . . 0101000111111100 .......... . . U U . . 4 4
844 trapf 16 . . 0101000111111010 .......... . . U U . . 6 6
845 trapf 32 . . 0101000111111011 .......... . . U U . . 8 8
846 trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4
847 trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6
848 trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8
849 trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4
850 tst 8 . d 0100101000000... .......... U U U U 4 4 2 2
851 tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2
852 tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7
853 tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9
854 tst 8 . i 0100101000111100 .......... . . U U . . 6 6
855 tst 16 . d 0100101001000... .......... U U U U 4 4 2 2
856 tst 16 . a 0100101001001... .......... . . U U . . 2 2
857 tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2
858 tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7
859 tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9
860 tst 16 . i 0100101001111100 .......... . . U U . . 6 6
861 tst 32 . d 0100101010000... .......... U U U U 4 4 2 2
862 tst 32 . a 0100101010001... .......... . . U U . . 2 2
863 tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2
864 tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7
865 tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9
866 tst 32 . i 0100101010111100 .......... . . U U . . 6 6
867 unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6
868 unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6
869 unpk 16 rr . 1000...110000... .......... . . U U . . 8 8
870 unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13
871 unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13
872 unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13
873 unpk 16 mm . 1000...110001... .......... . . U U . . 13 13
874
875
876
877 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
878 M68KMAKE_OPCODE_HANDLER_BODY
879
880 M68KMAKE_OP(1010, 0, ., .)
881 {
882 m68ki_exception_1010();
883 }
884
885
886 M68KMAKE_OP(1111, 0, ., .)
887 {
888 m68ki_exception_1111();
889 }
890
891
892 M68KMAKE_OP(040fpu0, 32, ., .)
893 {
894 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
895 {
896 m68040_fpu_op0();
897 return;
898 }
899 m68ki_exception_1111();
900 }
901
902
903 M68KMAKE_OP(040fpu1, 32, ., .)
904 {
905 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
906 {
907 m68040_fpu_op1();
908 return;
909 }
910 m68ki_exception_1111();
911 }
912
913
914
915 M68KMAKE_OP(abcd, 8, rr, .)
916 {
917 uint* r_dst = &DX;
918 uint src = DY;
919 uint dst = *r_dst;
920 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
921 uint corf = 0;
922
923 if(res > 9)
924 corf = 6;
925 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
926 FLAG_V = ~res; /* Undefined V behavior */
927
928 res += corf;
929 FLAG_X = FLAG_C = (res > 0x9f) << 8;
930 if(FLAG_C)
931 res -= 0xa0;
932
933 FLAG_V &= res; /* Undefined V behavior part II */
934 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
935
936 res = MASK_OUT_ABOVE_8(res);
937 FLAG_Z |= res;
938
939 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
940 }
941
942
943 M68KMAKE_OP(abcd, 8, mm, ax7)
944 {
945 uint src = OPER_AY_PD_8();
946 uint ea = EA_A7_PD_8();
947 uint dst = m68ki_read_8(ea);
948 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
949 uint corf = 0;
950
951 if(res > 9)
952 corf = 6;
953 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
954 FLAG_V = ~res; /* Undefined V behavior */
955
956 res += corf;
957 FLAG_X = FLAG_C = (res > 0x9f) << 8;
958 if(FLAG_C)
959 res -= 0xa0;
960
961 FLAG_V &= res; /* Undefined V behavior part II */
962 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
963
964 res = MASK_OUT_ABOVE_8(res);
965 FLAG_Z |= res;
966
967 m68ki_write_8(ea, res);
968 }
969
970
971 M68KMAKE_OP(abcd, 8, mm, ay7)
972 {
973 uint src = OPER_A7_PD_8();
974 uint ea = EA_AX_PD_8();
975 uint dst = m68ki_read_8(ea);
976 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
977 uint corf = 0;
978
979 if(res > 9)
980 corf = 6;
981 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
982 FLAG_V = ~res; /* Undefined V behavior */
983
984 res += corf;
985 FLAG_X = FLAG_C = (res > 0x9f) << 8;
986 if(FLAG_C)
987 res -= 0xa0;
988
989 FLAG_V &= res; /* Undefined V behavior part II */
990 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
991
992 res = MASK_OUT_ABOVE_8(res);
993 FLAG_Z |= res;
994
995 m68ki_write_8(ea, res);
996 }
997
998
999 M68KMAKE_OP(abcd, 8, mm, axy7)
1000 {
1001 uint src = OPER_A7_PD_8();
1002 uint ea = EA_A7_PD_8();
1003 uint dst = m68ki_read_8(ea);
1004 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1005 uint corf = 0;
1006
1007 if(res > 9)
1008 corf = 6;
1009 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1010 FLAG_V = ~res; /* Undefined V behavior */
1011
1012 res += corf;
1013 FLAG_X = FLAG_C = (res > 0x9f) << 8;
1014 if(FLAG_C)
1015 res -= 0xa0;
1016
1017 FLAG_V &= res; /* Undefined V behavior part II */
1018 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1019
1020 res = MASK_OUT_ABOVE_8(res);
1021 FLAG_Z |= res;
1022
1023 m68ki_write_8(ea, res);
1024 }
1025
1026
1027 M68KMAKE_OP(abcd, 8, mm, .)
1028 {
1029 uint src = OPER_AY_PD_8();
1030 uint ea = EA_AX_PD_8();
1031 uint dst = m68ki_read_8(ea);
1032 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
1033 uint corf = 0;
1034
1035 if(res > 9)
1036 corf = 6;
1037 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
1038 FLAG_V = ~res; /* Undefined V behavior */
1039
1040 res += corf;
1041 FLAG_X = FLAG_C = (res > 0x9f) << 8;
1042 if(FLAG_C)
1043 res -= 0xa0;
1044
1045 FLAG_V &= res; /* Undefined V behavior part II */
1046 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
1047
1048 res = MASK_OUT_ABOVE_8(res);
1049 FLAG_Z |= res;
1050
1051 m68ki_write_8(ea, res);
1052 }
1053
1054
1055 M68KMAKE_OP(add, 8, er, d)
1056 {
1057 uint* r_dst = &DX;
1058 uint src = MASK_OUT_ABOVE_8(DY);
1059 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1060 uint res = src + dst;
1061
1062 FLAG_N = NFLAG_8(res);
1063 FLAG_V = VFLAG_ADD_8(src, dst, res);
1064 FLAG_X = FLAG_C = CFLAG_8(res);
1065 FLAG_Z = MASK_OUT_ABOVE_8(res);
1066
1067 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1068 }
1069
1070
1071 M68KMAKE_OP(add, 8, er, .)
1072 {
1073 uint* r_dst = &DX;
1074 uint src = M68KMAKE_GET_OPER_AY_8;
1075 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1076 uint res = src + dst;
1077
1078 FLAG_N = NFLAG_8(res);
1079 FLAG_V = VFLAG_ADD_8(src, dst, res);
1080 FLAG_X = FLAG_C = CFLAG_8(res);
1081 FLAG_Z = MASK_OUT_ABOVE_8(res);
1082
1083 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1084 }
1085
1086
1087 M68KMAKE_OP(add, 16, er, d)
1088 {
1089 uint* r_dst = &DX;
1090 uint src = MASK_OUT_ABOVE_16(DY);
1091 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1092 uint res = src + dst;
1093
1094 FLAG_N = NFLAG_16(res);
1095 FLAG_V = VFLAG_ADD_16(src, dst, res);
1096 FLAG_X = FLAG_C = CFLAG_16(res);
1097 FLAG_Z = MASK_OUT_ABOVE_16(res);
1098
1099 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1100 }
1101
1102
1103 M68KMAKE_OP(add, 16, er, a)
1104 {
1105 uint* r_dst = &DX;
1106 uint src = MASK_OUT_ABOVE_16(AY);
1107 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1108 uint res = src + dst;
1109
1110 FLAG_N = NFLAG_16(res);
1111 FLAG_V = VFLAG_ADD_16(src, dst, res);
1112 FLAG_X = FLAG_C = CFLAG_16(res);
1113 FLAG_Z = MASK_OUT_ABOVE_16(res);
1114
1115 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1116 }
1117
1118
1119 M68KMAKE_OP(add, 16, er, .)
1120 {
1121 uint* r_dst = &DX;
1122 uint src = M68KMAKE_GET_OPER_AY_16;
1123 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1124 uint res = src + dst;
1125
1126 FLAG_N = NFLAG_16(res);
1127 FLAG_V = VFLAG_ADD_16(src, dst, res);
1128 FLAG_X = FLAG_C = CFLAG_16(res);
1129 FLAG_Z = MASK_OUT_ABOVE_16(res);
1130
1131 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1132 }
1133
1134
1135 M68KMAKE_OP(add, 32, er, d)
1136 {
1137 uint* r_dst = &DX;
1138 uint src = DY;
1139 uint dst = *r_dst;
1140 uint res = src + dst;
1141
1142 FLAG_N = NFLAG_32(res);
1143 FLAG_V = VFLAG_ADD_32(src, dst, res);
1144 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1145 FLAG_Z = MASK_OUT_ABOVE_32(res);
1146
1147 *r_dst = FLAG_Z;
1148 }
1149
1150
1151 M68KMAKE_OP(add, 32, er, a)
1152 {
1153 uint* r_dst = &DX;
1154 uint src = AY;
1155 uint dst = *r_dst;
1156 uint res = src + dst;
1157
1158 FLAG_N = NFLAG_32(res);
1159 FLAG_V = VFLAG_ADD_32(src, dst, res);
1160 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1161 FLAG_Z = MASK_OUT_ABOVE_32(res);
1162
1163 *r_dst = FLAG_Z;
1164 }
1165
1166
1167 M68KMAKE_OP(add, 32, er, .)
1168 {
1169 uint* r_dst = &DX;
1170 uint src = M68KMAKE_GET_OPER_AY_32;
1171 uint dst = *r_dst;
1172 uint res = src + dst;
1173
1174 FLAG_N = NFLAG_32(res);
1175 FLAG_V = VFLAG_ADD_32(src, dst, res);
1176 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1177 FLAG_Z = MASK_OUT_ABOVE_32(res);
1178
1179 *r_dst = FLAG_Z;
1180 }
1181
1182
1183 M68KMAKE_OP(add, 8, re, .)
1184 {
1185 uint ea = M68KMAKE_GET_EA_AY_8;
1186 uint src = MASK_OUT_ABOVE_8(DX);
1187 uint dst = m68ki_read_8(ea);
1188 uint res = src + dst;
1189
1190 FLAG_N = NFLAG_8(res);
1191 FLAG_V = VFLAG_ADD_8(src, dst, res);
1192 FLAG_X = FLAG_C = CFLAG_8(res);
1193 FLAG_Z = MASK_OUT_ABOVE_8(res);
1194
1195 m68ki_write_8(ea, FLAG_Z);
1196 }
1197
1198
1199 M68KMAKE_OP(add, 16, re, .)
1200 {
1201 uint ea = M68KMAKE_GET_EA_AY_16;
1202 uint src = MASK_OUT_ABOVE_16(DX);
1203 uint dst = m68ki_read_16(ea);
1204 uint res = src + dst;
1205
1206 FLAG_N = NFLAG_16(res);
1207 FLAG_V = VFLAG_ADD_16(src, dst, res);
1208 FLAG_X = FLAG_C = CFLAG_16(res);
1209 FLAG_Z = MASK_OUT_ABOVE_16(res);
1210
1211 m68ki_write_16(ea, FLAG_Z);
1212 }
1213
1214
1215 M68KMAKE_OP(add, 32, re, .)
1216 {
1217 uint ea = M68KMAKE_GET_EA_AY_32;
1218 uint src = DX;
1219 uint dst = m68ki_read_32(ea);
1220 uint res = src + dst;
1221
1222 FLAG_N = NFLAG_32(res);
1223 FLAG_V = VFLAG_ADD_32(src, dst, res);
1224 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1225 FLAG_Z = MASK_OUT_ABOVE_32(res);
1226
1227 m68ki_write_32(ea, FLAG_Z);
1228 }
1229
1230
1231 M68KMAKE_OP(adda, 16, ., d)
1232 {
1233 uint* r_dst = &AX;
1234
1235 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
1236 }
1237
1238
1239 M68KMAKE_OP(adda, 16, ., a)
1240 {
1241 uint* r_dst = &AX;
1242
1243 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
1244 }
1245
1246
1247 M68KMAKE_OP(adda, 16, ., .)
1248 {
1249 uint* r_dst = &AX;
1250 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
1251
1252 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1253 }
1254
1255
1256 M68KMAKE_OP(adda, 32, ., d)
1257 {
1258 uint* r_dst = &AX;
1259
1260 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
1261 }
1262
1263
1264 M68KMAKE_OP(adda, 32, ., a)
1265 {
1266 uint* r_dst = &AX;
1267
1268 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
1269 }
1270
1271
1272 M68KMAKE_OP(adda, 32, ., .)
1273 {
1274 uint* r_dst = &AX;
1275 uint src = M68KMAKE_GET_OPER_AY_32; // notaz
1276
1277 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);
1278 }
1279
1280
1281 M68KMAKE_OP(addi, 8, ., d)
1282 {
1283 uint* r_dst = &DY;
1284 uint src = OPER_I_8();
1285 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1286 uint res = src + dst;
1287
1288 FLAG_N = NFLAG_8(res);
1289 FLAG_V = VFLAG_ADD_8(src, dst, res);
1290 FLAG_X = FLAG_C = CFLAG_8(res);
1291 FLAG_Z = MASK_OUT_ABOVE_8(res);
1292
1293 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1294 }
1295
1296
1297 M68KMAKE_OP(addi, 8, ., .)
1298 {
1299 uint src = OPER_I_8();
1300 uint ea = M68KMAKE_GET_EA_AY_8;
1301 uint dst = m68ki_read_8(ea);
1302 uint res = src + dst;
1303
1304 FLAG_N = NFLAG_8(res);
1305 FLAG_V = VFLAG_ADD_8(src, dst, res);
1306 FLAG_X = FLAG_C = CFLAG_8(res);
1307 FLAG_Z = MASK_OUT_ABOVE_8(res);
1308
1309 m68ki_write_8(ea, FLAG_Z);
1310 }
1311
1312
1313 M68KMAKE_OP(addi, 16, ., d)
1314 {
1315 uint* r_dst = &DY;
1316 uint src = OPER_I_16();
1317 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1318 uint res = src + dst;
1319
1320 FLAG_N = NFLAG_16(res);
1321 FLAG_V = VFLAG_ADD_16(src, dst, res);
1322 FLAG_X = FLAG_C = CFLAG_16(res);
1323 FLAG_Z = MASK_OUT_ABOVE_16(res);
1324
1325 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1326 }
1327
1328
1329 M68KMAKE_OP(addi, 16, ., .)
1330 {
1331 uint src = OPER_I_16();
1332 uint ea = M68KMAKE_GET_EA_AY_16;
1333 uint dst = m68ki_read_16(ea);
1334 uint res = src + dst;
1335
1336 FLAG_N = NFLAG_16(res);
1337 FLAG_V = VFLAG_ADD_16(src, dst, res);
1338 FLAG_X = FLAG_C = CFLAG_16(res);
1339 FLAG_Z = MASK_OUT_ABOVE_16(res);
1340
1341 m68ki_write_16(ea, FLAG_Z);
1342 }
1343
1344
1345 M68KMAKE_OP(addi, 32, ., d)
1346 {
1347 uint* r_dst = &DY;
1348 uint src = OPER_I_32();
1349 uint dst = *r_dst;
1350 uint res = src + dst;
1351
1352 FLAG_N = NFLAG_32(res);
1353 FLAG_V = VFLAG_ADD_32(src, dst, res);
1354 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1355 FLAG_Z = MASK_OUT_ABOVE_32(res);
1356
1357 *r_dst = FLAG_Z;
1358 }
1359
1360
1361 M68KMAKE_OP(addi, 32, ., .)
1362 {
1363 uint src = OPER_I_32();
1364 uint ea = M68KMAKE_GET_EA_AY_32;
1365 uint dst = m68ki_read_32(ea);
1366 uint res = src + dst;
1367
1368 FLAG_N = NFLAG_32(res);
1369 FLAG_V = VFLAG_ADD_32(src, dst, res);
1370 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1371 FLAG_Z = MASK_OUT_ABOVE_32(res);
1372
1373 m68ki_write_32(ea, FLAG_Z);
1374 }
1375
1376
1377 M68KMAKE_OP(addq, 8, ., d)
1378 {
1379 uint* r_dst = &DY;
1380 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1381 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1382 uint res = src + dst;
1383
1384 FLAG_N = NFLAG_8(res);
1385 FLAG_V = VFLAG_ADD_8(src, dst, res);
1386 FLAG_X = FLAG_C = CFLAG_8(res);
1387 FLAG_Z = MASK_OUT_ABOVE_8(res);
1388
1389 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1390 }
1391
1392
1393 M68KMAKE_OP(addq, 8, ., .)
1394 {
1395 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1396 uint ea = M68KMAKE_GET_EA_AY_8;
1397 uint dst = m68ki_read_8(ea);
1398 uint res = src + dst;
1399
1400 FLAG_N = NFLAG_8(res);
1401 FLAG_V = VFLAG_ADD_8(src, dst, res);
1402 FLAG_X = FLAG_C = CFLAG_8(res);
1403 FLAG_Z = MASK_OUT_ABOVE_8(res);
1404
1405 m68ki_write_8(ea, FLAG_Z);
1406 }
1407
1408
1409 M68KMAKE_OP(addq, 16, ., d)
1410 {
1411 uint* r_dst = &DY;
1412 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1413 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1414 uint res = src + dst;
1415
1416 FLAG_N = NFLAG_16(res);
1417 FLAG_V = VFLAG_ADD_16(src, dst, res);
1418 FLAG_X = FLAG_C = CFLAG_16(res);
1419 FLAG_Z = MASK_OUT_ABOVE_16(res);
1420
1421 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1422 }
1423
1424
1425 M68KMAKE_OP(addq, 16, ., a)
1426 {
1427 uint* r_dst = &AY;
1428
1429 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1430 }
1431
1432
1433 M68KMAKE_OP(addq, 16, ., .)
1434 {
1435 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1436 uint ea = M68KMAKE_GET_EA_AY_16;
1437 uint dst = m68ki_read_16(ea);
1438 uint res = src + dst;
1439
1440 FLAG_N = NFLAG_16(res);
1441 FLAG_V = VFLAG_ADD_16(src, dst, res);
1442 FLAG_X = FLAG_C = CFLAG_16(res);
1443 FLAG_Z = MASK_OUT_ABOVE_16(res);
1444
1445 m68ki_write_16(ea, FLAG_Z);
1446 }
1447
1448
1449 M68KMAKE_OP(addq, 32, ., d)
1450 {
1451 uint* r_dst = &DY;
1452 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1453 uint dst = *r_dst;
1454 uint res = src + dst;
1455
1456 FLAG_N = NFLAG_32(res);
1457 FLAG_V = VFLAG_ADD_32(src, dst, res);
1458 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1459 FLAG_Z = MASK_OUT_ABOVE_32(res);
1460
1461 *r_dst = FLAG_Z;
1462 }
1463
1464
1465 M68KMAKE_OP(addq, 32, ., a)
1466 {
1467 uint* r_dst = &AY;
1468
1469 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1470 }
1471
1472
1473 M68KMAKE_OP(addq, 32, ., .)
1474 {
1475 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1476 uint ea = M68KMAKE_GET_EA_AY_32;
1477 uint dst = m68ki_read_32(ea);
1478 uint res = src + dst;
1479
1480
1481 FLAG_N = NFLAG_32(res);
1482 FLAG_V = VFLAG_ADD_32(src, dst, res);
1483 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1484 FLAG_Z = MASK_OUT_ABOVE_32(res);
1485
1486 m68ki_write_32(ea, FLAG_Z);
1487 }
1488
1489
1490 M68KMAKE_OP(addx, 8, rr, .)
1491 {
1492 uint* r_dst = &DX;
1493 uint src = MASK_OUT_ABOVE_8(DY);
1494 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1495 uint res = src + dst + XFLAG_AS_1();
1496
1497 FLAG_N = NFLAG_8(res);
1498 FLAG_V = VFLAG_ADD_8(src, dst, res);
1499 FLAG_X = FLAG_C = CFLAG_8(res);
1500
1501 res = MASK_OUT_ABOVE_8(res);
1502 FLAG_Z |= res;
1503
1504 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1505 }
1506
1507
1508 M68KMAKE_OP(addx, 16, rr, .)
1509 {
1510 uint* r_dst = &DX;
1511 uint src = MASK_OUT_ABOVE_16(DY);
1512 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1513 uint res = src + dst + XFLAG_AS_1();
1514
1515 FLAG_N = NFLAG_16(res);
1516 FLAG_V = VFLAG_ADD_16(src, dst, res);
1517 FLAG_X = FLAG_C = CFLAG_16(res);
1518
1519 res = MASK_OUT_ABOVE_16(res);
1520 FLAG_Z |= res;
1521
1522 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1523 }
1524
1525
1526 M68KMAKE_OP(addx, 32, rr, .)
1527 {
1528 uint* r_dst = &DX;
1529 uint src = DY;
1530 uint dst = *r_dst;
1531 uint res = src + dst + XFLAG_AS_1();
1532
1533 FLAG_N = NFLAG_32(res);
1534 FLAG_V = VFLAG_ADD_32(src, dst, res);
1535 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1536
1537 res = MASK_OUT_ABOVE_32(res);
1538 FLAG_Z |= res;
1539
1540 *r_dst = res;
1541 }
1542
1543
1544 M68KMAKE_OP(addx, 8, mm, ax7)
1545 {
1546 uint src = OPER_AY_PD_8();
1547 uint ea = EA_A7_PD_8();
1548 uint dst = m68ki_read_8(ea);
1549 uint res = src + dst + XFLAG_AS_1();
1550
1551 FLAG_N = NFLAG_8(res);
1552 FLAG_V = VFLAG_ADD_8(src, dst, res);
1553 FLAG_X = FLAG_C = CFLAG_8(res);
1554
1555 res = MASK_OUT_ABOVE_8(res);
1556 FLAG_Z |= res;
1557
1558 m68ki_write_8(ea, res);
1559 }
1560
1561
1562 M68KMAKE_OP(addx, 8, mm, ay7)
1563 {
1564 uint src = OPER_A7_PD_8();
1565 uint ea = EA_AX_PD_8();
1566 uint dst = m68ki_read_8(ea);
1567 uint res = src + dst + XFLAG_AS_1();
1568
1569 FLAG_N = NFLAG_8(res);
1570 FLAG_V = VFLAG_ADD_8(src, dst, res);
1571 FLAG_X = FLAG_C = CFLAG_8(res);
1572
1573 res = MASK_OUT_ABOVE_8(res);
1574 FLAG_Z |= res;
1575
1576 m68ki_write_8(ea, res);
1577 }
1578
1579
1580 M68KMAKE_OP(addx, 8, mm, axy7)
1581 {
1582 uint src = OPER_A7_PD_8();
1583 uint ea = EA_A7_PD_8();
1584 uint dst = m68ki_read_8(ea);
1585 uint res = src + dst + XFLAG_AS_1();
1586
1587 FLAG_N = NFLAG_8(res);
1588 FLAG_V = VFLAG_ADD_8(src, dst, res);
1589 FLAG_X = FLAG_C = CFLAG_8(res);
1590
1591 res = MASK_OUT_ABOVE_8(res);
1592 FLAG_Z |= res;
1593
1594 m68ki_write_8(ea, res);
1595 }
1596
1597
1598 M68KMAKE_OP(addx, 8, mm, .)
1599 {
1600 uint src = OPER_AY_PD_8();
1601 uint ea = EA_AX_PD_8();
1602 uint dst = m68ki_read_8(ea);
1603 uint res = src + dst + XFLAG_AS_1();
1604
1605 FLAG_N = NFLAG_8(res);
1606 FLAG_V = VFLAG_ADD_8(src, dst, res);
1607 FLAG_X = FLAG_C = CFLAG_8(res);
1608
1609 res = MASK_OUT_ABOVE_8(res);
1610 FLAG_Z |= res;
1611
1612 m68ki_write_8(ea, res);
1613 }
1614
1615
1616 M68KMAKE_OP(addx, 16, mm, .)
1617 {
1618 uint src = OPER_AY_PD_16();
1619 uint ea = EA_AX_PD_16();
1620 uint dst = m68ki_read_16(ea);
1621 uint res = src + dst + XFLAG_AS_1();
1622
1623 FLAG_N = NFLAG_16(res);
1624 FLAG_V = VFLAG_ADD_16(src, dst, res);
1625 FLAG_X = FLAG_C = CFLAG_16(res);
1626
1627 res = MASK_OUT_ABOVE_16(res);
1628 FLAG_Z |= res;
1629
1630 m68ki_write_16(ea, res);
1631 }
1632
1633
1634 M68KMAKE_OP(addx, 32, mm, .)
1635 {
1636 uint src = OPER_AY_PD_32();
1637 uint ea = EA_AX_PD_32();
1638 uint dst = m68ki_read_32(ea);
1639 uint res = src + dst + XFLAG_AS_1();
1640
1641 FLAG_N = NFLAG_32(res);
1642 FLAG_V = VFLAG_ADD_32(src, dst, res);
1643 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1644
1645 res = MASK_OUT_ABOVE_32(res);
1646 FLAG_Z |= res;
1647
1648 m68ki_write_32(ea, res);
1649 }
1650
1651
1652 M68KMAKE_OP(and, 8, er, d)
1653 {
1654 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
1655
1656 FLAG_N = NFLAG_8(FLAG_Z);
1657 FLAG_C = CFLAG_CLEAR;
1658 FLAG_V = VFLAG_CLEAR;
1659 }
1660
1661
1662 M68KMAKE_OP(and, 8, er, .)
1663 {
1664 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
1665
1666 FLAG_N = NFLAG_8(FLAG_Z);
1667 FLAG_C = CFLAG_CLEAR;
1668 FLAG_V = VFLAG_CLEAR;
1669 }
1670
1671
1672 M68KMAKE_OP(and, 16, er, d)
1673 {
1674 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
1675
1676 FLAG_N = NFLAG_16(FLAG_Z);
1677 FLAG_C = CFLAG_CLEAR;
1678 FLAG_V = VFLAG_CLEAR;
1679 }
1680
1681
1682 M68KMAKE_OP(and, 16, er, .)
1683 {
1684 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
1685
1686 FLAG_N = NFLAG_16(FLAG_Z);
1687 FLAG_C = CFLAG_CLEAR;
1688 FLAG_V = VFLAG_CLEAR;
1689 }
1690
1691
1692 M68KMAKE_OP(and, 32, er, d)
1693 {
1694 FLAG_Z = DX &= DY;
1695
1696 FLAG_N = NFLAG_32(FLAG_Z);
1697 FLAG_C = CFLAG_CLEAR;
1698 FLAG_V = VFLAG_CLEAR;
1699 }
1700
1701
1702 M68KMAKE_OP(and, 32, er, .)
1703 {
1704 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
1705
1706 FLAG_N = NFLAG_32(FLAG_Z);
1707 FLAG_C = CFLAG_CLEAR;
1708 FLAG_V = VFLAG_CLEAR;
1709 }
1710
1711
1712 M68KMAKE_OP(and, 8, re, .)
1713 {
1714 uint ea = M68KMAKE_GET_EA_AY_8;
1715 uint res = DX & m68ki_read_8(ea);
1716
1717 FLAG_N = NFLAG_8(res);
1718 FLAG_C = CFLAG_CLEAR;
1719 FLAG_V = VFLAG_CLEAR;
1720 FLAG_Z = MASK_OUT_ABOVE_8(res);
1721
1722 m68ki_write_8(ea, FLAG_Z);
1723 }
1724
1725
1726 M68KMAKE_OP(and, 16, re, .)
1727 {
1728 uint ea = M68KMAKE_GET_EA_AY_16;
1729 uint res = DX & m68ki_read_16(ea);
1730
1731 FLAG_N = NFLAG_16(res);
1732 FLAG_C = CFLAG_CLEAR;
1733 FLAG_V = VFLAG_CLEAR;
1734 FLAG_Z = MASK_OUT_ABOVE_16(res);
1735
1736 m68ki_write_16(ea, FLAG_Z);
1737 }
1738
1739
1740 M68KMAKE_OP(and, 32, re, .)
1741 {
1742 uint ea = M68KMAKE_GET_EA_AY_32;
1743 uint res = DX & m68ki_read_32(ea);
1744
1745 FLAG_N = NFLAG_32(res);
1746 FLAG_Z = res;
1747 FLAG_C = CFLAG_CLEAR;
1748 FLAG_V = VFLAG_CLEAR;
1749
1750 m68ki_write_32(ea, res);
1751 }
1752
1753
1754 M68KMAKE_OP(andi, 8, ., d)
1755 {
1756 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
1757
1758 FLAG_N = NFLAG_8(FLAG_Z);
1759 FLAG_C = CFLAG_CLEAR;
1760 FLAG_V = VFLAG_CLEAR;
1761 }
1762
1763
1764 M68KMAKE_OP(andi, 8, ., .)
1765 {
1766 uint src = OPER_I_8();
1767 uint ea = M68KMAKE_GET_EA_AY_8;
1768 uint res = src & m68ki_read_8(ea);
1769
1770 FLAG_N = NFLAG_8(res);
1771 FLAG_Z = res;
1772 FLAG_C = CFLAG_CLEAR;
1773 FLAG_V = VFLAG_CLEAR;
1774
1775 m68ki_write_8(ea, res);
1776 }
1777
1778
1779 M68KMAKE_OP(andi, 16, ., d)
1780 {
1781 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
1782
1783 FLAG_N = NFLAG_16(FLAG_Z);
1784 FLAG_C = CFLAG_CLEAR;
1785 FLAG_V = VFLAG_CLEAR;
1786 }
1787
1788
1789 M68KMAKE_OP(andi, 16, ., .)
1790 {
1791 uint src = OPER_I_16();
1792 uint ea = M68KMAKE_GET_EA_AY_16;
1793 uint res = src & m68ki_read_16(ea);
1794
1795 FLAG_N = NFLAG_16(res);
1796 FLAG_Z = res;
1797 FLAG_C = CFLAG_CLEAR;
1798 FLAG_V = VFLAG_CLEAR;
1799
1800 m68ki_write_16(ea, res);
1801 }
1802
1803
1804 M68KMAKE_OP(andi, 32, ., d)
1805 {
1806 FLAG_Z = DY &= (OPER_I_32());
1807
1808 FLAG_N = NFLAG_32(FLAG_Z);
1809 FLAG_C = CFLAG_CLEAR;
1810 FLAG_V = VFLAG_CLEAR;
1811 }
1812
1813
1814 M68KMAKE_OP(andi, 32, ., .)
1815 {
1816 uint src = OPER_I_32();
1817 uint ea = M68KMAKE_GET_EA_AY_32;
1818 uint res = src & m68ki_read_32(ea);
1819
1820 FLAG_N = NFLAG_32(res);
1821 FLAG_Z = res;
1822 FLAG_C = CFLAG_CLEAR;
1823 FLAG_V = VFLAG_CLEAR;
1824
1825 m68ki_write_32(ea, res);
1826 }
1827
1828
1829 M68KMAKE_OP(andi, 16, toc, .)
1830 {
1831 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
1832 }
1833
1834
1835 M68KMAKE_OP(andi, 16, tos, .)
1836 {
1837 if(FLAG_S)
1838 {
1839 uint src = OPER_I_16();
1840 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
1841 m68ki_set_sr(m68ki_get_sr() & src);
1842 return;
1843 }
1844 m68ki_exception_privilege_violation();
1845 }
1846
1847
1848 M68KMAKE_OP(asr, 8, s, .)
1849 {
1850 uint* r_dst = &DY;
1851 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1852 uint src = MASK_OUT_ABOVE_8(*r_dst);
1853 uint res = src >> shift;
1854
1855 if(shift != 0)
1856 USE_CYCLES(shift<<CYC_SHIFT);
1857
1858 if(GET_MSB_8(src))
1859 res |= m68ki_shift_8_table[shift];
1860
1861 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1862
1863 FLAG_N = NFLAG_8(res);
1864 FLAG_Z = res;
1865 FLAG_V = VFLAG_CLEAR;
1866 FLAG_X = FLAG_C = src << (9-shift);
1867 }
1868
1869
1870 M68KMAKE_OP(asr, 16, s, .)
1871 {
1872 uint* r_dst = &DY;
1873 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1874 uint src = MASK_OUT_ABOVE_16(*r_dst);
1875 uint res = src >> shift;
1876
1877 if(shift != 0)
1878 USE_CYCLES(shift<<CYC_SHIFT);
1879
1880 if(GET_MSB_16(src))
1881 res |= m68ki_shift_16_table[shift];
1882
1883 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1884
1885 FLAG_N = NFLAG_16(res);
1886 FLAG_Z = res;
1887 FLAG_V = VFLAG_CLEAR;
1888 FLAG_X = FLAG_C = src << (9-shift);
1889 }
1890
1891
1892 M68KMAKE_OP(asr, 32, s, .)
1893 {
1894 uint* r_dst = &DY;
1895 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1896 uint src = *r_dst;
1897 uint res = src >> shift;
1898
1899 if(shift != 0)
1900 USE_CYCLES(shift<<CYC_SHIFT);
1901
1902 if(GET_MSB_32(src))
1903 res |= m68ki_shift_32_table[shift];
1904
1905 *r_dst = res;
1906
1907 FLAG_N = NFLAG_32(res);
1908 FLAG_Z = res;
1909 FLAG_V = VFLAG_CLEAR;
1910 FLAG_X = FLAG_C = src << (9-shift);
1911 }
1912
1913
1914 M68KMAKE_OP(asr, 8, r, .)
1915 {
1916 uint* r_dst = &DY;
1917 uint shift = DX & 0x3f;
1918 uint src = MASK_OUT_ABOVE_8(*r_dst);
1919 uint res = src >> shift;
1920
1921 if(shift != 0)
1922 {
1923 USE_CYCLES(shift<<CYC_SHIFT);
1924
1925 if(shift < 8)
1926 {
1927 if(GET_MSB_8(src))
1928 res |= m68ki_shift_8_table[shift];
1929
1930 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1931
1932 FLAG_X = FLAG_C = src << (9-shift);
1933 FLAG_N = NFLAG_8(res);
1934 FLAG_Z = res;
1935 FLAG_V = VFLAG_CLEAR;
1936 return;
1937 }
1938
1939 if(GET_MSB_8(src))
1940 {
1941 *r_dst |= 0xff;
1942 FLAG_C = CFLAG_SET;
1943 FLAG_X = XFLAG_SET;
1944 FLAG_N = NFLAG_SET;
1945 FLAG_Z = ZFLAG_CLEAR;
1946 FLAG_V = VFLAG_CLEAR;
1947 return;
1948 }
1949
1950 *r_dst &= 0xffffff00;
1951 FLAG_C = CFLAG_CLEAR;
1952 FLAG_X = XFLAG_CLEAR;
1953 FLAG_N = NFLAG_CLEAR;
1954 FLAG_Z = ZFLAG_SET;
1955 FLAG_V = VFLAG_CLEAR;
1956 return;
1957 }
1958
1959 FLAG_C = CFLAG_CLEAR;
1960 FLAG_N = NFLAG_8(src);
1961 FLAG_Z = src;
1962 FLAG_V = VFLAG_CLEAR;
1963 }
1964
1965
1966 M68KMAKE_OP(asr, 16, r, .)
1967 {
1968 uint* r_dst = &DY;
1969 uint shift = DX & 0x3f;
1970 uint src = MASK_OUT_ABOVE_16(*r_dst);
1971 uint res = src >> shift;
1972
1973 if(shift != 0)
1974 {
1975 USE_CYCLES(shift<<CYC_SHIFT);
1976
1977 if(shift < 16)
1978 {
1979 if(GET_MSB_16(src))
1980 res |= m68ki_shift_16_table[shift];
1981
1982 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1983
1984 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
1985 FLAG_N = NFLAG_16(res);
1986 FLAG_Z = res;
1987 FLAG_V = VFLAG_CLEAR;
1988 return;
1989 }
1990
1991 if(GET_MSB_16(src))
1992 {
1993 *r_dst |= 0xffff;
1994 FLAG_C = CFLAG_SET;
1995 FLAG_X = XFLAG_SET;
1996 FLAG_N = NFLAG_SET;
1997 FLAG_Z = ZFLAG_CLEAR;
1998 FLAG_V = VFLAG_CLEAR;
1999 return;
2000 }
2001
2002 *r_dst &= 0xffff0000;
2003 FLAG_C = CFLAG_CLEAR;
2004 FLAG_X = XFLAG_CLEAR;
2005 FLAG_N = NFLAG_CLEAR;
2006 FLAG_Z = ZFLAG_SET;
2007 FLAG_V = VFLAG_CLEAR;
2008 return;
2009 }
2010
2011 FLAG_C = CFLAG_CLEAR;
2012 FLAG_N = NFLAG_16(src);
2013 FLAG_Z = src;
2014 FLAG_V = VFLAG_CLEAR;
2015 }
2016
2017
2018 M68KMAKE_OP(asr, 32, r, .)
2019 {
2020 uint* r_dst = &DY;
2021 uint shift = DX & 0x3f;
2022 uint src = *r_dst;
2023 uint res = src >> shift;
2024
2025 if(shift != 0)
2026 {
2027 USE_CYCLES(shift<<CYC_SHIFT);
2028
2029 if(shift < 32)
2030 {
2031 if(GET_MSB_32(src))
2032 res |= m68ki_shift_32_table[shift];
2033
2034 *r_dst = res;
2035
2036 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
2037 FLAG_N = NFLAG_32(res);
2038 FLAG_Z = res;
2039 FLAG_V = VFLAG_CLEAR;
2040 return;
2041 }
2042
2043 if(GET_MSB_32(src))
2044 {
2045 *r_dst = 0xffffffff;
2046 FLAG_C = CFLAG_SET;
2047 FLAG_X = XFLAG_SET;
2048 FLAG_N = NFLAG_SET;
2049 FLAG_Z = ZFLAG_CLEAR;
2050 FLAG_V = VFLAG_CLEAR;
2051 return;
2052 }
2053
2054 *r_dst = 0;
2055 FLAG_C = CFLAG_CLEAR;
2056 FLAG_X = XFLAG_CLEAR;
2057 FLAG_N = NFLAG_CLEAR;
2058 FLAG_Z = ZFLAG_SET;
2059 FLAG_V = VFLAG_CLEAR;
2060 return;
2061 }
2062
2063 FLAG_C = CFLAG_CLEAR;
2064 FLAG_N = NFLAG_32(src);
2065 FLAG_Z = src;
2066 FLAG_V = VFLAG_CLEAR;
2067 }
2068
2069
2070 M68KMAKE_OP(asr, 16, ., .)
2071 {
2072 uint ea = M68KMAKE_GET_EA_AY_16;
2073 uint src = m68ki_read_16(ea);
2074 uint res = src >> 1;
2075
2076 if(GET_MSB_16(src))
2077 res |= 0x8000;
2078
2079 m68ki_write_16(ea, res);
2080
2081 FLAG_N = NFLAG_16(res);
2082 FLAG_Z = res;
2083 FLAG_V = VFLAG_CLEAR;
2084 FLAG_C = FLAG_X = src << 8;
2085 }
2086
2087
2088 M68KMAKE_OP(asl, 8, s, .)
2089 {
2090 uint* r_dst = &DY;
2091 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2092 uint src = MASK_OUT_ABOVE_8(*r_dst);
2093 uint res = MASK_OUT_ABOVE_8(src << shift);
2094
2095 if(shift != 0)
2096 USE_CYCLES(shift<<CYC_SHIFT);
2097
2098 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2099
2100 FLAG_X = FLAG_C = src << shift;
2101 FLAG_N = NFLAG_8(res);
2102 FLAG_Z = res;
2103 src &= m68ki_shift_8_table[shift + 1];
2104 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
2105 }
2106
2107
2108 M68KMAKE_OP(asl, 16, s, .)
2109 {
2110 uint* r_dst = &DY;
2111 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2112 uint src = MASK_OUT_ABOVE_16(*r_dst);
2113 uint res = MASK_OUT_ABOVE_16(src << shift);
2114
2115 if(shift != 0)
2116 USE_CYCLES(shift<<CYC_SHIFT);
2117
2118 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2119
2120 FLAG_N = NFLAG_16(res);
2121 FLAG_Z = res;
2122 FLAG_X = FLAG_C = src >> (8-shift);
2123 src &= m68ki_shift_16_table[shift + 1];
2124 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2125 }
2126
2127
2128 M68KMAKE_OP(asl, 32, s, .)
2129 {
2130 uint* r_dst = &DY;
2131 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2132 uint src = *r_dst;
2133 uint res = MASK_OUT_ABOVE_32(src << shift);
2134
2135 if(shift != 0)
2136 USE_CYCLES(shift<<CYC_SHIFT);
2137
2138 *r_dst = res;
2139
2140 FLAG_N = NFLAG_32(res);
2141 FLAG_Z = res;
2142 FLAG_X = FLAG_C = src >> (24-shift);
2143 src &= m68ki_shift_32_table[shift + 1];
2144 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2145 }
2146
2147
2148 M68KMAKE_OP(asl, 8, r, .)
2149 {
2150 uint* r_dst = &DY;
2151 uint shift = DX & 0x3f;
2152 uint src = MASK_OUT_ABOVE_8(*r_dst);
2153 uint res = MASK_OUT_ABOVE_8(src << shift);
2154
2155 if(shift != 0)
2156 {
2157 USE_CYCLES(shift<<CYC_SHIFT);
2158
2159 if(shift < 8)
2160 {
2161 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2162 FLAG_X = FLAG_C = src << shift;
2163 FLAG_N = NFLAG_8(res);
2164 FLAG_Z = res;
2165 src &= m68ki_shift_8_table[shift + 1];
2166 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
2167 return;
2168 }
2169
2170 *r_dst &= 0xffffff00;
2171 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
2172 FLAG_N = NFLAG_CLEAR;
2173 FLAG_Z = ZFLAG_SET;
2174 FLAG_V = (!(src == 0))<<7;
2175 return;
2176 }
2177
2178 FLAG_C = CFLAG_CLEAR;
2179 FLAG_N = NFLAG_8(src);
2180 FLAG_Z = src;
2181 FLAG_V = VFLAG_CLEAR;
2182 }
2183
2184
2185 M68KMAKE_OP(asl, 16, r, .)
2186 {
2187 uint* r_dst = &DY;
2188 uint shift = DX & 0x3f;
2189 uint src = MASK_OUT_ABOVE_16(*r_dst);
2190 uint res = MASK_OUT_ABOVE_16(src << shift);
2191
2192 if(shift != 0)
2193 {
2194 USE_CYCLES(shift<<CYC_SHIFT);
2195
2196 if(shift < 16)
2197 {
2198 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2199 FLAG_X = FLAG_C = (src << shift) >> 8;
2200 FLAG_N = NFLAG_16(res);
2201 FLAG_Z = res;
2202 src &= m68ki_shift_16_table[shift + 1];
2203 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2204 return;
2205 }
2206
2207 *r_dst &= 0xffff0000;
2208 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
2209 FLAG_N = NFLAG_CLEAR;
2210 FLAG_Z = ZFLAG_SET;
2211 FLAG_V = (!(src == 0))<<7;
2212 return;
2213 }
2214
2215 FLAG_C = CFLAG_CLEAR;
2216 FLAG_N = NFLAG_16(src);
2217 FLAG_Z = src;
2218 FLAG_V = VFLAG_CLEAR;
2219 }
2220
2221
2222 M68KMAKE_OP(asl, 32, r, .)
2223 {
2224 uint* r_dst = &DY;
2225 uint shift = DX & 0x3f;
2226 uint src = *r_dst;
2227 uint res = MASK_OUT_ABOVE_32(src << shift);
2228
2229 if(shift != 0)
2230 {
2231 USE_CYCLES(shift<<CYC_SHIFT);
2232
2233 if(shift < 32)
2234 {
2235 *r_dst = res;
2236 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
2237 FLAG_N = NFLAG_32(res);
2238 FLAG_Z = res;
2239 src &= m68ki_shift_32_table[shift + 1];
2240 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2241 return;
2242 }
2243
2244 *r_dst = 0;
2245 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
2246 FLAG_N = NFLAG_CLEAR;
2247 FLAG_Z = ZFLAG_SET;
2248 FLAG_V = (!(src == 0))<<7;
2249 return;
2250 }
2251
2252 FLAG_C = CFLAG_CLEAR;
2253 FLAG_N = NFLAG_32(src);
2254 FLAG_Z = src;
2255 FLAG_V = VFLAG_CLEAR;
2256 }
2257
2258
2259 M68KMAKE_OP(asl, 16, ., .)
2260 {
2261 uint ea = M68KMAKE_GET_EA_AY_16;
2262 uint src = m68ki_read_16(ea);
2263 uint res = MASK_OUT_ABOVE_16(src << 1);
2264
2265 m68ki_write_16(ea, res);
2266
2267 FLAG_N = NFLAG_16(res);
2268 FLAG_Z = res;
2269 FLAG_X = FLAG_C = src >> 7;
2270 src &= 0xc000;
2271 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
2272 }
2273
2274
2275 M68KMAKE_OP(bcc, 8, ., .)
2276 {
2277 if(M68KMAKE_CC)
2278 {
2279 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2280 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2281 return;
2282 }
2283 USE_CYCLES(CYC_BCC_NOTAKE_B);
2284 }
2285
2286
2287 M68KMAKE_OP(bcc, 16, ., .)
2288 {
2289 if(M68KMAKE_CC)
2290 {
2291 uint offset = OPER_I_16();
2292 REG_PC -= 2;
2293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2294 m68ki_branch_16(offset);
2295 return;
2296 }
2297 REG_PC += 2;
2298 USE_CYCLES(CYC_BCC_NOTAKE_W);
2299 }
2300
2301
2302 M68KMAKE_OP(bcc, 32, ., .)
2303 {
2304 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2305 {
2306 if(M68KMAKE_CC)
2307 {
2308 uint offset = OPER_I_32();
2309 REG_PC -= 4;
2310 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2311 m68ki_branch_32(offset);
2312 return;
2313 }
2314 REG_PC += 4;
2315 return;
2316 }
2317 else
2318 {
2319 if(M68KMAKE_CC)
2320 {
2321 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2322 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2323 return;
2324 }
2325 USE_CYCLES(CYC_BCC_NOTAKE_B);
2326 }
2327 }
2328
2329
2330 M68KMAKE_OP(bchg, 32, r, d)
2331 {
2332 uint* r_dst = &DY;
2333 uint mask = 1 << (DX & 0x1f);
2334
2335 FLAG_Z = *r_dst & mask;
2336 *r_dst ^= mask;
2337 }
2338
2339
2340 M68KMAKE_OP(bchg, 8, r, .)
2341 {
2342 uint ea = M68KMAKE_GET_EA_AY_8;
2343 uint src = m68ki_read_8(ea);
2344 uint mask = 1 << (DX & 7);
2345
2346 FLAG_Z = src & mask;
2347 m68ki_write_8(ea, src ^ mask);
2348 }
2349
2350
2351 M68KMAKE_OP(bchg, 32, s, d)
2352 {
2353 uint* r_dst = &DY;
2354 uint mask = 1 << (OPER_I_8() & 0x1f);
2355
2356 FLAG_Z = *r_dst & mask;
2357 *r_dst ^= mask;
2358 }
2359
2360
2361 M68KMAKE_OP(bchg, 8, s, .)
2362 {
2363 uint mask = 1 << (OPER_I_8() & 7);
2364 uint ea = M68KMAKE_GET_EA_AY_8;
2365 uint src = m68ki_read_8(ea);
2366
2367 FLAG_Z = src & mask;
2368 m68ki_write_8(ea, src ^ mask);
2369 }
2370
2371
2372 M68KMAKE_OP(bclr, 32, r, d)
2373 {
2374 uint* r_dst = &DY;
2375 uint mask = 1 << (DX & 0x1f);
2376
2377 FLAG_Z = *r_dst & mask;
2378 *r_dst &= ~mask;
2379 }
2380
2381
2382 M68KMAKE_OP(bclr, 8, r, .)
2383 {
2384 uint ea = M68KMAKE_GET_EA_AY_8;
2385 uint src = m68ki_read_8(ea);
2386 uint mask = 1 << (DX & 7);
2387
2388 FLAG_Z = src & mask;
2389 m68ki_write_8(ea, src & ~mask);
2390 }
2391
2392
2393 M68KMAKE_OP(bclr, 32, s, d)
2394 {
2395 uint* r_dst = &DY;
2396 uint mask = 1 << (OPER_I_8() & 0x1f);
2397
2398 FLAG_Z = *r_dst & mask;
2399 *r_dst &= ~mask;
2400 }
2401
2402
2403 M68KMAKE_OP(bclr, 8, s, .)
2404 {
2405 uint mask = 1 << (OPER_I_8() & 7);
2406 uint ea = M68KMAKE_GET_EA_AY_8;
2407 uint src = m68ki_read_8(ea);
2408
2409 FLAG_Z = src & mask;
2410 m68ki_write_8(ea, src & ~mask);
2411 }
2412
2413
2414 M68KMAKE_OP(bfchg, 32, ., d)
2415 {
2416 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2417 {
2418 uint word2 = OPER_I_16();
2419 uint offset = (word2>>6)&31;
2420 uint width = word2;
2421 uint* data = &DY;
2422 uint64 mask;
2423
2424
2425 if(BIT_B(word2))
2426 offset = REG_D[offset&7];
2427 if(BIT_5(word2))
2428 width = REG_D[width&7];
2429
2430 offset &= 31;
2431 width = ((width-1) & 31) + 1;
2432
2433 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2434 mask = ROR_32(mask, offset);
2435
2436 FLAG_N = NFLAG_32(*data<<offset);
2437 FLAG_Z = *data & mask;
2438 FLAG_V = VFLAG_CLEAR;
2439 FLAG_C = CFLAG_CLEAR;
2440
2441 *data ^= mask;
2442
2443 return;
2444 }
2445 m68ki_exception_illegal();
2446 }
2447
2448
2449 M68KMAKE_OP(bfchg, 32, ., .)
2450 {
2451 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2452 {
2453 uint word2 = OPER_I_16();
2454 sint offset = (word2>>6)&31;
2455 uint width = word2;
2456 uint mask_base;
2457 uint data_long;
2458 uint mask_long;
2459 uint data_byte = 0;
2460 uint mask_byte = 0;
2461 uint ea = M68KMAKE_GET_EA_AY_8;
2462
2463
2464 if(BIT_B(word2))
2465 offset = MAKE_INT_32(REG_D[offset&7]);
2466 if(BIT_5(word2))
2467 width = REG_D[width&7];
2468
2469 /* Offset is signed so we have to use ugly math =( */
2470 ea += offset / 8;
2471 offset %= 8;
2472 if(offset < 0)
2473 {
2474 offset += 8;
2475 ea--;
2476 }
2477 width = ((width-1) & 31) + 1;
2478
2479 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2480 mask_long = mask_base >> offset;
2481
2482 data_long = m68ki_read_32(ea);
2483 FLAG_N = NFLAG_32(data_long << offset);
2484 FLAG_Z = data_long & mask_long;
2485 FLAG_V = VFLAG_CLEAR;
2486 FLAG_C = CFLAG_CLEAR;
2487
2488 m68ki_write_32(ea, data_long ^ mask_long);
2489
2490 if((width + offset) > 32)
2491 {
2492 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2493 data_byte = m68ki_read_8(ea+4);
2494 FLAG_Z |= (data_byte & mask_byte);
2495 m68ki_write_8(ea+4, data_byte ^ mask_byte);
2496 }
2497 return;
2498 }
2499 m68ki_exception_illegal();
2500 }
2501
2502
2503 M68KMAKE_OP(bfclr, 32, ., d)
2504 {
2505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2506 {
2507 uint word2 = OPER_I_16();
2508 uint offset = (word2>>6)&31;
2509 uint width = word2;
2510 uint* data = &DY;
2511 uint64 mask;
2512
2513
2514 if(BIT_B(word2))
2515 offset = REG_D[offset&7];
2516 if(BIT_5(word2))
2517 width = REG_D[width&7];
2518
2519
2520 offset &= 31;
2521 width = ((width-1) & 31) + 1;
2522
2523
2524 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2525 mask = ROR_32(mask, offset);
2526
2527 FLAG_N = NFLAG_32(*data<<offset);
2528 FLAG_Z = *data & mask;
2529 FLAG_V = VFLAG_CLEAR;
2530 FLAG_C = CFLAG_CLEAR;
2531
2532 *data &= ~mask;
2533
2534 return;
2535 }
2536 m68ki_exception_illegal();
2537 }
2538
2539
2540 M68KMAKE_OP(bfclr, 32, ., .)
2541 {
2542 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2543 {
2544 uint word2 = OPER_I_16();
2545 sint offset = (word2>>6)&31;
2546 uint width = word2;
2547 uint mask_base;
2548 uint data_long;
2549 uint mask_long;
2550 uint data_byte = 0;
2551 uint mask_byte = 0;
2552 uint ea = M68KMAKE_GET_EA_AY_8;
2553
2554
2555 if(BIT_B(word2))
2556 offset = MAKE_INT_32(REG_D[offset&7]);
2557 if(BIT_5(word2))
2558 width = REG_D[width&7];
2559
2560 /* Offset is signed so we have to use ugly math =( */
2561 ea += offset / 8;
2562 offset %= 8;
2563 if(offset < 0)
2564 {
2565 offset += 8;
2566 ea--;
2567 }
2568 width = ((width-1) & 31) + 1;
2569
2570 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2571 mask_long = mask_base >> offset;
2572
2573 data_long = m68ki_read_32(ea);
2574 FLAG_N = NFLAG_32(data_long << offset);
2575 FLAG_Z = data_long & mask_long;
2576 FLAG_V = VFLAG_CLEAR;
2577 FLAG_C = CFLAG_CLEAR;
2578
2579 m68ki_write_32(ea, data_long & ~mask_long);
2580
2581 if((width + offset) > 32)
2582 {
2583 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2584 data_byte = m68ki_read_8(ea+4);
2585 FLAG_Z |= (data_byte & mask_byte);
2586 m68ki_write_8(ea+4, data_byte & ~mask_byte);
2587 }
2588 return;
2589 }
2590 m68ki_exception_illegal();
2591 }
2592
2593
2594 M68KMAKE_OP(bfexts, 32, ., d)
2595 {
2596 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2597 {
2598 uint word2 = OPER_I_16();
2599 uint offset = (word2>>6)&31;
2600 uint width = word2;
2601 uint64 data = DY;
2602
2603
2604 if(BIT_B(word2))
2605 offset = REG_D[offset&7];
2606 if(BIT_5(word2))
2607 width = REG_D[width&7];
2608
2609 offset &= 31;
2610 width = ((width-1) & 31) + 1;
2611
2612 data = ROL_32(data, offset);
2613 FLAG_N = NFLAG_32(data);
2614 data = MAKE_INT_32(data) >> (32 - width);
2615
2616 FLAG_Z = data;
2617 FLAG_V = VFLAG_CLEAR;
2618 FLAG_C = CFLAG_CLEAR;
2619
2620 REG_D[(word2>>12)&7] = data;
2621
2622 return;
2623 }
2624 m68ki_exception_illegal();
2625 }
2626
2627
2628 M68KMAKE_OP(bfexts, 32, ., .)
2629 {
2630 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2631 {
2632 uint word2 = OPER_I_16();
2633 sint offset = (word2>>6)&31;
2634 uint width = word2;
2635 uint data;
2636 uint ea = M68KMAKE_GET_EA_AY_8;
2637
2638
2639 if(BIT_B(word2))
2640 offset = MAKE_INT_32(REG_D[offset&7]);
2641 if(BIT_5(word2))
2642 width = REG_D[width&7];
2643
2644 /* Offset is signed so we have to use ugly math =( */
2645 ea += offset / 8;
2646 offset %= 8;
2647 if(offset < 0)
2648 {
2649 offset += 8;
2650 ea--;
2651 }
2652 width = ((width-1) & 31) + 1;
2653
2654 data = m68ki_read_32(ea);
2655
2656 data = MASK_OUT_ABOVE_32(data<<offset);
2657
2658 if((offset+width) > 32)
2659 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2660
2661 FLAG_N = NFLAG_32(data);
2662 data = MAKE_INT_32(data) >> (32 - width);
2663
2664 FLAG_Z = data;
2665 FLAG_V = VFLAG_CLEAR;
2666 FLAG_C = CFLAG_CLEAR;
2667
2668 REG_D[(word2 >> 12) & 7] = data;
2669
2670 return;
2671 }
2672 m68ki_exception_illegal();
2673 }
2674
2675
2676 M68KMAKE_OP(bfextu, 32, ., d)
2677 {
2678 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2679 {
2680 uint word2 = OPER_I_16();
2681 uint offset = (word2>>6)&31;
2682 uint width = word2;
2683 uint64 data = DY;
2684
2685
2686 if(BIT_B(word2))
2687 offset = REG_D[offset&7];
2688 if(BIT_5(word2))
2689 width = REG_D[width&7];
2690
2691 offset &= 31;
2692 width = ((width-1) & 31) + 1;
2693
2694 data = ROL_32(data, offset);
2695 FLAG_N = NFLAG_32(data);
2696 data >>= 32 - width;
2697
2698 FLAG_Z = data;
2699 FLAG_V = VFLAG_CLEAR;
2700 FLAG_C = CFLAG_CLEAR;
2701
2702 REG_D[(word2>>12)&7] = data;
2703
2704 return;
2705 }
2706 m68ki_exception_illegal();
2707 }
2708
2709
2710 M68KMAKE_OP(bfextu, 32, ., .)
2711 {
2712 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2713 {
2714 uint word2 = OPER_I_16();
2715 sint offset = (word2>>6)&31;
2716 uint width = word2;
2717 uint data;
2718 uint ea = M68KMAKE_GET_EA_AY_8;
2719
2720
2721 if(BIT_B(word2))
2722 offset = MAKE_INT_32(REG_D[offset&7]);
2723 if(BIT_5(word2))
2724 width = REG_D[width&7];
2725
2726 /* Offset is signed so we have to use ugly math =( */
2727 ea += offset / 8;
2728 offset %= 8;
2729 if(offset < 0)
2730 {
2731 offset += 8;
2732 ea--;
2733 }
2734 width = ((width-1) & 31) + 1;
2735
2736 data = m68ki_read_32(ea);
2737 data = MASK_OUT_ABOVE_32(data<<offset);
2738
2739 if((offset+width) > 32)
2740 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2741
2742 FLAG_N = NFLAG_32(data);
2743 data >>= (32 - width);
2744
2745 FLAG_Z = data;
2746 FLAG_V = VFLAG_CLEAR;
2747 FLAG_C = CFLAG_CLEAR;
2748
2749 REG_D[(word2 >> 12) & 7] = data;
2750
2751 return;
2752 }
2753 m68ki_exception_illegal();
2754 }
2755
2756
2757 M68KMAKE_OP(bfffo, 32, ., d)
2758 {
2759 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2760 {
2761 uint word2 = OPER_I_16();
2762 uint offset = (word2>>6)&31;
2763 uint width = word2;
2764 uint64 data = DY;
2765 uint bit;
2766
2767
2768 if(BIT_B(word2))
2769 offset = REG_D[offset&7];
2770 if(BIT_5(word2))
2771 width = REG_D[width&7];
2772
2773 offset &= 31;
2774 width = ((width-1) & 31) + 1;
2775
2776 data = ROL_32(data, offset);
2777 FLAG_N = NFLAG_32(data);
2778 data >>= 32 - width;
2779
2780 FLAG_Z = data;
2781 FLAG_V = VFLAG_CLEAR;
2782 FLAG_C = CFLAG_CLEAR;
2783
2784 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2785 offset++;
2786
2787 REG_D[(word2>>12)&7] = offset;
2788
2789 return;
2790 }
2791 m68ki_exception_illegal();
2792 }
2793
2794
2795 M68KMAKE_OP(bfffo, 32, ., .)
2796 {
2797 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2798 {
2799 uint word2 = OPER_I_16();
2800 sint offset = (word2>>6)&31;
2801 sint local_offset;
2802 uint width = word2;
2803 uint data;
2804 uint bit;
2805 uint ea = M68KMAKE_GET_EA_AY_8;
2806
2807
2808 if(BIT_B(word2))
2809 offset = MAKE_INT_32(REG_D[offset&7]);
2810 if(BIT_5(word2))
2811 width = REG_D[width&7];
2812
2813 /* Offset is signed so we have to use ugly math =( */
2814 ea += offset / 8;
2815 local_offset = offset % 8;
2816 if(local_offset < 0)
2817 {
2818 local_offset += 8;
2819 ea--;
2820 }
2821 width = ((width-1) & 31) + 1;
2822
2823 data = m68ki_read_32(ea);
2824 data = MASK_OUT_ABOVE_32(data<<local_offset);
2825
2826 if((local_offset+width) > 32)
2827 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
2828
2829 FLAG_N = NFLAG_32(data);
2830 data >>= (32 - width);
2831
2832 FLAG_Z = data;
2833 FLAG_V = VFLAG_CLEAR;
2834 FLAG_C = CFLAG_CLEAR;
2835
2836 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2837 offset++;
2838
2839 REG_D[(word2>>12)&7] = offset;
2840
2841 return;
2842 }
2843 m68ki_exception_illegal();
2844 }
2845
2846
2847 M68KMAKE_OP(bfins, 32, ., d)
2848 {
2849 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2850 {
2851 uint word2 = OPER_I_16();
2852 uint offset = (word2>>6)&31;
2853 uint width = word2;
2854 uint* data = &DY;
2855 uint64 mask;
2856 uint64 insert = REG_D[(word2>>12)&7];
2857
2858
2859 if(BIT_B(word2))
2860 offset = REG_D[offset&7];
2861 if(BIT_5(word2))
2862 width = REG_D[width&7];
2863
2864
2865 offset &= 31;
2866 width = ((width-1) & 31) + 1;
2867
2868
2869 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2870 mask = ROR_32(mask, offset);
2871
2872 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
2873 FLAG_N = NFLAG_32(insert);
2874 FLAG_Z = insert;
2875 insert = ROR_32(insert, offset);
2876
2877 FLAG_V = VFLAG_CLEAR;
2878 FLAG_C = CFLAG_CLEAR;
2879
2880 *data &= ~mask;
2881 *data |= insert;
2882
2883 return;
2884 }
2885 m68ki_exception_illegal();
2886 }
2887
2888
2889 M68KMAKE_OP(bfins, 32, ., .)
2890 {
2891 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2892 {
2893 uint word2 = OPER_I_16();
2894 sint offset = (word2>>6)&31;
2895 uint width = word2;
2896 uint insert_base = REG_D[(word2>>12)&7];
2897 uint insert_long;
2898 uint insert_byte;
2899 uint mask_base;
2900 uint data_long;
2901 uint mask_long;
2902 uint data_byte = 0;
2903 uint mask_byte = 0;
2904 uint ea = M68KMAKE_GET_EA_AY_8;
2905
2906
2907 if(BIT_B(word2))
2908 offset = MAKE_INT_32(REG_D[offset&7]);
2909 if(BIT_5(word2))
2910 width = REG_D[width&7];
2911
2912 /* Offset is signed so we have to use ugly math =( */
2913 ea += offset / 8;
2914 offset %= 8;
2915 if(offset < 0)
2916 {
2917 offset += 8;
2918 ea--;
2919 }
2920 width = ((width-1) & 31) + 1;
2921
2922 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2923 mask_long = mask_base >> offset;
2924
2925 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
2926 FLAG_N = NFLAG_32(insert_base);
2927 FLAG_Z = insert_base;
2928 insert_long = insert_base >> offset;
2929
2930 data_long = m68ki_read_32(ea);
2931 FLAG_V = VFLAG_CLEAR;
2932 FLAG_C = CFLAG_CLEAR;
2933
2934 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
2935
2936 if((width + offset) > 32)
2937 {
2938 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2939 insert_byte = MASK_OUT_ABOVE_8(insert_base);
2940 data_byte = m68ki_read_8(ea+4);
2941 FLAG_Z |= (data_byte & mask_byte);
2942 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
2943 }
2944 return;
2945 }
2946 m68ki_exception_illegal();
2947 }
2948
2949
2950 M68KMAKE_OP(bfset, 32, ., d)
2951 {
2952 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2953 {
2954 uint word2 = OPER_I_16();
2955 uint offset = (word2>>6)&31;
2956 uint width = word2;
2957 uint* data = &DY;
2958 uint64 mask;
2959
2960
2961 if(BIT_B(word2))
2962 offset = REG_D[offset&7];
2963 if(BIT_5(word2))
2964 width = REG_D[width&7];
2965
2966
2967 offset &= 31;
2968 width = ((width-1) & 31) + 1;
2969
2970
2971 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2972 mask = ROR_32(mask, offset);
2973
2974 FLAG_N = NFLAG_32(*data<<offset);
2975 FLAG_Z = *data & mask;
2976 FLAG_V = VFLAG_CLEAR;
2977 FLAG_C = CFLAG_CLEAR;
2978
2979 *data |= mask;
2980
2981 return;
2982 }
2983 m68ki_exception_illegal();
2984 }
2985
2986
2987 M68KMAKE_OP(bfset, 32, ., .)
2988 {
2989 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2990 {
2991 uint word2 = OPER_I_16();
2992 sint offset = (word2>>6)&31;
2993 uint width = word2;
2994 uint mask_base;
2995 uint data_long;
2996 uint mask_long;
2997 uint data_byte = 0;
2998 uint mask_byte = 0;
2999 uint ea = M68KMAKE_GET_EA_AY_8;
3000
3001
3002 if(BIT_B(word2))
3003 offset = MAKE_INT_32(REG_D[offset&7]);
3004 if(BIT_5(word2))
3005 width = REG_D[width&7];
3006
3007 /* Offset is signed so we have to use ugly math =( */
3008 ea += offset / 8;
3009 offset %= 8;
3010 if(offset < 0)
3011 {
3012 offset += 8;
3013 ea--;
3014 }
3015 width = ((width-1) & 31) + 1;
3016
3017
3018 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3019 mask_long = mask_base >> offset;
3020
3021 data_long = m68ki_read_32(ea);
3022 FLAG_N = NFLAG_32(data_long << offset);
3023 FLAG_Z = data_long & mask_long;
3024 FLAG_V = VFLAG_CLEAR;
3025 FLAG_C = CFLAG_CLEAR;
3026
3027 m68ki_write_32(ea, data_long | mask_long);
3028
3029 if((width + offset) > 32)
3030 {
3031 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3032 data_byte = m68ki_read_8(ea+4);
3033 FLAG_Z |= (data_byte & mask_byte);
3034 m68ki_write_8(ea+4, data_byte | mask_byte);
3035 }
3036 return;
3037 }
3038 m68ki_exception_illegal();
3039 }
3040
3041
3042 M68KMAKE_OP(bftst, 32, ., d)
3043 {
3044 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3045 {
3046 uint word2 = OPER_I_16();
3047 uint offset = (word2>>6)&31;
3048 uint width = word2;
3049 uint* data = &DY;
3050 uint64 mask;
3051
3052
3053 if(BIT_B(word2))
3054 offset = REG_D[offset&7];
3055 if(BIT_5(word2))
3056 width = REG_D[width&7];
3057
3058
3059 offset &= 31;
3060 width = ((width-1) & 31) + 1;
3061
3062
3063 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3064 mask = ROR_32(mask, offset);
3065
3066 FLAG_N = NFLAG_32(*data<<offset);
3067 FLAG_Z = *data & mask;
3068 FLAG_V = VFLAG_CLEAR;
3069 FLAG_C = CFLAG_CLEAR;
3070
3071 return;
3072 }
3073 m68ki_exception_illegal();
3074 }
3075
3076
3077 M68KMAKE_OP(bftst, 32, ., .)
3078 {
3079 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3080 {
3081 uint word2 = OPER_I_16();
3082 sint offset = (word2>>6)&31;
3083 uint width = word2;
3084 uint mask_base;
3085 uint data_long;
3086 uint mask_long;
3087 uint data_byte = 0;
3088 uint mask_byte = 0;
3089 uint ea = M68KMAKE_GET_EA_AY_8;
3090
3091 if(BIT_B(word2))
3092 offset = MAKE_INT_32(REG_D[offset&7]);
3093 if(BIT_5(word2))
3094 width = REG_D[width&7];
3095
3096 /* Offset is signed so we have to use ugly math =( */
3097 ea += offset / 8;
3098 offset %= 8;
3099 if(offset < 0)
3100 {
3101 offset += 8;
3102 ea--;
3103 }
3104 width = ((width-1) & 31) + 1;
3105
3106
3107 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3108 mask_long = mask_base >> offset;
3109
3110 data_long = m68ki_read_32(ea);
3111 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
3112 FLAG_Z = data_long & mask_long;
3113 FLAG_V = VFLAG_CLEAR;
3114 FLAG_C = CFLAG_CLEAR;
3115
3116 if((width + offset) > 32)
3117 {
3118 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3119 data_byte = m68ki_read_8(ea+4);
3120 FLAG_Z |= (data_byte & mask_byte);
3121 }
3122 return;
3123 }
3124 m68ki_exception_illegal();
3125 }
3126
3127
3128 M68KMAKE_OP(bkpt, 0, ., .)
3129 {
3130 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
3131 {
3132 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
3133 }
3134 m68ki_exception_illegal();
3135 }
3136
3137
3138 M68KMAKE_OP(bra, 8, ., .)
3139 {
3140 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3141 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3142 if(REG_PC == REG_PPC)
3143 USE_ALL_CYCLES();
3144 }
3145
3146
3147 M68KMAKE_OP(bra, 16, ., .)
3148 {
3149 uint offset = OPER_I_16();
3150 REG_PC -= 2;
3151 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3152 m68ki_branch_16(offset);
3153 if(REG_PC == REG_PPC)
3154 USE_ALL_CYCLES();
3155 }
3156
3157
3158 M68KMAKE_OP(bra, 32, ., .)
3159 {
3160 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3161 {
3162 uint offset = OPER_I_32();
3163 REG_PC -= 4;
3164 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3165 m68ki_branch_32(offset);
3166 if(REG_PC == REG_PPC)
3167 USE_ALL_CYCLES();
3168 return;
3169 }
3170 else
3171 {
3172 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3173 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3174 if(REG_PC == REG_PPC)
3175 USE_ALL_CYCLES();
3176 }
3177 }
3178
3179
3180 M68KMAKE_OP(bset, 32, r, d)
3181 {
3182 uint* r_dst = &DY;
3183 uint mask = 1 << (DX & 0x1f);
3184
3185 FLAG_Z = *r_dst & mask;
3186 *r_dst |= mask;
3187 }
3188
3189
3190 M68KMAKE_OP(bset, 8, r, .)
3191 {
3192 uint ea = M68KMAKE_GET_EA_AY_8;
3193 uint src = m68ki_read_8(ea);
3194 uint mask = 1 << (DX & 7);
3195
3196 FLAG_Z = src & mask;
3197 m68ki_write_8(ea, src | mask);
3198 }
3199
3200
3201 M68KMAKE_OP(bset, 32, s, d)
3202 {
3203 uint* r_dst = &DY;
3204 uint mask = 1 << (OPER_I_8() & 0x1f);
3205
3206 FLAG_Z = *r_dst & mask;
3207 *r_dst |= mask;
3208 }
3209
3210
3211 M68KMAKE_OP(bset, 8, s, .)
3212 {
3213 uint mask = 1 << (OPER_I_8() & 7);
3214 uint ea = M68KMAKE_GET_EA_AY_8;
3215 uint src = m68ki_read_8(ea);
3216
3217 FLAG_Z = src & mask;
3218 m68ki_write_8(ea, src | mask);
3219 }
3220
3221
3222 M68KMAKE_OP(bsr, 8, ., .)
3223 {
3224 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3225 m68ki_push_32(REG_PC);
3226 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3227 }
3228
3229
3230 M68KMAKE_OP(bsr, 16, ., .)
3231 {
3232 uint offset = OPER_I_16();
3233 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3234 m68ki_push_32(REG_PC);
3235 REG_PC -= 2;
3236 m68ki_branch_16(offset);
3237 }
3238
3239
3240 M68KMAKE_OP(bsr, 32, ., .)
3241 {
3242 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3243 {
3244 uint offset = OPER_I_32();
3245 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3246 m68ki_push_32(REG_PC);
3247 REG_PC -= 4;
3248 m68ki_branch_32(offset);
3249 return;
3250 }
3251 else
3252 {
3253 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3254 m68ki_push_32(REG_PC);
3255 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3256 }
3257 }
3258
3259
3260 M68KMAKE_OP(btst, 32, r, d)
3261 {
3262 FLAG_Z = DY & (1 << (DX & 0x1f));
3263 }
3264
3265
3266 M68KMAKE_OP(btst, 8, r, .)
3267 {
3268 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
3269 }
3270
3271
3272 M68KMAKE_OP(btst, 32, s, d)
3273 {
3274 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
3275 }
3276
3277
3278 M68KMAKE_OP(btst, 8, s, .)
3279 {
3280 uint bit = OPER_I_8() & 7;
3281
3282 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
3283 }
3284
3285
3286 M68KMAKE_OP(callm, 32, ., .)
3287 {
3288 /* note: watch out for pcrelative modes */
3289 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
3290 {
3291 uint ea = M68KMAKE_GET_EA_AY_32;
3292
3293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3294 REG_PC += 2;
3295 (void)ea; /* just to avoid an 'unused variable' warning */
3296 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
3297 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
3298 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
3299 return;
3300 }
3301 m68ki_exception_illegal();
3302 }
3303
3304
3305 M68KMAKE_OP(cas, 8, ., .)
3306 {
3307 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3308 {
3309 uint word2 = OPER_I_16();
3310 uint ea = M68KMAKE_GET_EA_AY_8;
3311 uint dest = m68ki_read_8(ea);
3312 uint* compare = ®_D[word2 & 7];
3313 uint res = dest - MASK_OUT_ABOVE_8(*compare);
3314
3315 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3316 FLAG_N = NFLAG_8(res);
3317 FLAG_Z = MASK_OUT_ABOVE_8(res);
3318 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
3319 FLAG_C = CFLAG_8(res);
3320
3321 if(COND_NE())
3322 *compare = MASK_OUT_BELOW_8(*compare) | dest;
3323 else
3324 {
3325 USE_CYCLES(3);
3326 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
3327 }
3328 return;
3329 }
3330 m68ki_exception_illegal();
3331 }
3332
3333
3334 M68KMAKE_OP(cas, 16, ., .)
3335 {
3336 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3337 {
3338 uint word2 = OPER_I_16();
3339 uint ea = M68KMAKE_GET_EA_AY_16;
3340 uint dest = m68ki_read_16(ea);
3341 uint* compare = ®_D[word2 & 7];
3342 uint res = dest - MASK_OUT_ABOVE_16(*compare);
3343
3344 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3345 FLAG_N = NFLAG_16(res);
3346 FLAG_Z = MASK_OUT_ABOVE_16(res);
3347 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
3348 FLAG_C = CFLAG_16(res);
3349
3350 if(COND_NE())
3351 *compare = MASK_OUT_BELOW_16(*compare) | dest;
3352 else
3353 {
3354 USE_CYCLES(3);
3355 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
3356 }
3357 return;
3358 }
3359 m68ki_exception_illegal();
3360 }
3361
3362
3363 M68KMAKE_OP(cas, 32, ., .)
3364 {
3365 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3366 {
3367 uint word2 = OPER_I_16();
3368 uint ea = M68KMAKE_GET_EA_AY_32;
3369 uint dest = m68ki_read_32(ea);
3370 uint* compare = ®_D[word2 & 7];
3371 uint res = dest - *compare;
3372
3373 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3374 FLAG_N = NFLAG_32(res);
3375 FLAG_Z = MASK_OUT_ABOVE_32(res);
3376 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
3377 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
3378
3379 if(COND_NE())
3380 *compare = dest;
3381 else
3382 {
3383 USE_CYCLES(3);
3384 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
3385 }
3386 return;
3387 }
3388 m68ki_exception_illegal();
3389 }
3390
3391
3392 M68KMAKE_OP(cas2, 16, ., .)
3393 {
3394 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3395 {
3396 uint word2 = OPER_I_32();
3397 uint* compare1 = ®_D[(word2 >> 16) & 7];
3398 uint ea1 = REG_DA[(word2 >> 28) & 15];
3399 uint dest1 = m68ki_read_16(ea1);
3400 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
3401 uint* compare2 = ®_D[word2 & 7];
3402 uint ea2 = REG_DA[(word2 >> 12) & 15];
3403 uint dest2 = m68ki_read_16(ea2);
3404 uint res2;
3405
3406 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3407 FLAG_N = NFLAG_16(res1);
3408 FLAG_Z = MASK_OUT_ABOVE_16(res1);
3409 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
3410 FLAG_C = CFLAG_16(res1);
3411
3412 if(COND_EQ())
3413 {
3414 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
3415
3416 FLAG_N = NFLAG_16(res2);
3417 FLAG_Z = MASK_OUT_ABOVE_16(res2);
3418 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
3419 FLAG_C = CFLAG_16(res2);
3420
3421 if(COND_EQ())
3422 {
3423 USE_CYCLES(3);
3424 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
3425 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
3426 return;
3427 }
3428 }
3429 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
3430 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
3431 return;
3432 }
3433 m68ki_exception_illegal();
3434 }
3435
3436
3437 M68KMAKE_OP(cas2, 32, ., .)
3438 {
3439 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3440 {
3441 uint word2 = OPER_I_32();
3442 uint* compare1 = ®_D[(word2 >> 16) & 7];
3443 uint ea1 = REG_DA[(word2 >> 28) & 15];
3444 uint dest1 = m68ki_read_32(ea1);
3445 uint res1 = dest1 - *compare1;
3446 uint* compare2 = ®_D[word2 & 7];
3447 uint ea2 = REG_DA[(word2 >> 12) & 15];
3448 uint dest2 = m68ki_read_32(ea2);
3449 uint res2;
3450
3451 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3452 FLAG_N = NFLAG_32(res1);
3453 FLAG_Z = MASK_OUT_ABOVE_32(res1);
3454 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
3455 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
3456
3457 if(COND_EQ())
3458 {
3459 res2 = dest2 - *compare2;
3460
3461 FLAG_N = NFLAG_32(res2);
3462 FLAG_Z = MASK_OUT_ABOVE_32(res2);
3463 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
3464 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
3465
3466 if(COND_EQ())
3467 {
3468 USE_CYCLES(3);
3469 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
3470 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
3471 return;
3472 }
3473 }
3474 *compare1 = dest1;
3475 *compare2 = dest2;
3476 return;
3477 }
3478 m68ki_exception_illegal();
3479 }
3480
3481
3482 M68KMAKE_OP(chk, 16, ., d)
3483 {
3484 sint src = MAKE_INT_16(DX);
3485 sint bound = MAKE_INT_16(DY);
3486
3487 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3488 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3489 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3490
3491 if(src >= 0 && src <= bound)
3492 {
3493 return;
3494 }
3495 FLAG_N = (src < 0)<<7;
3496 m68ki_exception_trap(EXCEPTION_CHK);
3497 }
3498
3499
3500 M68KMAKE_OP(chk, 16, ., .)
3501 {
3502 sint src = MAKE_INT_16(DX);
3503 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3504
3505 FLAG_Z = ZFLAG_16(src); /* Undocumented */
3506 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3507 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3508
3509 if(src >= 0 && src <= bound)
3510 {
3511 return;
3512 }
3513 FLAG_N = (src < 0)<<7;
3514 m68ki_exception_trap(EXCEPTION_CHK);
3515 }
3516
3517
3518 M68KMAKE_OP(chk, 32, ., d)
3519 {
3520 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3521 {
3522 sint src = MAKE_INT_32(DX);
3523 sint bound = MAKE_INT_32(DY);
3524
3525 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3526 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3527 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3528
3529 if(src >= 0 && src <= bound)
3530 {
3531 return;
3532 }
3533 FLAG_N = (src < 0)<<7;
3534 m68ki_exception_trap(EXCEPTION_CHK);
3535 return;
3536 }
3537 m68ki_exception_illegal();
3538 }
3539
3540
3541 M68KMAKE_OP(chk, 32, ., .)
3542 {
3543 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3544 {
3545 sint src = MAKE_INT_32(DX);
3546 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
3547
3548 FLAG_Z = ZFLAG_32(src); /* Undocumented */
3549 FLAG_V = VFLAG_CLEAR; /* Undocumented */
3550 FLAG_C = CFLAG_CLEAR; /* Undocumented */
3551
3552 if(src >= 0 && src <= bound)
3553 {
3554 return;
3555 }
3556 FLAG_N = (src < 0)<<7;
3557 m68ki_exception_trap(EXCEPTION_CHK);
3558 return;
3559 }
3560 m68ki_exception_illegal();
3561 }
3562
3563
3564 M68KMAKE_OP(chk2cmp2, 8, ., pcdi)
3565 {
3566 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3567 {
3568 uint word2 = OPER_I_16();
3569 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3570 uint ea = EA_PCDI_8();
3571 uint lower_bound = m68ki_read_pcrel_8(ea);
3572 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
3573
3574 if(!BIT_F(word2))
3575 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
3576 else
3577 FLAG_C = compare - lower_bound;
3578 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
3579 if(COND_CS())
3580 {
3581 if(BIT_B(word2))
3582 m68ki_exception_trap(EXCEPTION_CHK);
3583 return;
3584 }
3585
3586 FLAG_C = upper_bound - compare;
3587 if(COND_CS() && BIT_B(word2))
3588 m68ki_exception_trap(EXCEPTION_CHK);
3589 return;
3590 }
3591 m68ki_exception_illegal();
3592 }
3593
3594
3595 M68KMAKE_OP(chk2cmp2, 8, ., pcix)
3596 {
3597 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3598 {
3599 uint word2 = OPER_I_16();
3600 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3601 uint ea = EA_PCIX_8();
3602 uint lower_bound = m68ki_read_pcrel_8(ea);
3603 uint upper_bound = m68ki_read_pcrel_8(ea + 1);
3604
3605 if(!BIT_F(word2))
3606 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
3607 else
3608 FLAG_C = compare - lower_bound;
3609 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
3610 if(COND_CS())
3611 {
3612 if(BIT_B(word2))
3613 m68ki_exception_trap(EXCEPTION_CHK);
3614 return;
3615 }
3616
3617 FLAG_C = upper_bound - compare;
3618 if(COND_CS() && BIT_B(word2))
3619 m68ki_exception_trap(EXCEPTION_CHK);
3620 return;
3621 }
3622 m68ki_exception_illegal();
3623 }
3624
3625
3626 M68KMAKE_OP(chk2cmp2, 8, ., .)
3627 {
3628 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3629 {
3630 uint word2 = OPER_I_16();
3631 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;
3632 uint ea = M68KMAKE_GET_EA_AY_8;
3633 uint lower_bound = m68ki_read_8(ea);
3634 uint upper_bound = m68ki_read_8(ea + 1);
3635
3636 if(!BIT_F(word2))
3637 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);
3638 else
3639 FLAG_C = compare - lower_bound;
3640 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
3641 if(COND_CS())
3642 {
3643 if(BIT_B(word2))
3644 m68ki_exception_trap(EXCEPTION_CHK);
3645 return;
3646 }
3647
3648 FLAG_C = upper_bound - compare;
3649 if(COND_CS() && BIT_B(word2))
3650 m68ki_exception_trap(EXCEPTION_CHK);
3651 return;
3652 }
3653 m68ki_exception_illegal();
3654 }
3655
3656
3657 M68KMAKE_OP(chk2cmp2, 16, ., pcdi)
3658 {
3659 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3660 {
3661 uint word2 = OPER_I_16();
3662 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3663 uint ea = EA_PCDI_16();
3664 uint lower_bound = m68ki_read_pcrel_16(ea);
3665 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
3666
3667 if(!BIT_F(word2))
3668 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
3669 else
3670 FLAG_C = compare - lower_bound;
3671 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
3672 FLAG_C = CFLAG_16(FLAG_C);
3673 if(COND_CS())
3674 {
3675 if(BIT_B(word2))
3676 m68ki_exception_trap(EXCEPTION_CHK);
3677 return;
3678 }
3679
3680 if(!BIT_F(word2))
3681 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
3682 else
3683 FLAG_C = upper_bound - compare;
3684 FLAG_C = CFLAG_16(FLAG_C);
3685 if(COND_CS() && BIT_B(word2))
3686 m68ki_exception_trap(EXCEPTION_CHK);
3687 return;
3688 }
3689 m68ki_exception_illegal();
3690 }
3691
3692
3693 M68KMAKE_OP(chk2cmp2, 16, ., pcix)
3694 {
3695 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3696 {
3697 uint word2 = OPER_I_16();
3698 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3699 uint ea = EA_PCIX_16();
3700 uint lower_bound = m68ki_read_pcrel_16(ea);
3701 uint upper_bound = m68ki_read_pcrel_16(ea + 2);
3702
3703 if(!BIT_F(word2))
3704 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
3705 else
3706 FLAG_C = compare - lower_bound;
3707 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
3708 FLAG_C = CFLAG_16(FLAG_C);
3709 if(COND_CS())
3710 {
3711 if(BIT_B(word2))
3712 m68ki_exception_trap(EXCEPTION_CHK);
3713 return;
3714 }
3715
3716 if(!BIT_F(word2))
3717 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
3718 else
3719 FLAG_C = upper_bound - compare;
3720 FLAG_C = CFLAG_16(FLAG_C);
3721 if(COND_CS() && BIT_B(word2))
3722 m68ki_exception_trap(EXCEPTION_CHK);
3723 return;
3724 }
3725 m68ki_exception_illegal();
3726 }
3727
3728
3729 M68KMAKE_OP(chk2cmp2, 16, ., .)
3730 {
3731 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3732 {
3733 uint word2 = OPER_I_16();
3734 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;
3735 uint ea = M68KMAKE_GET_EA_AY_16;
3736 uint lower_bound = m68ki_read_16(ea);
3737 uint upper_bound = m68ki_read_16(ea + 2);
3738
3739 if(!BIT_F(word2))
3740 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);
3741 else
3742 FLAG_C = compare - lower_bound;
3743
3744 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
3745 FLAG_C = CFLAG_16(FLAG_C);
3746 if(COND_CS())
3747 {
3748 if(BIT_B(word2))
3749 m68ki_exception_trap(EXCEPTION_CHK);
3750 return;
3751 }
3752 if(!BIT_F(word2))
3753 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);
3754 else
3755 FLAG_C = upper_bound - compare;
3756
3757 FLAG_C = CFLAG_16(FLAG_C);
3758 if(COND_CS() && BIT_B(word2))
3759 m68ki_exception_trap(EXCEPTION_CHK);
3760 return;
3761 }
3762 m68ki_exception_illegal();
3763 }
3764
3765
3766 M68KMAKE_OP(chk2cmp2, 32, ., pcdi)
3767 {
3768 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3769 {
3770 uint word2 = OPER_I_16();
3771 uint compare = REG_DA[(word2 >> 12) & 15];
3772 uint ea = EA_PCDI_32();
3773 uint lower_bound = m68ki_read_pcrel_32(ea);
3774 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
3775
3776 FLAG_C = compare - lower_bound;
3777 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
3778 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
3779 if(COND_CS())
3780 {
3781 if(BIT_B(word2))
3782 m68ki_exception_trap(EXCEPTION_CHK);
3783 return;
3784 }
3785
3786 FLAG_C = upper_bound - compare;
3787 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
3788 if(COND_CS() && BIT_B(word2))
3789 m68ki_exception_trap(EXCEPTION_CHK);
3790 return;
3791 }
3792 m68ki_exception_illegal();
3793 }
3794
3795
3796 M68KMAKE_OP(chk2cmp2, 32, ., pcix)
3797 {
3798 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3799 {
3800 uint word2 = OPER_I_16();
3801 uint compare = REG_DA[(word2 >> 12) & 15];
3802 uint ea = EA_PCIX_32();
3803 uint lower_bound = m68ki_read_pcrel_32(ea);
3804 uint upper_bound = m68ki_read_pcrel_32(ea + 4);
3805
3806 FLAG_C = compare - lower_bound;
3807 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
3808 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
3809 if(COND_CS())
3810 {
3811 if(BIT_B(word2))
3812 m68ki_exception_trap(EXCEPTION_CHK);
3813 return;
3814 }
3815
3816 FLAG_C = upper_bound - compare;
3817 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
3818 if(COND_CS() && BIT_B(word2))
3819 m68ki_exception_trap(EXCEPTION_CHK);
3820 return;
3821 }
3822 m68ki_exception_illegal();
3823 }
3824
3825
3826 M68KMAKE_OP(chk2cmp2, 32, ., .)
3827 {
3828 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3829 {
3830 uint word2 = OPER_I_16();
3831 uint compare = REG_DA[(word2 >> 12) & 15];
3832 uint ea = M68KMAKE_GET_EA_AY_32;
3833 uint lower_bound = m68ki_read_32(ea);
3834 uint upper_bound = m68ki_read_32(ea + 4);
3835
3836 FLAG_C = compare - lower_bound;
3837 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));
3838 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
3839 if(COND_CS())
3840 {
3841 if(BIT_B(word2))
3842 m68ki_exception_trap(EXCEPTION_CHK);
3843 return;
3844 }
3845
3846 FLAG_C = upper_bound - compare;
3847 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
3848 if(COND_CS() && BIT_B(word2))
3849 m68ki_exception_trap(EXCEPTION_CHK);
3850 return;
3851 }
3852 m68ki_exception_illegal();
3853 }
3854
3855
3856 M68KMAKE_OP(clr, 8, ., d)
3857 {
3858 DY &= 0xffffff00;
3859
3860 FLAG_N = NFLAG_CLEAR;
3861 FLAG_V = VFLAG_CLEAR;
3862 FLAG_C = CFLAG_CLEAR;
3863 FLAG_Z = ZFLAG_SET;
3864 }
3865
3866
3867 M68KMAKE_OP(clr, 8, ., .)
3868 {
3869 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
3870
3871 FLAG_N = NFLAG_CLEAR;
3872 FLAG_V = VFLAG_CLEAR;
3873 FLAG_C = CFLAG_CLEAR;
3874 FLAG_Z = ZFLAG_SET;
3875 }
3876
3877
3878 M68KMAKE_OP(clr, 16, ., d)
3879 {
3880 DY &= 0xffff0000;
3881
3882 FLAG_N = NFLAG_CLEAR;
3883 FLAG_V = VFLAG_CLEAR;
3884 FLAG_C = CFLAG_CLEAR;
3885 FLAG_Z = ZFLAG_SET;
3886 }
3887
3888
3889 M68KMAKE_OP(clr, 16, ., .)
3890 {
3891 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
3892
3893 FLAG_N = NFLAG_CLEAR;
3894 FLAG_V = VFLAG_CLEAR;
3895 FLAG_C = CFLAG_CLEAR;
3896 FLAG_Z = ZFLAG_SET;
3897 }
3898
3899
3900 M68KMAKE_OP(clr, 32, ., d)
3901 {
3902 DY = 0;
3903
3904 FLAG_N = NFLAG_CLEAR;
3905 FLAG_V = VFLAG_CLEAR;
3906 FLAG_C = CFLAG_CLEAR;
3907 FLAG_Z = ZFLAG_SET;
3908 }
3909
3910
3911 M68KMAKE_OP(clr, 32, ., .)
3912 {
3913 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
3914
3915 FLAG_N = NFLAG_CLEAR;
3916 FLAG_V = VFLAG_CLEAR;
3917 FLAG_C = CFLAG_CLEAR;
3918 FLAG_Z = ZFLAG_SET;
3919 }
3920
3921
3922 M68KMAKE_OP(cmp, 8, ., d)
3923 {
3924 uint src = MASK_OUT_ABOVE_8(DY);
3925 uint dst = MASK_OUT_ABOVE_8(DX);
3926 uint res = dst - src;
3927
3928 FLAG_N = NFLAG_8(res);
3929 FLAG_Z = MASK_OUT_ABOVE_8(res);
3930 FLAG_V = VFLAG_SUB_8(src, dst, res);
3931 FLAG_C = CFLAG_8(res);
3932 }
3933
3934
3935 M68KMAKE_OP(cmp, 8, ., .)
3936 {
3937 uint src = M68KMAKE_GET_OPER_AY_8;
3938 uint dst = MASK_OUT_ABOVE_8(DX);
3939 uint res = dst - src;
3940
3941 FLAG_N = NFLAG_8(res);
3942 FLAG_Z = MASK_OUT_ABOVE_8(res);
3943 FLAG_V = VFLAG_SUB_8(src, dst, res);
3944 FLAG_C = CFLAG_8(res);
3945 }
3946
3947
3948 M68KMAKE_OP(cmp, 16, ., d)
3949 {
3950 uint src = MASK_OUT_ABOVE_16(DY);
3951 uint dst = MASK_OUT_ABOVE_16(DX);
3952 uint res = dst - src;
3953
3954 FLAG_N = NFLAG_16(res);
3955 FLAG_Z = MASK_OUT_ABOVE_16(res);
3956 FLAG_V = VFLAG_SUB_16(src, dst, res);
3957 FLAG_C = CFLAG_16(res);
3958 }
3959
3960
3961 M68KMAKE_OP(cmp, 16, ., a)
3962 {
3963 uint src = MASK_OUT_ABOVE_16(AY);
3964 uint dst = MASK_OUT_ABOVE_16(DX);
3965 uint res = dst - src;
3966
3967 FLAG_N = NFLAG_16(res);
3968 FLAG_Z = MASK_OUT_ABOVE_16(res);
3969 FLAG_V = VFLAG_SUB_16(src, dst, res);
3970 FLAG_C = CFLAG_16(res);
3971 }
3972
3973
3974 M68KMAKE_OP(cmp, 16, ., .)
3975 {
3976 uint src = M68KMAKE_GET_OPER_AY_16;
3977 uint dst = MASK_OUT_ABOVE_16(DX);
3978 uint res = dst - src;
3979
3980 FLAG_N = NFLAG_16(res);
3981 FLAG_Z = MASK_OUT_ABOVE_16(res);
3982 FLAG_V = VFLAG_SUB_16(src, dst, res);
3983 FLAG_C = CFLAG_16(res);
3984 }
3985
3986
3987 M68KMAKE_OP(cmp, 32, ., d)
3988 {
3989 uint src = DY;
3990 uint dst = DX;
3991 uint res = dst - src;
3992
3993 FLAG_N = NFLAG_32(res);
3994 FLAG_Z = MASK_OUT_ABOVE_32(res);
3995 FLAG_V = VFLAG_SUB_32(src, dst, res);
3996 FLAG_C = CFLAG_SUB_32(src, dst, res);
3997 }
3998
3999
4000 M68KMAKE_OP(cmp, 32, ., a)
4001 {
4002 uint src = AY;
4003 uint dst = DX;
4004 uint res = dst - src;
4005
4006 FLAG_N = NFLAG_32(res);
4007 FLAG_Z = MASK_OUT_ABOVE_32(res);
4008 FLAG_V = VFLAG_SUB_32(src, dst, res);
4009 FLAG_C = CFLAG_SUB_32(src, dst, res);
4010 }
4011
4012
4013 M68KMAKE_OP(cmp, 32, ., .)
4014 {
4015 uint src = M68KMAKE_GET_OPER_AY_32;
4016 uint dst = DX;
4017 uint res = dst - src;
4018
4019 FLAG_N = NFLAG_32(res);
4020 FLAG_Z = MASK_OUT_ABOVE_32(res);
4021 FLAG_V = VFLAG_SUB_32(src, dst, res);
4022 FLAG_C = CFLAG_SUB_32(src, dst, res);
4023 }
4024
4025
4026 M68KMAKE_OP(cmpa, 16, ., d)
4027 {
4028 uint src = MAKE_INT_16(DY);
4029 uint dst = AX;
4030 uint res = dst - src;
4031
4032 FLAG_N = NFLAG_32(res);
4033 FLAG_Z = MASK_OUT_ABOVE_32(res);
4034 FLAG_V = VFLAG_SUB_32(src, dst, res);
4035 FLAG_C = CFLAG_SUB_32(src, dst, res);
4036 }
4037
4038
4039 M68KMAKE_OP(cmpa, 16, ., a)
4040 {
4041 uint src = MAKE_INT_16(AY);
4042 uint dst = AX;
4043 uint res = dst - src;
4044
4045 FLAG_N = NFLAG_32(res);
4046 FLAG_Z = MASK_OUT_ABOVE_32(res);
4047 FLAG_V = VFLAG_SUB_32(src, dst, res);
4048 FLAG_C = CFLAG_SUB_32(src, dst, res);
4049 }
4050
4051
4052 M68KMAKE_OP(cmpa, 16, ., .)
4053 {
4054 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4055 uint dst = AX;
4056 uint res = dst - src;
4057
4058 FLAG_N = NFLAG_32(res);
4059 FLAG_Z = MASK_OUT_ABOVE_32(res);
4060 FLAG_V = VFLAG_SUB_32(src, dst, res);
4061 FLAG_C = CFLAG_SUB_32(src, dst, res);
4062 }
4063
4064
4065 M68KMAKE_OP(cmpa, 32, ., d)
4066 {
4067 uint src = DY;
4068 uint dst = AX;
4069 uint res = dst - src;
4070
4071 FLAG_N = NFLAG_32(res);
4072 FLAG_Z = MASK_OUT_ABOVE_32(res);
4073 FLAG_V = VFLAG_SUB_32(src, dst, res);
4074 FLAG_C = CFLAG_SUB_32(src, dst, res);
4075 }
4076
4077
4078 M68KMAKE_OP(cmpa, 32, ., a)
4079 {
4080 uint src = AY;
4081 uint dst = AX;
4082 uint res = dst - src;
4083
4084 FLAG_N = NFLAG_32(res);
4085 FLAG_Z = MASK_OUT_ABOVE_32(res);
4086 FLAG_V = VFLAG_SUB_32(src, dst, res);
4087 FLAG_C = CFLAG_SUB_32(src, dst, res);
4088 }
4089
4090
4091 M68KMAKE_OP(cmpa, 32, ., .)
4092 {
4093 uint src = M68KMAKE_GET_OPER_AY_32;
4094 uint dst = AX;
4095 uint res = dst - src;
4096
4097 FLAG_N = NFLAG_32(res);
4098 FLAG_Z = MASK_OUT_ABOVE_32(res);
4099 FLAG_V = VFLAG_SUB_32(src, dst, res);
4100 FLAG_C = CFLAG_SUB_32(src, dst, res);
4101 }
4102
4103
4104 M68KMAKE_OP(cmpi, 8, ., d)
4105 {
4106 uint src = OPER_I_8();
4107 uint dst = MASK_OUT_ABOVE_8(DY);
4108 uint res = dst - src;
4109
4110 FLAG_N = NFLAG_8(res);
4111 FLAG_Z = MASK_OUT_ABOVE_8(res);
4112 FLAG_V = VFLAG_SUB_8(src, dst, res);
4113 FLAG_C = CFLAG_8(res);
4114 }
4115
4116
4117 M68KMAKE_OP(cmpi, 8, ., .)
4118 {
4119 uint src = OPER_I_8();
4120 uint dst = M68KMAKE_GET_OPER_AY_8;
4121 uint res = dst - src;
4122
4123 FLAG_N = NFLAG_8(res);
4124 FLAG_Z = MASK_OUT_ABOVE_8(res);
4125 FLAG_V = VFLAG_SUB_8(src, dst, res);
4126 FLAG_C = CFLAG_8(res);
4127 }
4128
4129
4130 M68KMAKE_OP(cmpi, 8, ., pcdi)
4131 {
4132 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4133 {
4134 uint src = OPER_I_8();
4135 uint dst = OPER_PCDI_8();
4136 uint res = dst - src;
4137
4138 FLAG_N = NFLAG_8(res);
4139 FLAG_Z = MASK_OUT_ABOVE_8(res);
4140 FLAG_V = VFLAG_SUB_8(src, dst, res);
4141 FLAG_C = CFLAG_8(res);
4142 return;
4143 }
4144 m68ki_exception_illegal();
4145 }
4146
4147
4148 M68KMAKE_OP(cmpi, 8, ., pcix)
4149 {
4150 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4151 {
4152 uint src = OPER_I_8();
4153 uint dst = OPER_PCIX_8();
4154 uint res = dst - src;
4155
4156 FLAG_N = NFLAG_8(res);
4157 FLAG_Z = MASK_OUT_ABOVE_8(res);
4158 FLAG_V = VFLAG_SUB_8(src, dst, res);
4159 FLAG_C = CFLAG_8(res);
4160 return;
4161 }
4162 m68ki_exception_illegal();
4163 }
4164
4165
4166 M68KMAKE_OP(cmpi, 16, ., d)
4167 {
4168 uint src = OPER_I_16();
4169 uint dst = MASK_OUT_ABOVE_16(DY);
4170 uint res = dst - src;
4171
4172 FLAG_N = NFLAG_16(res);
4173 FLAG_Z = MASK_OUT_ABOVE_16(res);
4174 FLAG_V = VFLAG_SUB_16(src, dst, res);
4175 FLAG_C = CFLAG_16(res);
4176 }
4177
4178
4179 M68KMAKE_OP(cmpi, 16, ., .)
4180 {
4181 uint src = OPER_I_16();
4182 uint dst = M68KMAKE_GET_OPER_AY_16;
4183 uint res = dst - src;
4184
4185 FLAG_N = NFLAG_16(res);
4186 FLAG_Z = MASK_OUT_ABOVE_16(res);
4187 FLAG_V = VFLAG_SUB_16(src, dst, res);
4188 FLAG_C = CFLAG_16(res);
4189 }
4190
4191
4192 M68KMAKE_OP(cmpi, 16, ., pcdi)
4193 {
4194 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4195 {
4196 uint src = OPER_I_16();
4197 uint dst = OPER_PCDI_16();
4198 uint res = dst - src;
4199
4200 FLAG_N = NFLAG_16(res);
4201 FLAG_Z = MASK_OUT_ABOVE_16(res);
4202 FLAG_V = VFLAG_SUB_16(src, dst, res);
4203 FLAG_C = CFLAG_16(res);
4204 return;
4205 }
4206 m68ki_exception_illegal();
4207 }
4208
4209
4210 M68KMAKE_OP(cmpi, 16, ., pcix)
4211 {
4212 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4213 {
4214 uint src = OPER_I_16();
4215 uint dst = OPER_PCIX_16();
4216 uint res = dst - src;
4217
4218 FLAG_N = NFLAG_16(res);
4219 FLAG_Z = MASK_OUT_ABOVE_16(res);
4220 FLAG_V = VFLAG_SUB_16(src, dst, res);
4221 FLAG_C = CFLAG_16(res);
4222 return;
4223 }
4224 m68ki_exception_illegal();
4225 }
4226
4227
4228 M68KMAKE_OP(cmpi, 32, ., d)
4229 {
4230 uint src = OPER_I_32();
4231 uint dst = DY;
4232 uint res = dst - src;
4233
4234 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */
4235
4236 FLAG_N = NFLAG_32(res);
4237 FLAG_Z = MASK_OUT_ABOVE_32(res);
4238 FLAG_V = VFLAG_SUB_32(src, dst, res);
4239 FLAG_C = CFLAG_SUB_32(src, dst, res);
4240 }
4241
4242
4243 M68KMAKE_OP(cmpi, 32, ., .)
4244 {
4245 uint src = OPER_I_32();
4246 uint dst = M68KMAKE_GET_OPER_AY_32;
4247 uint res = dst - src;
4248
4249 FLAG_N = NFLAG_32(res);
4250 FLAG_Z = MASK_OUT_ABOVE_32(res);
4251 FLAG_V = VFLAG_SUB_32(src, dst, res);
4252 FLAG_C = CFLAG_SUB_32(src, dst, res);
4253 }
4254
4255
4256 M68KMAKE_OP(cmpi, 32, ., pcdi)
4257 {
4258 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4259 {
4260 uint src = OPER_I_32();
4261 uint dst = OPER_PCDI_32();
4262 uint res = dst - src;
4263
4264 FLAG_N = NFLAG_32(res);
4265 FLAG_Z = MASK_OUT_ABOVE_32(res);
4266 FLAG_V = VFLAG_SUB_32(src, dst, res);
4267 FLAG_C = CFLAG_SUB_32(src, dst, res);
4268 return;
4269 }
4270 m68ki_exception_illegal();
4271 }
4272
4273
4274 M68KMAKE_OP(cmpi, 32, ., pcix)
4275 {
4276 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4277 {
4278 uint src = OPER_I_32();
4279 uint dst = OPER_PCIX_32();
4280 uint res = dst - src;
4281
4282 FLAG_N = NFLAG_32(res);
4283 FLAG_Z = MASK_OUT_ABOVE_32(res);
4284 FLAG_V = VFLAG_SUB_32(src, dst, res);
4285 FLAG_C = CFLAG_SUB_32(src, dst, res);
4286 return;
4287 }
4288 m68ki_exception_illegal();
4289 }
4290
4291
4292 M68KMAKE_OP(cmpm, 8, ., ax7)
4293 {
4294 uint src = OPER_AY_PI_8();
4295 uint dst = OPER_A7_PI_8();
4296 uint res = dst - src;
4297
4298 FLAG_N = NFLAG_8(res);
4299 FLAG_Z = MASK_OUT_ABOVE_8(res);
4300 FLAG_V = VFLAG_SUB_8(src, dst, res);
4301 FLAG_C = CFLAG_8(res);
4302 }
4303
4304
4305 M68KMAKE_OP(cmpm, 8, ., ay7)
4306 {
4307 uint src = OPER_A7_PI_8();
4308 uint dst = OPER_AX_PI_8();
4309 uint res = dst - src;
4310
4311 FLAG_N = NFLAG_8(res);
4312 FLAG_Z = MASK_OUT_ABOVE_8(res);
4313 FLAG_V = VFLAG_SUB_8(src, dst, res);
4314 FLAG_C = CFLAG_8(res);
4315 }
4316
4317
4318 M68KMAKE_OP(cmpm, 8, ., axy7)
4319 {
4320 uint src = OPER_A7_PI_8();
4321 uint dst = OPER_A7_PI_8();
4322 uint res = dst - src;
4323
4324 FLAG_N = NFLAG_8(res);
4325 FLAG_Z = MASK_OUT_ABOVE_8(res);
4326 FLAG_V = VFLAG_SUB_8(src, dst, res);
4327 FLAG_C = CFLAG_8(res);
4328 }
4329
4330
4331 M68KMAKE_OP(cmpm, 8, ., .)
4332 {
4333 uint src = OPER_AY_PI_8();
4334 uint dst = OPER_AX_PI_8();
4335 uint res = dst - src;
4336
4337 FLAG_N = NFLAG_8(res);
4338 FLAG_Z = MASK_OUT_ABOVE_8(res);
4339 FLAG_V = VFLAG_SUB_8(src, dst, res);
4340 FLAG_C = CFLAG_8(res);
4341 }
4342
4343
4344 M68KMAKE_OP(cmpm, 16, ., .)
4345 {
4346 uint src = OPER_AY_PI_16();
4347 uint dst = OPER_AX_PI_16();
4348 uint res = dst - src;
4349
4350 FLAG_N = NFLAG_16(res);
4351 FLAG_Z = MASK_OUT_ABOVE_16(res);
4352 FLAG_V = VFLAG_SUB_16(src, dst, res);
4353 FLAG_C = CFLAG_16(res);
4354 }
4355
4356
4357 M68KMAKE_OP(cmpm, 32, ., .)
4358 {
4359 uint src = OPER_AY_PI_32();
4360 uint dst = OPER_AX_PI_32();
4361 uint res = dst - src;
4362
4363 FLAG_N = NFLAG_32(res);
4364 FLAG_Z = MASK_OUT_ABOVE_32(res);
4365 FLAG_V = VFLAG_SUB_32(src, dst, res);
4366 FLAG_C = CFLAG_SUB_32(src, dst, res);
4367 }
4368
4369
4370 M68KMAKE_OP(cpbcc, 32, ., .)
4371 {
4372 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4373 {
4374 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4375 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4376 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4377 return;
4378 }
4379 m68ki_exception_1111();
4380 }
4381
4382
4383 M68KMAKE_OP(cpdbcc, 32, ., .)
4384 {
4385 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4386 {
4387 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4388 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4389 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4390 return;
4391 }
4392 m68ki_exception_1111();
4393 }
4394
4395
4396 M68KMAKE_OP(cpgen, 32, ., .)
4397 {
4398 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4399 {
4400 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4401 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4402 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4403 return;
4404 }
4405 m68ki_exception_1111();
4406 }
4407
4408
4409 M68KMAKE_OP(cpscc, 32, ., .)
4410 {
4411 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4412 {
4413 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4414 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4415 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4416 return;
4417 }
4418 m68ki_exception_1111();
4419 }
4420
4421
4422 M68KMAKE_OP(cptrapcc, 32, ., .)
4423 {
4424 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4425 {
4426 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4427 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4428 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4429 return;
4430 }
4431 m68ki_exception_1111();
4432 }
4433
4434
4435 M68KMAKE_OP(dbt, 16, ., .)
4436 {
4437 REG_PC += 2;
4438 }
4439
4440
4441 M68KMAKE_OP(dbf, 16, ., .)
4442 {
4443 uint* r_dst = &DY;
4444 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4445
4446 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4447 if(res != 0xffff)
4448 {
4449 uint offset = OPER_I_16();
4450 REG_PC -= 2;
4451 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4452 m68ki_branch_16(offset);
4453 USE_CYCLES(CYC_DBCC_F_NOEXP);
4454 return;
4455 }
4456 REG_PC += 2;
4457 USE_CYCLES(CYC_DBCC_F_EXP);
4458 }
4459
4460
4461 M68KMAKE_OP(dbcc, 16, ., .)
4462 {
4463 if(M68KMAKE_NOT_CC)
4464 {
4465 uint* r_dst = &DY;
4466 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4467
4468 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4469 if(res != 0xffff)
4470 {
4471 uint offset = OPER_I_16();
4472 REG_PC -= 2;
4473 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4474 m68ki_branch_16(offset);
4475 USE_CYCLES(CYC_DBCC_F_NOEXP);
4476 return;
4477 }
4478 REG_PC += 2;
4479 USE_CYCLES(CYC_DBCC_F_EXP);
4480 return;
4481 }
4482 REG_PC += 2;
4483 }
4484
4485
4486 M68KMAKE_OP(divs, 16, ., d)
4487 {
4488 uint* r_dst = &DX;
4489 sint src = MAKE_INT_16(DY);
4490 sint quotient;
4491 sint remainder;
4492
4493 if(src != 0)
4494 {
4495 if((uint32)*r_dst == 0x80000000 && src == -1)
4496 {
4497 FLAG_Z = 0;
4498 FLAG_N = NFLAG_CLEAR;
4499 FLAG_V = VFLAG_CLEAR;
4500 FLAG_C = CFLAG_CLEAR;
4501 *r_dst = 0;
4502 return;
4503 }
4504
4505 quotient = MAKE_INT_32(*r_dst) / src;
4506 remainder = MAKE_INT_32(*r_dst) % src;
4507
4508 if(quotient == MAKE_INT_16(quotient))
4509 {
4510 FLAG_Z = quotient;
4511 FLAG_N = NFLAG_16(quotient);
4512 FLAG_V = VFLAG_CLEAR;
4513 FLAG_C = CFLAG_CLEAR;
4514 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4515 return;
4516 }
4517 FLAG_V = VFLAG_SET;
4518 return;
4519 }
4520 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4521 }
4522
4523
4524 M68KMAKE_OP(divs, 16, ., .)
4525 {
4526 uint* r_dst = &DX;
4527 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4528 sint quotient;
4529 sint remainder;
4530
4531 if(src != 0)
4532 {
4533 if((uint32)*r_dst == 0x80000000 && src == -1)
4534 {
4535 FLAG_Z = 0;
4536 FLAG_N = NFLAG_CLEAR;
4537 FLAG_V = VFLAG_CLEAR;
4538 FLAG_C = CFLAG_CLEAR;
4539 *r_dst = 0;
4540 return;
4541 }
4542
4543 quotient = MAKE_INT_32(*r_dst) / src;
4544 remainder = MAKE_INT_32(*r_dst) % src;
4545
4546 if(quotient == MAKE_INT_16(quotient))
4547 {
4548 FLAG_Z = quotient;
4549 FLAG_N = NFLAG_16(quotient);
4550 FLAG_V = VFLAG_CLEAR;
4551 FLAG_C = CFLAG_CLEAR;
4552 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4553 return;
4554 }
4555 FLAG_V = VFLAG_SET;
4556 return;
4557 }
4558 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4559 }
4560
4561
4562 M68KMAKE_OP(divu, 16, ., d)
4563 {
4564 uint* r_dst = &DX;
4565 uint src = MASK_OUT_ABOVE_16(DY);
4566
4567 if(src != 0)
4568 {
4569 uint quotient = *r_dst / src;
4570 uint remainder = *r_dst % src;
4571
4572 if(quotient < 0x10000)
4573 {
4574 FLAG_Z = quotient;
4575 FLAG_N = NFLAG_16(quotient);
4576 FLAG_V = VFLAG_CLEAR;
4577 FLAG_C = CFLAG_CLEAR;
4578 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4579 return;
4580 }
4581 FLAG_V = VFLAG_SET;
4582 return;
4583 }
4584 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4585 }
4586
4587
4588 M68KMAKE_OP(divu, 16, ., .)
4589 {
4590 uint* r_dst = &DX;
4591 uint src = M68KMAKE_GET_OPER_AY_16;
4592
4593 if(src != 0)
4594 {
4595 uint quotient = *r_dst / src;
4596 uint remainder = *r_dst % src;
4597
4598 if(quotient < 0x10000)
4599 {
4600 FLAG_Z = quotient;
4601 FLAG_N = NFLAG_16(quotient);
4602 FLAG_V = VFLAG_CLEAR;
4603 FLAG_C = CFLAG_CLEAR;
4604 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4605 return;
4606 }
4607 FLAG_V = VFLAG_SET;
4608 return;
4609 }
4610 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4611 }
4612
4613
4614 M68KMAKE_OP(divl, 32, ., d)
4615 {
4616 #if M68K_USE_64_BIT
4617
4618 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4619 {
4620 uint word2 = OPER_I_16();
4621 uint64 divisor = DY;
4622 uint64 dividend = 0;
4623 uint64 quotient = 0;
4624 uint64 remainder = 0;
4625
4626 if(divisor != 0)
4627 {
4628 if(BIT_A(word2)) /* 64 bit */
4629 {
4630 dividend = REG_D[word2 & 7];
4631 dividend <<= 32;
4632 dividend |= REG_D[(word2 >> 12) & 7];
4633
4634 if(BIT_B(word2)) /* signed */
4635 {
4636 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4637 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4638 if((sint64)quotient != (sint64)((sint32)quotient))
4639 {
4640 FLAG_V = VFLAG_SET;
4641 return;
4642 }
4643 }
4644 else /* unsigned */
4645 {
4646 quotient = dividend / divisor;
4647 if(quotient > 0xffffffff)
4648 {
4649 FLAG_V = VFLAG_SET;
4650 return;
4651 }
4652 remainder = dividend % divisor;
4653 }
4654 }
4655 else /* 32 bit */
4656 {
4657 dividend = REG_D[(word2 >> 12) & 7];
4658 if(BIT_B(word2)) /* signed */
4659 {
4660 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4661 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4662 }
4663 else /* unsigned */
4664 {
4665 quotient = dividend / divisor;
4666 remainder = dividend % divisor;
4667 }
4668 }
4669
4670 REG_D[word2 & 7] = remainder;
4671 REG_D[(word2 >> 12) & 7] = quotient;
4672
4673 FLAG_N = NFLAG_32(quotient);
4674 FLAG_Z = quotient;
4675 FLAG_V = VFLAG_CLEAR;
4676 FLAG_C = CFLAG_CLEAR;
4677 return;
4678 }
4679 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4680 return;
4681 }
4682 m68ki_exception_illegal();
4683
4684 #else
4685
4686 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4687 {
4688 uint word2 = OPER_I_16();
4689 uint divisor = DY;
4690 uint dividend_hi = REG_D[word2 & 7];
4691 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4692 uint quotient = 0;
4693 uint remainder = 0;
4694 uint dividend_neg = 0;
4695 uint divisor_neg = 0;
4696 sint i;
4697 uint overflow;
4698
4699 if(divisor != 0)
4700 {
4701 /* quad / long : long quotient, long remainder */
4702 if(BIT_A(word2))
4703 {
4704 if(BIT_B(word2)) /* signed */
4705 {
4706 /* special case in signed divide */
4707 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4708 {
4709 REG_D[word2 & 7] = 0;
4710 REG_D[(word2 >> 12) & 7] = 0x80000000;
4711
4712 FLAG_N = NFLAG_SET;
4713 FLAG_Z = ZFLAG_CLEAR;
4714 FLAG_V = VFLAG_CLEAR;
4715 FLAG_C = CFLAG_CLEAR;
4716 return;
4717 }
4718 if(GET_MSB_32(dividend_hi))
4719 {
4720 dividend_neg = 1;
4721 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4722 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4723 }
4724 if(GET_MSB_32(divisor))
4725 {
4726 divisor_neg = 1;
4727 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4728
4729 }
4730 }
4731
4732 /* if the upper long is greater than the divisor, we're overflowing. */
4733 if(dividend_hi >= divisor)
4734 {
4735 FLAG_V = VFLAG_SET;
4736 return;
4737 }
4738
4739 for(i = 31; i >= 0; i--)
4740 {
4741 quotient <<= 1;
4742 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4743 if(remainder >= divisor)
4744 {
4745 remainder -= divisor;
4746 quotient++;
4747 }
4748 }
4749 for(i = 31; i >= 0; i--)
4750 {
4751 quotient <<= 1;
4752 overflow = GET_MSB_32(remainder);
4753 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4754 if(remainder >= divisor || overflow)
4755 {
4756 remainder -= divisor;
4757 quotient++;
4758 }
4759 }
4760
4761 if(BIT_B(word2)) /* signed */
4762 {
4763 if(quotient > 0x7fffffff)
4764 {
4765 FLAG_V = VFLAG_SET;
4766 return;
4767 }
4768 if(dividend_neg)
4769 {
4770 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4771 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4772 }
4773 if(divisor_neg)
4774 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4775 }
4776
4777 REG_D[word2 & 7] = remainder;
4778 REG_D[(word2 >> 12) & 7] = quotient;
4779
4780 FLAG_N = NFLAG_32(quotient);
4781 FLAG_Z = quotient;
4782 FLAG_V = VFLAG_CLEAR;
4783 FLAG_C = CFLAG_CLEAR;
4784 return;
4785 }
4786
4787 /* long / long: long quotient, maybe long remainder */
4788 if(BIT_B(word2)) /* signed */
4789 {
4790 /* Special case in divide */
4791 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4792 {
4793 FLAG_N = NFLAG_SET;
4794 FLAG_Z = ZFLAG_CLEAR;
4795 FLAG_V = VFLAG_CLEAR;
4796 FLAG_C = CFLAG_CLEAR;
4797 REG_D[(word2 >> 12) & 7] = 0x80000000;
4798 REG_D[word2 & 7] = 0;
4799 return;
4800 }
4801 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4802 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4803 }
4804 else
4805 {
4806 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4807 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4808 }
4809
4810 FLAG_N = NFLAG_32(quotient);
4811 FLAG_Z = quotient;
4812 FLAG_V = VFLAG_CLEAR;
4813 FLAG_C = CFLAG_CLEAR;
4814 return;
4815 }
4816 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4817 return;
4818 }
4819 m68ki_exception_illegal();
4820
4821 #endif
4822 }
4823
4824
4825 M68KMAKE_OP(divl, 32, ., .)
4826 {
4827 #if M68K_USE_64_BIT
4828
4829 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4830 {
4831 uint word2 = OPER_I_16();
4832 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
4833 uint64 dividend = 0;
4834 uint64 quotient = 0;
4835 uint64 remainder = 0;
4836
4837 if(divisor != 0)
4838 {
4839 if(BIT_A(word2)) /* 64 bit */
4840 {
4841 dividend = REG_D[word2 & 7];
4842 dividend <<= 32;
4843 dividend |= REG_D[(word2 >> 12) & 7];
4844
4845 if(BIT_B(word2)) /* signed */
4846 {
4847 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4848 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4849 if((sint64)quotient != (sint64)((sint32)quotient))
4850 {
4851 FLAG_V = VFLAG_SET;
4852 return;
4853 }
4854 }
4855 else /* unsigned */
4856 {
4857 quotient = dividend / divisor;
4858 if(quotient > 0xffffffff)
4859 {
4860 FLAG_V = VFLAG_SET;
4861 return;
4862 }
4863 remainder = dividend % divisor;
4864 }
4865 }
4866 else /* 32 bit */
4867 {
4868 dividend = REG_D[(word2 >> 12) & 7];
4869 if(BIT_B(word2)) /* signed */
4870 {
4871 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4872 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4873 }
4874 else /* unsigned */
4875 {
4876 quotient = dividend / divisor;
4877 remainder = dividend % divisor;
4878 }
4879 }
4880
4881 REG_D[word2 & 7] = remainder;
4882 REG_D[(word2 >> 12) & 7] = quotient;
4883
4884 FLAG_N = NFLAG_32(quotient);
4885 FLAG_Z = quotient;
4886 FLAG_V = VFLAG_CLEAR;
4887 FLAG_C = CFLAG_CLEAR;
4888 return;
4889 }
4890 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4891 return;
4892 }
4893 m68ki_exception_illegal();
4894
4895 #else
4896
4897 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4898 {
4899 uint word2 = OPER_I_16();
4900 uint divisor = M68KMAKE_GET_OPER_AY_32;
4901 uint dividend_hi = REG_D[word2 & 7];
4902 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4903 uint quotient = 0;
4904 uint remainder = 0;
4905 uint dividend_neg = 0;
4906 uint divisor_neg = 0;
4907 sint i;
4908 uint overflow;
4909
4910 if(divisor != 0)
4911 {
4912 /* quad / long : long quotient, long remainder */
4913 if(BIT_A(word2))
4914 {
4915 if(BIT_B(word2)) /* signed */
4916 {
4917 /* special case in signed divide */
4918 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4919 {
4920 REG_D[word2 & 7] = 0;
4921 REG_D[(word2 >> 12) & 7] = 0x80000000;
4922
4923 FLAG_N = NFLAG_SET;
4924 FLAG_Z = ZFLAG_CLEAR;
4925 FLAG_V = VFLAG_CLEAR;
4926 FLAG_C = CFLAG_CLEAR;
4927 return;
4928 }
4929 if(GET_MSB_32(dividend_hi))
4930 {
4931 dividend_neg = 1;
4932 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4933 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4934 }
4935 if(GET_MSB_32(divisor))
4936 {
4937 divisor_neg = 1;
4938 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4939
4940 }
4941 }
4942
4943 /* if the upper long is greater than the divisor, we're overflowing. */
4944 if(dividend_hi >= divisor)
4945 {
4946 FLAG_V = VFLAG_SET;
4947 return;
4948 }
4949
4950 for(i = 31; i >= 0; i--)
4951 {
4952 quotient <<= 1;
4953 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4954 if(remainder >= divisor)
4955 {
4956 remainder -= divisor;
4957 quotient++;
4958 }
4959 }
4960 for(i = 31; i >= 0; i--)
4961 {
4962 quotient <<= 1;
4963 overflow = GET_MSB_32(remainder);
4964 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4965 if(remainder >= divisor || overflow)
4966 {
4967 remainder -= divisor;
4968 quotient++;
4969 }
4970 }
4971
4972 if(BIT_B(word2)) /* signed */
4973 {
4974 if(quotient > 0x7fffffff)
4975 {
4976 FLAG_V = VFLAG_SET;
4977 return;
4978 }
4979 if(dividend_neg)
4980 {
4981 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4982 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4983 }
4984 if(divisor_neg)
4985 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4986 }
4987
4988 REG_D[word2 & 7] = remainder;
4989 REG_D[(word2 >> 12) & 7] = quotient;
4990
4991 FLAG_N = NFLAG_32(quotient);
4992 FLAG_Z = quotient;
4993 FLAG_V = VFLAG_CLEAR;
4994 FLAG_C = CFLAG_CLEAR;
4995 return;
4996 }
4997
4998 /* long / long: long quotient, maybe long remainder */
4999 if(BIT_B(word2)) /* signed */
5000 {
5001 /* Special case in divide */
5002 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
5003 {
5004 FLAG_N = NFLAG_SET;
5005 FLAG_Z = ZFLAG_CLEAR;
5006 FLAG_V = VFLAG_CLEAR;
5007 FLAG_C = CFLAG_CLEAR;
5008 REG_D[(word2 >> 12) & 7] = 0x80000000;
5009 REG_D[word2 & 7] = 0;
5010 return;
5011 }
5012 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
5013 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
5014 }
5015 else
5016 {
5017 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
5018 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
5019 }
5020
5021 FLAG_N = NFLAG_32(quotient);
5022 FLAG_Z = quotient;
5023 FLAG_V = VFLAG_CLEAR;
5024 FLAG_C = CFLAG_CLEAR;
5025 return;
5026 }
5027 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
5028 return;
5029 }
5030 m68ki_exception_illegal();
5031
5032 #endif
5033 }
5034
5035
5036 M68KMAKE_OP(eor, 8, ., d)
5037 {
5038 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
5039
5040 FLAG_N = NFLAG_8(res);
5041 FLAG_Z = res;
5042 FLAG_C = CFLAG_CLEAR;
5043 FLAG_V = VFLAG_CLEAR;
5044 }
5045
5046
5047 M68KMAKE_OP(eor, 8, ., .)
5048 {
5049 uint ea = M68KMAKE_GET_EA_AY_8;
5050 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
5051
5052 m68ki_write_8(ea, res);
5053
5054 FLAG_N = NFLAG_8(res);
5055 FLAG_Z = res;
5056 FLAG_C = CFLAG_CLEAR;
5057 FLAG_V = VFLAG_CLEAR;
5058 }
5059
5060
5061 M68KMAKE_OP(eor, 16, ., d)
5062 {
5063 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
5064
5065 FLAG_N = NFLAG_16(res);
5066 FLAG_Z = res;
5067 FLAG_C = CFLAG_CLEAR;
5068 FLAG_V = VFLAG_CLEAR;
5069 }
5070
5071
5072 M68KMAKE_OP(eor, 16, ., .)
5073 {
5074 uint ea = M68KMAKE_GET_EA_AY_16;
5075 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
5076
5077 m68ki_write_16(ea, res);
5078
5079 FLAG_N = NFLAG_16(res);
5080 FLAG_Z = res;
5081 FLAG_C = CFLAG_CLEAR;
5082 FLAG_V = VFLAG_CLEAR;
5083 }
5084
5085
5086 M68KMAKE_OP(eor, 32, ., d)
5087 {
5088 uint res = DY ^= DX;
5089
5090 FLAG_N = NFLAG_32(res);
5091 FLAG_Z = res;
5092 FLAG_C = CFLAG_CLEAR;
5093 FLAG_V = VFLAG_CLEAR;
5094 }
5095
5096
5097 M68KMAKE_OP(eor, 32, ., .)
5098 {
5099 uint ea = M68KMAKE_GET_EA_AY_32;
5100 uint res = DX ^ m68ki_read_32(ea);
5101
5102 m68ki_write_32(ea, res);
5103
5104 FLAG_N = NFLAG_32(res);
5105 FLAG_Z = res;
5106 FLAG_C = CFLAG_CLEAR;
5107 FLAG_V = VFLAG_CLEAR;
5108 }
5109
5110
5111 M68KMAKE_OP(eori, 8, ., d)
5112 {
5113 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
5114
5115 FLAG_N = NFLAG_8(res);
5116 FLAG_Z = res;
5117 FLAG_C = CFLAG_CLEAR;
5118 FLAG_V = VFLAG_CLEAR;
5119 }
5120
5121
5122 M68KMAKE_OP(eori, 8, ., .)
5123 {
5124 uint src = OPER_I_8();
5125 uint ea = M68KMAKE_GET_EA_AY_8;
5126 uint res = src ^ m68ki_read_8(ea);
5127
5128 m68ki_write_8(ea, res);
5129
5130 FLAG_N = NFLAG_8(res);
5131 FLAG_Z = res;
5132 FLAG_C = CFLAG_CLEAR;
5133 FLAG_V = VFLAG_CLEAR;
5134 }
5135
5136
5137 M68KMAKE_OP(eori, 16, ., d)
5138 {
5139 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
5140
5141 FLAG_N = NFLAG_16(res);
5142 FLAG_Z = res;
5143 FLAG_C = CFLAG_CLEAR;
5144 FLAG_V = VFLAG_CLEAR;
5145 }
5146
5147
5148 M68KMAKE_OP(eori, 16, ., .)
5149 {
5150 uint src = OPER_I_16();
5151 uint ea = M68KMAKE_GET_EA_AY_16;
5152 uint res = src ^ m68ki_read_16(ea);
5153
5154 m68ki_write_16(ea, res);
5155
5156 FLAG_N = NFLAG_16(res);
5157 FLAG_Z = res;
5158 FLAG_C = CFLAG_CLEAR;
5159 FLAG_V = VFLAG_CLEAR;
5160 }
5161
5162
5163 M68KMAKE_OP(eori, 32, ., d)
5164 {
5165 uint res = DY ^= OPER_I_32();
5166
5167 FLAG_N = NFLAG_32(res);
5168 FLAG_Z = res;
5169 FLAG_C = CFLAG_CLEAR;
5170 FLAG_V = VFLAG_CLEAR;
5171 }
5172
5173
5174 M68KMAKE_OP(eori, 32, ., .)
5175 {
5176 uint src = OPER_I_32();
5177 uint ea = M68KMAKE_GET_EA_AY_32;
5178 uint res = src ^ m68ki_read_32(ea);
5179
5180 m68ki_write_32(ea, res);
5181
5182 FLAG_N = NFLAG_32(res);
5183 FLAG_Z = res;
5184 FLAG_C = CFLAG_CLEAR;
5185 FLAG_V = VFLAG_CLEAR;
5186 }
5187
5188
5189 M68KMAKE_OP(eori, 16, toc, .)
5190 {
5191 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
5192 }
5193
5194
5195 M68KMAKE_OP(eori, 16, tos, .)
5196 {
5197 if(FLAG_S)
5198 {
5199 uint src = OPER_I_16();
5200 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5201 m68ki_set_sr(m68ki_get_sr() ^ src);
5202 return;
5203 }
5204 m68ki_exception_privilege_violation();
5205 }
5206
5207
5208 M68KMAKE_OP(exg, 32, dd, .)
5209 {
5210 uint* reg_a = &DX;
5211 uint* reg_b = &DY;
5212 uint tmp = *reg_a;
5213 *reg_a = *reg_b;
5214 *reg_b = tmp;
5215 }
5216
5217
5218 M68KMAKE_OP(exg, 32, aa, .)
5219 {
5220 uint* reg_a = &AX;
5221 uint* reg_b = &AY;
5222 uint tmp = *reg_a;
5223 *reg_a = *reg_b;
5224 *reg_b = tmp;
5225 }
5226
5227
5228 M68KMAKE_OP(exg, 32, da, .)
5229 {
5230 uint* reg_a = &DX;
5231 uint* reg_b = &AY;
5232 uint tmp = *reg_a;
5233 *reg_a = *reg_b;
5234 *reg_b = tmp;
5235 }
5236
5237
5238 M68KMAKE_OP(ext, 16, ., .)
5239 {
5240 uint* r_dst = &DY;
5241
5242 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
5243
5244 FLAG_N = NFLAG_16(*r_dst);
5245 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
5246 FLAG_V = VFLAG_CLEAR;
5247 FLAG_C = CFLAG_CLEAR;
5248 }
5249
5250
5251 M68KMAKE_OP(ext, 32, ., .)
5252 {
5253 uint* r_dst = &DY;
5254
5255 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
5256
5257 FLAG_N = NFLAG_32(*r_dst);
5258 FLAG_Z = *r_dst;
5259 FLAG_V = VFLAG_CLEAR;
5260 FLAG_C = CFLAG_CLEAR;
5261 }
5262
5263
5264 M68KMAKE_OP(extb, 32, ., .)
5265 {
5266 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5267 {
5268 uint* r_dst = &DY;
5269
5270 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
5271
5272 FLAG_N = NFLAG_32(*r_dst);
5273 FLAG_Z = *r_dst;
5274 FLAG_V = VFLAG_CLEAR;
5275 FLAG_C = CFLAG_CLEAR;
5276 return;
5277 }
5278 m68ki_exception_illegal();
5279 }
5280
5281
5282 M68KMAKE_OP(illegal, 0, ., .)
5283 {
5284 m68ki_exception_illegal();
5285 }
5286
5287 M68KMAKE_OP(jmp, 32, ., .)
5288 {
5289 m68ki_jump(M68KMAKE_GET_EA_AY_32);
5290 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5291 if(REG_PC == REG_PPC)
5292 USE_ALL_CYCLES();
5293 }
5294
5295
5296 M68KMAKE_OP(jsr, 32, ., .)
5297 {
5298 uint ea = M68KMAKE_GET_EA_AY_32;
5299 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
5300 m68ki_push_32(REG_PC);
5301 m68ki_jump(ea);
5302 }
5303
5304
5305 M68KMAKE_OP(lea, 32, ., .)
5306 {
5307 AX = M68KMAKE_GET_EA_AY_32;
5308 }
5309
5310
5311 M68KMAKE_OP(link, 16, ., a7)
5312 {
5313 REG_A[7] -= 4;
5314 m68ki_write_32(REG_A[7], REG_A[7]);
5315 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5316 }
5317
5318
5319 M68KMAKE_OP(link, 16, ., .)
5320 {
5321 uint* r_dst = &AY;
5322
5323 m68ki_push_32(*r_dst);
5324 *r_dst = REG_A[7];
5325 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5326 }
5327
5328
5329 M68KMAKE_OP(link, 32, ., a7)
5330 {
5331 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5332 {
5333 REG_A[7] -= 4;
5334 m68ki_write_32(REG_A[7], REG_A[7]);
5335 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5336 return;
5337 }
5338 m68ki_exception_illegal();
5339 }
5340
5341
5342 M68KMAKE_OP(link, 32, ., .)
5343 {
5344 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5345 {
5346 uint* r_dst = &AY;
5347
5348 m68ki_push_32(*r_dst);
5349 *r_dst = REG_A[7];
5350 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5351 return;
5352 }
5353 m68ki_exception_illegal();
5354 }
5355
5356
5357 M68KMAKE_OP(lsr, 8, s, .)
5358 {
5359 uint* r_dst = &DY;
5360 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5361 uint src = MASK_OUT_ABOVE_8(*r_dst);
5362 uint res = src >> shift;
5363
5364 if(shift != 0)
5365 USE_CYCLES(shift<<CYC_SHIFT);
5366
5367 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5368
5369 FLAG_N = NFLAG_CLEAR;
5370 FLAG_Z = res;
5371 FLAG_X = FLAG_C = src << (9-shift);
5372 FLAG_V = VFLAG_CLEAR;
5373 }
5374
5375
5376 M68KMAKE_OP(lsr, 16, s, .)
5377 {
5378 uint* r_dst = &DY;
5379 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5380 uint src = MASK_OUT_ABOVE_16(*r_dst);
5381 uint res = src >> shift;
5382
5383 if(shift != 0)
5384 USE_CYCLES(shift<<CYC_SHIFT);
5385
5386 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5387
5388 FLAG_N = NFLAG_CLEAR;
5389 FLAG_Z = res;
5390 FLAG_X = FLAG_C = src << (9-shift);
5391 FLAG_V = VFLAG_CLEAR;
5392 }
5393
5394
5395 M68KMAKE_OP(lsr, 32, s, .)
5396 {
5397 uint* r_dst = &DY;
5398 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5399 uint src = *r_dst;
5400 uint res = src >> shift;
5401
5402 if(shift != 0)
5403 USE_CYCLES(shift<<CYC_SHIFT);
5404
5405 *r_dst = res;
5406
5407 FLAG_N = NFLAG_CLEAR;
5408 FLAG_Z = res;
5409 FLAG_X = FLAG_C = src << (9-shift);
5410 FLAG_V = VFLAG_CLEAR;
5411 }
5412
5413
5414 M68KMAKE_OP(lsr, 8, r, .)
5415 {
5416 uint* r_dst = &DY;
5417 uint shift = DX & 0x3f;
5418 uint src = MASK_OUT_ABOVE_8(*r_dst);
5419 uint res = src >> shift;
5420
5421 if(shift != 0)
5422 {
5423 USE_CYCLES(shift<<CYC_SHIFT);
5424
5425 if(shift <= 8)
5426 {
5427 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5428 FLAG_X = FLAG_C = src << (9-shift);
5429 FLAG_N = NFLAG_CLEAR;
5430 FLAG_Z = res;
5431 FLAG_V = VFLAG_CLEAR;
5432 return;
5433 }
5434
5435 *r_dst &= 0xffffff00;
5436 FLAG_X = XFLAG_CLEAR;
5437 FLAG_C = CFLAG_CLEAR;
5438 FLAG_N = NFLAG_CLEAR;
5439 FLAG_Z = ZFLAG_SET;
5440 FLAG_V = VFLAG_CLEAR;
5441 return;
5442 }
5443
5444 FLAG_C = CFLAG_CLEAR;
5445 FLAG_N = NFLAG_8(src);
5446 FLAG_Z = src;
5447 FLAG_V = VFLAG_CLEAR;
5448 }
5449
5450
5451 M68KMAKE_OP(lsr, 16, r, .)
5452 {
5453 uint* r_dst = &DY;
5454 uint shift = DX & 0x3f;
5455 uint src = MASK_OUT_ABOVE_16(*r_dst);
5456 uint res = src >> shift;
5457
5458 if(shift != 0)
5459 {
5460 USE_CYCLES(shift<<CYC_SHIFT);
5461
5462 if(shift <= 16)
5463 {
5464 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5465 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5466 FLAG_N = NFLAG_CLEAR;
5467 FLAG_Z = res;
5468 FLAG_V = VFLAG_CLEAR;
5469 return;
5470 }
5471
5472 *r_dst &= 0xffff0000;
5473 FLAG_X = XFLAG_CLEAR;
5474 FLAG_C = CFLAG_CLEAR;
5475 FLAG_N = NFLAG_CLEAR;
5476 FLAG_Z = ZFLAG_SET;
5477 FLAG_V = VFLAG_CLEAR;
5478 return;
5479 }
5480
5481 FLAG_C = CFLAG_CLEAR;
5482 FLAG_N = NFLAG_16(src);
5483 FLAG_Z = src;
5484 FLAG_V = VFLAG_CLEAR;
5485 }
5486
5487
5488 M68KMAKE_OP(lsr, 32, r, .)
5489 {
5490 uint* r_dst = &DY;
5491 uint shift = DX & 0x3f;
5492 uint src = *r_dst;
5493 uint res = src >> shift;
5494
5495 if(shift != 0)
5496 {
5497 USE_CYCLES(shift<<CYC_SHIFT);
5498
5499 if(shift < 32)
5500 {
5501 *r_dst = res;
5502 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5503 FLAG_N = NFLAG_CLEAR;
5504 FLAG_Z = res;
5505 FLAG_V = VFLAG_CLEAR;
5506 return;
5507 }
5508
5509 *r_dst = 0;
5510 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
5511 FLAG_N = NFLAG_CLEAR;
5512 FLAG_Z = ZFLAG_SET;
5513 FLAG_V = VFLAG_CLEAR;
5514 return;
5515 }
5516
5517 FLAG_C = CFLAG_CLEAR;
5518 FLAG_N = NFLAG_32(src);
5519 FLAG_Z = src;
5520 FLAG_V = VFLAG_CLEAR;
5521 }
5522
5523
5524 M68KMAKE_OP(lsr, 16, ., .)
5525 {
5526 uint ea = M68KMAKE_GET_EA_AY_16;
5527 uint src = m68ki_read_16(ea);
5528 uint res = src >> 1;
5529
5530 m68ki_write_16(ea, res);
5531
5532 FLAG_N = NFLAG_CLEAR;
5533 FLAG_Z = res;
5534 FLAG_C = FLAG_X = src << 8;
5535 FLAG_V = VFLAG_CLEAR;
5536 }
5537
5538
5539 M68KMAKE_OP(lsl, 8, s, .)
5540 {
5541 uint* r_dst = &DY;
5542 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5543 uint src = MASK_OUT_ABOVE_8(*r_dst);
5544 uint res = MASK_OUT_ABOVE_8(src << shift);
5545
5546 if(shift != 0)
5547 USE_CYCLES(shift<<CYC_SHIFT);
5548
5549 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5550
5551 FLAG_N = NFLAG_8(res);
5552 FLAG_Z = res;
5553 FLAG_X = FLAG_C = src << shift;
5554 FLAG_V = VFLAG_CLEAR;
5555 }
5556
5557
5558 M68KMAKE_OP(lsl, 16, s, .)
5559 {
5560 uint* r_dst = &DY;
5561 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5562 uint src = MASK_OUT_ABOVE_16(*r_dst);
5563 uint res = MASK_OUT_ABOVE_16(src << shift);
5564
5565 if(shift != 0)
5566 USE_CYCLES(shift<<CYC_SHIFT);
5567
5568 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5569
5570 FLAG_N = NFLAG_16(res);
5571 FLAG_Z = res;
5572 FLAG_X = FLAG_C = src >> (8-shift);
5573 FLAG_V = VFLAG_CLEAR;
5574 }
5575
5576
5577 M68KMAKE_OP(lsl, 32, s, .)
5578 {
5579 uint* r_dst = &DY;
5580 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5581 uint src = *r_dst;
5582 uint res = MASK_OUT_ABOVE_32(src << shift);
5583
5584 if(shift != 0)
5585 USE_CYCLES(shift<<CYC_SHIFT);
5586
5587 *r_dst = res;
5588
5589 FLAG_N = NFLAG_32(res);
5590 FLAG_Z = res;
5591 FLAG_X = FLAG_C = src >> (24-shift);
5592 FLAG_V = VFLAG_CLEAR;
5593 }
5594
5595
5596 M68KMAKE_OP(lsl, 8, r, .)
5597 {
5598 uint* r_dst = &DY;
5599 uint shift = DX & 0x3f;
5600 uint src = MASK_OUT_ABOVE_8(*r_dst);
5601 uint res = MASK_OUT_ABOVE_8(src << shift);
5602
5603 if(shift != 0)
5604 {
5605 USE_CYCLES(shift<<CYC_SHIFT);
5606
5607 if(shift <= 8)
5608 {
5609 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5610 FLAG_X = FLAG_C = src << shift;
5611 FLAG_N = NFLAG_8(res);
5612 FLAG_Z = res;
5613 FLAG_V = VFLAG_CLEAR;
5614 return;
5615 }
5616
5617 *r_dst &= 0xffffff00;
5618 FLAG_X = XFLAG_CLEAR;
5619 FLAG_C = CFLAG_CLEAR;
5620 FLAG_N = NFLAG_CLEAR;
5621 FLAG_Z = ZFLAG_SET;
5622 FLAG_V = VFLAG_CLEAR;
5623 return;
5624 }
5625
5626 FLAG_C = CFLAG_CLEAR;
5627 FLAG_N = NFLAG_8(src);
5628 FLAG_Z = src;
5629 FLAG_V = VFLAG_CLEAR;
5630 }
5631
5632
5633 M68KMAKE_OP(lsl, 16, r, .)
5634 {
5635 uint* r_dst = &DY;
5636 uint shift = DX & 0x3f;
5637 uint src = MASK_OUT_ABOVE_16(*r_dst);
5638 uint res = MASK_OUT_ABOVE_16(src << shift);
5639
5640 if(shift != 0)
5641 {
5642 USE_CYCLES(shift<<CYC_SHIFT);
5643
5644 if(shift <= 16)
5645 {
5646 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5647 FLAG_X = FLAG_C = (src << shift) >> 8;
5648 FLAG_N = NFLAG_16(res);
5649 FLAG_Z = res;
5650 FLAG_V = VFLAG_CLEAR;
5651 return;
5652 }
5653
5654 *r_dst &= 0xffff0000;
5655 FLAG_X = XFLAG_CLEAR;
5656 FLAG_C = CFLAG_CLEAR;
5657 FLAG_N = NFLAG_CLEAR;
5658 FLAG_Z = ZFLAG_SET;
5659 FLAG_V = VFLAG_CLEAR;
5660 return;
5661 }
5662
5663 FLAG_C = CFLAG_CLEAR;
5664 FLAG_N = NFLAG_16(src);
5665 FLAG_Z = src;
5666 FLAG_V = VFLAG_CLEAR;
5667 }
5668
5669
5670 M68KMAKE_OP(lsl, 32, r, .)
5671 {
5672 uint* r_dst = &DY;
5673 uint shift = DX & 0x3f;
5674 uint src = *r_dst;
5675 uint res = MASK_OUT_ABOVE_32(src << shift);
5676
5677 if(shift != 0)
5678 {
5679 USE_CYCLES(shift<<CYC_SHIFT);
5680
5681 if(shift < 32)
5682 {
5683 *r_dst = res;
5684 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
5685 FLAG_N = NFLAG_32(res);
5686 FLAG_Z = res;
5687 FLAG_V = VFLAG_CLEAR;
5688 return;
5689 }
5690
5691 *r_dst = 0;
5692 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
5693 FLAG_N = NFLAG_CLEAR;
5694 FLAG_Z = ZFLAG_SET;
5695 FLAG_V = VFLAG_CLEAR;
5696 return;
5697 }
5698
5699 FLAG_C = CFLAG_CLEAR;
5700 FLAG_N = NFLAG_32(src);
5701 FLAG_Z = src;
5702 FLAG_V = VFLAG_CLEAR;
5703 }
5704
5705
5706 M68KMAKE_OP(lsl, 16, ., .)
5707 {
5708 uint ea = M68KMAKE_GET_EA_AY_16;
5709 uint src = m68ki_read_16(ea);
5710 uint res = MASK_OUT_ABOVE_16(src << 1);
5711
5712 m68ki_write_16(ea, res);
5713
5714 FLAG_N = NFLAG_16(res);
5715 FLAG_Z = res;
5716 FLAG_X = FLAG_C = src >> 7;
5717 FLAG_V = VFLAG_CLEAR;
5718 }
5719
5720
5721 M68KMAKE_OP(move, 8, d, d)
5722 {
5723 uint res = MASK_OUT_ABOVE_8(DY);
5724 uint* r_dst = &DX;
5725
5726 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5727
5728 FLAG_N = NFLAG_8(res);
5729 FLAG_Z = res;
5730 FLAG_V = VFLAG_CLEAR;
5731 FLAG_C = CFLAG_CLEAR;
5732 }
5733
5734
5735 M68KMAKE_OP(move, 8, d, .)
5736 {
5737 uint res = M68KMAKE_GET_OPER_AY_8;
5738 uint* r_dst = &DX;
5739
5740 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5741
5742 FLAG_N = NFLAG_8(res);
5743 FLAG_Z = res;
5744 FLAG_V = VFLAG_CLEAR;
5745 FLAG_C = CFLAG_CLEAR;
5746 }
5747
5748
5749 M68KMAKE_OP(move, 8, ai, d)
5750 {
5751 uint res = MASK_OUT_ABOVE_8(DY);
5752 uint ea = EA_AX_AI_8();
5753
5754 m68ki_write_8(ea, res);
5755
5756 FLAG_N = NFLAG_8(res);
5757 FLAG_Z = res;
5758 FLAG_V = VFLAG_CLEAR;
5759 FLAG_C = CFLAG_CLEAR;
5760 }
5761
5762
5763 M68KMAKE_OP(move, 8, ai, .)
5764 {
5765 uint res = M68KMAKE_GET_OPER_AY_8;
5766 uint ea = EA_AX_AI_8();
5767
5768 m68ki_write_8(ea, res);
5769
5770 FLAG_N = NFLAG_8(res);
5771 FLAG_Z = res;
5772 FLAG_V = VFLAG_CLEAR;
5773 FLAG_C = CFLAG_CLEAR;
5774 }
5775
5776
5777 M68KMAKE_OP(move, 8, pi7, d)
5778 {
5779 uint res = MASK_OUT_ABOVE_8(DY);
5780 uint ea = EA_A7_PI_8();
5781
5782 m68ki_write_8(ea, res);
5783
5784 FLAG_N = NFLAG_8(res);
5785 FLAG_Z = res;
5786 FLAG_V = VFLAG_CLEAR;
5787 FLAG_C = CFLAG_CLEAR;
5788 }
5789
5790
5791 M68KMAKE_OP(move, 8, pi, d)
5792 {
5793 uint res = MASK_OUT_ABOVE_8(DY);
5794 uint ea = EA_AX_PI_8();
5795
5796 m68ki_write_8(ea, res);
5797
5798 FLAG_N = NFLAG_8(res);
5799 FLAG_Z = res;
5800 FLAG_V = VFLAG_CLEAR;
5801 FLAG_C = CFLAG_CLEAR;
5802 }
5803
5804
5805 M68KMAKE_OP(move, 8, pi7, .)
5806 {
5807 uint res = M68KMAKE_GET_OPER_AY_8;
5808 uint ea = EA_A7_PI_8();
5809
5810 m68ki_write_8(ea, res);
5811
5812 FLAG_N = NFLAG_8(res);
5813 FLAG_Z = res;
5814 FLAG_V = VFLAG_CLEAR;
5815 FLAG_C = CFLAG_CLEAR;
5816 }
5817
5818
5819 M68KMAKE_OP(move, 8, pi, .)
5820 {
5821 uint res = M68KMAKE_GET_OPER_AY_8;
5822 uint ea = EA_AX_PI_8();
5823
5824 m68ki_write_8(ea, res);
5825
5826 FLAG_N = NFLAG_8(res);
5827 FLAG_Z = res;
5828 FLAG_V = VFLAG_CLEAR;
5829 FLAG_C = CFLAG_CLEAR;
5830 }
5831
5832
5833 M68KMAKE_OP(move, 8, pd7, d)
5834 {
5835 uint res = MASK_OUT_ABOVE_8(DY);
5836 uint ea = EA_A7_PD_8();
5837
5838 m68ki_write_8(ea, res);
5839
5840 FLAG_N = NFLAG_8(res);
5841 FLAG_Z = res;
5842 FLAG_V = VFLAG_CLEAR;
5843 FLAG_C = CFLAG_CLEAR;
5844 }
5845
5846
5847 M68KMAKE_OP(move, 8, pd, d)
5848 {
5849 uint res = MASK_OUT_ABOVE_8(DY);
5850 uint ea = EA_AX_PD_8();
5851
5852 m68ki_write_8(ea, res);
5853
5854 FLAG_N = NFLAG_8(res);
5855 FLAG_Z = res;
5856 FLAG_V = VFLAG_CLEAR;
5857 FLAG_C = CFLAG_CLEAR;
5858 }
5859
5860
5861 M68KMAKE_OP(move, 8, pd7, .)
5862 {
5863 uint res = M68KMAKE_GET_OPER_AY_8;
5864 uint ea = EA_A7_PD_8();
5865
5866 m68ki_write_8(ea, res);
5867
5868 FLAG_N = NFLAG_8(res);
5869 FLAG_Z = res;
5870 FLAG_V = VFLAG_CLEAR;
5871 FLAG_C = CFLAG_CLEAR;
5872 }
5873
5874
5875 M68KMAKE_OP(move, 8, pd, .)
5876 {
5877 uint res = M68KMAKE_GET_OPER_AY_8;
5878 uint ea = EA_AX_PD_8();
5879
5880 m68ki_write_8(ea, res);
5881
5882 FLAG_N = NFLAG_8(res);
5883 FLAG_Z = res;
5884 FLAG_V = VFLAG_CLEAR;
5885 FLAG_C = CFLAG_CLEAR;
5886 }
5887
5888
5889 M68KMAKE_OP(move, 8, di, d)
5890 {
5891 uint res = MASK_OUT_ABOVE_8(DY);
5892 uint ea = EA_AX_DI_8();
5893
5894 m68ki_write_8(ea, res);
5895
5896 FLAG_N = NFLAG_8(res);
5897 FLAG_Z = res;
5898 FLAG_V = VFLAG_CLEAR;
5899 FLAG_C = CFLAG_CLEAR;
5900 }
5901
5902
5903 M68KMAKE_OP(move, 8, di, .)
5904 {
5905 uint res = M68KMAKE_GET_OPER_AY_8;
5906 uint ea = EA_AX_DI_8();
5907
5908 m68ki_write_8(ea, res);
5909
5910 FLAG_N = NFLAG_8(res);
5911 FLAG_Z = res;
5912 FLAG_V = VFLAG_CLEAR;
5913 FLAG_C = CFLAG_CLEAR;
5914 }
5915
5916
5917 M68KMAKE_OP(move, 8, ix, d)
5918 {
5919 uint res = MASK_OUT_ABOVE_8(DY);
5920 uint ea = EA_AX_IX_8();
5921
5922 m68ki_write_8(ea, res);
5923
5924 FLAG_N = NFLAG_8(res);
5925 FLAG_Z = res;
5926 FLAG_V = VFLAG_CLEAR;
5927 FLAG_C = CFLAG_CLEAR;
5928 }
5929
5930
5931 M68KMAKE_OP(move, 8, ix, .)
5932 {
5933 uint res = M68KMAKE_GET_OPER_AY_8;
5934 uint ea = EA_AX_IX_8();
5935
5936 m68ki_write_8(ea, res);
5937
5938 FLAG_N = NFLAG_8(res);
5939 FLAG_Z = res;
5940 FLAG_V = VFLAG_CLEAR;
5941 FLAG_C = CFLAG_CLEAR;
5942 }
5943
5944
5945 M68KMAKE_OP(move, 8, aw, d)
5946 {
5947 uint res = MASK_OUT_ABOVE_8(DY);
5948 uint ea = EA_AW_8();
5949
5950 m68ki_write_8(ea, res);
5951
5952 FLAG_N = NFLAG_8(res);
5953 FLAG_Z = res;
5954 FLAG_V = VFLAG_CLEAR;
5955 FLAG_C = CFLAG_CLEAR;
5956 }
5957
5958
5959 M68KMAKE_OP(move, 8, aw, .)
5960 {
5961 uint res = M68KMAKE_GET_OPER_AY_8;
5962 uint ea = EA_AW_8();
5963
5964 m68ki_write_8(ea, res);
5965
5966 FLAG_N = NFLAG_8(res);
5967 FLAG_Z = res;
5968 FLAG_V = VFLAG_CLEAR;
5969 FLAG_C = CFLAG_CLEAR;
5970 }
5971
5972
5973 M68KMAKE_OP(move, 8, al, d)
5974 {
5975 uint res = MASK_OUT_ABOVE_8(DY);
5976 uint ea = EA_AL_8();
5977
5978 m68ki_write_8(ea, res);
5979
5980 FLAG_N = NFLAG_8(res);
5981 FLAG_Z = res;
5982 FLAG_V = VFLAG_CLEAR;
5983 FLAG_C = CFLAG_CLEAR;
5984 }
5985
5986
5987 M68KMAKE_OP(move, 8, al, .)
5988 {
5989 uint res = M68KMAKE_GET_OPER_AY_8;
5990 uint ea = EA_AL_8();
5991
5992 m68ki_write_8(ea, res);
5993
5994 FLAG_N = NFLAG_8(res);
5995 FLAG_Z = res;
5996 FLAG_V = VFLAG_CLEAR;
5997 FLAG_C = CFLAG_CLEAR;
5998 }
5999
6000
6001 M68KMAKE_OP(move, 16, d, d)
6002 {
6003 uint res = MASK_OUT_ABOVE_16(DY);
6004 uint* r_dst = &DX;
6005
6006 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
6007
6008 FLAG_N = NFLAG_16(res);
6009 FLAG_Z = res;
6010 FLAG_V = VFLAG_CLEAR;
6011 FLAG_C = CFLAG_CLEAR;
6012 }
6013
6014
6015 M68KMAKE_OP(move, 16, d, a)
6016 {
6017 uint res = MASK_OUT_ABOVE_16(AY);
6018 uint* r_dst = &DX;
6019
6020 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
6021
6022 FLAG_N = NFLAG_16(res);
6023 FLAG_Z = res;
6024 FLAG_V = VFLAG_CLEAR;
6025 FLAG_C = CFLAG_CLEAR;
6026 }
6027
6028
6029 M68KMAKE_OP(move, 16, d, .)
6030 {
6031 uint res = M68KMAKE_GET_OPER_AY_16;
6032 uint* r_dst = &DX;
6033
6034 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
6035
6036 FLAG_N = NFLAG_16(res);
6037 FLAG_Z = res;
6038 FLAG_V = VFLAG_CLEAR;
6039 FLAG_C = CFLAG_CLEAR;
6040 }
6041
6042
6043 M68KMAKE_OP(move, 16, ai, d)
6044 {
6045 uint res = MASK_OUT_ABOVE_16(DY);
6046 uint ea = EA_AX_AI_16();
6047
6048 m68ki_write_16(ea, res);
6049
6050 FLAG_N = NFLAG_16(res);
6051 FLAG_Z = res;
6052 FLAG_V = VFLAG_CLEAR;
6053 FLAG_C = CFLAG_CLEAR;
6054 }
6055
6056
6057 M68KMAKE_OP(move, 16, ai, a)
6058 {
6059 uint res = MASK_OUT_ABOVE_16(AY);
6060 uint ea = EA_AX_AI_16();
6061
6062 m68ki_write_16(ea, res);
6063
6064 FLAG_N = NFLAG_16(res);
6065 FLAG_Z = res;
6066 FLAG_V = VFLAG_CLEAR;
6067 FLAG_C = CFLAG_CLEAR;
6068 }
6069
6070
6071 M68KMAKE_OP(move, 16, ai, .)
6072 {
6073 uint res = M68KMAKE_GET_OPER_AY_16;
6074 uint ea = EA_AX_AI_16();
6075
6076 m68ki_write_16(ea, res);
6077
6078 FLAG_N = NFLAG_16(res);
6079 FLAG_Z = res;
6080 FLAG_V = VFLAG_CLEAR;
6081 FLAG_C = CFLAG_CLEAR;
6082 }
6083
6084
6085 M68KMAKE_OP(move, 16, pi, d)
6086 {
6087 uint res = MASK_OUT_ABOVE_16(DY);
6088 uint ea = EA_AX_PI_16();
6089
6090 m68ki_write_16(ea, res);
6091
6092 FLAG_N = NFLAG_16(res);
6093 FLAG_Z = res;
6094 FLAG_V = VFLAG_CLEAR;
6095 FLAG_C = CFLAG_CLEAR;
6096 }
6097
6098
6099 M68KMAKE_OP(move, 16, pi, a)
6100 {
6101 uint res = MASK_OUT_ABOVE_16(AY);
6102 uint ea = EA_AX_PI_16();
6103
6104 m68ki_write_16(ea, res);
6105
6106 FLAG_N = NFLAG_16(res);
6107 FLAG_Z = res;
6108 FLAG_V = VFLAG_CLEAR;
6109 FLAG_C = CFLAG_CLEAR;
6110 }
6111
6112
6113 M68KMAKE_OP(move, 16, pi, .)
6114 {
6115 uint res = M68KMAKE_GET_OPER_AY_16;
6116 uint ea = EA_AX_PI_16();
6117
6118 m68ki_write_16(ea, res);
6119
6120 FLAG_N = NFLAG_16(res);
6121 FLAG_Z = res;
6122 FLAG_V = VFLAG_CLEAR;
6123 FLAG_C = CFLAG_CLEAR;
6124 }
6125
6126
6127 M68KMAKE_OP(move, 16, pd, d)
6128 {
6129 uint res = MASK_OUT_ABOVE_16(DY);
6130 uint ea = EA_AX_PD_16();
6131
6132 m68ki_write_16(ea, res);
6133
6134 FLAG_N = NFLAG_16(res);
6135 FLAG_Z = res;
6136 FLAG_V = VFLAG_CLEAR;
6137 FLAG_C = CFLAG_CLEAR;
6138 }
6139
6140
6141 M68KMAKE_OP(move, 16, pd, a)
6142 {
6143 uint res = MASK_OUT_ABOVE_16(AY);
6144 uint ea = EA_AX_PD_16();
6145
6146 m68ki_write_16(ea, res);
6147
6148 FLAG_N = NFLAG_16(res);
6149 FLAG_Z = res;
6150 FLAG_V = VFLAG_CLEAR;
6151 FLAG_C = CFLAG_CLEAR;
6152 }
6153
6154
6155 M68KMAKE_OP(move, 16, pd, .)
6156 {
6157 uint res = M68KMAKE_GET_OPER_AY_16;
6158 uint ea = EA_AX_PD_16();
6159
6160 m68ki_write_16(ea, res);
6161
6162 FLAG_N = NFLAG_16(res);
6163 FLAG_Z = res;
6164 FLAG_V = VFLAG_CLEAR;
6165 FLAG_C = CFLAG_CLEAR;
6166 }
6167
6168
6169 M68KMAKE_OP(move, 16, di, d)
6170 {
6171 uint res = MASK_OUT_ABOVE_16(DY);
6172 uint ea = EA_AX_DI_16();
6173
6174 m68ki_write_16(ea, res);
6175
6176 FLAG_N = NFLAG_16(res);
6177 FLAG_Z = res;
6178 FLAG_V = VFLAG_CLEAR;
6179 FLAG_C = CFLAG_CLEAR;
6180 }
6181
6182
6183 M68KMAKE_OP(move, 16, di, a)
6184 {
6185 uint res = MASK_OUT_ABOVE_16(AY);
6186 uint ea = EA_AX_DI_16();
6187
6188 m68ki_write_16(ea, res);
6189
6190 FLAG_N = NFLAG_16(res);
6191 FLAG_Z = res;
6192 FLAG_V = VFLAG_CLEAR;
6193 FLAG_C = CFLAG_CLEAR;
6194 }
6195
6196
6197 M68KMAKE_OP(move, 16, di, .)
6198 {
6199 uint res = M68KMAKE_GET_OPER_AY_16;
6200 uint ea = EA_AX_DI_16();
6201
6202 m68ki_write_16(ea, res);
6203
6204 FLAG_N = NFLAG_16(res);
6205 FLAG_Z = res;
6206 FLAG_V = VFLAG_CLEAR;
6207 FLAG_C = CFLAG_CLEAR;
6208 }
6209
6210
6211 M68KMAKE_OP(move, 16, ix, d)
6212 {
6213 uint res = MASK_OUT_ABOVE_16(DY);
6214 uint ea = EA_AX_IX_16();
6215
6216 m68ki_write_16(ea, res);
6217
6218 FLAG_N = NFLAG_16(res);
6219 FLAG_Z = res;
6220 FLAG_V = VFLAG_CLEAR;
6221 FLAG_C = CFLAG_CLEAR;
6222 }
6223
6224
6225 M68KMAKE_OP(move, 16, ix, a)
6226 {
6227 uint res = MASK_OUT_ABOVE_16(AY);
6228 uint ea = EA_AX_IX_16();
6229
6230 m68ki_write_16(ea, res);
6231
6232 FLAG_N = NFLAG_16(res);
6233 FLAG_Z = res;
6234 FLAG_V = VFLAG_CLEAR;
6235 FLAG_C = CFLAG_CLEAR;
6236 }
6237
6238
6239 M68KMAKE_OP(move, 16, ix, .)
6240 {
6241 uint res = M68KMAKE_GET_OPER_AY_16;
6242 uint ea = EA_AX_IX_16();
6243
6244 m68ki_write_16(ea, res);
6245
6246 FLAG_N = NFLAG_16(res);
6247 FLAG_Z = res;
6248 FLAG_V = VFLAG_CLEAR;
6249 FLAG_C = CFLAG_CLEAR;
6250 }
6251
6252
6253 M68KMAKE_OP(move, 16, aw, d)
6254 {
6255 uint res = MASK_OUT_ABOVE_16(DY);
6256 uint ea = EA_AW_16();
6257
6258 m68ki_write_16(ea, res);
6259
6260 FLAG_N = NFLAG_16(res);
6261 FLAG_Z = res;
6262 FLAG_V = VFLAG_CLEAR;
6263 FLAG_C = CFLAG_CLEAR;
6264 }
6265
6266
6267 M68KMAKE_OP(move, 16, aw, a)
6268 {
6269 uint res = MASK_OUT_ABOVE_16(AY);
6270 uint ea = EA_AW_16();
6271
6272 m68ki_write_16(ea, res);
6273
6274 FLAG_N = NFLAG_16(res);
6275 FLAG_Z = res;
6276 FLAG_V = VFLAG_CLEAR;
6277 FLAG_C = CFLAG_CLEAR;
6278 }
6279
6280
6281 M68KMAKE_OP(move, 16, aw, .)
6282 {
6283 uint res = M68KMAKE_GET_OPER_AY_16;
6284 uint ea = EA_AW_16();
6285
6286 m68ki_write_16(ea, res);
6287
6288 FLAG_N = NFLAG_16(res);
6289 FLAG_Z = res;
6290 FLAG_V = VFLAG_CLEAR;
6291 FLAG_C = CFLAG_CLEAR;
6292 }
6293
6294
6295 M68KMAKE_OP(move, 16, al, d)
6296 {
6297 uint res = MASK_OUT_ABOVE_16(DY);
6298 uint ea = EA_AL_16();
6299
6300 m68ki_write_16(ea, res);
6301
6302 FLAG_N = NFLAG_16(res);
6303 FLAG_Z = res;
6304 FLAG_V = VFLAG_CLEAR;
6305 FLAG_C = CFLAG_CLEAR;
6306 }
6307
6308
6309 M68KMAKE_OP(move, 16, al, a)
6310 {
6311 uint res = MASK_OUT_ABOVE_16(AY);
6312 uint ea = EA_AL_16();
6313
6314 m68ki_write_16(ea, res);
6315
6316 FLAG_N = NFLAG_16(res);
6317 FLAG_Z = res;
6318 FLAG_V = VFLAG_CLEAR;
6319 FLAG_C = CFLAG_CLEAR;
6320 }
6321
6322
6323 M68KMAKE_OP(move, 16, al, .)
6324 {
6325 uint res = M68KMAKE_GET_OPER_AY_16;
6326 uint ea = EA_AL_16();
6327
6328 m68ki_write_16(ea, res);
6329
6330 FLAG_N = NFLAG_16(res);
6331 FLAG_Z = res;
6332 FLAG_V = VFLAG_CLEAR;
6333 FLAG_C = CFLAG_CLEAR;
6334 }
6335
6336
6337 M68KMAKE_OP(move, 32, d, d)
6338 {
6339 uint res = DY;
6340 uint* r_dst = &DX;
6341
6342 *r_dst = res;
6343
6344 FLAG_N = NFLAG_32(res);
6345 FLAG_Z = res;
6346 FLAG_V = VFLAG_CLEAR;
6347 FLAG_C = CFLAG_CLEAR;
6348 }
6349
6350
6351 M68KMAKE_OP(move, 32, d, a)
6352 {
6353 uint res = AY;
6354 uint* r_dst = &DX;
6355
6356 *r_dst = res;
6357
6358 FLAG_N = NFLAG_32(res);
6359 FLAG_Z = res;
6360 FLAG_V = VFLAG_CLEAR;
6361 FLAG_C = CFLAG_CLEAR;
6362 }
6363
6364
6365 M68KMAKE_OP(move, 32, d, .)
6366 {
6367 uint res = M68KMAKE_GET_OPER_AY_32;
6368 uint* r_dst = &DX;
6369
6370 *r_dst = res;
6371
6372 FLAG_N = NFLAG_32(res);
6373 FLAG_Z = res;
6374 FLAG_V = VFLAG_CLEAR;
6375 FLAG_C = CFLAG_CLEAR;
6376 }
6377
6378
6379 M68KMAKE_OP(move, 32, ai, d)
6380 {
6381 uint res = DY;
6382 uint ea = EA_AX_AI_32();
6383
6384 m68ki_write_32(ea, res);
6385
6386 FLAG_N = NFLAG_32(res);
6387 FLAG_Z = res;
6388 FLAG_V = VFLAG_CLEAR;
6389 FLAG_C = CFLAG_CLEAR;
6390 }
6391
6392
6393 M68KMAKE_OP(move, 32, ai, a)
6394 {
6395 uint res = AY;
6396 uint ea = EA_AX_AI_32();
6397
6398 m68ki_write_32(ea, res);
6399
6400 FLAG_N = NFLAG_32(res);
6401 FLAG_Z = res;
6402 FLAG_V = VFLAG_CLEAR;
6403 FLAG_C = CFLAG_CLEAR;
6404 }
6405
6406
6407 M68KMAKE_OP(move, 32, ai, .)
6408 {
6409 uint res = M68KMAKE_GET_OPER_AY_32;
6410 uint ea = EA_AX_AI_32();
6411
6412 m68ki_write_32(ea, res);
6413
6414 FLAG_N = NFLAG_32(res);
6415 FLAG_Z = res;
6416 FLAG_V = VFLAG_CLEAR;
6417 FLAG_C = CFLAG_CLEAR;
6418 }
6419
6420
6421 M68KMAKE_OP(move, 32, pi, d)
6422 {
6423 uint res = DY;
6424 uint ea = EA_AX_PI_32();
6425
6426 m68ki_write_32(ea, res);
6427
6428 FLAG_N = NFLAG_32(res);
6429 FLAG_Z = res;
6430 FLAG_V = VFLAG_CLEAR;
6431 FLAG_C = CFLAG_CLEAR;
6432 }
6433
6434
6435 M68KMAKE_OP(move, 32, pi, a)
6436 {
6437 uint res = AY;
6438 uint ea = EA_AX_PI_32();
6439
6440 m68ki_write_32(ea, res);
6441
6442 FLAG_N = NFLAG_32(res);
6443 FLAG_Z = res;
6444 FLAG_V = VFLAG_CLEAR;
6445 FLAG_C = CFLAG_CLEAR;
6446 }
6447
6448
6449 M68KMAKE_OP(move, 32, pi, .)
6450 {
6451 uint res = M68KMAKE_GET_OPER_AY_32;
6452 uint ea = EA_AX_PI_32();
6453
6454 m68ki_write_32(ea, res);
6455
6456 FLAG_N = NFLAG_32(res);
6457 FLAG_Z = res;
6458 FLAG_V = VFLAG_CLEAR;
6459 FLAG_C = CFLAG_CLEAR;
6460 }
6461
6462
6463 M68KMAKE_OP(move, 32, pd, d)
6464 {
6465 uint res = DY;
6466 uint ea = EA_AX_PD_32();
6467
6468 m68ki_write_16(ea+2, res & 0xFFFF );
6469 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6470
6471 FLAG_N = NFLAG_32(res);
6472 FLAG_Z = res;
6473 FLAG_V = VFLAG_CLEAR;
6474 FLAG_C = CFLAG_CLEAR;
6475 }
6476
6477
6478 M68KMAKE_OP(move, 32, pd, a)
6479 {
6480 uint res = AY;
6481 uint ea = EA_AX_PD_32();
6482
6483 m68ki_write_16(ea+2, res & 0xFFFF );
6484 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6485
6486 FLAG_N = NFLAG_32(res);
6487 FLAG_Z = res;
6488 FLAG_V = VFLAG_CLEAR;
6489 FLAG_C = CFLAG_CLEAR;
6490 }
6491
6492
6493 M68KMAKE_OP(move, 32, pd, .)
6494 {
6495 uint res = M68KMAKE_GET_OPER_AY_32;
6496 uint ea = EA_AX_PD_32();
6497
6498 m68ki_write_16(ea+2, res & 0xFFFF );
6499 m68ki_write_16(ea, (res >> 16) & 0xFFFF );
6500
6501 FLAG_N = NFLAG_32(res);
6502 FLAG_Z = res;
6503 FLAG_V = VFLAG_CLEAR;
6504 FLAG_C = CFLAG_CLEAR;
6505 }
6506
6507
6508 M68KMAKE_OP(move, 32, di, d)
6509 {
6510 uint res = DY;
6511 uint ea = EA_AX_DI_32();
6512
6513 m68ki_write_32(ea, res);
6514
6515 FLAG_N = NFLAG_32(res);
6516 FLAG_Z = res;
6517 FLAG_V = VFLAG_CLEAR;
6518 FLAG_C = CFLAG_CLEAR;
6519 }
6520
6521
6522 M68KMAKE_OP(move, 32, di, a)
6523 {
6524 uint res = AY;
6525 uint ea = EA_AX_DI_32();
6526
6527 m68ki_write_32(ea, res);
6528
6529 FLAG_N = NFLAG_32(res);
6530 FLAG_Z = res;
6531 FLAG_V = VFLAG_CLEAR;
6532 FLAG_C = CFLAG_CLEAR;
6533 }
6534
6535
6536 M68KMAKE_OP(move, 32, di, .)
6537 {
6538 uint res = M68KMAKE_GET_OPER_AY_32;
6539 uint ea = EA_AX_DI_32();
6540
6541 m68ki_write_32(ea, res);
6542
6543 FLAG_N = NFLAG_32(res);
6544 FLAG_Z = res;
6545 FLAG_V = VFLAG_CLEAR;
6546 FLAG_C = CFLAG_CLEAR;
6547 }
6548
6549
6550 M68KMAKE_OP(move, 32, ix, d)
6551 {
6552 uint res = DY;
6553 uint ea = EA_AX_IX_32();
6554
6555 m68ki_write_32(ea, res);
6556
6557 FLAG_N = NFLAG_32(res);
6558 FLAG_Z = res;
6559 FLAG_V = VFLAG_CLEAR;
6560 FLAG_C = CFLAG_CLEAR;
6561 }
6562
6563
6564 M68KMAKE_OP(move, 32, ix, a)
6565 {
6566 uint res = AY;
6567 uint ea = EA_AX_IX_32();
6568
6569 m68ki_write_32(ea, res);
6570
6571 FLAG_N = NFLAG_32(res);
6572 FLAG_Z = res;
6573 FLAG_V = VFLAG_CLEAR;
6574 FLAG_C = CFLAG_CLEAR;
6575 }
6576
6577
6578 M68KMAKE_OP(move, 32, ix, .)
6579 {
6580 uint res = M68KMAKE_GET_OPER_AY_32;
6581 uint ea = EA_AX_IX_32();
6582
6583 m68ki_write_32(ea, res);
6584
6585 FLAG_N = NFLAG_32(res);
6586 FLAG_Z = res;
6587 FLAG_V = VFLAG_CLEAR;
6588 FLAG_C = CFLAG_CLEAR;
6589 }
6590
6591
6592 M68KMAKE_OP(move, 32, aw, d)
6593 {
6594 uint res = DY;
6595 uint ea = EA_AW_32();
6596
6597 m68ki_write_32(ea, res);
6598
6599 FLAG_N = NFLAG_32(res);
6600 FLAG_Z = res;
6601 FLAG_V = VFLAG_CLEAR;
6602 FLAG_C = CFLAG_CLEAR;
6603 }
6604
6605
6606 M68KMAKE_OP(move, 32, aw, a)
6607 {
6608 uint res = AY;
6609 uint ea = EA_AW_32();
6610
6611 m68ki_write_32(ea, res);
6612
6613 FLAG_N = NFLAG_32(res);
6614 FLAG_Z = res;
6615 FLAG_V = VFLAG_CLEAR;
6616 FLAG_C = CFLAG_CLEAR;
6617 }
6618
6619
6620 M68KMAKE_OP(move, 32, aw, .)
6621 {
6622 uint res = M68KMAKE_GET_OPER_AY_32;
6623 uint ea = EA_AW_32();
6624
6625 m68ki_write_32(ea, res);
6626
6627 FLAG_N = NFLAG_32(res);
6628 FLAG_Z = res;
6629 FLAG_V = VFLAG_CLEAR;
6630 FLAG_C = CFLAG_CLEAR;
6631 }
6632
6633
6634 M68KMAKE_OP(move, 32, al, d)
6635 {
6636 uint res = DY;
6637 uint ea = EA_AL_32();
6638
6639 m68ki_write_32(ea, res);
6640
6641 FLAG_N = NFLAG_32(res);
6642 FLAG_Z = res;
6643 FLAG_V = VFLAG_CLEAR;
6644 FLAG_C = CFLAG_CLEAR;
6645 }
6646
6647
6648 M68KMAKE_OP(move, 32, al, a)
6649 {
6650 uint res = AY;
6651 uint ea = EA_AL_32();
6652
6653 m68ki_write_32(ea, res);
6654
6655 FLAG_N = NFLAG_32(res);
6656 FLAG_Z = res;
6657 FLAG_V = VFLAG_CLEAR;
6658 FLAG_C = CFLAG_CLEAR;
6659 }
6660
6661
6662 M68KMAKE_OP(move, 32, al, .)
6663 {
6664 uint res = M68KMAKE_GET_OPER_AY_32;
6665 uint ea = EA_AL_32();
6666
6667 m68ki_write_32(ea, res);
6668
6669 FLAG_N = NFLAG_32(res);
6670 FLAG_Z = res;
6671 FLAG_V = VFLAG_CLEAR;
6672 FLAG_C = CFLAG_CLEAR;
6673 }
6674
6675
6676 M68KMAKE_OP(movea, 16, ., d)
6677 {
6678 AX = MAKE_INT_16(DY);
6679 }
6680
6681
6682 M68KMAKE_OP(movea, 16, ., a)
6683 {
6684 AX = MAKE_INT_16(AY);
6685 }
6686
6687
6688 M68KMAKE_OP(movea, 16, ., .)
6689 {
6690 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
6691 }
6692
6693
6694 M68KMAKE_OP(movea, 32, ., d)
6695 {
6696 AX = DY;
6697 }
6698
6699
6700 M68KMAKE_OP(movea, 32, ., a)
6701 {
6702 AX = AY;
6703 }
6704
6705
6706 M68KMAKE_OP(movea, 32, ., .)
6707 {
6708 AX = M68KMAKE_GET_OPER_AY_32;
6709 }
6710
6711
6712 M68KMAKE_OP(move, 16, frc, d)
6713 {
6714 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6715 {
6716 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
6717 return;
6718 }
6719 m68ki_exception_illegal();
6720 }
6721
6722
6723 M68KMAKE_OP(move, 16, frc, .)
6724 {
6725 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6726 {
6727 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
6728 return;
6729 }
6730 m68ki_exception_illegal();
6731 }
6732
6733
6734 M68KMAKE_OP(move, 16, toc, d)
6735 {
6736 m68ki_set_ccr(DY);
6737 }
6738
6739
6740 M68KMAKE_OP(move, 16, toc, .)
6741 {
6742 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
6743 }
6744
6745
6746 M68KMAKE_OP(move, 16, frs, d)
6747 {
6748 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6749 {
6750 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
6751 return;
6752 }
6753 m68ki_exception_privilege_violation();
6754 }
6755
6756
6757 M68KMAKE_OP(move, 16, frs, .)
6758 {
6759 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6760 {
6761 uint ea = M68KMAKE_GET_EA_AY_16;
6762 m68ki_write_16(ea, m68ki_get_sr());
6763 return;
6764 }
6765 m68ki_exception_privilege_violation();
6766 }
6767
6768
6769 M68KMAKE_OP(move, 16, tos, d)
6770 {
6771 if(FLAG_S)
6772 {
6773 m68ki_set_sr(DY);
6774 return;
6775 }
6776 m68ki_exception_privilege_violation();
6777 }
6778
6779
6780 M68KMAKE_OP(move, 16, tos, .)
6781 {
6782 if(FLAG_S)
6783 {
6784 uint new_sr = M68KMAKE_GET_OPER_AY_16;
6785 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6786 m68ki_set_sr(new_sr);
6787 return;
6788 }
6789 m68ki_exception_privilege_violation();
6790 }
6791
6792
6793 M68KMAKE_OP(move, 32, fru, .)
6794 {
6795 if(FLAG_S)
6796 {
6797 AY = REG_USP;
6798 return;
6799 }
6800 m68ki_exception_privilege_violation();
6801 }
6802
6803
6804 M68KMAKE_OP(move, 32, tou, .)
6805 {
6806 if(FLAG_S)
6807 {
6808 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6809 REG_USP = AY;
6810 return;
6811 }
6812 m68ki_exception_privilege_violation();
6813 }
6814
6815
6816 M68KMAKE_OP(movec, 32, cr, .)
6817 {
6818 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6819 {
6820 if(FLAG_S)
6821 {
6822 uint word2 = OPER_I_16();
6823
6824 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6825 switch (word2 & 0xfff)
6826 {
6827 case 0x000: /* SFC */
6828 REG_DA[(word2 >> 12) & 15] = REG_SFC;
6829 return;
6830 case 0x001: /* DFC */
6831 REG_DA[(word2 >> 12) & 15] = REG_DFC;
6832 return;
6833 case 0x002: /* CACR */
6834 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6835 {
6836 REG_DA[(word2 >> 12) & 15] = REG_CACR;
6837 return;
6838 }
6839 return;
6840 case 0x800: /* USP */
6841 REG_DA[(word2 >> 12) & 15] = REG_USP;
6842 return;
6843 case 0x801: /* VBR */
6844 REG_DA[(word2 >> 12) & 15] = REG_VBR;
6845 return;
6846 case 0x802: /* CAAR */
6847 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6848 {
6849 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
6850 return;
6851 }
6852 m68ki_exception_illegal();
6853 break;
6854 case 0x803: /* MSP */
6855 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6856 {
6857 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
6858 return;
6859 }
6860 m68ki_exception_illegal();
6861 return;
6862 case 0x804: /* ISP */
6863 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6864 {
6865 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
6866 return;
6867 }
6868 m68ki_exception_illegal();
6869 return;
6870 case 0x003: /* TC */
6871 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6872 {
6873 /* TODO */
6874 return;
6875 }
6876 m68ki_exception_illegal();
6877 return;
6878 case 0x004: /* ITT0 */
6879 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6880 {
6881 /* TODO */
6882 return;
6883 }
6884 m68ki_exception_illegal();
6885 return;
6886 case 0x005: /* ITT1 */
6887 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6888 {
6889 /* TODO */
6890 return;
6891 }
6892 m68ki_exception_illegal();
6893 return;
6894 case 0x006: /* DTT0 */
6895 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6896 {
6897 /* TODO */
6898 return;
6899 }
6900 m68ki_exception_illegal();
6901 return;
6902 case 0x007: /* DTT1 */
6903 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6904 {
6905 /* TODO */
6906 return;
6907 }
6908 m68ki_exception_illegal();
6909 return;
6910 case 0x805: /* MMUSR */
6911 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6912 {
6913 /* TODO */
6914 return;
6915 }
6916 m68ki_exception_illegal();
6917 return;
6918 case 0x806: /* URP */
6919 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6920 {
6921 /* TODO */
6922 return;
6923 }
6924 m68ki_exception_illegal();
6925 return;
6926 case 0x807: /* SRP */
6927 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6928 {
6929 /* TODO */
6930 return;
6931 }
6932 m68ki_exception_illegal();
6933 return;
6934 default:
6935 m68ki_exception_illegal();
6936 return;
6937 }
6938 }
6939 m68ki_exception_privilege_violation();
6940 return;
6941 }
6942 m68ki_exception_illegal();
6943 }
6944
6945
6946 M68KMAKE_OP(movec, 32, rc, .)
6947 {
6948 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6949 {
6950 if(FLAG_S)
6951 {
6952 uint word2 = OPER_I_16();
6953
6954 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6955 switch (word2 & 0xfff)
6956 {
6957 case 0x000: /* SFC */
6958 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
6959 return;
6960 case 0x001: /* DFC */
6961 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
6962 return;
6963 case 0x002: /* CACR */
6964 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6965 {
6966 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
6967 {
6968 REG_CACR = REG_DA[(word2 >> 12) & 15];
6969 }
6970 else
6971 {
6972 /* non 68040 can only set the lower 4 bits (C,CE,F,E) */
6973 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;
6974 }
6975 return;
6976 }
6977 m68ki_exception_illegal();
6978 return;
6979 case 0x800: /* USP */
6980 REG_USP = REG_DA[(word2 >> 12) & 15];
6981 return;
6982 case 0x801: /* VBR */
6983 REG_VBR = REG_DA[(word2 >> 12) & 15];
6984 return;
6985 case 0x802: /* CAAR */
6986 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6987 {
6988 REG_CAAR = REG_DA[(word2 >> 12) & 15];
6989 return;
6990 }
6991 m68ki_exception_illegal();
6992 return;
6993 case 0x803: /* MSP */
6994 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6995 {
6996 /* we are in supervisor mode so just check for M flag */
6997 if(!FLAG_M)
6998 {
6999 REG_MSP = REG_DA[(word2 >> 12) & 15];
7000 return;
7001 }
7002 REG_SP = REG_DA[(word2 >> 12) & 15];
7003 return;
7004 }
7005 m68ki_exception_illegal();
7006 return;
7007 case 0x804: /* ISP */
7008 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7009 {
7010 if(!FLAG_M)
7011 {
7012 REG_SP = REG_DA[(word2 >> 12) & 15];
7013 return;
7014 }
7015 REG_ISP = REG_DA[(word2 >> 12) & 15];
7016 return;
7017 }
7018 m68ki_exception_illegal();
7019 return;
7020 case 0x003: /* TC */
7021 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7022 {
7023 /* TODO */
7024 return;
7025 }
7026 m68ki_exception_illegal();
7027 return;
7028 case 0x004: /* ITT0 */
7029 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7030 {
7031 /* TODO */
7032 return;
7033 }
7034 m68ki_exception_illegal();
7035 return;
7036 case 0x005: /* ITT1 */
7037 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7038 {
7039 /* TODO */
7040 return;
7041 }
7042 m68ki_exception_illegal();
7043 return;
7044 case 0x006: /* DTT0 */
7045 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7046 {
7047 /* TODO */
7048 return;
7049 }
7050 m68ki_exception_illegal();
7051 return;
7052 case 0x007: /* DTT1 */
7053 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7054 {
7055 /* TODO */
7056 return;
7057 }
7058 m68ki_exception_illegal();
7059 return;
7060 case 0x805: /* MMUSR */
7061 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7062 {
7063 /* TODO */
7064 return;
7065 }
7066 m68ki_exception_illegal();
7067 return;
7068 case 0x806: /* URP */
7069 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7070 {
7071 /* TODO */
7072 return;
7073 }
7074 m68ki_exception_illegal();
7075 return;
7076 case 0x807: /* SRP */
7077 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))
7078 {
7079 /* TODO */
7080 return;
7081 }
7082 m68ki_exception_illegal();
7083 return;
7084 default:
7085 m68ki_exception_illegal();
7086 return;
7087 }
7088 }
7089 m68ki_exception_privilege_violation();
7090 return;
7091 }
7092 m68ki_exception_illegal();
7093 }
7094
7095
7096 M68KMAKE_OP(movem, 16, re, pd)
7097 {
7098 uint i = 0;
7099 uint register_list = OPER_I_16();
7100 uint ea = AY;
7101 uint count = 0;
7102
7103 for(; i < 16; i++)
7104 if(register_list & (1 << i))
7105 {
7106 ea -= 2;
7107 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
7108 count++;
7109 }
7110 AY = ea;
7111
7112 USE_CYCLES(count<<CYC_MOVEM_W);
7113 }
7114
7115
7116 M68KMAKE_OP(movem, 16, re, .)
7117 {
7118 uint i = 0;
7119 uint register_list = OPER_I_16();
7120 uint ea = M68KMAKE_GET_EA_AY_16;
7121 uint count = 0;
7122
7123 for(; i < 16; i++)
7124 if(register_list & (1 << i))
7125 {
7126 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
7127 ea += 2;
7128 count++;
7129 }
7130
7131 USE_CYCLES(count<<CYC_MOVEM_W);
7132 }
7133
7134
7135 M68KMAKE_OP(movem, 32, re, pd)
7136 {
7137 uint i = 0;
7138 uint register_list = OPER_I_16();
7139 uint ea = AY;
7140 uint count = 0;
7141
7142 for(; i < 16; i++)
7143 if(register_list & (1 << i))
7144 {
7145 ea -= 4;
7146 #if 0
7147 m68ki_write_32(ea, REG_DA[15-i] ); // notaz Cyclone hack
7148 #else
7149 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );
7150 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );
7151 #endif
7152 count++;
7153 }
7154 AY = ea;
7155
7156 USE_CYCLES(count<<CYC_MOVEM_L);
7157 }
7158
7159
7160 M68KMAKE_OP(movem, 32, re, .)
7161 {
7162 uint i = 0;
7163 uint register_list = OPER_I_16();
7164 uint ea = M68KMAKE_GET_EA_AY_32;
7165 uint count = 0;
7166
7167 for(; i < 16; i++)
7168 if(register_list & (1 << i))
7169 {
7170 m68ki_write_32(ea, REG_DA[i]);
7171 ea += 4;
7172 count++;
7173 }
7174
7175 USE_CYCLES(count<<CYC_MOVEM_L);
7176 }
7177
7178
7179 M68KMAKE_OP(movem, 16, er, pi)
7180 {
7181 uint i = 0;
7182 uint register_list = OPER_I_16();
7183 uint ea = AY;
7184 uint count = 0;
7185
7186 for(; i < 16; i++)
7187 if(register_list & (1 << i))
7188 {
7189 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7190 ea += 2;
7191 count++;
7192 }
7193 AY = ea;
7194
7195 USE_CYCLES(count<<CYC_MOVEM_W);
7196 }
7197
7198
7199 M68KMAKE_OP(movem, 16, er, pcdi)
7200 {
7201 uint i = 0;
7202 uint register_list = OPER_I_16();
7203 uint ea = EA_PCDI_16();
7204 uint count = 0;
7205
7206 for(; i < 16; i++)
7207 if(register_list & (1 << i))
7208 {
7209 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7210 ea += 2;
7211 count++;
7212 }
7213
7214 USE_CYCLES(count<<CYC_MOVEM_W);
7215 }
7216
7217
7218 M68KMAKE_OP(movem, 16, er, pcix)
7219 {
7220 uint i = 0;
7221 uint register_list = OPER_I_16();
7222 uint ea = EA_PCIX_16();
7223 uint count = 0;
7224
7225 for(; i < 16; i++)
7226 if(register_list & (1 << i))
7227 {
7228 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));
7229 ea += 2;
7230 count++;
7231 }
7232
7233 USE_CYCLES(count<<CYC_MOVEM_W);
7234 }
7235
7236
7237 M68KMAKE_OP(movem, 16, er, .)
7238 {
7239 uint i = 0;
7240 uint register_list = OPER_I_16();
7241 uint ea = M68KMAKE_GET_EA_AY_16;
7242 uint count = 0;
7243
7244 for(; i < 16; i++)
7245 if(register_list & (1 << i))
7246 {
7247 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
7248 ea += 2;
7249 count++;
7250 }
7251
7252 USE_CYCLES(count<<CYC_MOVEM_W);
7253 }
7254
7255
7256 M68KMAKE_OP(movem, 32, er, pi)
7257 {
7258 uint i = 0;
7259 uint register_list = OPER_I_16();
7260 uint ea = AY;
7261 uint count = 0;
7262
7263 for(; i < 16; i++)
7264 if(register_list & (1 << i))
7265 {
7266 REG_DA[i] = m68ki_read_32(ea);
7267 ea += 4;
7268 count++;
7269 }
7270 AY = ea;
7271
7272 USE_CYCLES(count<<CYC_MOVEM_L);
7273 }
7274
7275
7276 M68KMAKE_OP(movem, 32, er, pcdi)
7277 {
7278 uint i = 0;
7279 uint register_list = OPER_I_16();
7280 uint ea = EA_PCDI_32();
7281 uint count = 0;
7282
7283 for(; i < 16; i++)
7284 if(register_list & (1 << i))
7285 {
7286 REG_DA[i] = m68ki_read_pcrel_32(ea);
7287 ea += 4;
7288 count++;
7289 }
7290
7291 USE_CYCLES(count<<CYC_MOVEM_L);
7292 }
7293
7294
7295 M68KMAKE_OP(movem, 32, er, pcix)
7296 {
7297 uint i = 0;
7298 uint register_list = OPER_I_16();
7299 uint ea = EA_PCIX_32();
7300 uint count = 0;
7301
7302 for(; i < 16; i++)
7303 if(register_list & (1 << i))
7304 {
7305 REG_DA[i] = m68ki_read_pcrel_32(ea);
7306 ea += 4;
7307 count++;
7308 }
7309
7310 USE_CYCLES(count<<CYC_MOVEM_L);
7311 }
7312
7313
7314 M68KMAKE_OP(movem, 32, er, .)
7315 {
7316 uint i = 0;
7317 uint register_list = OPER_I_16();
7318 uint ea = M68KMAKE_GET_EA_AY_32;
7319 uint count = 0;
7320
7321 for(; i < 16; i++)
7322 if(register_list & (1 << i))
7323 {
7324 REG_DA[i] = m68ki_read_32(ea);
7325 ea += 4;
7326 count++;
7327 }
7328
7329 USE_CYCLES(count<<CYC_MOVEM_L);
7330 }
7331
7332
7333 M68KMAKE_OP(movep, 16, re, .)
7334 {
7335 uint ea = EA_AY_DI_16();
7336 uint src = DX;
7337
7338 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
7339 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7340 }
7341
7342
7343 M68KMAKE_OP(movep, 32, re, .)
7344 {
7345 uint ea = EA_AY_DI_32();
7346 uint src = DX;
7347
7348 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
7349 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
7350 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
7351 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
7352 }
7353
7354
7355 M68KMAKE_OP(movep, 16, er, .)
7356 {
7357 uint ea = EA_AY_DI_16();
7358 uint* r_dst = &DX;
7359
7360 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
7361 }
7362
7363
7364 M68KMAKE_OP(movep, 32, er, .)
7365 {
7366 uint ea = EA_AY_DI_32();
7367
7368 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
7369 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
7370 }
7371
7372
7373 M68KMAKE_OP(moves, 8, ., .)
7374 {
7375 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7376 {
7377 if(FLAG_S)
7378 {
7379 uint word2 = OPER_I_16();
7380 uint ea = M68KMAKE_GET_EA_AY_8;
7381
7382 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7383 if(BIT_B(word2)) /* Register to memory */
7384 {
7385 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
7386 return;
7387 }
7388 if(BIT_F(word2)) /* Memory to address register */
7389 {
7390 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
7391 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7392 USE_CYCLES(2);
7393 return;
7394 }
7395 /* Memory to data register */
7396 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
7397 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7398 USE_CYCLES(2);
7399 return;
7400 }
7401 m68ki_exception_privilege_violation();
7402 return;
7403 }
7404 m68ki_exception_illegal();
7405 }
7406
7407
7408 M68KMAKE_OP(moves, 16, ., .)
7409 {
7410 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7411 {
7412 if(FLAG_S)
7413 {
7414 uint word2 = OPER_I_16();
7415 uint ea = M68KMAKE_GET_EA_AY_16;
7416
7417 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7418 if(BIT_B(word2)) /* Register to memory */
7419 {
7420 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
7421 return;
7422 }
7423 if(BIT_F(word2)) /* Memory to address register */
7424 {
7425 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
7426 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7427 USE_CYCLES(2);
7428 return;
7429 }
7430 /* Memory to data register */
7431 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
7432 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7433 USE_CYCLES(2);
7434 return;
7435 }
7436 m68ki_exception_privilege_violation();
7437 return;
7438 }
7439 m68ki_exception_illegal();
7440 }
7441
7442
7443 M68KMAKE_OP(moves, 32, ., .)
7444 {
7445 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
7446 {
7447 if(FLAG_S)
7448 {
7449 uint word2 = OPER_I_16();
7450 uint ea = M68KMAKE_GET_EA_AY_32;
7451
7452 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7453 if(BIT_B(word2)) /* Register to memory */
7454 {
7455 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
7456 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7457 USE_CYCLES(2);
7458 return;
7459 }
7460 /* Memory to register */
7461 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
7462 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
7463 USE_CYCLES(2);
7464 return;
7465 }
7466 m68ki_exception_privilege_violation();
7467 return;
7468 }
7469 m68ki_exception_illegal();
7470 }
7471
7472
7473 M68KMAKE_OP(moveq, 32, ., .)
7474 {
7475 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
7476
7477 FLAG_N = NFLAG_32(res);
7478 FLAG_Z = res;
7479 FLAG_V = VFLAG_CLEAR;
7480 FLAG_C = CFLAG_CLEAR;
7481 }
7482
7483
7484 M68KMAKE_OP(move16, 32, ., .)
7485 {
7486 UINT16 w2 = OPER_I_16();
7487 int ax = REG_IR & 7;
7488 int ay = (w2 >> 12) & 7;
7489
7490 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));
7491 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));
7492 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));
7493 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));
7494
7495 REG_A[ax] += 16;
7496 REG_A[ay] += 16;
7497 }
7498
7499
7500 M68KMAKE_OP(muls, 16, ., d)
7501 {
7502 uint* r_dst = &DX;
7503 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7504
7505 *r_dst = res;
7506
7507 FLAG_Z = res;
7508 FLAG_N = NFLAG_32(res);
7509 FLAG_V = VFLAG_CLEAR;
7510 FLAG_C = CFLAG_CLEAR;
7511 }
7512
7513
7514 M68KMAKE_OP(muls, 16, ., .)
7515 {
7516 uint* r_dst = &DX;
7517 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
7518
7519 *r_dst = res;
7520
7521 FLAG_Z = res;
7522 FLAG_N = NFLAG_32(res);
7523 FLAG_V = VFLAG_CLEAR;
7524 FLAG_C = CFLAG_CLEAR;
7525 }
7526
7527
7528 M68KMAKE_OP(mulu, 16, ., d)
7529 {
7530 uint* r_dst = &DX;
7531 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
7532
7533 *r_dst = res;
7534
7535 FLAG_Z = res;
7536 FLAG_N = NFLAG_32(res);
7537 FLAG_V = VFLAG_CLEAR;
7538 FLAG_C = CFLAG_CLEAR;
7539 }
7540
7541
7542 M68KMAKE_OP(mulu, 16, ., .)
7543 {
7544 uint* r_dst = &DX;
7545 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
7546
7547 *r_dst = res;
7548
7549 FLAG_Z = res;
7550 FLAG_N = NFLAG_32(res);
7551 FLAG_V = VFLAG_CLEAR;
7552 FLAG_C = CFLAG_CLEAR;
7553 }
7554
7555
7556 M68KMAKE_OP(mull, 32, ., d)
7557 {
7558 #if M68K_USE_64_BIT
7559
7560 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7561 {
7562 uint word2 = OPER_I_16();
7563 uint64 src = DY;
7564 uint64 dst = REG_D[(word2 >> 12) & 7];
7565 uint64 res;
7566
7567 FLAG_C = CFLAG_CLEAR;
7568
7569 if(BIT_B(word2)) /* signed */
7570 {
7571 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7572 if(!BIT_A(word2))
7573 {
7574 FLAG_Z = MASK_OUT_ABOVE_32(res);
7575 FLAG_N = NFLAG_32(res);
7576 FLAG_V = ((sint64)res != (sint32)res)<<7;
7577 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7578 return;
7579 }
7580 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7581 FLAG_N = NFLAG_64(res);
7582 FLAG_V = VFLAG_CLEAR;
7583 REG_D[word2 & 7] = (res >> 32);
7584 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7585 return;
7586 }
7587
7588 res = src * dst;
7589 if(!BIT_A(word2))
7590 {
7591 FLAG_Z = MASK_OUT_ABOVE_32(res);
7592 FLAG_N = NFLAG_32(res);
7593 FLAG_V = (res > 0xffffffff)<<7;
7594 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7595 return;
7596 }
7597 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7598 FLAG_N = NFLAG_64(res);
7599 FLAG_V = VFLAG_CLEAR;
7600 REG_D[word2 & 7] = (res >> 32);
7601 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7602 return;
7603 }
7604 m68ki_exception_illegal();
7605
7606 #else
7607
7608 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7609 {
7610 uint word2 = OPER_I_16();
7611 uint src = DY;
7612 uint dst = REG_D[(word2 >> 12) & 7];
7613 uint neg = GET_MSB_32(src ^ dst);
7614 uint src1;
7615 uint src2;
7616 uint dst1;
7617 uint dst2;
7618 uint r1;
7619 uint r2;
7620 uint r3;
7621 uint r4;
7622 uint lo;
7623 uint hi;
7624
7625 FLAG_C = CFLAG_CLEAR;
7626
7627 if(BIT_B(word2)) /* signed */
7628 {
7629 if(GET_MSB_32(src))
7630 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7631 if(GET_MSB_32(dst))
7632 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7633 }
7634
7635 src1 = MASK_OUT_ABOVE_16(src);
7636 src2 = src>>16;
7637 dst1 = MASK_OUT_ABOVE_16(dst);
7638 dst2 = dst>>16;
7639
7640
7641 r1 = src1 * dst1;
7642 r2 = src1 * dst2;
7643 r3 = src2 * dst1;
7644 r4 = src2 * dst2;
7645
7646 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7647 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7648
7649 if(BIT_B(word2) && neg)
7650 {
7651 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7652 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7653 }
7654
7655 if(BIT_A(word2))
7656 {
7657 REG_D[word2 & 7] = hi;
7658 REG_D[(word2 >> 12) & 7] = lo;
7659 FLAG_N = NFLAG_32(hi);
7660 FLAG_Z = hi | lo;
7661 FLAG_V = VFLAG_CLEAR;
7662 return;
7663 }
7664
7665 REG_D[(word2 >> 12) & 7] = lo;
7666 FLAG_N = NFLAG_32(lo);
7667 FLAG_Z = lo;
7668 if(BIT_B(word2))
7669 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7670 else
7671 FLAG_V = (hi != 0) << 7;
7672 return;
7673 }
7674 m68ki_exception_illegal();
7675
7676 #endif
7677 }
7678
7679
7680 M68KMAKE_OP(mull, 32, ., .)
7681 {
7682 #if M68K_USE_64_BIT
7683
7684 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7685 {
7686 uint word2 = OPER_I_16();
7687 uint64 src = M68KMAKE_GET_OPER_AY_32;
7688 uint64 dst = REG_D[(word2 >> 12) & 7];
7689 uint64 res;
7690
7691 FLAG_C = CFLAG_CLEAR;
7692
7693 if(BIT_B(word2)) /* signed */
7694 {
7695 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7696 if(!BIT_A(word2))
7697 {
7698 FLAG_Z = MASK_OUT_ABOVE_32(res);
7699 FLAG_N = NFLAG_32(res);
7700 FLAG_V = ((sint64)res != (sint32)res)<<7;
7701 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7702 return;
7703 }
7704 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7705 FLAG_N = NFLAG_64(res);
7706 FLAG_V = VFLAG_CLEAR;
7707 REG_D[word2 & 7] = (res >> 32);
7708 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7709 return;
7710 }
7711
7712 res = src * dst;
7713 if(!BIT_A(word2))
7714 {
7715 FLAG_Z = MASK_OUT_ABOVE_32(res);
7716 FLAG_N = NFLAG_32(res);
7717 FLAG_V = (res > 0xffffffff)<<7;
7718 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7719 return;
7720 }
7721 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7722 FLAG_N = NFLAG_64(res);
7723 FLAG_V = VFLAG_CLEAR;
7724 REG_D[word2 & 7] = (res >> 32);
7725 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7726 return;
7727 }
7728 m68ki_exception_illegal();
7729
7730 #else
7731
7732 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7733 {
7734 uint word2 = OPER_I_16();
7735 uint src = M68KMAKE_GET_OPER_AY_32;
7736 uint dst = REG_D[(word2 >> 12) & 7];
7737 uint neg = GET_MSB_32(src ^ dst);
7738 uint src1;
7739 uint src2;
7740 uint dst1;
7741 uint dst2;
7742 uint r1;
7743 uint r2;
7744 uint r3;
7745 uint r4;
7746 uint lo;
7747 uint hi;
7748
7749 FLAG_C = CFLAG_CLEAR;
7750
7751 if(BIT_B(word2)) /* signed */
7752 {
7753 if(GET_MSB_32(src))
7754 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7755 if(GET_MSB_32(dst))
7756 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7757 }
7758
7759 src1 = MASK_OUT_ABOVE_16(src);
7760 src2 = src>>16;
7761 dst1 = MASK_OUT_ABOVE_16(dst);
7762 dst2 = dst>>16;
7763
7764
7765 r1 = src1 * dst1;
7766 r2 = src1 * dst2;
7767 r3 = src2 * dst1;
7768 r4 = src2 * dst2;
7769
7770 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7771 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7772
7773 if(BIT_B(word2) && neg)
7774 {
7775 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7776 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7777 }
7778
7779 if(BIT_A(word2))
7780 {
7781 REG_D[word2 & 7] = hi;
7782 REG_D[(word2 >> 12) & 7] = lo;
7783 FLAG_N = NFLAG_32(hi);
7784 FLAG_Z = hi | lo;
7785 FLAG_V = VFLAG_CLEAR;
7786 return;
7787 }
7788
7789 REG_D[(word2 >> 12) & 7] = lo;
7790 FLAG_N = NFLAG_32(lo);
7791 FLAG_Z = lo;
7792 if(BIT_B(word2))
7793 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7794 else
7795 FLAG_V = (hi != 0) << 7;
7796 return;
7797 }
7798 m68ki_exception_illegal();
7799
7800 #endif
7801 }
7802
7803
7804 M68KMAKE_OP(nbcd, 8, ., d)
7805 {
7806 uint* r_dst = &DY;
7807 uint dst = MASK_OUT_ABOVE_8(*r_dst);
7808 uint res = -dst - XFLAG_AS_1();
7809
7810 if(res != 0)
7811 {
7812 FLAG_V = res; /* Undefined V behavior */
7813
7814 if(((res|dst) & 0x0f) == 0)
7815 res = (res & 0xf0) + 6;
7816
7817 res = MASK_OUT_ABOVE_8(res + 0x9a);
7818
7819 FLAG_V &= ~res; /* Undefined V behavior part II */
7820
7821 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7822
7823 FLAG_Z |= res;
7824 FLAG_C = CFLAG_SET;
7825 FLAG_X = XFLAG_SET;
7826 }
7827 else
7828 {
7829 FLAG_V = VFLAG_CLEAR;
7830 FLAG_C = CFLAG_CLEAR;
7831 FLAG_X = XFLAG_CLEAR;
7832 }
7833 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7834 }
7835
7836
7837 M68KMAKE_OP(nbcd, 8, ., .)
7838 {
7839 uint ea = M68KMAKE_GET_EA_AY_8;
7840 uint dst = m68ki_read_8(ea);
7841 uint res = -dst - XFLAG_AS_1();
7842
7843 if(res != 0)
7844 {
7845 FLAG_V = res; /* Undefined V behavior */
7846
7847 if(((res|dst) & 0x0f) == 0)
7848 res = (res & 0xf0) + 6;
7849
7850 res = MASK_OUT_ABOVE_8(res + 0x9a);
7851
7852 FLAG_V &= ~res; /* Undefined V behavior part II */
7853
7854 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
7855
7856 FLAG_Z |= res;
7857 FLAG_C = CFLAG_SET;
7858 FLAG_X = XFLAG_SET;
7859 }
7860 else
7861 {
7862 FLAG_V = VFLAG_CLEAR;
7863 FLAG_C = CFLAG_CLEAR;
7864 FLAG_X = XFLAG_CLEAR;
7865 }
7866 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
7867 }
7868
7869
7870 M68KMAKE_OP(neg, 8, ., d)
7871 {
7872 uint* r_dst = &DY;
7873 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
7874
7875 FLAG_N = NFLAG_8(res);
7876 FLAG_C = FLAG_X = CFLAG_8(res);
7877 FLAG_V = *r_dst & res;
7878 FLAG_Z = MASK_OUT_ABOVE_8(res);
7879
7880 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
7881 }
7882
7883
7884 M68KMAKE_OP(neg, 8, ., .)
7885 {
7886 uint ea = M68KMAKE_GET_EA_AY_8;
7887 uint src = m68ki_read_8(ea);
7888 uint res = 0 - src;
7889
7890 FLAG_N = NFLAG_8(res);
7891 FLAG_C = FLAG_X = CFLAG_8(res);
7892 FLAG_V = src & res;
7893 FLAG_Z = MASK_OUT_ABOVE_8(res);
7894
7895 m68ki_write_8(ea, FLAG_Z);
7896 }
7897
7898
7899 M68KMAKE_OP(neg, 16, ., d)
7900 {
7901 uint* r_dst = &DY;
7902 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
7903
7904 FLAG_N = NFLAG_16(res);
7905 FLAG_C = FLAG_X = CFLAG_16(res);
7906 FLAG_V = (*r_dst & res)>>8;
7907 FLAG_Z = MASK_OUT_ABOVE_16(res);
7908
7909 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
7910 }
7911
7912
7913 M68KMAKE_OP(neg, 16, ., .)
7914 {
7915 uint ea = M68KMAKE_GET_EA_AY_16;
7916 uint src = m68ki_read_16(ea);
7917 uint res = 0 - src;
7918
7919 FLAG_N = NFLAG_16(res);
7920 FLAG_C = FLAG_X = CFLAG_16(res);
7921 FLAG_V = (src & res)>>8;
7922 FLAG_Z = MASK_OUT_ABOVE_16(res);
7923
7924 m68ki_write_16(ea, FLAG_Z);
7925 }
7926
7927
7928 M68KMAKE_OP(neg, 32, ., d)
7929 {
7930 uint* r_dst = &DY;
7931 uint res = 0 - *r_dst;
7932
7933 FLAG_N = NFLAG_32(res);
7934 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
7935 FLAG_V = (*r_dst & res)>>24;
7936 FLAG_Z = MASK_OUT_ABOVE_32(res);
7937
7938 *r_dst = FLAG_Z;
7939 }
7940
7941
7942 M68KMAKE_OP(neg, 32, ., .)
7943 {
7944 uint ea = M68KMAKE_GET_EA_AY_32;
7945 uint src = m68ki_read_32(ea);
7946 uint res = 0 - src;
7947
7948 FLAG_N = NFLAG_32(res);
7949 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
7950 FLAG_V = (src & res)>>24;
7951 FLAG_Z = MASK_OUT_ABOVE_32(res);
7952
7953 m68ki_write_32(ea, FLAG_Z);
7954 }
7955
7956
7957 M68KMAKE_OP(negx, 8, ., d)
7958 {
7959 uint* r_dst = &DY;
7960 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
7961
7962 FLAG_N = NFLAG_8(res);
7963 FLAG_X = FLAG_C = CFLAG_8(res);
7964 FLAG_V = *r_dst & res;
7965
7966 res = MASK_OUT_ABOVE_8(res);
7967 FLAG_Z |= res;
7968
7969 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7970 }
7971
7972
7973 M68KMAKE_OP(negx, 8, ., .)
7974 {
7975 uint ea = M68KMAKE_GET_EA_AY_8;
7976 uint src = m68ki_read_8(ea);
7977 uint res = 0 - src - XFLAG_AS_1();
7978
7979 FLAG_N = NFLAG_8(res);
7980 FLAG_X = FLAG_C = CFLAG_8(res);
7981 FLAG_V = src & res;
7982
7983 res = MASK_OUT_ABOVE_8(res);
7984 FLAG_Z |= res;
7985
7986 m68ki_write_8(ea, res);
7987 }
7988
7989
7990 M68KMAKE_OP(negx, 16, ., d)
7991 {
7992 uint* r_dst = &DY;
7993 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
7994
7995 FLAG_N = NFLAG_16(res);
7996 FLAG_X = FLAG_C = CFLAG_16(res);
7997 FLAG_V = (*r_dst & res)>>8;
7998
7999 res = MASK_OUT_ABOVE_16(res);
8000 FLAG_Z |= res;
8001
8002 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8003 }
8004
8005
8006 M68KMAKE_OP(negx, 16, ., .)
8007 {
8008 uint ea = M68KMAKE_GET_EA_AY_16;
8009 uint src = m68ki_read_16(ea);
8010 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
8011
8012 FLAG_N = NFLAG_16(res);
8013 FLAG_X = FLAG_C = CFLAG_16(res);
8014 FLAG_V = (src & res)>>8;
8015
8016 res = MASK_OUT_ABOVE_16(res);
8017 FLAG_Z |= res;
8018
8019 m68ki_write_16(ea, res);
8020 }
8021
8022
8023 M68KMAKE_OP(negx, 32, ., d)
8024 {
8025 uint* r_dst = &DY;
8026 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
8027
8028 FLAG_N = NFLAG_32(res);
8029 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
8030 FLAG_V = (*r_dst & res)>>24;
8031
8032 res = MASK_OUT_ABOVE_32(res);
8033 FLAG_Z |= res;
8034
8035 *r_dst = res;
8036 }
8037
8038
8039 M68KMAKE_OP(negx, 32, ., .)
8040 {
8041 uint ea = M68KMAKE_GET_EA_AY_32;
8042 uint src = m68ki_read_32(ea);
8043 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
8044
8045 FLAG_N = NFLAG_32(res);
8046 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
8047 FLAG_V = (src & res)>>24;
8048
8049 res = MASK_OUT_ABOVE_32(res);
8050 FLAG_Z |= res;
8051
8052 m68ki_write_32(ea, res);
8053 }
8054
8055
8056 M68KMAKE_OP(nop, 0, ., .)
8057 {
8058 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8059 }
8060
8061
8062 M68KMAKE_OP(not, 8, ., d)
8063 {
8064 uint* r_dst = &DY;
8065 uint res = MASK_OUT_ABOVE_8(~*r_dst);
8066
8067 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8068
8069 FLAG_N = NFLAG_8(res);
8070 FLAG_Z = res;
8071 FLAG_C = CFLAG_CLEAR;
8072 FLAG_V = VFLAG_CLEAR;
8073 }
8074
8075
8076 M68KMAKE_OP(not, 8, ., .)
8077 {
8078 uint ea = M68KMAKE_GET_EA_AY_8;
8079 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
8080
8081 m68ki_write_8(ea, res);
8082
8083 FLAG_N = NFLAG_8(res);
8084 FLAG_Z = res;
8085 FLAG_C = CFLAG_CLEAR;
8086 FLAG_V = VFLAG_CLEAR;
8087 }
8088
8089
8090 M68KMAKE_OP(not, 16, ., d)
8091 {
8092 uint* r_dst = &DY;
8093 uint res = MASK_OUT_ABOVE_16(~*r_dst);
8094
8095 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8096
8097 FLAG_N = NFLAG_16(res);
8098 FLAG_Z = res;
8099 FLAG_C = CFLAG_CLEAR;
8100 FLAG_V = VFLAG_CLEAR;
8101 }
8102
8103
8104 M68KMAKE_OP(not, 16, ., .)
8105 {
8106 uint ea = M68KMAKE_GET_EA_AY_16;
8107 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
8108
8109 m68ki_write_16(ea, res);
8110
8111 FLAG_N = NFLAG_16(res);
8112 FLAG_Z = res;
8113 FLAG_C = CFLAG_CLEAR;
8114 FLAG_V = VFLAG_CLEAR;
8115 }
8116
8117
8118 M68KMAKE_OP(not, 32, ., d)
8119 {
8120 uint* r_dst = &DY;
8121 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
8122
8123 FLAG_N = NFLAG_32(res);
8124 FLAG_Z = res;
8125 FLAG_C = CFLAG_CLEAR;
8126 FLAG_V = VFLAG_CLEAR;
8127 }
8128
8129
8130 M68KMAKE_OP(not, 32, ., .)
8131 {
8132 uint ea = M68KMAKE_GET_EA_AY_32;
8133 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
8134
8135 m68ki_write_32(ea, res);
8136
8137 FLAG_N = NFLAG_32(res);
8138 FLAG_Z = res;
8139 FLAG_C = CFLAG_CLEAR;
8140 FLAG_V = VFLAG_CLEAR;
8141 }
8142
8143
8144 M68KMAKE_OP(or, 8, er, d)
8145 {
8146 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
8147
8148 FLAG_N = NFLAG_8(res);
8149 FLAG_Z = res;
8150 FLAG_C = CFLAG_CLEAR;
8151 FLAG_V = VFLAG_CLEAR;
8152 }
8153
8154
8155 M68KMAKE_OP(or, 8, er, .)
8156 {
8157 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
8158
8159 FLAG_N = NFLAG_8(res);
8160 FLAG_Z = res;
8161 FLAG_C = CFLAG_CLEAR;
8162 FLAG_V = VFLAG_CLEAR;
8163 }
8164
8165
8166 M68KMAKE_OP(or, 16, er, d)
8167 {
8168 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
8169
8170 FLAG_N = NFLAG_16(res);
8171 FLAG_Z = res;
8172 FLAG_C = CFLAG_CLEAR;
8173 FLAG_V = VFLAG_CLEAR;
8174 }
8175
8176
8177 M68KMAKE_OP(or, 16, er, .)
8178 {
8179 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
8180
8181 FLAG_N = NFLAG_16(res);
8182 FLAG_Z = res;
8183 FLAG_C = CFLAG_CLEAR;
8184 FLAG_V = VFLAG_CLEAR;
8185 }
8186
8187
8188 M68KMAKE_OP(or, 32, er, d)
8189 {
8190 uint res = DX |= DY;
8191
8192 FLAG_N = NFLAG_32(res);
8193 FLAG_Z = res;
8194 FLAG_C = CFLAG_CLEAR;
8195 FLAG_V = VFLAG_CLEAR;
8196 }
8197
8198
8199 M68KMAKE_OP(or, 32, er, .)
8200 {
8201 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
8202
8203 FLAG_N = NFLAG_32(res);
8204 FLAG_Z = res;
8205 FLAG_C = CFLAG_CLEAR;
8206 FLAG_V = VFLAG_CLEAR;
8207 }
8208
8209
8210 M68KMAKE_OP(or, 8, re, .)
8211 {
8212 uint ea = M68KMAKE_GET_EA_AY_8;
8213 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
8214
8215 m68ki_write_8(ea, res);
8216
8217 FLAG_N = NFLAG_8(res);
8218 FLAG_Z = res;
8219 FLAG_C = CFLAG_CLEAR;
8220 FLAG_V = VFLAG_CLEAR;
8221 }
8222
8223
8224 M68KMAKE_OP(or, 16, re, .)
8225 {
8226 uint ea = M68KMAKE_GET_EA_AY_16;
8227 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
8228
8229 m68ki_write_16(ea, res);
8230
8231 FLAG_N = NFLAG_16(res);
8232 FLAG_Z = res;
8233 FLAG_C = CFLAG_CLEAR;
8234 FLAG_V = VFLAG_CLEAR;
8235 }
8236
8237
8238 M68KMAKE_OP(or, 32, re, .)
8239 {
8240 uint ea = M68KMAKE_GET_EA_AY_32;
8241 uint res = DX | m68ki_read_32(ea);
8242
8243 m68ki_write_32(ea, res);
8244
8245 FLAG_N = NFLAG_32(res);
8246 FLAG_Z = res;
8247 FLAG_C = CFLAG_CLEAR;
8248 FLAG_V = VFLAG_CLEAR;
8249 }
8250
8251
8252 M68KMAKE_OP(ori, 8, ., d)
8253 {
8254 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
8255
8256 FLAG_N = NFLAG_8(res);
8257 FLAG_Z = res;
8258 FLAG_C = CFLAG_CLEAR;
8259 FLAG_V = VFLAG_CLEAR;
8260 }
8261
8262
8263 M68KMAKE_OP(ori, 8, ., .)
8264 {
8265 uint src = OPER_I_8();
8266 uint ea = M68KMAKE_GET_EA_AY_8;
8267 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
8268
8269 m68ki_write_8(ea, res);
8270
8271 FLAG_N = NFLAG_8(res);
8272 FLAG_Z = res;
8273 FLAG_C = CFLAG_CLEAR;
8274 FLAG_V = VFLAG_CLEAR;
8275 }
8276
8277
8278 M68KMAKE_OP(ori, 16, ., d)
8279 {
8280 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
8281
8282 FLAG_N = NFLAG_16(res);
8283 FLAG_Z = res;
8284 FLAG_C = CFLAG_CLEAR;
8285 FLAG_V = VFLAG_CLEAR;
8286 }
8287
8288
8289 M68KMAKE_OP(ori, 16, ., .)
8290 {
8291 uint src = OPER_I_16();
8292 uint ea = M68KMAKE_GET_EA_AY_16;
8293 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
8294
8295 m68ki_write_16(ea, res);
8296
8297 FLAG_N = NFLAG_16(res);
8298 FLAG_Z = res;
8299 FLAG_C = CFLAG_CLEAR;
8300 FLAG_V = VFLAG_CLEAR;
8301 }
8302
8303
8304 M68KMAKE_OP(ori, 32, ., d)
8305 {
8306 uint res = DY |= OPER_I_32();
8307
8308 FLAG_N = NFLAG_32(res);
8309 FLAG_Z = res;
8310 FLAG_C = CFLAG_CLEAR;
8311 FLAG_V = VFLAG_CLEAR;
8312 }
8313
8314
8315 M68KMAKE_OP(ori, 32, ., .)
8316 {
8317 uint src = OPER_I_32();
8318 uint ea = M68KMAKE_GET_EA_AY_32;
8319 uint res = src | m68ki_read_32(ea);
8320
8321 m68ki_write_32(ea, res);
8322
8323 FLAG_N = NFLAG_32(res);
8324 FLAG_Z = res;
8325 FLAG_C = CFLAG_CLEAR;
8326 FLAG_V = VFLAG_CLEAR;
8327 }
8328
8329
8330 M68KMAKE_OP(ori, 16, toc, .)
8331 {
8332 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
8333 }
8334
8335
8336 M68KMAKE_OP(ori, 16, tos, .)
8337 {
8338 if(FLAG_S)
8339 {
8340 uint src = OPER_I_16();
8341 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8342 m68ki_set_sr(m68ki_get_sr() | src);
8343 return;
8344 }
8345 m68ki_exception_privilege_violation();
8346 }
8347
8348
8349 M68KMAKE_OP(pack, 16, rr, .)
8350 {
8351 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8352 {
8353 /* Note: DX and DY are reversed in Motorola's docs */
8354 uint src = DY + OPER_I_16();
8355 uint* r_dst = &DX;
8356
8357 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
8358 return;
8359 }
8360 m68ki_exception_illegal();
8361 }
8362
8363
8364 M68KMAKE_OP(pack, 16, mm, ax7)
8365 {
8366 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8367 {
8368 /* Note: AX and AY are reversed in Motorola's docs */
8369 uint ea_src = EA_AY_PD_8();
8370 uint src = m68ki_read_8(ea_src);
8371 ea_src = EA_AY_PD_8();
8372 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8373
8374 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8375 return;
8376 }
8377 m68ki_exception_illegal();
8378 }
8379
8380
8381 M68KMAKE_OP(pack, 16, mm, ay7)
8382 {
8383 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8384 {
8385 /* Note: AX and AY are reversed in Motorola's docs */
8386 uint ea_src = EA_A7_PD_8();
8387 uint src = m68ki_read_8(ea_src);
8388 ea_src = EA_A7_PD_8();
8389 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8390
8391 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8392 return;
8393 }
8394 m68ki_exception_illegal();
8395 }
8396
8397
8398 M68KMAKE_OP(pack, 16, mm, axy7)
8399 {
8400 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8401 {
8402 uint ea_src = EA_A7_PD_8();
8403 uint src = m68ki_read_8(ea_src);
8404 ea_src = EA_A7_PD_8();
8405 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8406
8407 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8408 return;
8409 }
8410 m68ki_exception_illegal();
8411 }
8412
8413
8414 M68KMAKE_OP(pack, 16, mm, .)
8415 {
8416 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
8417 {
8418 /* Note: AX and AY are reversed in Motorola's docs */
8419 uint ea_src = EA_AY_PD_8();
8420 uint src = m68ki_read_8(ea_src);
8421 ea_src = EA_AY_PD_8();
8422 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
8423
8424 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
8425 return;
8426 }
8427 m68ki_exception_illegal();
8428 }
8429
8430
8431 M68KMAKE_OP(pea, 32, ., .)
8432 {
8433 uint ea = M68KMAKE_GET_EA_AY_32;
8434
8435 m68ki_push_32(ea);
8436 }
8437
8438
8439 M68KMAKE_OP(pflush, 32, ., .)
8440 {
8441 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))
8442 {
8443 // Nothing to do, unless address translation cache is emulated
8444 return;
8445 }
8446 m68ki_exception_illegal();
8447 }
8448
8449
8450 M68KMAKE_OP(reset, 0, ., .)
8451 {
8452 if(FLAG_S)
8453 {
8454 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
8455 USE_CYCLES(CYC_RESET);
8456 return;
8457 }
8458 m68ki_exception_privilege_violation();
8459 }
8460
8461
8462 M68KMAKE_OP(ror, 8, s, .)
8463 {
8464 uint* r_dst = &DY;
8465 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8466 uint shift = orig_shift & 7;
8467 uint src = MASK_OUT_ABOVE_8(*r_dst);
8468 uint res = ROR_8(src, shift);
8469
8470 if(orig_shift != 0)
8471 USE_CYCLES(orig_shift<<CYC_SHIFT);
8472
8473 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8474
8475 FLAG_N = NFLAG_8(res);
8476 FLAG_Z = res;
8477 FLAG_C = src << (9-orig_shift);
8478 FLAG_V = VFLAG_CLEAR;
8479 }
8480
8481
8482 M68KMAKE_OP(ror, 16, s, .)
8483 {
8484 uint* r_dst = &DY;
8485 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8486 uint src = MASK_OUT_ABOVE_16(*r_dst);
8487 uint res = ROR_16(src, shift);
8488
8489 if(shift != 0)
8490 USE_CYCLES(shift<<CYC_SHIFT);
8491
8492 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8493
8494 FLAG_N = NFLAG_16(res);
8495 FLAG_Z = res;
8496 FLAG_C = src << (9-shift);
8497 FLAG_V = VFLAG_CLEAR;
8498 }
8499
8500
8501 M68KMAKE_OP(ror, 32, s, .)
8502 {
8503 uint* r_dst = &DY;
8504 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8505 uint64 src = *r_dst;
8506 uint res = ROR_32(src, shift);
8507
8508 if(shift != 0)
8509 USE_CYCLES(shift<<CYC_SHIFT);
8510
8511 *r_dst = res;
8512
8513 FLAG_N = NFLAG_32(res);
8514 FLAG_Z = res;
8515 FLAG_C = src << (9-shift);
8516 FLAG_V = VFLAG_CLEAR;
8517 }
8518
8519
8520 M68KMAKE_OP(ror, 8, r, .)
8521 {
8522 uint* r_dst = &DY;
8523 uint orig_shift = DX & 0x3f;
8524 uint shift = orig_shift & 7;
8525 uint src = MASK_OUT_ABOVE_8(*r_dst);
8526 uint res = ROR_8(src, shift);
8527
8528 if(orig_shift != 0)
8529 {
8530 USE_CYCLES(orig_shift<<CYC_SHIFT);
8531
8532 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8533 FLAG_C = src << (8-((shift-1)&7));
8534 FLAG_N = NFLAG_8(res);
8535 FLAG_Z = res;
8536 FLAG_V = VFLAG_CLEAR;
8537 return;
8538 }
8539
8540 FLAG_C = CFLAG_CLEAR;
8541 FLAG_N = NFLAG_8(src);
8542 FLAG_Z = src;
8543 FLAG_V = VFLAG_CLEAR;
8544 }
8545
8546
8547 M68KMAKE_OP(ror, 16, r, .)
8548 {
8549 uint* r_dst = &DY;
8550 uint orig_shift = DX & 0x3f;
8551 uint shift = orig_shift & 15;
8552 uint src = MASK_OUT_ABOVE_16(*r_dst);
8553 uint res = ROR_16(src, shift);
8554
8555 if(orig_shift != 0)
8556 {
8557 USE_CYCLES(orig_shift<<CYC_SHIFT);
8558
8559 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8560 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
8561 FLAG_N = NFLAG_16(res);
8562 FLAG_Z = res;
8563 FLAG_V = VFLAG_CLEAR;
8564 return;
8565 }
8566
8567 FLAG_C = CFLAG_CLEAR;
8568 FLAG_N = NFLAG_16(src);
8569 FLAG_Z = src;
8570 FLAG_V = VFLAG_CLEAR;
8571 }
8572
8573
8574 M68KMAKE_OP(ror, 32, r, .)
8575 {
8576 uint* r_dst = &DY;
8577 uint orig_shift = DX & 0x3f;
8578 uint shift = orig_shift & 31;
8579 uint64 src = *r_dst;
8580 uint res = ROR_32(src, shift);
8581
8582 if(orig_shift != 0)
8583 {
8584 USE_CYCLES(orig_shift<<CYC_SHIFT);
8585
8586 *r_dst = res;
8587 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
8588 FLAG_N = NFLAG_32(res);
8589 FLAG_Z = res;
8590 FLAG_V = VFLAG_CLEAR;
8591 return;
8592 }
8593
8594 FLAG_C = CFLAG_CLEAR;
8595 FLAG_N = NFLAG_32(src);
8596 FLAG_Z = src;
8597 FLAG_V = VFLAG_CLEAR;
8598 }
8599
8600
8601 M68KMAKE_OP(ror, 16, ., .)
8602 {
8603 uint ea = M68KMAKE_GET_EA_AY_16;
8604 uint src = m68ki_read_16(ea);
8605 uint res = ROR_16(src, 1);
8606
8607 m68ki_write_16(ea, res);
8608
8609 FLAG_N = NFLAG_16(res);
8610 FLAG_Z = res;
8611 FLAG_C = src << 8;
8612 FLAG_V = VFLAG_CLEAR;
8613 }
8614
8615
8616 M68KMAKE_OP(rol, 8, s, .)
8617 {
8618 uint* r_dst = &DY;
8619 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8620 uint shift = orig_shift & 7;
8621 uint src = MASK_OUT_ABOVE_8(*r_dst);
8622 uint res = ROL_8(src, shift);
8623
8624 if(orig_shift != 0)
8625 USE_CYCLES(orig_shift<<CYC_SHIFT);
8626
8627 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8628
8629 FLAG_N = NFLAG_8(res);
8630 FLAG_Z = res;
8631 FLAG_C = src << orig_shift;
8632 FLAG_V = VFLAG_CLEAR;
8633 }
8634
8635
8636 M68KMAKE_OP(rol, 16, s, .)
8637 {
8638 uint* r_dst = &DY;
8639 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8640 uint src = MASK_OUT_ABOVE_16(*r_dst);
8641 uint res = ROL_16(src, shift);
8642
8643 if(shift != 0)
8644 USE_CYCLES(shift<<CYC_SHIFT);
8645
8646 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8647
8648 FLAG_N = NFLAG_16(res);
8649 FLAG_Z = res;
8650 FLAG_C = src >> (8-shift);
8651 FLAG_V = VFLAG_CLEAR;
8652 }
8653
8654
8655 M68KMAKE_OP(rol, 32, s, .)
8656 {
8657 uint* r_dst = &DY;
8658 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8659 uint64 src = *r_dst;
8660 uint res = ROL_32(src, shift);
8661
8662 if(shift != 0)
8663 USE_CYCLES(shift<<CYC_SHIFT);
8664
8665 *r_dst = res;
8666
8667 FLAG_N = NFLAG_32(res);
8668 FLAG_Z = res;
8669 FLAG_C = src >> (24-shift);
8670 FLAG_V = VFLAG_CLEAR;
8671 }
8672
8673
8674 M68KMAKE_OP(rol, 8, r, .)
8675 {
8676 uint* r_dst = &DY;
8677 uint orig_shift = DX & 0x3f;
8678 uint shift = orig_shift & 7;
8679 uint src = MASK_OUT_ABOVE_8(*r_dst);
8680 uint res = ROL_8(src, shift);
8681
8682 if(orig_shift != 0)
8683 {
8684 USE_CYCLES(orig_shift<<CYC_SHIFT);
8685
8686 if(shift != 0)
8687 {
8688 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8689 FLAG_C = src << shift;
8690 FLAG_N = NFLAG_8(res);
8691 FLAG_Z = res;
8692 FLAG_V = VFLAG_CLEAR;
8693 return;
8694 }
8695 FLAG_C = (src & 1)<<8;
8696 FLAG_N = NFLAG_8(src);
8697 FLAG_Z = src;
8698 FLAG_V = VFLAG_CLEAR;
8699 return;
8700 }
8701
8702 FLAG_C = CFLAG_CLEAR;
8703 FLAG_N = NFLAG_8(src);
8704 FLAG_Z = src;
8705 FLAG_V = VFLAG_CLEAR;
8706 }
8707
8708
8709 M68KMAKE_OP(rol, 16, r, .)
8710 {
8711 uint* r_dst = &DY;
8712 uint orig_shift = DX & 0x3f;
8713 uint shift = orig_shift & 15;
8714 uint src = MASK_OUT_ABOVE_16(*r_dst);
8715 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
8716
8717 if(orig_shift != 0)
8718 {
8719 USE_CYCLES(orig_shift<<CYC_SHIFT);
8720
8721 if(shift != 0)
8722 {
8723 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8724 FLAG_C = (src << shift) >> 8;
8725 FLAG_N = NFLAG_16(res);
8726 FLAG_Z = res;
8727 FLAG_V = VFLAG_CLEAR;
8728 return;
8729 }
8730 FLAG_C = (src & 1)<<8;
8731 FLAG_N = NFLAG_16(src);
8732 FLAG_Z = src;
8733 FLAG_V = VFLAG_CLEAR;
8734 return;
8735 }
8736
8737 FLAG_C = CFLAG_CLEAR;
8738 FLAG_N = NFLAG_16(src);
8739 FLAG_Z = src;
8740 FLAG_V = VFLAG_CLEAR;
8741 }
8742
8743
8744 M68KMAKE_OP(rol, 32, r, .)
8745 {
8746 uint* r_dst = &DY;
8747 uint orig_shift = DX & 0x3f;
8748 uint shift = orig_shift & 31;
8749 uint64 src = *r_dst;
8750 uint res = ROL_32(src, shift);
8751
8752 if(orig_shift != 0)
8753 {
8754 USE_CYCLES(orig_shift<<CYC_SHIFT);
8755
8756 *r_dst = res;
8757
8758 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;
8759 FLAG_N = NFLAG_32(res);
8760 FLAG_Z = res;
8761 FLAG_V = VFLAG_CLEAR;
8762 return;
8763 }
8764
8765 FLAG_C = CFLAG_CLEAR;
8766 FLAG_N = NFLAG_32(src);
8767 FLAG_Z = src;
8768 FLAG_V = VFLAG_CLEAR;
8769 }
8770
8771
8772 M68KMAKE_OP(rol, 16, ., .)
8773 {
8774 uint ea = M68KMAKE_GET_EA_AY_16;
8775 uint src = m68ki_read_16(ea);
8776 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
8777
8778 m68ki_write_16(ea, res);
8779
8780 FLAG_N = NFLAG_16(res);
8781 FLAG_Z = res;
8782 FLAG_C = src >> 7;
8783 FLAG_V = VFLAG_CLEAR;
8784 }
8785
8786
8787 M68KMAKE_OP(roxr, 8, s, .)
8788 {
8789 uint* r_dst = &DY;
8790 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8791 uint src = MASK_OUT_ABOVE_8(*r_dst);
8792 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8793
8794 if(shift != 0)
8795 USE_CYCLES(shift<<CYC_SHIFT);
8796
8797 FLAG_C = FLAG_X = res;
8798 res = MASK_OUT_ABOVE_8(res);
8799
8800 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8801
8802 FLAG_N = NFLAG_8(res);
8803 FLAG_Z = res;
8804 FLAG_V = VFLAG_CLEAR;
8805 }
8806
8807
8808 M68KMAKE_OP(roxr, 16, s, .)
8809 {
8810 uint* r_dst = &DY;
8811 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8812 uint src = MASK_OUT_ABOVE_16(*r_dst);
8813 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8814
8815 if(shift != 0)
8816 USE_CYCLES(shift<<CYC_SHIFT);
8817
8818 FLAG_C = FLAG_X = res >> 8;
8819 res = MASK_OUT_ABOVE_16(res);
8820
8821 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8822
8823 FLAG_N = NFLAG_16(res);
8824 FLAG_Z = res;
8825 FLAG_V = VFLAG_CLEAR;
8826 }
8827
8828
8829 M68KMAKE_OP(roxr, 32, s, .)
8830 {
8831 #if M68K_USE_64_BIT
8832
8833 uint* r_dst = &DY;
8834 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8835 uint64 src = *r_dst;
8836 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8837
8838 if(shift != 0)
8839 USE_CYCLES(shift<<CYC_SHIFT);
8840
8841 res = ROR_33_64(res, shift);
8842
8843 FLAG_C = FLAG_X = res >> 24;
8844 res = MASK_OUT_ABOVE_32(res);
8845
8846 *r_dst = res;
8847
8848 FLAG_N = NFLAG_32(res);
8849 FLAG_Z = res;
8850 FLAG_V = VFLAG_CLEAR;
8851
8852 #else
8853
8854 uint* r_dst = &DY;
8855 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8856 uint src = *r_dst;
8857 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8858 uint new_x_flag = src & (1 << (shift - 1));
8859
8860 if(shift != 0)
8861 USE_CYCLES(shift<<CYC_SHIFT);
8862
8863 *r_dst = res;
8864
8865 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
8866 FLAG_N = NFLAG_32(res);
8867 FLAG_Z = res;
8868 FLAG_V = VFLAG_CLEAR;
8869
8870 #endif
8871 }
8872
8873
8874 M68KMAKE_OP(roxr, 8, r, .)
8875 {
8876 uint* r_dst = &DY;
8877 uint orig_shift = DX & 0x3f;
8878
8879 if(orig_shift != 0)
8880 {
8881 uint shift = orig_shift % 9;
8882 uint src = MASK_OUT_ABOVE_8(*r_dst);
8883 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8884
8885 USE_CYCLES(orig_shift<<CYC_SHIFT);
8886
8887 FLAG_C = FLAG_X = res;
8888 res = MASK_OUT_ABOVE_8(res);
8889
8890 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8891 FLAG_N = NFLAG_8(res);
8892 FLAG_Z = res;
8893 FLAG_V = VFLAG_CLEAR;
8894 return;
8895 }
8896
8897 FLAG_C = FLAG_X;
8898 FLAG_N = NFLAG_8(*r_dst);
8899 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
8900 FLAG_V = VFLAG_CLEAR;
8901 }
8902
8903
8904 M68KMAKE_OP(roxr, 16, r, .)
8905 {
8906 uint* r_dst = &DY;
8907 uint orig_shift = DX & 0x3f;
8908
8909 if(orig_shift != 0)
8910 {
8911 uint shift = orig_shift % 17;
8912 uint src = MASK_OUT_ABOVE_16(*r_dst);
8913 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8914
8915 USE_CYCLES(orig_shift<<CYC_SHIFT);
8916
8917 FLAG_C = FLAG_X = res >> 8;
8918 res = MASK_OUT_ABOVE_16(res);
8919
8920 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8921 FLAG_N = NFLAG_16(res);
8922 FLAG_Z = res;
8923 FLAG_V = VFLAG_CLEAR;
8924 return;
8925 }
8926
8927 FLAG_C = FLAG_X;
8928 FLAG_N = NFLAG_16(*r_dst);
8929 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
8930 FLAG_V = VFLAG_CLEAR;
8931 }
8932
8933
8934 M68KMAKE_OP(roxr, 32, r, .)
8935 {
8936 #if M68K_USE_64_BIT
8937
8938 uint* r_dst = &DY;
8939 uint orig_shift = DX & 0x3f;
8940
8941 if(orig_shift != 0)
8942 {
8943 uint shift = orig_shift % 33;
8944 uint64 src = *r_dst;
8945 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8946
8947 res = ROR_33_64(res, shift);
8948
8949 USE_CYCLES(orig_shift<<CYC_SHIFT);
8950
8951 FLAG_C = FLAG_X = res >> 24;
8952 res = MASK_OUT_ABOVE_32(res);
8953
8954 *r_dst = res;
8955 FLAG_N = NFLAG_32(res);
8956 FLAG_Z = res;
8957 FLAG_V = VFLAG_CLEAR;
8958 return;
8959 }
8960
8961 FLAG_C = FLAG_X;
8962 FLAG_N = NFLAG_32(*r_dst);
8963 FLAG_Z = *r_dst;
8964 FLAG_V = VFLAG_CLEAR;
8965
8966 #else
8967
8968 uint* r_dst = &DY;
8969 uint orig_shift = DX & 0x3f;
8970 uint shift = orig_shift % 33;
8971 uint src = *r_dst;
8972 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8973 uint new_x_flag = src & (1 << (shift - 1));
8974
8975 if(orig_shift != 0)
8976 USE_CYCLES(orig_shift<<CYC_SHIFT);
8977
8978 if(shift != 0)
8979 {
8980 *r_dst = res;
8981 FLAG_X = (new_x_flag != 0)<<8;
8982 }
8983 else
8984 res = src;
8985 FLAG_C = FLAG_X;
8986 FLAG_N = NFLAG_32(res);
8987 FLAG_Z = res;
8988 FLAG_V = VFLAG_CLEAR;
8989
8990 #endif
8991 }
8992
8993
8994 M68KMAKE_OP(roxr, 16, ., .)
8995 {
8996 uint ea = M68KMAKE_GET_EA_AY_16;
8997 uint src = m68ki_read_16(ea);
8998 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
8999
9000 FLAG_C = FLAG_X = res >> 8;
9001 res = MASK_OUT_ABOVE_16(res);
9002
9003 m68ki_write_16(ea, res);
9004
9005 FLAG_N = NFLAG_16(res);
9006 FLAG_Z = res;
9007 FLAG_V = VFLAG_CLEAR;
9008 }
9009
9010
9011 M68KMAKE_OP(roxl, 8, s, .)
9012 {
9013 uint* r_dst = &DY;
9014 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9015 uint src = MASK_OUT_ABOVE_8(*r_dst);
9016 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9017
9018 if(shift != 0)
9019 USE_CYCLES(shift<<CYC_SHIFT);
9020
9021 FLAG_C = FLAG_X = res;
9022 res = MASK_OUT_ABOVE_8(res);
9023
9024 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9025
9026 FLAG_N = NFLAG_8(res);
9027 FLAG_Z = res;
9028 FLAG_V = VFLAG_CLEAR;
9029 }
9030
9031
9032 M68KMAKE_OP(roxl, 16, s, .)
9033 {
9034 uint* r_dst = &DY;
9035 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9036 uint src = MASK_OUT_ABOVE_16(*r_dst);
9037 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9038
9039 if(shift != 0)
9040 USE_CYCLES(shift<<CYC_SHIFT);
9041
9042 FLAG_C = FLAG_X = res >> 8;
9043 res = MASK_OUT_ABOVE_16(res);
9044
9045 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9046
9047 FLAG_N = NFLAG_16(res);
9048 FLAG_Z = res;
9049 FLAG_V = VFLAG_CLEAR;
9050 }
9051
9052
9053 M68KMAKE_OP(roxl, 32, s, .)
9054 {
9055 #if M68K_USE_64_BIT
9056
9057 uint* r_dst = &DY;
9058 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9059 uint64 src = *r_dst;
9060 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9061
9062 if(shift != 0)
9063 USE_CYCLES(shift<<CYC_SHIFT);
9064
9065 res = ROL_33_64(res, shift);
9066
9067 FLAG_C = FLAG_X = res >> 24;
9068 res = MASK_OUT_ABOVE_32(res);
9069
9070 *r_dst = res;
9071
9072 FLAG_N = NFLAG_32(res);
9073 FLAG_Z = res;
9074 FLAG_V = VFLAG_CLEAR;
9075
9076 #else
9077
9078 uint* r_dst = &DY;
9079 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
9080 uint src = *r_dst;
9081 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9082 uint new_x_flag = src & (1 << (32 - shift));
9083
9084 if(shift != 0)
9085 USE_CYCLES(shift<<CYC_SHIFT);
9086
9087 *r_dst = res;
9088
9089 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
9090 FLAG_N = NFLAG_32(res);
9091 FLAG_Z = res;
9092 FLAG_V = VFLAG_CLEAR;
9093
9094 #endif
9095 }
9096
9097
9098 M68KMAKE_OP(roxl, 8, r, .)
9099 {
9100 uint* r_dst = &DY;
9101 uint orig_shift = DX & 0x3f;
9102
9103
9104 if(orig_shift != 0)
9105 {
9106 uint shift = orig_shift % 9;
9107 uint src = MASK_OUT_ABOVE_8(*r_dst);
9108 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
9109
9110 USE_CYCLES(orig_shift<<CYC_SHIFT);
9111
9112 FLAG_C = FLAG_X = res;
9113 res = MASK_OUT_ABOVE_8(res);
9114
9115 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9116 FLAG_N = NFLAG_8(res);
9117 FLAG_Z = res;
9118 FLAG_V = VFLAG_CLEAR;
9119 return;
9120 }
9121
9122 FLAG_C = FLAG_X;
9123 FLAG_N = NFLAG_8(*r_dst);
9124 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
9125 FLAG_V = VFLAG_CLEAR;
9126 }
9127
9128
9129 M68KMAKE_OP(roxl, 16, r, .)
9130 {
9131 uint* r_dst = &DY;
9132 uint orig_shift = DX & 0x3f;
9133
9134 if(orig_shift != 0)
9135 {
9136 uint shift = orig_shift % 17;
9137 uint src = MASK_OUT_ABOVE_16(*r_dst);
9138 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
9139
9140 USE_CYCLES(orig_shift<<CYC_SHIFT);
9141
9142 FLAG_C = FLAG_X = res >> 8;
9143 res = MASK_OUT_ABOVE_16(res);
9144
9145 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9146 FLAG_N = NFLAG_16(res);
9147 FLAG_Z = res;
9148 FLAG_V = VFLAG_CLEAR;
9149 return;
9150 }
9151
9152 FLAG_C = FLAG_X;
9153 FLAG_N = NFLAG_16(*r_dst);
9154 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
9155 FLAG_V = VFLAG_CLEAR;
9156 }
9157
9158
9159 M68KMAKE_OP(roxl, 32, r, .)
9160 {
9161 #if M68K_USE_64_BIT
9162
9163 uint* r_dst = &DY;
9164 uint orig_shift = DX & 0x3f;
9165
9166 if(orig_shift != 0)
9167 {
9168 uint shift = orig_shift % 33;
9169 uint64 src = *r_dst;
9170 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
9171
9172 res = ROL_33_64(res, shift);
9173
9174 USE_CYCLES(orig_shift<<CYC_SHIFT);
9175
9176 FLAG_C = FLAG_X = res >> 24;
9177 res = MASK_OUT_ABOVE_32(res);
9178
9179 *r_dst = res;
9180 FLAG_N = NFLAG_32(res);
9181 FLAG_Z = res;
9182 FLAG_V = VFLAG_CLEAR;
9183 return;
9184 }
9185
9186 FLAG_C = FLAG_X;
9187 FLAG_N = NFLAG_32(*r_dst);
9188 FLAG_Z = *r_dst;
9189 FLAG_V = VFLAG_CLEAR;
9190
9191 #else
9192
9193 uint* r_dst = &DY;
9194 uint orig_shift = DX & 0x3f;
9195 uint shift = orig_shift % 33;
9196 uint src = *r_dst;
9197 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
9198 uint new_x_flag = src & (1 << (32 - shift));
9199
9200 if(orig_shift != 0)
9201 USE_CYCLES(orig_shift<<CYC_SHIFT);
9202
9203 if(shift != 0)
9204 {
9205 *r_dst = res;
9206 FLAG_X = (new_x_flag != 0)<<8;
9207 }
9208 else
9209 res = src;
9210 FLAG_C = FLAG_X;
9211 FLAG_N = NFLAG_32(res);
9212 FLAG_Z = res;
9213 FLAG_V = VFLAG_CLEAR;
9214
9215 #endif
9216 }
9217
9218
9219 M68KMAKE_OP(roxl, 16, ., .)
9220 {
9221 uint ea = M68KMAKE_GET_EA_AY_16;
9222 uint src = m68ki_read_16(ea);
9223 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
9224
9225 FLAG_C = FLAG_X = res >> 8;
9226 res = MASK_OUT_ABOVE_16(res);
9227
9228 m68ki_write_16(ea, res);
9229
9230 FLAG_N = NFLAG_16(res);
9231 FLAG_Z = res;
9232 FLAG_V = VFLAG_CLEAR;
9233 }
9234
9235
9236 M68KMAKE_OP(rtd, 32, ., .)
9237 {
9238 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
9239 {
9240 uint new_pc = m68ki_pull_32();
9241
9242 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9243 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
9244 m68ki_jump(new_pc);
9245 return;
9246 }
9247 m68ki_exception_illegal();
9248 }
9249
9250
9251 M68KMAKE_OP(rte, 32, ., .)
9252 {
9253 if(FLAG_S)
9254 {
9255 uint new_sr;
9256 uint new_pc;
9257 uint format_word;
9258
9259 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */
9260 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9261
9262 if(CPU_TYPE_IS_000(CPU_TYPE))
9263 {
9264 new_sr = m68ki_pull_16();
9265 new_pc = m68ki_pull_32();
9266 m68ki_jump(new_pc);
9267 m68ki_set_sr(new_sr);
9268
9269 CPU_INSTR_MODE = INSTRUCTION_YES;
9270 CPU_RUN_MODE = RUN_MODE_NORMAL;
9271
9272 return;
9273 }
9274
9275 if(CPU_TYPE_IS_010(CPU_TYPE))
9276 {
9277 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9278 if(format_word == 0)
9279 {
9280 new_sr = m68ki_pull_16();
9281 new_pc = m68ki_pull_32();
9282 m68ki_fake_pull_16(); /* format word */
9283 m68ki_jump(new_pc);
9284 m68ki_set_sr(new_sr);
9285 CPU_INSTR_MODE = INSTRUCTION_YES;
9286 CPU_RUN_MODE = RUN_MODE_NORMAL;
9287 return;
9288 }
9289 CPU_INSTR_MODE = INSTRUCTION_YES;
9290 CPU_RUN_MODE = RUN_MODE_NORMAL;
9291 /* Not handling bus fault (9) */
9292 m68ki_exception_format_error();
9293 return;
9294 }
9295
9296 /* Otherwise it's 020 */
9297 rte_loop:
9298 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
9299 switch(format_word)
9300 {
9301 case 0: /* Normal */
9302 new_sr = m68ki_pull_16();
9303 new_pc = m68ki_pull_32();
9304 m68ki_fake_pull_16(); /* format word */
9305 m68ki_jump(new_pc);
9306 m68ki_set_sr(new_sr);
9307 CPU_INSTR_MODE = INSTRUCTION_YES;
9308 CPU_RUN_MODE = RUN_MODE_NORMAL;
9309 return;
9310 case 1: /* Throwaway */
9311 new_sr = m68ki_pull_16();
9312 m68ki_fake_pull_32(); /* program counter */
9313 m68ki_fake_pull_16(); /* format word */
9314 m68ki_set_sr_noint(new_sr);
9315 goto rte_loop;
9316 case 2: /* Trap */
9317 new_sr = m68ki_pull_16();
9318 new_pc = m68ki_pull_32();
9319 m68ki_fake_pull_16(); /* format word */
9320 m68ki_fake_pull_32(); /* address */
9321 m68ki_jump(new_pc);
9322 m68ki_set_sr(new_sr);
9323 CPU_INSTR_MODE = INSTRUCTION_YES;
9324 CPU_RUN_MODE = RUN_MODE_NORMAL;
9325 return;
9326 }
9327 /* Not handling long or short bus fault */
9328 CPU_INSTR_MODE = INSTRUCTION_YES;
9329 CPU_RUN_MODE = RUN_MODE_NORMAL;
9330 m68ki_exception_format_error();
9331 return;
9332 }
9333 m68ki_exception_privilege_violation();
9334 }
9335
9336
9337 M68KMAKE_OP(rtm, 32, ., .)
9338 {
9339 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
9340 {
9341 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9342 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
9343 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
9344 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
9345 return;
9346 }
9347 m68ki_exception_illegal();
9348 }
9349
9350
9351 M68KMAKE_OP(rtr, 32, ., .)
9352 {
9353 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9354 m68ki_set_ccr(m68ki_pull_16());
9355 m68ki_jump(m68ki_pull_32());
9356 }
9357
9358
9359 M68KMAKE_OP(rts, 32, ., .)
9360 {
9361 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9362 m68ki_jump(m68ki_pull_32());
9363 }
9364
9365
9366 M68KMAKE_OP(sbcd, 8, rr, .)
9367 {
9368 uint* r_dst = &DX;
9369 uint src = DY;
9370 uint dst = *r_dst;
9371 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9372 uint corf = 0;
9373
9374 if(res > 0xf)
9375 corf = 6;
9376 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9377 FLAG_V = res; /* Undefined V behavior */
9378 if(res > 0xff)
9379 {
9380 res += 0xa0;
9381 FLAG_X = FLAG_C = CFLAG_SET;
9382 }
9383 else if(res < corf)
9384 FLAG_X = FLAG_C = CFLAG_SET;
9385 else
9386 FLAG_X = FLAG_C = 0;
9387
9388 res = MASK_OUT_ABOVE_8(res - corf);
9389
9390 FLAG_V &= ~res; /* Undefined V behavior part II */
9391 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9392 FLAG_Z |= res;
9393
9394 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9395 }
9396
9397
9398 M68KMAKE_OP(sbcd, 8, mm, ax7)
9399 {
9400 uint src = OPER_AY_PD_8();
9401 uint ea = EA_A7_PD_8();
9402 uint dst = m68ki_read_8(ea);
9403 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9404 uint corf = 0;
9405
9406 if(res > 0xf)
9407 corf = 6;
9408 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9409 FLAG_V = res; /* Undefined V behavior */
9410 if(res > 0xff)
9411 {
9412 res += 0xa0;
9413 FLAG_X = FLAG_C = CFLAG_SET;
9414 }
9415 else if(res < corf)
9416 FLAG_X = FLAG_C = CFLAG_SET;
9417 else
9418 FLAG_X = FLAG_C = 0;
9419
9420 res = MASK_OUT_ABOVE_8(res - corf);
9421
9422 FLAG_V &= ~res; /* Undefined V behavior part II */
9423 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9424 FLAG_Z |= res;
9425
9426 m68ki_write_8(ea, res);
9427 }
9428
9429
9430 M68KMAKE_OP(sbcd, 8, mm, ay7)
9431 {
9432 uint src = OPER_A7_PD_8();
9433 uint ea = EA_AX_PD_8();
9434 uint dst = m68ki_read_8(ea);
9435 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9436 uint corf = 0;
9437
9438 if(res > 0xf)
9439 corf = 6;
9440 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9441 FLAG_V = res; /* Undefined V behavior */
9442 if(res > 0xff)
9443 {
9444 res += 0xa0;
9445 FLAG_X = FLAG_C = CFLAG_SET;
9446 }
9447 else if(res < corf)
9448 FLAG_X = FLAG_C = CFLAG_SET;
9449 else
9450 FLAG_X = FLAG_C = 0;
9451
9452 res = MASK_OUT_ABOVE_8(res - corf);
9453
9454 FLAG_V &= ~res; /* Undefined V behavior part II */
9455 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9456 FLAG_Z |= res;
9457
9458 m68ki_write_8(ea, res);
9459 }
9460
9461
9462 M68KMAKE_OP(sbcd, 8, mm, axy7)
9463 {
9464 uint src = OPER_A7_PD_8();
9465 uint ea = EA_A7_PD_8();
9466 uint dst = m68ki_read_8(ea);
9467 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9468 uint corf = 0;
9469
9470 if(res > 0xf)
9471 corf = 6;
9472 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9473 FLAG_V = res; /* Undefined V behavior */
9474 if(res > 0xff)
9475 {
9476 res += 0xa0;
9477 FLAG_X = FLAG_C = CFLAG_SET;
9478 }
9479 else if(res < corf)
9480 FLAG_X = FLAG_C = CFLAG_SET;
9481 else
9482 FLAG_X = FLAG_C = 0;
9483
9484 res = MASK_OUT_ABOVE_8(res - corf);
9485
9486 FLAG_V &= ~res; /* Undefined V behavior part II */
9487 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9488 FLAG_Z |= res;
9489
9490 m68ki_write_8(ea, res);
9491 }
9492
9493
9494 M68KMAKE_OP(sbcd, 8, mm, .)
9495 {
9496 uint src = OPER_AY_PD_8();
9497 uint ea = EA_AX_PD_8();
9498 uint dst = m68ki_read_8(ea);
9499 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
9500 uint corf = 0;
9501
9502 if(res > 0xf)
9503 corf = 6;
9504 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
9505 FLAG_V = res; /* Undefined V behavior */
9506 if(res > 0xff)
9507 {
9508 res += 0xa0;
9509 FLAG_X = FLAG_C = CFLAG_SET;
9510 }
9511 else if(res < corf)
9512 FLAG_X = FLAG_C = CFLAG_SET;
9513 else
9514 FLAG_X = FLAG_C = 0;
9515
9516 res = MASK_OUT_ABOVE_8(res - corf);
9517
9518 FLAG_V &= ~res; /* Undefined V behavior part II */
9519 FLAG_N = NFLAG_8(res); /* Undefined N behavior */
9520 FLAG_Z |= res;
9521
9522 m68ki_write_8(ea, res);
9523 }
9524
9525
9526 M68KMAKE_OP(st, 8, ., d)
9527 {
9528 DY |= 0xff;
9529 }
9530
9531
9532 M68KMAKE_OP(st, 8, ., .)
9533 {
9534 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
9535 }
9536
9537
9538 M68KMAKE_OP(sf, 8, ., d)
9539 {
9540 DY &= 0xffffff00;
9541 }
9542
9543
9544 M68KMAKE_OP(sf, 8, ., .)
9545 {
9546 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
9547 }
9548
9549
9550 M68KMAKE_OP(scc, 8, ., d)
9551 {
9552 if(M68KMAKE_CC)
9553 {
9554 DY |= 0xff;
9555 USE_CYCLES(CYC_SCC_R_TRUE);
9556 return;
9557 }
9558 DY &= 0xffffff00;
9559 }
9560
9561
9562 M68KMAKE_OP(scc, 8, ., .)
9563 {
9564 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
9565 }
9566
9567
9568 M68KMAKE_OP(stop, 0, ., .)
9569 {
9570 if(FLAG_S)
9571 {
9572 uint new_sr = OPER_I_16();
9573 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
9574 CPU_STOPPED |= STOP_LEVEL_STOP;
9575 m68ki_set_sr(new_sr);
9576 m68ki_remaining_cycles = 0;
9577 return;
9578 }
9579 m68ki_exception_privilege_violation();
9580 }
9581
9582
9583 M68KMAKE_OP(sub, 8, er, d)
9584 {
9585 uint* r_dst = &DX;
9586 uint src = MASK_OUT_ABOVE_8(DY);
9587 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9588 uint res = dst - src;
9589
9590 FLAG_N = NFLAG_8(res);
9591 FLAG_X = FLAG_C = CFLAG_8(res);
9592 FLAG_V = VFLAG_SUB_8(src, dst, res);
9593 FLAG_Z = MASK_OUT_ABOVE_8(res);
9594
9595 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9596 }
9597
9598
9599 M68KMAKE_OP(sub, 8, er, .)
9600 {
9601 uint* r_dst = &DX;
9602 uint src = M68KMAKE_GET_OPER_AY_8;
9603 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9604 uint res = dst - src;
9605
9606 FLAG_N = NFLAG_8(res);
9607 FLAG_X = FLAG_C = CFLAG_8(res);
9608 FLAG_V = VFLAG_SUB_8(src, dst, res);
9609 FLAG_Z = MASK_OUT_ABOVE_8(res);
9610
9611 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9612 }
9613
9614
9615 M68KMAKE_OP(sub, 16, er, d)
9616 {
9617 uint* r_dst = &DX;
9618 uint src = MASK_OUT_ABOVE_16(DY);
9619 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9620 uint res = dst - src;
9621
9622 FLAG_N = NFLAG_16(res);
9623 FLAG_X = FLAG_C = CFLAG_16(res);
9624 FLAG_V = VFLAG_SUB_16(src, dst, res);
9625 FLAG_Z = MASK_OUT_ABOVE_16(res);
9626
9627 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9628 }
9629
9630
9631 M68KMAKE_OP(sub, 16, er, a)
9632 {
9633 uint* r_dst = &DX;
9634 uint src = MASK_OUT_ABOVE_16(AY);
9635 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9636 uint res = dst - src;
9637
9638 FLAG_N = NFLAG_16(res);
9639 FLAG_X = FLAG_C = CFLAG_16(res);
9640 FLAG_V = VFLAG_SUB_16(src, dst, res);
9641 FLAG_Z = MASK_OUT_ABOVE_16(res);
9642
9643 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9644 }
9645
9646
9647 M68KMAKE_OP(sub, 16, er, .)
9648 {
9649 uint* r_dst = &DX;
9650 uint src = M68KMAKE_GET_OPER_AY_16;
9651 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9652 uint res = dst - src;
9653
9654 FLAG_N = NFLAG_16(res);
9655 FLAG_X = FLAG_C = CFLAG_16(res);
9656 FLAG_V = VFLAG_SUB_16(src, dst, res);
9657 FLAG_Z = MASK_OUT_ABOVE_16(res);
9658
9659 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9660 }
9661
9662
9663 M68KMAKE_OP(sub, 32, er, d)
9664 {
9665 uint* r_dst = &DX;
9666 uint src = DY;
9667 uint dst = *r_dst;
9668 uint res = dst - src;
9669
9670 FLAG_N = NFLAG_32(res);
9671 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9672 FLAG_V = VFLAG_SUB_32(src, dst, res);
9673 FLAG_Z = MASK_OUT_ABOVE_32(res);
9674
9675 *r_dst = FLAG_Z;
9676 }
9677
9678
9679 M68KMAKE_OP(sub, 32, er, a)
9680 {
9681 uint* r_dst = &DX;
9682 uint src = AY;
9683 uint dst = *r_dst;
9684 uint res = dst - src;
9685
9686 FLAG_N = NFLAG_32(res);
9687 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9688 FLAG_V = VFLAG_SUB_32(src, dst, res);
9689 FLAG_Z = MASK_OUT_ABOVE_32(res);
9690
9691 *r_dst = FLAG_Z;
9692 }
9693
9694
9695 M68KMAKE_OP(sub, 32, er, .)
9696 {
9697 uint* r_dst = &DX;
9698 uint src = M68KMAKE_GET_OPER_AY_32;
9699 uint dst = *r_dst;
9700 uint res = dst - src;
9701
9702 FLAG_N = NFLAG_32(res);
9703 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9704 FLAG_V = VFLAG_SUB_32(src, dst, res);
9705 FLAG_Z = MASK_OUT_ABOVE_32(res);
9706
9707 *r_dst = FLAG_Z;
9708 }
9709
9710
9711 M68KMAKE_OP(sub, 8, re, .)
9712 {
9713 uint ea = M68KMAKE_GET_EA_AY_8;
9714 uint src = MASK_OUT_ABOVE_8(DX);
9715 uint dst = m68ki_read_8(ea);
9716 uint res = dst - src;
9717
9718 FLAG_N = NFLAG_8(res);
9719 FLAG_Z = MASK_OUT_ABOVE_8(res);
9720 FLAG_X = FLAG_C = CFLAG_8(res);
9721 FLAG_V = VFLAG_SUB_8(src, dst, res);
9722
9723 m68ki_write_8(ea, FLAG_Z);
9724 }
9725
9726
9727 M68KMAKE_OP(sub, 16, re, .)
9728 {
9729 uint ea = M68KMAKE_GET_EA_AY_16;
9730 uint src = MASK_OUT_ABOVE_16(DX);
9731 uint dst = m68ki_read_16(ea);
9732 uint res = dst - src;
9733
9734 FLAG_N = NFLAG_16(res);
9735 FLAG_Z = MASK_OUT_ABOVE_16(res);
9736 FLAG_X = FLAG_C = CFLAG_16(res);
9737 FLAG_V = VFLAG_SUB_16(src, dst, res);
9738
9739 m68ki_write_16(ea, FLAG_Z);
9740 }
9741
9742
9743 M68KMAKE_OP(sub, 32, re, .)
9744 {
9745 uint ea = M68KMAKE_GET_EA_AY_32;
9746 uint src = DX;
9747 uint dst = m68ki_read_32(ea);
9748 uint res = dst - src;
9749
9750 FLAG_N = NFLAG_32(res);
9751 FLAG_Z = MASK_OUT_ABOVE_32(res);
9752 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9753 FLAG_V = VFLAG_SUB_32(src, dst, res);
9754
9755 m68ki_write_32(ea, FLAG_Z);
9756 }
9757
9758
9759 M68KMAKE_OP(suba, 16, ., d)
9760 {
9761 uint* r_dst = &AX;
9762
9763 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
9764 }
9765
9766
9767 M68KMAKE_OP(suba, 16, ., a)
9768 {
9769 uint* r_dst = &AX;
9770
9771 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
9772 }
9773
9774
9775 M68KMAKE_OP(suba, 16, ., .)
9776 {
9777 uint* r_dst = &AX;
9778 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
9779
9780 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9781 }
9782
9783
9784 M68KMAKE_OP(suba, 32, ., d)
9785 {
9786 uint* r_dst = &AX;
9787
9788 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
9789 }
9790
9791
9792 M68KMAKE_OP(suba, 32, ., a)
9793 {
9794 uint* r_dst = &AX;
9795
9796 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
9797 }
9798
9799
9800 M68KMAKE_OP(suba, 32, ., .)
9801 {
9802 uint* r_dst = &AX;
9803 uint src = M68KMAKE_GET_OPER_AY_32; // notaz
9804
9805 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);
9806 }
9807
9808
9809 M68KMAKE_OP(subi, 8, ., d)
9810 {
9811 uint* r_dst = &DY;
9812 uint src = OPER_I_8();
9813 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9814 uint res = dst - src;
9815
9816 FLAG_N = NFLAG_8(res);
9817 FLAG_Z = MASK_OUT_ABOVE_8(res);
9818 FLAG_X = FLAG_C = CFLAG_8(res);
9819 FLAG_V = VFLAG_SUB_8(src, dst, res);
9820
9821 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9822 }
9823
9824
9825 M68KMAKE_OP(subi, 8, ., .)
9826 {
9827 uint src = OPER_I_8();
9828 uint ea = M68KMAKE_GET_EA_AY_8;
9829 uint dst = m68ki_read_8(ea);
9830 uint res = dst - src;
9831
9832 FLAG_N = NFLAG_8(res);
9833 FLAG_Z = MASK_OUT_ABOVE_8(res);
9834 FLAG_X = FLAG_C = CFLAG_8(res);
9835 FLAG_V = VFLAG_SUB_8(src, dst, res);
9836
9837 m68ki_write_8(ea, FLAG_Z);
9838 }
9839
9840
9841 M68KMAKE_OP(subi, 16, ., d)
9842 {
9843 uint* r_dst = &DY;
9844 uint src = OPER_I_16();
9845 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9846 uint res = dst - src;
9847
9848 FLAG_N = NFLAG_16(res);
9849 FLAG_Z = MASK_OUT_ABOVE_16(res);
9850 FLAG_X = FLAG_C = CFLAG_16(res);
9851 FLAG_V = VFLAG_SUB_16(src, dst, res);
9852
9853 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9854 }
9855
9856
9857 M68KMAKE_OP(subi, 16, ., .)
9858 {
9859 uint src = OPER_I_16();
9860 uint ea = M68KMAKE_GET_EA_AY_16;
9861 uint dst = m68ki_read_16(ea);
9862 uint res = dst - src;
9863
9864 FLAG_N = NFLAG_16(res);
9865 FLAG_Z = MASK_OUT_ABOVE_16(res);
9866 FLAG_X = FLAG_C = CFLAG_16(res);
9867 FLAG_V = VFLAG_SUB_16(src, dst, res);
9868
9869 m68ki_write_16(ea, FLAG_Z);
9870 }
9871
9872
9873 M68KMAKE_OP(subi, 32, ., d)
9874 {
9875 uint* r_dst = &DY;
9876 uint src = OPER_I_32();
9877 uint dst = *r_dst;
9878 uint res = dst - src;
9879
9880 FLAG_N = NFLAG_32(res);
9881 FLAG_Z = MASK_OUT_ABOVE_32(res);
9882 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9883 FLAG_V = VFLAG_SUB_32(src, dst, res);
9884
9885 *r_dst = FLAG_Z;
9886 }
9887
9888
9889 M68KMAKE_OP(subi, 32, ., .)
9890 {
9891 uint src = OPER_I_32();
9892 uint ea = M68KMAKE_GET_EA_AY_32;
9893 uint dst = m68ki_read_32(ea);
9894 uint res = dst - src;
9895
9896 FLAG_N = NFLAG_32(res);
9897 FLAG_Z = MASK_OUT_ABOVE_32(res);
9898 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9899 FLAG_V = VFLAG_SUB_32(src, dst, res);
9900
9901 m68ki_write_32(ea, FLAG_Z);
9902 }
9903
9904
9905 M68KMAKE_OP(subq, 8, ., d)
9906 {
9907 uint* r_dst = &DY;
9908 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9909 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9910 uint res = dst - src;
9911
9912 FLAG_N = NFLAG_8(res);
9913 FLAG_Z = MASK_OUT_ABOVE_8(res);
9914 FLAG_X = FLAG_C = CFLAG_8(res);
9915 FLAG_V = VFLAG_SUB_8(src, dst, res);
9916
9917 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9918 }
9919
9920
9921 M68KMAKE_OP(subq, 8, ., .)
9922 {
9923 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9924 uint ea = M68KMAKE_GET_EA_AY_8;
9925 uint dst = m68ki_read_8(ea);
9926 uint res = dst - src;
9927
9928 FLAG_N = NFLAG_8(res);
9929 FLAG_Z = MASK_OUT_ABOVE_8(res);
9930 FLAG_X = FLAG_C = CFLAG_8(res);
9931 FLAG_V = VFLAG_SUB_8(src, dst, res);
9932
9933 m68ki_write_8(ea, FLAG_Z);
9934 }
9935
9936
9937 M68KMAKE_OP(subq, 16, ., d)
9938 {
9939 uint* r_dst = &DY;
9940 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9941 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9942 uint res = dst - src;
9943
9944 FLAG_N = NFLAG_16(res);
9945 FLAG_Z = MASK_OUT_ABOVE_16(res);
9946 FLAG_X = FLAG_C = CFLAG_16(res);
9947 FLAG_V = VFLAG_SUB_16(src, dst, res);
9948
9949 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9950 }
9951
9952
9953 M68KMAKE_OP(subq, 16, ., a)
9954 {
9955 uint* r_dst = &AY;
9956
9957 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9958 }
9959
9960
9961 M68KMAKE_OP(subq, 16, ., .)
9962 {
9963 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9964 uint ea = M68KMAKE_GET_EA_AY_16;
9965 uint dst = m68ki_read_16(ea);
9966 uint res = dst - src;
9967
9968 FLAG_N = NFLAG_16(res);
9969 FLAG_Z = MASK_OUT_ABOVE_16(res);
9970 FLAG_X = FLAG_C = CFLAG_16(res);
9971 FLAG_V = VFLAG_SUB_16(src, dst, res);
9972
9973 m68ki_write_16(ea, FLAG_Z);
9974 }
9975
9976
9977 M68KMAKE_OP(subq, 32, ., d)
9978 {
9979 uint* r_dst = &DY;
9980 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9981 uint dst = *r_dst;
9982 uint res = dst - src;
9983
9984 FLAG_N = NFLAG_32(res);
9985 FLAG_Z = MASK_OUT_ABOVE_32(res);
9986 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9987 FLAG_V = VFLAG_SUB_32(src, dst, res);
9988
9989 *r_dst = FLAG_Z;
9990 }
9991
9992
9993 M68KMAKE_OP(subq, 32, ., a)
9994 {
9995 uint* r_dst = &AY;
9996
9997 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9998 }
9999
10000
10001 M68KMAKE_OP(subq, 32, ., .)
10002 {
10003 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
10004 uint ea = M68KMAKE_GET_EA_AY_32;
10005 uint dst = m68ki_read_32(ea);
10006 uint res = dst - src;
10007
10008 FLAG_N = NFLAG_32(res);
10009 FLAG_Z = MASK_OUT_ABOVE_32(res);
10010 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10011 FLAG_V = VFLAG_SUB_32(src, dst, res);
10012
10013 m68ki_write_32(ea, FLAG_Z);
10014 }
10015
10016
10017 M68KMAKE_OP(subx, 8, rr, .)
10018 {
10019 uint* r_dst = &DX;
10020 uint src = MASK_OUT_ABOVE_8(DY);
10021 uint dst = MASK_OUT_ABOVE_8(*r_dst);
10022 uint res = dst - src - XFLAG_AS_1();
10023
10024 FLAG_N = NFLAG_8(res);
10025 FLAG_X = FLAG_C = CFLAG_8(res);
10026 FLAG_V = VFLAG_SUB_8(src, dst, res);
10027
10028 res = MASK_OUT_ABOVE_8(res);
10029 FLAG_Z |= res;
10030
10031 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
10032 }
10033
10034
10035 M68KMAKE_OP(subx, 16, rr, .)
10036 {
10037 uint* r_dst = &DX;
10038 uint src = MASK_OUT_ABOVE_16(DY);
10039 uint dst = MASK_OUT_ABOVE_16(*r_dst);
10040 uint res = dst - src - XFLAG_AS_1();
10041
10042 FLAG_N = NFLAG_16(res);
10043 FLAG_X = FLAG_C = CFLAG_16(res);
10044 FLAG_V = VFLAG_SUB_16(src, dst, res);
10045
10046 res = MASK_OUT_ABOVE_16(res);
10047 FLAG_Z |= res;
10048
10049 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
10050 }
10051
10052
10053 M68KMAKE_OP(subx, 32, rr, .)
10054 {
10055 uint* r_dst = &DX;
10056 uint src = DY;
10057 uint dst = *r_dst;
10058 uint res = dst - src - XFLAG_AS_1();
10059
10060 FLAG_N = NFLAG_32(res);
10061 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10062 FLAG_V = VFLAG_SUB_32(src, dst, res);
10063
10064 res = MASK_OUT_ABOVE_32(res);
10065 FLAG_Z |= res;
10066
10067 *r_dst = res;
10068 }
10069
10070
10071 M68KMAKE_OP(subx, 8, mm, ax7)
10072 {
10073 uint src = OPER_AY_PD_8();
10074 uint ea = EA_A7_PD_8();
10075 uint dst = m68ki_read_8(ea);
10076 uint res = dst - src - XFLAG_AS_1();
10077
10078 FLAG_N = NFLAG_8(res);
10079 FLAG_X = FLAG_C = CFLAG_8(res);
10080 FLAG_V = VFLAG_SUB_8(src, dst, res);
10081
10082 res = MASK_OUT_ABOVE_8(res);
10083 FLAG_Z |= res;
10084
10085 m68ki_write_8(ea, res);
10086 }
10087
10088
10089 M68KMAKE_OP(subx, 8, mm, ay7)
10090 {
10091 uint src = OPER_A7_PD_8();
10092 uint ea = EA_AX_PD_8();
10093 uint dst = m68ki_read_8(ea);
10094 uint res = dst - src - XFLAG_AS_1();
10095
10096 FLAG_N = NFLAG_8(res);
10097 FLAG_X = FLAG_C = CFLAG_8(res);
10098 FLAG_V = VFLAG_SUB_8(src, dst, res);
10099
10100 res = MASK_OUT_ABOVE_8(res);
10101 FLAG_Z |= res;
10102
10103 m68ki_write_8(ea, res);
10104 }
10105
10106
10107 M68KMAKE_OP(subx, 8, mm, axy7)
10108 {
10109 uint src = OPER_A7_PD_8();
10110 uint ea = EA_A7_PD_8();
10111 uint dst = m68ki_read_8(ea);
10112 uint res = dst - src - XFLAG_AS_1();
10113
10114 FLAG_N = NFLAG_8(res);
10115 FLAG_X = FLAG_C = CFLAG_8(res);
10116 FLAG_V = VFLAG_SUB_8(src, dst, res);
10117
10118 res = MASK_OUT_ABOVE_8(res);
10119 FLAG_Z |= res;
10120
10121 m68ki_write_8(ea, res);
10122 }
10123
10124
10125 M68KMAKE_OP(subx, 8, mm, .)
10126 {
10127 uint src = OPER_AY_PD_8();
10128 uint ea = EA_AX_PD_8();
10129 uint dst = m68ki_read_8(ea);
10130 uint res = dst - src - XFLAG_AS_1();
10131
10132 FLAG_N = NFLAG_8(res);
10133 FLAG_X = FLAG_C = CFLAG_8(res);
10134 FLAG_V = VFLAG_SUB_8(src, dst, res);
10135
10136 res = MASK_OUT_ABOVE_8(res);
10137 FLAG_Z |= res;
10138
10139 m68ki_write_8(ea, res);
10140 }
10141
10142
10143 M68KMAKE_OP(subx, 16, mm, .)
10144 {
10145 uint src = OPER_AY_PD_16();
10146 uint ea = EA_AX_PD_16();
10147 uint dst = m68ki_read_16(ea);
10148 uint res = dst - src - XFLAG_AS_1();
10149
10150 FLAG_N = NFLAG_16(res);
10151 FLAG_X = FLAG_C = CFLAG_16(res);
10152 FLAG_V = VFLAG_SUB_16(src, dst, res);
10153
10154 res = MASK_OUT_ABOVE_16(res);
10155 FLAG_Z |= res;
10156
10157 m68ki_write_16(ea, res);
10158 }
10159
10160
10161 M68KMAKE_OP(subx, 32, mm, .)
10162 {
10163 uint src = OPER_AY_PD_32();
10164 uint ea = EA_AX_PD_32();
10165 uint dst = m68ki_read_32(ea);
10166 uint res = dst - src - XFLAG_AS_1();
10167
10168 FLAG_N = NFLAG_32(res);
10169 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
10170 FLAG_V = VFLAG_SUB_32(src, dst, res);
10171
10172 res = MASK_OUT_ABOVE_32(res);
10173 FLAG_Z |= res;
10174
10175 m68ki_write_32(ea, res);
10176 }
10177
10178
10179 M68KMAKE_OP(swap, 32, ., .)
10180 {
10181 uint* r_dst = &DY;
10182
10183 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
10184 *r_dst = (*r_dst>>16) | FLAG_Z;
10185
10186 FLAG_Z = *r_dst;
10187 FLAG_N = NFLAG_32(*r_dst);
10188 FLAG_C = CFLAG_CLEAR;
10189 FLAG_V = VFLAG_CLEAR;
10190 }
10191
10192
10193 M68KMAKE_OP(tas, 8, ., d)
10194 {
10195 uint* r_dst = &DY;
10196
10197 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
10198 FLAG_N = NFLAG_8(*r_dst);
10199 FLAG_V = VFLAG_CLEAR;
10200 FLAG_C = CFLAG_CLEAR;
10201 *r_dst |= 0x80;
10202 }
10203
10204
10205 M68KMAKE_OP(tas, 8, ., .)
10206 {
10207 uint ea = M68KMAKE_GET_EA_AY_8;
10208 uint dst = m68ki_read_8(ea);
10209 uint allow_writeback;
10210
10211 FLAG_Z = dst;
10212 FLAG_N = NFLAG_8(dst);
10213 FLAG_V = VFLAG_CLEAR;
10214 FLAG_C = CFLAG_CLEAR;
10215
10216 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback
10217 disabled in order to function properly. Some Amiga software may also rely
10218 on this, but only when accessing specific addresses so additional functionality
10219 will be needed. */
10220 allow_writeback = m68ki_tas_callback();
10221
10222 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);
10223 }
10224
10225
10226 M68KMAKE_OP(trap, 0, ., .)
10227 {
10228 /* Trap#n stacks exception frame type 0 */
10229 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
10230 }
10231
10232
10233 M68KMAKE_OP(trapt, 0, ., .)
10234 {
10235 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10236 {
10237 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10238 return;
10239 }
10240 m68ki_exception_illegal();
10241 }
10242
10243
10244 M68KMAKE_OP(trapt, 16, ., .)
10245 {
10246 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10247 {
10248 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10249 return;
10250 }
10251 m68ki_exception_illegal();
10252 }
10253
10254
10255 M68KMAKE_OP(trapt, 32, ., .)
10256 {
10257 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10258 {
10259 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10260 return;
10261 }
10262 m68ki_exception_illegal();
10263 }
10264
10265
10266 M68KMAKE_OP(trapf, 0, ., .)
10267 {
10268 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10269 {
10270 return;
10271 }
10272 m68ki_exception_illegal();
10273 }
10274
10275
10276 M68KMAKE_OP(trapf, 16, ., .)
10277 {
10278 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10279 {
10280 REG_PC += 2;
10281 return;
10282 }
10283 m68ki_exception_illegal();
10284 }
10285
10286
10287 M68KMAKE_OP(trapf, 32, ., .)
10288 {
10289 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10290 {
10291 REG_PC += 4;
10292 return;
10293 }
10294 m68ki_exception_illegal();
10295 }
10296
10297
10298 M68KMAKE_OP(trapcc, 0, ., .)
10299 {
10300 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10301 {
10302 if(M68KMAKE_CC)
10303 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10304 return;
10305 }
10306 m68ki_exception_illegal();
10307 }
10308
10309
10310 M68KMAKE_OP(trapcc, 16, ., .)
10311 {
10312 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10313 {
10314 if(M68KMAKE_CC)
10315 {
10316 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10317 return;
10318 }
10319 REG_PC += 2;
10320 return;
10321 }
10322 m68ki_exception_illegal();
10323 }
10324
10325
10326 M68KMAKE_OP(trapcc, 32, ., .)
10327 {
10328 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10329 {
10330 if(M68KMAKE_CC)
10331 {
10332 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10333 return;
10334 }
10335 REG_PC += 4;
10336 return;
10337 }
10338 m68ki_exception_illegal();
10339 }
10340
10341
10342 M68KMAKE_OP(trapv, 0, ., .)
10343 {
10344 if(COND_VC())
10345 {
10346 return;
10347 }
10348 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
10349 }
10350
10351
10352 M68KMAKE_OP(tst, 8, ., d)
10353 {
10354 uint res = MASK_OUT_ABOVE_8(DY);
10355
10356 FLAG_N = NFLAG_8(res);
10357 FLAG_Z = res;
10358 FLAG_V = VFLAG_CLEAR;
10359 FLAG_C = CFLAG_CLEAR;
10360 }
10361
10362
10363 M68KMAKE_OP(tst, 8, ., .)
10364 {
10365 uint res = M68KMAKE_GET_OPER_AY_8;
10366
10367 FLAG_N = NFLAG_8(res);
10368 FLAG_Z = res;
10369 FLAG_V = VFLAG_CLEAR;
10370 FLAG_C = CFLAG_CLEAR;
10371 }
10372
10373
10374 M68KMAKE_OP(tst, 8, ., pcdi)
10375 {
10376 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10377 {
10378 uint res = OPER_PCDI_8();
10379
10380 FLAG_N = NFLAG_8(res);
10381 FLAG_Z = res;
10382 FLAG_V = VFLAG_CLEAR;
10383 FLAG_C = CFLAG_CLEAR;
10384 return;
10385 }
10386 m68ki_exception_illegal();
10387 }
10388
10389
10390 M68KMAKE_OP(tst, 8, ., pcix)
10391 {
10392 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10393 {
10394 uint res = OPER_PCIX_8();
10395
10396 FLAG_N = NFLAG_8(res);
10397 FLAG_Z = res;
10398 FLAG_V = VFLAG_CLEAR;
10399 FLAG_C = CFLAG_CLEAR;
10400 return;
10401 }
10402 m68ki_exception_illegal();
10403 }
10404
10405
10406 M68KMAKE_OP(tst, 8, ., i)
10407 {
10408 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10409 {
10410 uint res = OPER_I_8();
10411
10412 FLAG_N = NFLAG_8(res);
10413 FLAG_Z = res;
10414 FLAG_V = VFLAG_CLEAR;
10415 FLAG_C = CFLAG_CLEAR;
10416 return;
10417 }
10418 m68ki_exception_illegal();
10419 }
10420
10421
10422 M68KMAKE_OP(tst, 16, ., d)
10423 {
10424 uint res = MASK_OUT_ABOVE_16(DY);
10425
10426 FLAG_N = NFLAG_16(res);
10427 FLAG_Z = res;
10428 FLAG_V = VFLAG_CLEAR;
10429 FLAG_C = CFLAG_CLEAR;
10430 }
10431
10432
10433 M68KMAKE_OP(tst, 16, ., a)
10434 {
10435 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10436 {
10437 uint res = MAKE_INT_16(AY);
10438
10439 FLAG_N = NFLAG_16(res);
10440 FLAG_Z = res;
10441 FLAG_V = VFLAG_CLEAR;
10442 FLAG_C = CFLAG_CLEAR;
10443 return;
10444 }
10445 m68ki_exception_illegal();
10446 }
10447
10448
10449 M68KMAKE_OP(tst, 16, ., .)
10450 {
10451 uint res = M68KMAKE_GET_OPER_AY_16;
10452
10453 FLAG_N = NFLAG_16(res);
10454 FLAG_Z = res;
10455 FLAG_V = VFLAG_CLEAR;
10456 FLAG_C = CFLAG_CLEAR;
10457 }
10458
10459
10460 M68KMAKE_OP(tst, 16, ., pcdi)
10461 {
10462 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10463 {
10464 uint res = OPER_PCDI_16();
10465
10466 FLAG_N = NFLAG_16(res);
10467 FLAG_Z = res;
10468 FLAG_V = VFLAG_CLEAR;
10469 FLAG_C = CFLAG_CLEAR;
10470 return;
10471 }
10472 m68ki_exception_illegal();
10473 }
10474
10475
10476 M68KMAKE_OP(tst, 16, ., pcix)
10477 {
10478 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10479 {
10480 uint res = OPER_PCIX_16();
10481
10482 FLAG_N = NFLAG_16(res);
10483 FLAG_Z = res;
10484 FLAG_V = VFLAG_CLEAR;
10485 FLAG_C = CFLAG_CLEAR;
10486 return;
10487 }
10488 m68ki_exception_illegal();
10489 }
10490
10491
10492 M68KMAKE_OP(tst, 16, ., i)
10493 {
10494 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10495 {
10496 uint res = OPER_I_16();
10497
10498 FLAG_N = NFLAG_16(res);
10499 FLAG_Z = res;
10500 FLAG_V = VFLAG_CLEAR;
10501 FLAG_C = CFLAG_CLEAR;
10502 return;
10503 }
10504 m68ki_exception_illegal();
10505 }
10506
10507
10508 M68KMAKE_OP(tst, 32, ., d)
10509 {
10510 uint res = DY;
10511
10512 FLAG_N = NFLAG_32(res);
10513 FLAG_Z = res;
10514 FLAG_V = VFLAG_CLEAR;
10515 FLAG_C = CFLAG_CLEAR;
10516 }
10517
10518
10519 M68KMAKE_OP(tst, 32, ., a)
10520 {
10521 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10522 {
10523 uint res = AY;
10524
10525 FLAG_N = NFLAG_32(res);
10526 FLAG_Z = res;
10527 FLAG_V = VFLAG_CLEAR;
10528 FLAG_C = CFLAG_CLEAR;
10529 return;
10530 }
10531 m68ki_exception_illegal();
10532 }
10533
10534
10535 M68KMAKE_OP(tst, 32, ., .)
10536 {
10537 uint res = M68KMAKE_GET_OPER_AY_32;
10538
10539 FLAG_N = NFLAG_32(res);
10540 FLAG_Z = res;
10541 FLAG_V = VFLAG_CLEAR;
10542 FLAG_C = CFLAG_CLEAR;
10543 }
10544
10545
10546 M68KMAKE_OP(tst, 32, ., pcdi)
10547 {
10548 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10549 {
10550 uint res = OPER_PCDI_32();
10551
10552 FLAG_N = NFLAG_32(res);
10553 FLAG_Z = res;
10554 FLAG_V = VFLAG_CLEAR;
10555 FLAG_C = CFLAG_CLEAR;
10556 return;
10557 }
10558 m68ki_exception_illegal();
10559 }
10560
10561
10562 M68KMAKE_OP(tst, 32, ., pcix)
10563 {
10564 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10565 {
10566 uint res = OPER_PCIX_32();
10567
10568 FLAG_N = NFLAG_32(res);
10569 FLAG_Z = res;
10570 FLAG_V = VFLAG_CLEAR;
10571 FLAG_C = CFLAG_CLEAR;
10572 return;
10573 }
10574 m68ki_exception_illegal();
10575 }
10576
10577
10578 M68KMAKE_OP(tst, 32, ., i)
10579 {
10580 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10581 {
10582 uint res = OPER_I_32();
10583
10584 FLAG_N = NFLAG_32(res);
10585 FLAG_Z = res;
10586 FLAG_V = VFLAG_CLEAR;
10587 FLAG_C = CFLAG_CLEAR;
10588 return;
10589 }
10590 m68ki_exception_illegal();
10591 }
10592
10593
10594 M68KMAKE_OP(unlk, 32, ., a7)
10595 {
10596 REG_A[7] = m68ki_read_32(REG_A[7]);
10597 }
10598
10599
10600 M68KMAKE_OP(unlk, 32, ., .)
10601 {
10602 uint* r_dst = &AY;
10603
10604 REG_A[7] = *r_dst;
10605 *r_dst = m68ki_pull_32();
10606 }
10607
10608
10609 M68KMAKE_OP(unpk, 16, rr, .)
10610 {
10611 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10612 {
10613 /* Note: DX and DY are reversed in Motorola's docs */
10614 uint src = DY;
10615 uint* r_dst = &DX;
10616
10617 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
10618 return;
10619 }
10620 m68ki_exception_illegal();
10621 }
10622
10623
10624 M68KMAKE_OP(unpk, 16, mm, ax7)
10625 {
10626 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10627 {
10628 /* Note: AX and AY are reversed in Motorola's docs */
10629 uint src = OPER_AY_PD_8();
10630 uint ea_dst;
10631
10632 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10633 ea_dst = EA_A7_PD_8();
10634 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10635 ea_dst = EA_A7_PD_8();
10636 m68ki_write_8(ea_dst, src & 0xff);
10637 return;
10638 }
10639 m68ki_exception_illegal();
10640 }
10641
10642
10643 M68KMAKE_OP(unpk, 16, mm, ay7)
10644 {
10645 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10646 {
10647 /* Note: AX and AY are reversed in Motorola's docs */
10648 uint src = OPER_A7_PD_8();
10649 uint ea_dst;
10650
10651 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10652 ea_dst = EA_AX_PD_8();
10653 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10654 ea_dst = EA_AX_PD_8();
10655 m68ki_write_8(ea_dst, src & 0xff);
10656 return;
10657 }
10658 m68ki_exception_illegal();
10659 }
10660
10661
10662 M68KMAKE_OP(unpk, 16, mm, axy7)
10663 {
10664 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10665 {
10666 uint src = OPER_A7_PD_8();
10667 uint ea_dst;
10668
10669 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10670 ea_dst = EA_A7_PD_8();
10671 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10672 ea_dst = EA_A7_PD_8();
10673 m68ki_write_8(ea_dst, src & 0xff);
10674 return;
10675 }
10676 m68ki_exception_illegal();
10677 }
10678
10679
10680 M68KMAKE_OP(unpk, 16, mm, .)
10681 {
10682 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
10683 {
10684 /* Note: AX and AY are reversed in Motorola's docs */
10685 uint src = OPER_AY_PD_8();
10686 uint ea_dst;
10687
10688 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10689 ea_dst = EA_AX_PD_8();
10690 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10691 ea_dst = EA_AX_PD_8();
10692 m68ki_write_8(ea_dst, src & 0xff);
10693 return;
10694 }
10695 m68ki_exception_illegal();
10696 }
10697
10698
10699
10700 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
10701 M68KMAKE_END
10702