1 /*
2 ** This is a bunch of remains of original fm.c from MAME project. All stuff
3 ** unrelated to ym2612 was removed, multiple chip support was removed,
4 ** some parts of code were slightly rewritten and tied to the emulator.
5 **
6 ** SSG-EG was also removed, because it's rarely used, Sega2.doc even does not
7 ** document it ("proprietary") and tells to write 0 to SSG-EG control register.
8 **
9 ** updated with fixes from mame 0.216 (file version 1.5.1) (kub)
10 ** SSG-EG readded from GenPlus (kub)
11 ** linear sample interpolation for chip to output rate adaption (kub)
12 */
13
14 /*
15 **
16 ** File: fm.c -- software implementation of Yamaha FM sound generator
17 **
18 ** Copyright (C) 2001, 2002, 2003 Jarek Burczynski (bujar at mame dot net)
19 ** Copyright (C) 1998 Tatsuyuki Satoh , MultiArcadeMachineEmulator development
20 **
21 ** Version 1.4 (final beta)
22 **
23 */
24
25 /*
26 ** History:
27 **
28 ** 03-08-2003 Jarek Burczynski:
29 ** - fixed YM2608 initial values (after the reset)
30 ** - fixed flag and irqmask handling (YM2608)
31 ** - fixed BUFRDY flag handling (YM2608)
32 **
33 ** 14-06-2003 Jarek Burczynski:
34 ** - implemented all of the YM2608 status register flags
35 ** - implemented support for external memory read/write via YM2608
36 ** - implemented support for deltat memory limit register in YM2608 emulation
37 **
38 ** 22-05-2003 Jarek Burczynski:
39 ** - fixed LFO PM calculations (copy&paste bugfix)
40 **
41 ** 08-05-2003 Jarek Burczynski:
42 ** - fixed SSG support
43 **
44 ** 22-04-2003 Jarek Burczynski:
45 ** - implemented 100% correct LFO generator (verified on real YM2610 and YM2608)
46 **
47 ** 15-04-2003 Jarek Burczynski:
48 ** - added support for YM2608's register 0x110 - status mask
49 **
50 ** 01-12-2002 Jarek Burczynski:
51 ** - fixed register addressing in YM2608, YM2610, YM2610B chips. (verified on real YM2608)
52 ** The addressing patch used for early Neo-Geo games can be removed now.
53 **
54 ** 26-11-2002 Jarek Burczynski, Nicola Salmoria:
55 ** - recreated YM2608 ADPCM ROM using data from real YM2608's output which leads to:
56 ** - added emulation of YM2608 drums.
57 ** - output of YM2608 is two times lower now - same as YM2610 (verified on real YM2608)
58 **
59 ** 16-08-2002 Jarek Burczynski:
60 ** - binary exact Envelope Generator (verified on real YM2203);
61 ** identical to YM2151
62 ** - corrected 'off by one' error in feedback calculations (when feedback is off)
63 ** - corrected connection (algorithm) calculation (verified on real YM2203 and YM2610)
64 **
65 ** 18-12-2001 Jarek Burczynski:
66 ** - added SSG-EG support (verified on real YM2203)
67 **
68 ** 12-08-2001 Jarek Burczynski:
69 ** - corrected ym_sin_tab and ym_tl_tab data (verified on real chip)
70 ** - corrected feedback calculations (verified on real chip)
71 ** - corrected phase generator calculations (verified on real chip)
72 ** - corrected envelope generator calculations (verified on real chip)
73 ** - corrected FM volume level (YM2610 and YM2610B).
74 ** - changed YMxxxUpdateOne() functions (YM2203, YM2608, YM2610, YM2610B, YM2612) :
75 ** this was needed to calculate YM2610 FM channels output correctly.
76 ** (Each FM channel is calculated as in other chips, but the output of the channel
77 ** gets shifted right by one *before* sending to accumulator. That was impossible to do
78 ** with previous implementation).
79 **
80 ** 23-07-2001 Jarek Burczynski, Nicola Salmoria:
81 ** - corrected YM2610 ADPCM type A algorithm and tables (verified on real chip)
82 **
83 ** 11-06-2001 Jarek Burczynski:
84 ** - corrected end of sample bug in ADPCMA_calc_cha().
85 ** Real YM2610 checks for equality between current and end addresses (only 20 LSB bits).
86 **
87 ** 08-12-98 hiro-shi:
88 ** rename ADPCMA -> ADPCMB, ADPCMB -> ADPCMA
89 ** move ROM limit check.(CALC_CH? -> 2610Write1/2)
90 ** test program (ADPCMB_TEST)
91 ** move ADPCM A/B end check.
92 ** ADPCMB repeat flag(no check)
93 ** change ADPCM volume rate (8->16) (32->48).
94 **
95 ** 09-12-98 hiro-shi:
96 ** change ADPCM volume. (8->16, 48->64)
97 ** replace ym2610 ch0/3 (YM-2610B)
98 ** change ADPCM_SHIFT (10->8) missing bank change 0x4000-0xffff.
99 ** add ADPCM_SHIFT_MASK
100 ** change ADPCMA_DECODE_MIN/MAX.
101 */
102
103
104
105
106 /************************************************************************/
107 /* comment of hiro-shi(Hiromitsu Shioya) */
108 /* YM2610(B) = OPN-B */
109 /* YM2610 : PSG:3ch FM:4ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
110 /* YM2610B : PSG:3ch FM:6ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
111 /************************************************************************/
112
113 //#include <stdio.h>
114
115 #include <string.h>
116 #include <math.h>
117
118 #include "ym2612.h"
119
120 #ifndef EXTERNAL_YM2612
121 #include <stdlib.h>
122 // let it be 1 global to simplify things
123 YM2612 ym2612;
124
125 #else
126 extern YM2612 *ym2612_940;
127 #define ym2612 (*ym2612_940)
128
129 #endif
130
131 void memset32(void *dest, int c, int count);
132
133
134 #ifndef __GNUC__
135 #pragma warning (disable:4100) // unreferenced formal parameter
136 #pragma warning (disable:4244)
137 #pragma warning (disable:4245) // signed/unsigned in conversion
138 #pragma warning (disable:4710)
139 #pragma warning (disable:4018) // signed/unsigned
140 #endif
141
142 #ifndef INLINE
143 #define INLINE static __inline
144 #endif
145
146 #ifndef M_PI
147 #define M_PI 3.14159265358979323846
148 #endif
149
150
151 /* globals */
152
153 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
154 #define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
155 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
156 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
157
158 #define ENV_BITS 10
159 #define ENV_LEN (1<<ENV_BITS)
160 #define ENV_STEP (128.0/ENV_LEN)
161
162 #define MAX_ATT_INDEX (ENV_LEN-1) /* 1023 */
163 #define MIN_ATT_INDEX (0) /* 0 */
164
165 #define EG_ATT 4
166 #define EG_DEC 3
167 #define EG_SUS 2
168 #define EG_REL 1
169 #define EG_OFF 0
170
171 #define SIN_BITS 10
172 #define SIN_LEN (1<<SIN_BITS)
173 #define SIN_MASK (SIN_LEN-1)
174
175 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
176
177 #define EG_TIMER_OVERFLOW (3*(1<<EG_SH)) /* envelope generator timer overflows every 3 samples (on real chip) */
178
179 /* TL_TAB_LEN is calculated as:
180 * 13 - sinus amplitude bits (Y axis)
181 * 2 - sinus sign bit (Y axis)
182 * TL_RES_LEN - sinus resolution (X axis)
183 */
184 //#define TL_TAB_LEN (13*2*TL_RES_LEN)
185 #define TL_TAB_LEN (13*TL_RES_LEN*256/8) // 106496*2
186 UINT16 ym_tl_tab[TL_TAB_LEN];
187
188 /* ~3K wasted but oh well */
189 UINT16 ym_tl_tab2[13*TL_RES_LEN];
190
191 #define ENV_QUIET (2*13*TL_RES_LEN/8)
192
193 /* sin waveform table in 'decibel' scale (use only period/4 values) */
194 static UINT16 ym_sin_tab[256];
195
196 /* sustain level table (3dB per step) */
197 /* bit0, bit1, bit2, bit3, bit4, bit5, bit6 */
198 /* 1, 2, 4, 8, 16, 32, 64 (value)*/
199 /* 0.75, 1.5, 3, 6, 12, 24, 48 (dB)*/
200
201 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
202 #define SC(db) (UINT32) ( db * (4.0/ENV_STEP) )
203 static const UINT32 sl_table[16]={
204 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
205 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
206 };
207 #undef SC
208
209
210 #if 0
211 #define RATE_STEPS (8)
212 static const UINT8 eg_inc[19*RATE_STEPS]={
213
214 /*cycle:0 1 2 3 4 5 6 7*/
215
216 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..11 0 (increment by 0 or 1) */
217 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..11 1 */
218 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..11 2 */
219 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..11 3 */
220
221 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 12 0 (increment by 1) */
222 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 12 1 */
223 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 12 2 */
224 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 12 3 */
225
226 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 13 0 (increment by 2) */
227 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 13 1 */
228 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 13 2 */
229 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 13 3 */
230
231 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rate 14 0 (increment by 4) */
232 /*13 */ 4,4, 4,8, 4,4, 4,8, /* rate 14 1 */
233 /*14 */ 4,8, 4,8, 4,8, 4,8, /* rate 14 2 */
234 /*15 */ 4,8, 8,8, 4,8, 8,8, /* rate 14 3 */
235
236 /*16 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
237 /*17 */ 16,16,16,16,16,16,16,16, /* rates 15 2, 15 3 for attack */
238 /*18 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
239 };
240 #endif
241
242
243 #define PACK(a0,a1,a2,a3,a4,a5,a6,a7) ((a7<<21)|(a6<<18)|(a5<<15)|(a4<<12)|(a3<<9)|(a2<<6)|(a1<<3)|(a0<<0))
244 static const UINT32 eg_inc_pack[19] =
245 {
246 /* 0 */ PACK(0,1,0,1,0,1,0,1), /* rates 00..11 0 (increment by 0 or 1) */
247 /* 1 */ PACK(0,1,0,1,1,1,0,1), /* rates 00..11 1 */
248 /* 2 */ PACK(0,1,1,1,0,1,1,1), /* rates 00..11 2 */
249 /* 3 */ PACK(0,1,1,1,1,1,1,1), /* rates 00..11 3 */
250
251 /* 4 */ PACK(1,1,1,1,1,1,1,1), /* rate 12 0 (increment by 1) */
252 /* 5 */ PACK(1,1,1,2,1,1,1,2), /* rate 12 1 */
253 /* 6 */ PACK(1,2,1,2,1,2,1,2), /* rate 12 2 */
254 /* 7 */ PACK(1,2,2,2,1,2,2,2), /* rate 12 3 */
255
256 /* 8 */ PACK(2,2,2,2,2,2,2,2), /* rate 13 0 (increment by 2) */
257 /* 9 */ PACK(2,2,2,3,2,2,2,3), /* rate 13 1 */
258 /*10 */ PACK(2,3,2,3,2,3,2,3), /* rate 13 2 */
259 /*11 */ PACK(2,3,3,3,2,3,3,3), /* rate 13 3 */
260
261 /*12 */ PACK(3,3,3,3,3,3,3,3), /* rate 14 0 (increment by 4) */
262 /*13 */ PACK(3,3,3,4,3,3,3,4), /* rate 14 1 */
263 /*14 */ PACK(3,4,3,4,3,4,3,4), /* rate 14 2 */
264 /*15 */ PACK(3,4,4,4,3,4,4,4), /* rate 14 3 */
265
266 /*16 */ PACK(4,4,4,4,4,4,4,4), /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
267 /*17 */ PACK(5,5,5,5,5,5,5,5), /* rates 15 2, 15 3 for attack */
268 /*18 */ PACK(0,0,0,0,0,0,0,0), /* infinity rates for attack and decay(s) */
269 };
270
271
272 //#define O(a) (a*RATE_STEPS)
273 #define O(a) a
274
275 /*note that there is no O(17) in this table - it's directly in the code */
276 static const UINT8 eg_rate_select[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
277 /* 32 infinite time rates */
278 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
279 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
280 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
281 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
282
283 /* rates 00-11 */
284 O(18),O(18),O( 2),O( 3),
285 O( 0),O( 1),O( 2),O( 3),
286 O( 0),O( 1),O( 2),O( 3),
287 O( 0),O( 1),O( 2),O( 3),
288 O( 0),O( 1),O( 2),O( 3),
289 O( 0),O( 1),O( 2),O( 3),
290 O( 0),O( 1),O( 2),O( 3),
291 O( 0),O( 1),O( 2),O( 3),
292 O( 0),O( 1),O( 2),O( 3),
293 O( 0),O( 1),O( 2),O( 3),
294 O( 0),O( 1),O( 2),O( 3),
295 O( 0),O( 1),O( 2),O( 3),
296
297 /* rate 12 */
298 O( 4),O( 5),O( 6),O( 7),
299
300 /* rate 13 */
301 O( 8),O( 9),O(10),O(11),
302
303 /* rate 14 */
304 O(12),O(13),O(14),O(15),
305
306 /* rate 15 */
307 O(16),O(16),O(16),O(16),
308
309 /* 32 dummy rates (same as 15 3) */
310 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
311 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
312 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
313 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
314
315 };
316 #undef O
317
318 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15*/
319 /*shift 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0 */
320 /*mask 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0, 0 */
321
322 #define O(a) (a*1)
323 static const UINT8 eg_rate_shift[32+64+32]={ /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
324 /* 32 infinite time rates */
325 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
326 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
327 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
328 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
329
330 /* rates 00-11 */
331 O(11),O(11),O(11),O(11),
332 O(10),O(10),O(10),O(10),
333 O( 9),O( 9),O( 9),O( 9),
334 O( 8),O( 8),O( 8),O( 8),
335 O( 7),O( 7),O( 7),O( 7),
336 O( 6),O( 6),O( 6),O( 6),
337 O( 5),O( 5),O( 5),O( 5),
338 O( 4),O( 4),O( 4),O( 4),
339 O( 3),O( 3),O( 3),O( 3),
340 O( 2),O( 2),O( 2),O( 2),
341 O( 1),O( 1),O( 1),O( 1),
342 O( 0),O( 0),O( 0),O( 0),
343
344 /* rate 12 */
345 O( 0),O( 0),O( 0),O( 0),
346
347 /* rate 13 */
348 O( 0),O( 0),O( 0),O( 0),
349
350 /* rate 14 */
351 O( 0),O( 0),O( 0),O( 0),
352
353 /* rate 15 */
354 O( 0),O( 0),O( 0),O( 0),
355
356 /* 32 dummy rates (same as 15 3) */
357 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
358 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
359 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
360 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0)
361
362 };
363 #undef O
364
365 static const UINT8 dt_tab[4 * 32]={
366 /* this is YM2151 and YM2612 phase increment data (in 10.10 fixed point format)*/
367 /* FD=0 */
368 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
369 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
370 /* FD=1 */
371 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
372 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
373 /* FD=2 */
374 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
375 5, 6, 6, 7, 8, 8, 9,10,11,12,13,14,16,16,16,16,
376 /* FD=3 */
377 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
378 8 ,8, 9,10,11,12,13,14,16,17,19,20,22,22,22,22
379 };
380
381
382 /* OPN key frequency number -> key code follow table */
383 /* fnum higher 4bit -> keycode lower 2bit */
384 static const UINT8 opn_fktable[16] = {0,0,0,0,0,0,0,1,2,3,3,3,3,3,3,3};
385
386
387 /* 8 LFO speed parameters */
388 /* each value represents number of samples that one LFO level will last for */
389 static const UINT32 lfo_samples_per_step[8] = {108, 77, 71, 67, 62, 44, 8, 5};
390
391
392
393 /*There are 4 different LFO AM depths available, they are:
394 0 dB, 1.4 dB, 5.9 dB, 11.8 dB
395 Here is how it is generated (in EG steps):
396
397 11.8 dB = 0, 2, 4, 6, 8, 10,12,14,16...126,126,124,122,120,118,....4,2,0
398 5.9 dB = 0, 1, 2, 3, 4, 5, 6, 7, 8....63, 63, 62, 61, 60, 59,.....2,1,0
399 1.4 dB = 0, 0, 0, 0, 1, 1, 1, 1, 2,...15, 15, 15, 15, 14, 14,.....0,0,0
400
401 (1.4 dB is loosing precision as you can see)
402
403 It's implemented as generator from 0..126 with step 2 then a shift
404 right N times, where N is:
405 8 for 0 dB
406 3 for 1.4 dB
407 1 for 5.9 dB
408 0 for 11.8 dB
409 */
410 static const UINT8 lfo_ams_depth_shift[4] = {8, 3, 1, 0};
411
412
413
414 /*There are 8 different LFO PM depths available, they are:
415 0, 3.4, 6.7, 10, 14, 20, 40, 80 (cents)
416
417 Modulation level at each depth depends on F-NUMBER bits: 4,5,6,7,8,9,10
418 (bits 8,9,10 = FNUM MSB from OCT/FNUM register)
419
420 Here we store only first quarter (positive one) of full waveform.
421 Full table (lfo_pm_table) containing all 128 waveforms is build
422 at run (init) time.
423
424 One value in table below represents 4 (four) basic LFO steps
425 (1 PM step = 4 AM steps).
426
427 For example:
428 at LFO SPEED=0 (which is 108 samples per basic LFO step)
429 one value from "lfo_pm_output" table lasts for 432 consecutive
430 samples (4*108=432) and one full LFO waveform cycle lasts for 13824
431 samples (32*432=13824; 32 because we store only a quarter of whole
432 waveform in the table below)
433 */
434 static const UINT8 lfo_pm_output[7*8][8]={ /* 7 bits meaningful (of F-NUMBER), 8 LFO output levels per one depth (out of 32), 8 LFO depths */
435 /* FNUM BIT 4: 000 0001xxxx */
436 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
437 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
438 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
439 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
440 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
441 /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
442 /* DEPTH 6 */ {0, 0, 0, 0, 0, 0, 0, 0},
443 /* DEPTH 7 */ {0, 0, 0, 0, 1, 1, 1, 1},
444
445 /* FNUM BIT 5: 000 0010xxxx */
446 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
447 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
448 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
449 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
450 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
451 /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
452 /* DEPTH 6 */ {0, 0, 0, 0, 1, 1, 1, 1},
453 /* DEPTH 7 */ {0, 0, 1, 1, 2, 2, 2, 3},
454
455 /* FNUM BIT 6: 000 0100xxxx */
456 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
457 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
458 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
459 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
460 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 1},
461 /* DEPTH 5 */ {0, 0, 0, 0, 1, 1, 1, 1},
462 /* DEPTH 6 */ {0, 0, 1, 1, 2, 2, 2, 3},
463 /* DEPTH 7 */ {0, 0, 2, 3, 4, 4, 5, 6},
464
465 /* FNUM BIT 7: 000 1000xxxx */
466 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
467 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
468 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 1, 1},
469 /* DEPTH 3 */ {0, 0, 0, 0, 1, 1, 1, 1},
470 /* DEPTH 4 */ {0, 0, 0, 1, 1, 1, 1, 2},
471 /* DEPTH 5 */ {0, 0, 1, 1, 2, 2, 2, 3},
472 /* DEPTH 6 */ {0, 0, 2, 3, 4, 4, 5, 6},
473 /* DEPTH 7 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
474
475 /* FNUM BIT 8: 001 0000xxxx */
476 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
477 /* DEPTH 1 */ {0, 0, 0, 0, 1, 1, 1, 1},
478 /* DEPTH 2 */ {0, 0, 0, 1, 1, 1, 2, 2},
479 /* DEPTH 3 */ {0, 0, 1, 1, 2, 2, 3, 3},
480 /* DEPTH 4 */ {0, 0, 1, 2, 2, 2, 3, 4},
481 /* DEPTH 5 */ {0, 0, 2, 3, 4, 4, 5, 6},
482 /* DEPTH 6 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
483 /* DEPTH 7 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
484
485 /* FNUM BIT 9: 010 0000xxxx */
486 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
487 /* DEPTH 1 */ {0, 0, 0, 0, 2, 2, 2, 2},
488 /* DEPTH 2 */ {0, 0, 0, 2, 2, 2, 4, 4},
489 /* DEPTH 3 */ {0, 0, 2, 2, 4, 4, 6, 6},
490 /* DEPTH 4 */ {0, 0, 2, 4, 4, 4, 6, 8},
491 /* DEPTH 5 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
492 /* DEPTH 6 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
493 /* DEPTH 7 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
494
495 /* FNUM BIT10: 100 0000xxxx */
496 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
497 /* DEPTH 1 */ {0, 0, 0, 0, 4, 4, 4, 4},
498 /* DEPTH 2 */ {0, 0, 0, 4, 4, 4, 8, 8},
499 /* DEPTH 3 */ {0, 0, 4, 4, 8, 8, 0xc, 0xc},
500 /* DEPTH 4 */ {0, 0, 4, 8, 8, 8, 0xc,0x10},
501 /* DEPTH 5 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
502 /* DEPTH 6 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
503 /* DEPTH 7 */ {0, 0,0x20,0x30,0x40,0x40,0x50,0x60},
504
505 };
506
507 /* all 128 LFO PM waveforms */
508 static INT32 lfo_pm_table[128*8*32]; /* 128 combinations of 7 bits meaningful (of F-NUMBER), 8 LFO depths, 32 LFO output levels per one depth */
509
510 /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
511 but LFO works with one more bit of a precision so we really need 4096 elements */
512 static UINT32 fn_table[4096]; /* fnumber->increment counter */
513
514 static int g_lfo_ampm;
515
516 /* register number to channel number , slot offset */
517 #define OPN_CHAN(N) (N&3)
518 #define OPN_SLOT(N) ((N>>2)&3)
519
520 /* slot number */
521 #define SLOT1 0
522 #define SLOT2 2
523 #define SLOT3 1
524 #define SLOT4 3
525
526
527 /* OPN Mode Register Write */
set_timers(int v)528 INLINE void set_timers( int v )
529 {
530 /* b7 = CSM MODE */
531 /* b6 = 3 slot mode */
532 /* b5 = reset b */
533 /* b4 = reset a */
534 /* b3 = timer enable b */
535 /* b2 = timer enable a */
536 /* b1 = load b */
537 /* b0 = load a */
538 ym2612.OPN.ST.mode = v;
539
540 /* reset Timer b flag */
541 if( v & 0x20 )
542 ym2612.OPN.ST.status &= ~2;
543
544 /* reset Timer a flag */
545 if( v & 0x10 )
546 ym2612.OPN.ST.status &= ~1;
547 }
548
recalc_volout(FM_SLOT * SLOT)549 INLINE void recalc_volout(FM_SLOT *SLOT)
550 {
551 INT16 vol_out = SLOT->volume;
552 if ((SLOT->ssg&0x0c) == 0x0c)
553 vol_out = (0x200 - SLOT->volume) & MAX_ATT_INDEX;
554 SLOT->vol_out = vol_out + SLOT->tl;
555 }
556
FM_KEYON(int c,int s)557 INLINE void FM_KEYON(int c , int s )
558 {
559 FM_SLOT *SLOT = &ym2612.CH[c].SLOT[s];
560 if( !SLOT->key )
561 {
562 SLOT->key = 1;
563 SLOT->phase = 0; /* restart Phase Generator */
564 SLOT->ssg ^= SLOT->ssgn;
565 SLOT->ssgn = 0;
566 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
567 if (SLOT->ar_ksr < 32+62) {
568 if (SLOT->volume > MIN_ATT_INDEX) SLOT->state = EG_ATT;
569 } else {
570 SLOT->volume = MIN_ATT_INDEX;
571 }
572 // recalc_volout(SLOT);
573 ym2612.slot_mask |= (1<<s) << (c*4);
574 }
575 }
576
FM_KEYOFF(int c,int s)577 INLINE void FM_KEYOFF(int c , int s )
578 {
579 FM_SLOT *SLOT = &ym2612.CH[c].SLOT[s];
580 if( SLOT->key )
581 {
582 SLOT->key = 0;
583 if (SLOT->state>EG_REL) {
584 SLOT->state = EG_REL;/* phase -> Release */
585 if (SLOT->ssg&0x08) {
586 if (SLOT->ssg&0x04)
587 SLOT->volume = (0x200 - SLOT->volume);
588 if (SLOT->volume >= 0x200) {
589 SLOT->volume = MAX_ATT_INDEX;
590 SLOT->state = EG_OFF;
591 }
592 }
593 }
594 SLOT->vol_out = SLOT->volume + SLOT->tl;
595 }
596 }
597
598
599 /* set detune & multiple */
set_det_mul(FM_CH * CH,FM_SLOT * SLOT,int v)600 INLINE void set_det_mul(FM_CH *CH, FM_SLOT *SLOT, int v)
601 {
602 SLOT->mul = (v&0x0f)? (v&0x0f)*2 : 1;
603 SLOT->DT = ym2612.OPN.ST.dt_tab[(v>>4)&7];
604 CH->SLOT[SLOT1].Incr=-1;
605 }
606
607 /* set total level */
set_tl(FM_SLOT * SLOT,int v)608 INLINE void set_tl(FM_SLOT *SLOT, int v)
609 {
610 SLOT->tl = (v&0x7f)<<(ENV_BITS-7); /* 7bit TL */
611 // if (SLOT->state > EG_REL)
612 // recalc_volout(SLOT);
613 }
614
615 /* set attack rate & key scale */
set_ar_ksr(FM_CH * CH,FM_SLOT * SLOT,int v)616 INLINE void set_ar_ksr(FM_CH *CH, FM_SLOT *SLOT, int v)
617 {
618 UINT8 old_KSR = SLOT->KSR;
619 int eg_sh_ar, eg_sel_ar;
620
621 SLOT->ar = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
622 SLOT->ar_ksr = SLOT->ar + SLOT->ksr;
623
624 SLOT->KSR = 3-(v>>6);
625 if (SLOT->KSR != old_KSR)
626 {
627 CH->SLOT[SLOT1].Incr=-1;
628 }
629
630 /* refresh Attack rate */
631 if ((SLOT->ar_ksr) < 32+62)
632 {
633 eg_sh_ar = eg_rate_shift [SLOT->ar_ksr];
634 eg_sel_ar = eg_rate_select[SLOT->ar_ksr];
635 }
636 else
637 {
638 eg_sh_ar = 0;
639 eg_sel_ar = 18;
640 }
641
642 SLOT->eg_pack_ar = eg_inc_pack[eg_sel_ar] | (eg_sh_ar<<24);
643 }
644
645 /* set decay rate */
set_dr(FM_SLOT * SLOT,int v)646 INLINE void set_dr(FM_SLOT *SLOT, int v)
647 {
648 int eg_sh_d1r, eg_sel_d1r;
649
650 SLOT->d1r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
651
652 eg_sh_d1r = eg_rate_shift [SLOT->d1r + SLOT->ksr];
653 eg_sel_d1r= eg_rate_select[SLOT->d1r + SLOT->ksr];
654
655 SLOT->eg_pack_d1r = eg_inc_pack[eg_sel_d1r] | (eg_sh_d1r<<24);
656 }
657
658 /* set sustain rate */
set_sr(FM_SLOT * SLOT,int v)659 INLINE void set_sr(FM_SLOT *SLOT, int v)
660 {
661 int eg_sh_d2r, eg_sel_d2r;
662
663 SLOT->d2r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
664
665 eg_sh_d2r = eg_rate_shift [SLOT->d2r + SLOT->ksr];
666 eg_sel_d2r= eg_rate_select[SLOT->d2r + SLOT->ksr];
667
668 SLOT->eg_pack_d2r = eg_inc_pack[eg_sel_d2r] | (eg_sh_d2r<<24);
669 }
670
671 /* set release rate */
set_sl_rr(FM_SLOT * SLOT,int v)672 INLINE void set_sl_rr(FM_SLOT *SLOT, int v)
673 {
674 int eg_sh_rr, eg_sel_rr;
675
676 SLOT->sl = sl_table[ v>>4 ];
677
678 if (SLOT->state == EG_DEC && (SLOT->volume >= (INT32)(SLOT->sl)))
679 SLOT->state = EG_SUS;
680
681 SLOT->rr = 34 + ((v&0x0f)<<2);
682
683 eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr];
684 eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr];
685
686 SLOT->eg_pack_rr = eg_inc_pack[eg_sel_rr] | (eg_sh_rr<<24);
687 }
688
689
690
op_calc(UINT32 phase,unsigned int env,signed int pm)691 INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm)
692 {
693 int ret, sin = (phase>>16) + (pm>>1);
694 int neg = sin & 0x200;
695 if (sin & 0x100) sin ^= 0xff;
696 sin&=0xff;
697 env&=~1;
698
699 // this was already checked
700 // if (env >= ENV_QUIET) // 384
701 // return 0;
702
703 ret = ym_tl_tab[sin | (env<<7)];
704
705 return neg ? -ret : ret;
706 }
707
op_calc1(UINT32 phase,unsigned int env,signed int pm)708 INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm)
709 {
710 int ret, sin = (phase+pm)>>16;
711 int neg = sin & 0x200;
712 if (sin & 0x100) sin ^= 0xff;
713 sin&=0xff;
714 env&=~1;
715
716 // if (env >= ENV_QUIET) // 384
717 // return 0;
718
719 ret = ym_tl_tab[sin | (env<<7)];
720
721 return neg ? -ret : ret;
722 }
723
724 #if !defined(_ASM_YM2612_C) || defined(EXTERNAL_YM2612)
725 /* advance LFO to next sample */
advance_lfo(int lfo_ampm,UINT32 lfo_cnt_old,UINT32 lfo_cnt)726 INLINE int advance_lfo(int lfo_ampm, UINT32 lfo_cnt_old, UINT32 lfo_cnt)
727 {
728 UINT8 pos;
729 UINT8 prev_pos;
730
731 prev_pos = (lfo_cnt_old >> LFO_SH) & 127;
732
733 pos = (lfo_cnt >> LFO_SH) & 127;
734
735 /* update AM when LFO output changes */
736
737 if (prev_pos != pos)
738 {
739 lfo_ampm &= 0xff;
740 /* triangle (inverted) */
741 /* AM: 0 to 126 step +2, 126 to 0 step -2 */
742 if (pos<64)
743 lfo_ampm |= ((pos^63) * 2) << 8; /* 0 - 126 */
744 else
745 lfo_ampm |= ((pos&63) * 2) << 8;
746 }
747 else
748 {
749 return lfo_ampm;
750 }
751
752 /* PM works with 4 times slower clock */
753 prev_pos >>= 2;
754 pos >>= 2;
755 /* update PM when LFO output changes */
756 if (prev_pos != pos)
757 {
758 lfo_ampm &= ~0xff;
759 lfo_ampm |= pos; /* 0 - 32 */
760 }
761 return lfo_ampm;
762 }
763
update_eg_phase(FM_SLOT * SLOT,UINT32 eg_cnt,UINT32 ssg_en)764 INLINE void update_eg_phase(FM_SLOT *SLOT, UINT32 eg_cnt, UINT32 ssg_en)
765 {
766 INT32 volume = SLOT->volume;
767 UINT32 pack = SLOT->eg_pack[SLOT->state - 1];
768 UINT32 shift = pack >> 24;
769 INT32 eg_inc_val;
770
771 if (eg_cnt & ((1 << shift) - 1))
772 return;
773
774 eg_inc_val = pack >> ((eg_cnt >> shift) & 7) * 3;
775 eg_inc_val = (1 << (eg_inc_val & 7)) >> 1;
776
777 if ((SLOT->ssg&0x08) && ssg_en) {
778 switch (SLOT->state)
779 {
780 case EG_ATT: /* attack phase */
781 volume += ( ~volume * eg_inc_val ) >> 4;
782 if ( volume <= MIN_ATT_INDEX )
783 {
784 volume = MIN_ATT_INDEX;
785 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS: EG_DEC;
786 }
787 break;
788
789 case EG_DEC: /* decay phase */
790 if (volume < 0x200)
791 volume += 4*eg_inc_val;
792 if ( volume >= (INT32) SLOT->sl )
793 SLOT->state = EG_SUS;
794 break;
795
796 case EG_SUS: /* sustain phase */
797 if (volume < 0x200)
798 volume += 4*eg_inc_val;
799 break;
800
801 case EG_REL: /* release phase */
802 if (volume < 0x200)
803 volume += 4*eg_inc_val;
804 if ( volume >= 0x200 )
805 {
806 volume = MAX_ATT_INDEX;
807 SLOT->state = EG_OFF;
808 }
809 break;
810 }
811
812 SLOT->vol_out = volume + SLOT->tl;
813 if ((SLOT->ssg&0x04) && (SLOT->state > EG_REL))
814 SLOT->vol_out = ((0x200 - volume) & MAX_ATT_INDEX) + SLOT->tl;
815 } else {
816 switch (SLOT->state)
817 {
818 case EG_ATT: /* attack phase */
819 volume += ( ~volume * eg_inc_val ) >> 4;
820 if ( volume <= MIN_ATT_INDEX )
821 {
822 volume = MIN_ATT_INDEX;
823 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS: EG_DEC;
824 }
825 break;
826
827 case EG_DEC: /* decay phase */
828 volume += eg_inc_val;
829 if ( volume >= (INT32) SLOT->sl )
830 SLOT->state = EG_SUS;
831 break;
832
833 case EG_SUS: /* sustain phase */
834 volume += eg_inc_val;
835 if ( volume >= MAX_ATT_INDEX )
836 {
837 volume = MAX_ATT_INDEX;
838 /* do not change SLOT->state (verified on real chip) */
839 }
840 break;
841
842 case EG_REL: /* release phase */
843 volume += eg_inc_val;
844 if ( volume >= MAX_ATT_INDEX )
845 {
846 volume = MAX_ATT_INDEX;
847 SLOT->state = EG_OFF;
848 }
849 break;
850 }
851
852 SLOT->vol_out = volume + SLOT->tl;
853 }
854 SLOT->volume = volume;
855 }
856
update_ssg_eg_phase(FM_SLOT * SLOT,UINT32 phase)857 INLINE UINT32 update_ssg_eg_phase(FM_SLOT *SLOT, UINT32 phase)
858 {
859 if (SLOT->ssg&0x01) {
860 if (SLOT->ssg&0x02) {
861 SLOT->ssg ^= SLOT->ssgn ^ 4;
862 SLOT->ssgn = 4;
863 }
864
865 if (SLOT->state != EG_ATT && !(SLOT->ssg&0x04))
866 SLOT->volume = MAX_ATT_INDEX;
867 } else {
868 if (SLOT->ssg&0x02) {
869 SLOT->ssg ^= 4;
870 SLOT->ssgn ^= 4;
871 } else
872 phase = 0;
873
874 if (SLOT->state != EG_ATT) {
875 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
876 if (SLOT->ar_ksr < 32+62) {
877 if (SLOT->volume > MIN_ATT_INDEX) SLOT->state = EG_ATT;
878 } else {
879 SLOT->volume = MIN_ATT_INDEX;
880 }
881 }
882 }
883 // recalc_volout(SLOT);
884 return phase;
885 }
886 #endif
887
888
889 typedef struct
890 {
891 UINT16 vol_out1; /* 00: current output from EG circuit (without AM from LFO) */
892 UINT16 vol_out2;
893 UINT16 vol_out3;
894 UINT16 vol_out4;
895 UINT32 pad[2];
896 UINT32 phase1; /* 10 */
897 UINT32 phase2;
898 UINT32 phase3;
899 UINT32 phase4;
900 UINT32 incr1; /* 20: phase step */
901 UINT32 incr2;
902 UINT32 incr3;
903 UINT32 incr4;
904 UINT32 lfo_cnt; /* 30 */
905 UINT32 lfo_inc;
906 INT32 mem; /* one sample delay memory */
907 UINT32 eg_cnt; /* envelope generator counter */
908 FM_CH *CH; /* 40: envelope generator counter */
909 UINT32 eg_timer;
910 UINT32 eg_timer_add;
911 UINT32 pack; // 4c: stereo, lastchan, disabled, lfo_enabled | pan_r, pan_l, ams[2] | AMmasks[4] | FB[4] | lfo_ampm[16]
912 UINT32 algo; /* 50: algo[3], was_update */
913 INT32 op1_out;
914 #ifdef _MIPS_ARCH_ALLEGREX
915 UINT32 pad1[3+8];
916 #endif
917 } chan_rend_context;
918
919
920 #if !defined(_ASM_YM2612_C) || defined(EXTERNAL_YM2612)
chan_render_loop(chan_rend_context * ct,int * buffer,int length)921 static void chan_render_loop(chan_rend_context *ct, int *buffer, int length)
922 {
923 int scounter; /* sample counter */
924
925 /* sample generating loop */
926 for (scounter = 0; scounter < length; scounter++)
927 {
928 int smp = 0; /* produced sample */
929 unsigned int eg_out, eg_out2, eg_out4;
930 FM_SLOT *SLOT;
931 UINT32 cnt = ct->eg_timer_add+(ct->eg_timer & ((1<<EG_SH)-1));
932
933 if (ct->pack & 2) while (cnt >= 1<<EG_SH) {
934 cnt -= 1<<EG_SH;
935 SLOT = &ct->CH->SLOT[SLOT1];
936 if ((SLOT->ssg&0x08) && SLOT->state > EG_REL && SLOT->volume >= 0x200)
937 ct->phase1 = update_ssg_eg_phase(SLOT, ct->phase1);
938 SLOT = &ct->CH->SLOT[SLOT2];
939 if ((SLOT->ssg&0x08) && SLOT->state > EG_REL && SLOT->volume >= 0x200)
940 ct->phase2 = update_ssg_eg_phase(SLOT, ct->phase2);
941 SLOT = &ct->CH->SLOT[SLOT3];
942 if ((SLOT->ssg&0x08) && SLOT->state > EG_REL && SLOT->volume >= 0x200)
943 ct->phase3 = update_ssg_eg_phase(SLOT, ct->phase3);
944 SLOT = &ct->CH->SLOT[SLOT4];
945 if ((SLOT->ssg&0x08) && SLOT->state > EG_REL && SLOT->volume >= 0x200)
946 ct->phase4 = update_ssg_eg_phase(SLOT, ct->phase4);
947 }
948
949 if (ct->pack & 8) { /* LFO enabled ? (test Earthworm Jim in between demo 1 and 2) */
950 ct->pack = (ct->pack&0xffff) | (advance_lfo(ct->pack >> 16, ct->lfo_cnt, ct->lfo_cnt + ct->lfo_inc) << 16);
951 ct->lfo_cnt += ct->lfo_inc;
952 }
953
954 ct->eg_timer += ct->eg_timer_add;
955 if (ct->eg_timer < EG_TIMER_OVERFLOW) {
956 SLOT = &ct->CH->SLOT[SLOT1];
957 SLOT->vol_ipol = SLOT->vol_out;
958 if (SLOT->state > EG_REL) recalc_volout(SLOT);
959 SLOT = &ct->CH->SLOT[SLOT2];
960 SLOT->vol_ipol = SLOT->vol_out;
961 if (SLOT->state > EG_REL) recalc_volout(SLOT);
962 SLOT = &ct->CH->SLOT[SLOT3];
963 SLOT->vol_ipol = SLOT->vol_out;
964 if (SLOT->state > EG_REL) recalc_volout(SLOT);
965 SLOT = &ct->CH->SLOT[SLOT4];
966 SLOT->vol_ipol = SLOT->vol_out;
967 if (SLOT->state > EG_REL) recalc_volout(SLOT);
968 }
969 else while (ct->eg_timer >= EG_TIMER_OVERFLOW)
970 {
971 ct->eg_timer -= EG_TIMER_OVERFLOW;
972 ct->eg_cnt++;
973 if (ct->eg_cnt >= 4096) ct->eg_cnt = 1;
974
975 SLOT = &ct->CH->SLOT[SLOT1];
976 SLOT->vol_ipol = SLOT->vol_out;
977 if (SLOT->state != EG_OFF) update_eg_phase(SLOT, ct->eg_cnt, ct->pack & 2);
978 SLOT = &ct->CH->SLOT[SLOT2];
979 SLOT->vol_ipol = SLOT->vol_out;
980 if (SLOT->state != EG_OFF) update_eg_phase(SLOT, ct->eg_cnt, ct->pack & 2);
981 SLOT = &ct->CH->SLOT[SLOT3];
982 SLOT->vol_ipol = SLOT->vol_out;
983 if (SLOT->state != EG_OFF) update_eg_phase(SLOT, ct->eg_cnt, ct->pack & 2);
984 SLOT = &ct->CH->SLOT[SLOT4];
985 SLOT->vol_ipol = SLOT->vol_out;
986 if (SLOT->state != EG_OFF) update_eg_phase(SLOT, ct->eg_cnt, ct->pack & 2);
987 }
988
989 #if 0
990 UINT32 ifrac0 = ct->eg_timer / (EG_TIMER_OVERFLOW>>EG_SH);
991 UINT32 ifrac1 = (1<<EG_SH) - ifrac0;
992 SLOT = &ct->CH->SLOT[SLOT1];
993 ct->vol_out1 = (SLOT->vol_ipol*ifrac1 + SLOT->vol_out*ifrac0) >> EG_SH;
994 SLOT = &ct->CH->SLOT[SLOT2];
995 ct->vol_out2 = (SLOT->vol_ipol*ifrac1 + SLOT->vol_out*ifrac0) >> EG_SH;
996 SLOT = &ct->CH->SLOT[SLOT3];
997 ct->vol_out3 = (SLOT->vol_ipol*ifrac1 + SLOT->vol_out*ifrac0) >> EG_SH;
998 SLOT = &ct->CH->SLOT[SLOT4];
999 ct->vol_out4 = (SLOT->vol_ipol*ifrac1 + SLOT->vol_out*ifrac0) >> EG_SH;
1000 #elif 1
1001 switch (ct->eg_timer >> EG_SH)
1002 {
1003 case 0:
1004 ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_ipol;
1005 ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_ipol;
1006 ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_ipol;
1007 ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_ipol;
1008 break;
1009 case (EG_TIMER_OVERFLOW>>EG_SH)-1:
1010 ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_out;
1011 ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_out;
1012 ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_out;
1013 ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_out;
1014 break;
1015 default:
1016 ct->vol_out1 = (ct->CH->SLOT[SLOT1].vol_ipol +
1017 ct->CH->SLOT[SLOT1].vol_out) >> 1;
1018 ct->vol_out2 = (ct->CH->SLOT[SLOT2].vol_ipol +
1019 ct->CH->SLOT[SLOT2].vol_out) >> 1;
1020 ct->vol_out3 = (ct->CH->SLOT[SLOT3].vol_ipol +
1021 ct->CH->SLOT[SLOT3].vol_out) >> 1;
1022 ct->vol_out4 = (ct->CH->SLOT[SLOT4].vol_ipol +
1023 ct->CH->SLOT[SLOT4].vol_out) >> 1;
1024 break;
1025 }
1026 #elif 0
1027 if (ct->eg_timer >> (EG_SH-1) < EG_TIMER_OVERFLOW >> EG_SH) {
1028 ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_ipol;
1029 ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_ipol;
1030 ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_ipol;
1031 ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_ipol;
1032 } else {
1033 ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_out;
1034 ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_out;
1035 ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_out;
1036 ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_out;
1037 }
1038 #else
1039 ct->vol_out1 = ct->CH->SLOT[SLOT1].vol_out;
1040 ct->vol_out2 = ct->CH->SLOT[SLOT2].vol_out;
1041 ct->vol_out3 = ct->CH->SLOT[SLOT3].vol_out;
1042 ct->vol_out4 = ct->CH->SLOT[SLOT4].vol_out;
1043 #endif
1044
1045 if (ct->pack & 4) continue; /* output disabled */
1046
1047 /* calculate channel sample */
1048 eg_out = ct->vol_out1;
1049 if ( (ct->pack & 8) && (ct->pack&(1<<(SLOT1+8))) ) eg_out += ct->pack >> (((ct->pack&0xc0)>>6)+24);
1050
1051 if( eg_out < ENV_QUIET ) /* SLOT 1 */
1052 {
1053 int out = 0;
1054
1055 if (ct->pack&0xf000) out = ((ct->op1_out>>16) + ((ct->op1_out<<16)>>16)) << ((ct->pack&0xf000)>>12); /* op1_out0 + op1_out1 */
1056 ct->op1_out <<= 16;
1057 ct->op1_out |= (unsigned short)op_calc1(ct->phase1, eg_out, out);
1058 } else {
1059 ct->op1_out <<= 16; /* op1_out0 = op1_out1; op1_out1 = 0; */
1060 }
1061
1062 eg_out = ct->vol_out3; // volume_calc(&CH->SLOT[SLOT3]);
1063 eg_out2 = ct->vol_out2; // volume_calc(&CH->SLOT[SLOT2]);
1064 eg_out4 = ct->vol_out4; // volume_calc(&CH->SLOT[SLOT4]);
1065
1066 if (ct->pack & 8) {
1067 unsigned int add = ct->pack >> (((ct->pack&0xc0)>>6)+24);
1068 if (ct->pack & (1<<(SLOT3+8))) eg_out += add;
1069 if (ct->pack & (1<<(SLOT2+8))) eg_out2 += add;
1070 if (ct->pack & (1<<(SLOT4+8))) eg_out4 += add;
1071 }
1072
1073 switch( ct->algo&0x7 )
1074 {
1075 case 0:
1076 {
1077 /* M1---C1---MEM---M2---C2---OUT */
1078 int m2,c1,c2=0; /* Phase Modulation input for operators 2,3,4 */
1079 m2 = ct->mem;
1080 c1 = ct->op1_out>>16;
1081 if( eg_out < ENV_QUIET ) { /* SLOT 3 */
1082 c2 = op_calc(ct->phase3, eg_out, m2);
1083 }
1084 if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
1085 ct->mem = op_calc(ct->phase2, eg_out2, c1);
1086 }
1087 else ct->mem = 0;
1088 if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
1089 smp = op_calc(ct->phase4, eg_out4, c2);
1090 }
1091 break;
1092 }
1093 case 1:
1094 {
1095 /* M1------+-MEM---M2---C2---OUT */
1096 /* C1-+ */
1097 int m2,c2=0;
1098 m2 = ct->mem;
1099 ct->mem = ct->op1_out>>16;
1100 if( eg_out < ENV_QUIET ) { /* SLOT 3 */
1101 c2 = op_calc(ct->phase3, eg_out, m2);
1102 }
1103 if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
1104 ct->mem+= op_calc(ct->phase2, eg_out2, 0);
1105 }
1106 if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
1107 smp = op_calc(ct->phase4, eg_out4, c2);
1108 }
1109 break;
1110 }
1111 case 2:
1112 {
1113 /* M1-----------------+-C2---OUT */
1114 /* C1---MEM---M2-+ */
1115 int m2,c2;
1116 m2 = ct->mem;
1117 c2 = ct->op1_out>>16;
1118 if( eg_out < ENV_QUIET ) { /* SLOT 3 */
1119 c2 += op_calc(ct->phase3, eg_out, m2);
1120 }
1121 if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
1122 ct->mem = op_calc(ct->phase2, eg_out2, 0);
1123 }
1124 else ct->mem = 0;
1125 if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
1126 smp = op_calc(ct->phase4, eg_out4, c2);
1127 }
1128 break;
1129 }
1130 case 3:
1131 {
1132 /* M1---C1---MEM------+-C2---OUT */
1133 /* M2-+ */
1134 int c1,c2;
1135 c2 = ct->mem;
1136 c1 = ct->op1_out>>16;
1137 if( eg_out < ENV_QUIET ) { /* SLOT 3 */
1138 c2 += op_calc(ct->phase3, eg_out, 0);
1139 }
1140 if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
1141 ct->mem = op_calc(ct->phase2, eg_out2, c1);
1142 }
1143 else ct->mem = 0;
1144 if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
1145 smp = op_calc(ct->phase4, eg_out4, c2);
1146 }
1147 break;
1148 }
1149 case 4:
1150 {
1151 /* M1---C1-+-OUT */
1152 /* M2---C2-+ */
1153 /* MEM: not used */
1154 int c1,c2=0;
1155 c1 = ct->op1_out>>16;
1156 if( eg_out < ENV_QUIET ) { /* SLOT 3 */
1157 c2 = op_calc(ct->phase3, eg_out, 0);
1158 }
1159 if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
1160 smp = op_calc(ct->phase2, eg_out2, c1);
1161 }
1162 if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
1163 smp+= op_calc(ct->phase4, eg_out4, c2);
1164 }
1165 break;
1166 }
1167 case 5:
1168 {
1169 /* +----C1----+ */
1170 /* M1-+-MEM---M2-+-OUT */
1171 /* +----C2----+ */
1172 int m2,c1,c2;
1173 m2 = ct->mem;
1174 ct->mem = c1 = c2 = ct->op1_out>>16;
1175 if( eg_out < ENV_QUIET ) { /* SLOT 3 */
1176 smp = op_calc(ct->phase3, eg_out, m2);
1177 }
1178 if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
1179 smp+= op_calc(ct->phase2, eg_out2, c1);
1180 }
1181 if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
1182 smp+= op_calc(ct->phase4, eg_out4, c2);
1183 }
1184 break;
1185 }
1186 case 6:
1187 {
1188 /* M1---C1-+ */
1189 /* M2-+-OUT */
1190 /* C2-+ */
1191 /* MEM: not used */
1192 int c1;
1193 c1 = ct->op1_out>>16;
1194 if( eg_out < ENV_QUIET ) { /* SLOT 3 */
1195 smp = op_calc(ct->phase3, eg_out, 0);
1196 }
1197 if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
1198 smp+= op_calc(ct->phase2, eg_out2, c1);
1199 }
1200 if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
1201 smp+= op_calc(ct->phase4, eg_out4, 0);
1202 }
1203 break;
1204 }
1205 case 7:
1206 {
1207 /* M1-+ */
1208 /* C1-+-OUT */
1209 /* M2-+ */
1210 /* C2-+ */
1211 /* MEM: not used*/
1212 smp = ct->op1_out>>16;
1213 if( eg_out < ENV_QUIET ) { /* SLOT 3 */
1214 smp += op_calc(ct->phase3, eg_out, 0);
1215 }
1216 if( eg_out2 < ENV_QUIET ) { /* SLOT 2 */
1217 smp += op_calc(ct->phase2, eg_out2, 0);
1218 }
1219 if( eg_out4 < ENV_QUIET ) { /* SLOT 4 */
1220 smp += op_calc(ct->phase4, eg_out4, 0);
1221 }
1222 break;
1223 }
1224 }
1225 /* done calculating channel sample */
1226
1227 /* mix sample to output buffer */
1228 if (smp) {
1229 if (ct->pack & 1) { /* stereo */
1230 if (ct->pack & 0x20) /* L */ /* TODO: check correctness */
1231 buffer[scounter*2] += smp;
1232 if (ct->pack & 0x10) /* R */
1233 buffer[scounter*2+1] += smp;
1234 } else {
1235 buffer[scounter] += smp;
1236 }
1237 ct->algo |= 8;
1238 }
1239
1240 /* update phase counters AFTER output calculations */
1241 ct->phase1 += ct->incr1;
1242 ct->phase2 += ct->incr2;
1243 ct->phase3 += ct->incr3;
1244 ct->phase4 += ct->incr4;
1245 }
1246 }
1247 #else
1248 void chan_render_loop(chan_rend_context *ct, int *buffer, unsigned short length);
1249 #endif
1250
1251 static chan_rend_context crct;
1252
chan_render_prep(void)1253 static void chan_render_prep(void)
1254 {
1255 crct.eg_timer_add = ym2612.OPN.eg_timer_add;
1256 crct.lfo_inc = ym2612.OPN.lfo_inc;
1257 }
1258
chan_render_finish(void)1259 static void chan_render_finish(void)
1260 {
1261 ym2612.OPN.eg_cnt = crct.eg_cnt;
1262 ym2612.OPN.eg_timer = crct.eg_timer;
1263 g_lfo_ampm = crct.pack >> 16; // need_save
1264 ym2612.OPN.lfo_cnt = crct.lfo_cnt;
1265 }
1266
update_lfo_phase(FM_SLOT * SLOT,UINT32 block_fnum)1267 static UINT32 update_lfo_phase(FM_SLOT *SLOT, UINT32 block_fnum)
1268 {
1269 UINT32 fnum_lfo;
1270 INT32 lfo_fn_table_index_offset;
1271 UINT8 blk;
1272 UINT32 fn;
1273 int fc,fdt;
1274
1275 fnum_lfo = ((block_fnum & 0x7f0) >> 4) * 32 * 8;
1276 lfo_fn_table_index_offset = lfo_pm_table[ fnum_lfo + crct.CH->pms + ((crct.pack>>16)&0xff) ];
1277 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
1278 {
1279 block_fnum = block_fnum*2 + lfo_fn_table_index_offset;
1280 blk = (block_fnum&0x7000) >> 12;
1281 fn = block_fnum & 0xfff;
1282
1283 /* phase increment counter */
1284 fc = (fn_table[fn]>>(7-blk));
1285
1286 fdt = fc + SLOT->DT[crct.CH->kcode];
1287 if (fdt < 0) fdt += fn_table[0x7ff*2] >> 2;
1288
1289 return (fdt * SLOT->mul) >> 1;
1290 } else
1291 return SLOT->Incr;
1292 }
1293
chan_render(int * buffer,int length,int c,UINT32 flags)1294 static int chan_render(int *buffer, int length, int c, UINT32 flags) // flags: stereo, ?, disabled, ?, pan_r, pan_l
1295 {
1296 crct.CH = &ym2612.CH[c];
1297 crct.mem = crct.CH->mem_value; /* one sample delay memory */
1298 crct.lfo_cnt = ym2612.OPN.lfo_cnt;
1299
1300 flags &= 0x37;
1301
1302 if (crct.lfo_inc) {
1303 flags |= 8;
1304 flags |= g_lfo_ampm << 16;
1305 flags |= crct.CH->AMmasks << 8;
1306 if (crct.CH->ams == 8) // no ams
1307 flags &= ~0xf00;
1308 else flags |= (crct.CH->ams&3)<<6;
1309 }
1310 flags |= (crct.CH->FB&0xf)<<12; /* feedback shift */
1311 crct.pack = flags;
1312
1313 crct.eg_cnt = ym2612.OPN.eg_cnt; /* envelope generator counter */
1314 crct.eg_timer = ym2612.OPN.eg_timer;
1315
1316 /* precalculate phase modulation incr */
1317 crct.phase1 = crct.CH->SLOT[SLOT1].phase;
1318 crct.phase2 = crct.CH->SLOT[SLOT2].phase;
1319 crct.phase3 = crct.CH->SLOT[SLOT3].phase;
1320 crct.phase4 = crct.CH->SLOT[SLOT4].phase;
1321
1322 crct.op1_out = crct.CH->op1_out;
1323 crct.algo = crct.CH->ALGO & 7;
1324
1325 if(crct.CH->pms && (ym2612.OPN.ST.mode & 0xC0) && c == 2) {
1326 /* 3 slot mode */
1327 crct.incr1 = update_lfo_phase(&crct.CH->SLOT[SLOT1], ym2612.OPN.SL3.block_fnum[1]);
1328 crct.incr2 = update_lfo_phase(&crct.CH->SLOT[SLOT2], ym2612.OPN.SL3.block_fnum[2]);
1329 crct.incr3 = update_lfo_phase(&crct.CH->SLOT[SLOT3], ym2612.OPN.SL3.block_fnum[0]);
1330 crct.incr4 = update_lfo_phase(&crct.CH->SLOT[SLOT4], crct.CH->block_fnum);
1331 }
1332 else if(crct.CH->pms)
1333 {
1334 crct.incr1 = update_lfo_phase(&crct.CH->SLOT[SLOT1], crct.CH->block_fnum);
1335 crct.incr2 = update_lfo_phase(&crct.CH->SLOT[SLOT2], crct.CH->block_fnum);
1336 crct.incr3 = update_lfo_phase(&crct.CH->SLOT[SLOT3], crct.CH->block_fnum);
1337 crct.incr4 = update_lfo_phase(&crct.CH->SLOT[SLOT4], crct.CH->block_fnum);
1338 }
1339 else /* no LFO phase modulation */
1340 {
1341 crct.incr1 = crct.CH->SLOT[SLOT1].Incr;
1342 crct.incr2 = crct.CH->SLOT[SLOT2].Incr;
1343 crct.incr3 = crct.CH->SLOT[SLOT3].Incr;
1344 crct.incr4 = crct.CH->SLOT[SLOT4].Incr;
1345 }
1346
1347 chan_render_loop(&crct, buffer, length);
1348
1349 crct.CH->op1_out = crct.op1_out;
1350 crct.CH->mem_value = crct.mem;
1351 if (crct.CH->SLOT[SLOT1].state | crct.CH->SLOT[SLOT2].state | crct.CH->SLOT[SLOT3].state | crct.CH->SLOT[SLOT4].state)
1352 {
1353 crct.CH->SLOT[SLOT1].phase = crct.phase1;
1354 crct.CH->SLOT[SLOT2].phase = crct.phase2;
1355 crct.CH->SLOT[SLOT3].phase = crct.phase3;
1356 crct.CH->SLOT[SLOT4].phase = crct.phase4;
1357 }
1358 else
1359 ym2612.slot_mask &= ~(0xf << (c*4));
1360
1361 return (crct.algo & 8) >> 3; // had output
1362 }
1363
1364 /* update phase increment and envelope generator */
refresh_fc_eg_slot(FM_SLOT * SLOT,int fc,int kc)1365 INLINE void refresh_fc_eg_slot(FM_SLOT *SLOT, int fc, int kc)
1366 {
1367 int ksr, fdt;
1368
1369 /* (frequency) phase increment counter */
1370 fdt = fc+SLOT->DT[kc];
1371 /* detect overflow */
1372 // if (fdt < 0) fdt += fn_table[0x7ff*2] >> (7-blk-1);
1373 if (fdt < 0) fdt += fn_table[0x7ff*2] >> 2;
1374 SLOT->Incr = fdt*SLOT->mul >> 1;
1375
1376 ksr = kc >> SLOT->KSR;
1377 if( SLOT->ksr != ksr )
1378 {
1379 int eg_sh, eg_sel;
1380 SLOT->ksr = ksr;
1381 SLOT->ar_ksr = SLOT->ar + ksr;
1382
1383 /* calculate envelope generator rates */
1384 if ((SLOT->ar_ksr) < 32+62)
1385 {
1386 eg_sh = eg_rate_shift [SLOT->ar_ksr];
1387 eg_sel = eg_rate_select[SLOT->ar_ksr];
1388 }
1389 else
1390 {
1391 eg_sh = 0;
1392 eg_sel = 18;
1393 }
1394
1395 SLOT->eg_pack_ar = eg_inc_pack[eg_sel] | (eg_sh<<24);
1396
1397 eg_sh = eg_rate_shift [SLOT->d1r + ksr];
1398 eg_sel = eg_rate_select[SLOT->d1r + ksr];
1399
1400 SLOT->eg_pack_d1r = eg_inc_pack[eg_sel] | (eg_sh<<24);
1401
1402 eg_sh = eg_rate_shift [SLOT->d2r + ksr];
1403 eg_sel = eg_rate_select[SLOT->d2r + ksr];
1404
1405 SLOT->eg_pack_d2r = eg_inc_pack[eg_sel] | (eg_sh<<24);
1406
1407 eg_sh = eg_rate_shift [SLOT->rr + ksr];
1408 eg_sel = eg_rate_select[SLOT->rr + ksr];
1409
1410 SLOT->eg_pack_rr = eg_inc_pack[eg_sel] | (eg_sh<<24);
1411 }
1412 }
1413
1414 /* update phase increment counters */
refresh_fc_eg_chan(FM_CH * CH)1415 INLINE void refresh_fc_eg_chan(FM_CH *CH)
1416 {
1417 if( CH->SLOT[SLOT1].Incr==-1){
1418 int fc = CH->fc;
1419 int kc = CH->kcode;
1420 refresh_fc_eg_slot(&CH->SLOT[SLOT1] , fc , kc );
1421 refresh_fc_eg_slot(&CH->SLOT[SLOT2] , fc , kc );
1422 refresh_fc_eg_slot(&CH->SLOT[SLOT3] , fc , kc );
1423 refresh_fc_eg_slot(&CH->SLOT[SLOT4] , fc , kc );
1424 }
1425 }
1426
refresh_fc_eg_chan_sl3(void)1427 INLINE void refresh_fc_eg_chan_sl3(void)
1428 {
1429 if( ym2612.CH[2].SLOT[SLOT1].Incr==-1)
1430 {
1431 refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT1], ym2612.OPN.SL3.fc[1], ym2612.OPN.SL3.kcode[1] );
1432 refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT2], ym2612.OPN.SL3.fc[2], ym2612.OPN.SL3.kcode[2] );
1433 refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT3], ym2612.OPN.SL3.fc[0], ym2612.OPN.SL3.kcode[0] );
1434 refresh_fc_eg_slot(&ym2612.CH[2].SLOT[SLOT4], ym2612.CH[2].fc , ym2612.CH[2].kcode );
1435 }
1436 }
1437
1438 /* initialize time tables */
init_timetables(const UINT8 * dttable)1439 static void init_timetables(const UINT8 *dttable)
1440 {
1441 int i,d;
1442 double rate;
1443
1444 /* DeTune table */
1445 for (d = 0;d <= 3;d++){
1446 for (i = 0;i <= 31;i++){
1447 rate = ((double)dttable[d*32 + i]) * ym2612.OPN.ST.freqbase * (1<<(FREQ_SH-10));
1448 ym2612.OPN.ST.dt_tab[d][i] = (INT32) rate;
1449 ym2612.OPN.ST.dt_tab[d+4][i] = -ym2612.OPN.ST.dt_tab[d][i];
1450 }
1451 }
1452 }
1453
1454
reset_channels(FM_CH * CH)1455 static void reset_channels(FM_CH *CH)
1456 {
1457 int c,s;
1458
1459 ym2612.OPN.ST.mode = 0; /* normal mode */
1460 ym2612.OPN.ST.TA = 0;
1461 ym2612.OPN.ST.TAC = 0;
1462 ym2612.OPN.ST.TB = 0;
1463 ym2612.OPN.ST.TBC = 0;
1464
1465 for( c = 0 ; c < 6 ; c++ )
1466 {
1467 CH[c].fc = 0;
1468 for(s = 0 ; s < 4 ; s++ )
1469 {
1470 CH[c].SLOT[s].Incr = -1;
1471 CH[c].SLOT[s].key = 0;
1472 CH[c].SLOT[s].phase = 0;
1473 CH[c].SLOT[s].ar = CH[c].SLOT[s].ksr = 0;
1474 CH[c].SLOT[s].ar_ksr = 0;
1475 CH[c].SLOT[s].ssg = CH[c].SLOT[s].ssgn = 0;
1476 CH[c].SLOT[s].state= EG_OFF;
1477 CH[c].SLOT[s].volume = MAX_ATT_INDEX;
1478 CH[c].SLOT[s].vol_out = MAX_ATT_INDEX;
1479 }
1480 CH[c].mem_value = CH[c].op1_out = 0;
1481 }
1482 ym2612.slot_mask = 0;
1483 ym2612.ssg_mask = 0;
1484 }
1485
1486 /* initialize generic tables */
init_tables(void)1487 static void init_tables(void)
1488 {
1489 signed int i,x,y,p;
1490 signed int n;
1491 double o,m;
1492
1493 for (i=0; i < 256; i++)
1494 {
1495 /* non-standard sinus */
1496 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
1497
1498 /* we never reach zero here due to ((i*2)+1) */
1499
1500 if (m>0.0)
1501 o = 8*log(1.0/m)/log(2); /* convert to 'decibels' */
1502 else
1503 o = 8*log(-1.0/m)/log(2); /* convert to 'decibels' */
1504
1505 o = o / (ENV_STEP/4);
1506
1507 n = (int)(2.0*o);
1508 if (n&1) /* round to nearest */
1509 n = (n>>1)+1;
1510 else
1511 n = n>>1;
1512
1513 ym_sin_tab[ i ] = n;
1514 //dprintf("FM.C: sin [%4i]= %4i", i, ym_sin_tab[i]);
1515 }
1516
1517 //dprintf("FM.C: ENV_QUIET= %08x", ENV_QUIET );
1518
1519
1520 for (x=0; x < TL_RES_LEN; x++)
1521 {
1522 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
1523 m = floor(m);
1524
1525 /* we never reach (1<<16) here due to the (x+1) */
1526 /* result fits within 16 bits at maximum */
1527
1528 n = (int)m; /* 16 bits here */
1529 n >>= 4; /* 12 bits here */
1530 if (n&1) /* round to nearest */
1531 n = (n>>1)+1;
1532 else
1533 n = n>>1;
1534 /* 11 bits here (rounded) */
1535 n <<= 2; /* 13 bits here (as in real chip) */
1536 ym_tl_tab2[ x ] = n;
1537
1538 for (i=1; i < 13; i++)
1539 {
1540 ym_tl_tab2[ x + i*TL_RES_LEN ] = n >> i;
1541 }
1542 }
1543
1544 for (x=0; x < 256; x++)
1545 {
1546 int sin = ym_sin_tab[ x ];
1547
1548 for (y=0; y < 2*13*TL_RES_LEN/8; y+=2)
1549 {
1550 p = (y<<2) + sin;
1551 if (p >= 13*TL_RES_LEN)
1552 ym_tl_tab[(y<<7) | x] = 0;
1553 else ym_tl_tab[(y<<7) | x] = ym_tl_tab2[p];
1554 }
1555 }
1556
1557
1558 /* build LFO PM modulation table */
1559 for(i = 0; i < 8; i++) /* 8 PM depths */
1560 {
1561 UINT8 fnum;
1562 for (fnum=0; fnum<128; fnum++) /* 7 bits meaningful of F-NUMBER */
1563 {
1564 UINT8 value;
1565 UINT8 step;
1566 UINT32 offset_depth = i;
1567 UINT32 offset_fnum_bit;
1568 UINT32 bit_tmp;
1569
1570 for (step=0; step<8; step++)
1571 {
1572 value = 0;
1573 for (bit_tmp=0; bit_tmp<7; bit_tmp++) /* 7 bits */
1574 {
1575 if (fnum & (1<<bit_tmp)) /* only if bit "bit_tmp" is set */
1576 {
1577 offset_fnum_bit = bit_tmp * 8;
1578 value += lfo_pm_output[offset_fnum_bit + offset_depth][step];
1579 }
1580 }
1581 lfo_pm_table[(fnum*32*8) + (i*32) + step + 0] = value;
1582 lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+ 8] = value;
1583 lfo_pm_table[(fnum*32*8) + (i*32) + step +16] = -value;
1584 lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+24] = -value;
1585 }
1586 }
1587 }
1588 }
1589
1590
1591 /* CSM Key Controll */
1592 #if 0
1593 INLINE void CSMKeyControll(FM_CH *CH)
1594 {
1595 /* this is wrong, atm */
1596
1597 /* all key on */
1598 FM_KEYON(CH,SLOT1);
1599 FM_KEYON(CH,SLOT2);
1600 FM_KEYON(CH,SLOT3);
1601 FM_KEYON(CH,SLOT4);
1602 }
1603 #endif
1604
1605
1606 /* prescaler set (and make time tables) */
OPNSetPres(int pres)1607 static void OPNSetPres(int pres)
1608 {
1609 int i;
1610
1611 /* frequency base */
1612 ym2612.OPN.ST.freqbase = (ym2612.OPN.ST.rate) ? ((double)ym2612.OPN.ST.clock / ym2612.OPN.ST.rate) / pres : 0;
1613
1614 ym2612.OPN.eg_timer_add = (1<<EG_SH) * ym2612.OPN.ST.freqbase;
1615
1616 /* make time tables */
1617 init_timetables( dt_tab );
1618
1619 /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
1620 but LFO works with one more bit of a precision so we really need 4096 elements */
1621 /* calculate fnumber -> increment counter table */
1622 for(i = 0; i < 4096; i++)
1623 {
1624 /* freq table for octave 7 */
1625 /* OPN phase increment counter = 20bit */
1626 fn_table[i] = (UINT32)( (double)i * 32 * ym2612.OPN.ST.freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
1627 }
1628
1629 /* LFO freq. table */
1630 for(i = 0; i < 8; i++)
1631 {
1632 /* Amplitude modulation: 64 output levels (triangle waveform); 1 level lasts for one of "lfo_samples_per_step" samples */
1633 /* Phase modulation: one entry from lfo_pm_output lasts for one of 4 * "lfo_samples_per_step" samples */
1634 ym2612.OPN.lfo_freq[i] = (1.0 / lfo_samples_per_step[i]) * (1<<LFO_SH) * ym2612.OPN.ST.freqbase;
1635 }
1636 }
1637
1638
1639 /* write a OPN register (0x30-0xff) */
OPNWriteReg(int r,int v)1640 static int OPNWriteReg(int r, int v)
1641 {
1642 int ret = 1;
1643 FM_CH *CH;
1644 FM_SLOT *SLOT;
1645
1646 UINT8 c = OPN_CHAN(r);
1647
1648 if (c == 3) return 0; /* 0xX3,0xX7,0xXB,0xXF */
1649
1650 if (r >= 0x100) c+=3;
1651
1652 CH = &ym2612.CH[c];
1653
1654 SLOT = &(CH->SLOT[OPN_SLOT(r)]);
1655
1656 switch( r & 0xf0 ) {
1657 case 0x30: /* DET , MUL */
1658 set_det_mul(CH,SLOT,v);
1659 break;
1660
1661 case 0x40: /* TL */
1662 set_tl(SLOT,v);
1663 break;
1664
1665 case 0x50: /* KS, AR */
1666 set_ar_ksr(CH,SLOT,v);
1667 break;
1668
1669 case 0x60: /* bit7 = AM ENABLE, DR | depends on ksr */
1670 set_dr(SLOT,v);
1671 if(v&0x80) CH->AMmasks |= 1<<OPN_SLOT(r);
1672 else CH->AMmasks &= ~(1<<OPN_SLOT(r));
1673 break;
1674
1675 case 0x70: /* SR | depends on ksr */
1676 set_sr(SLOT,v);
1677 break;
1678
1679 case 0x80: /* SL, RR | depends on ksr */
1680 set_sl_rr(SLOT,v);
1681 break;
1682
1683 case 0x90: /* SSG-EG */
1684 SLOT->ssg = v&0x0f;
1685 SLOT->ssg ^= SLOT->ssgn;
1686 if (v&0x08) ym2612.ssg_mask |= 1<<(OPN_SLOT(r) + c*4);
1687 else ym2612.ssg_mask &= ~(1<<(OPN_SLOT(r) + c*4));
1688 // if (SLOT->state > EG_REL)
1689 // recalc_volout(SLOT);
1690 break;
1691
1692 case 0xa0:
1693 switch( OPN_SLOT(r) ){
1694 case 0: /* 0xa0-0xa2 : FNUM1 | depends on fn_h (below) */
1695 {
1696 UINT32 fn = (((UINT32)( (CH->fn_h)&7))<<8) + v;
1697 UINT8 blk = CH->fn_h>>3;
1698 /* keyscale code */
1699 CH->kcode = (blk<<2) | opn_fktable[fn >> 7];
1700 /* phase increment counter */
1701 CH->fc = fn_table[fn*2]>>(7-blk);
1702
1703 /* store fnum in clear form for LFO PM calculations */
1704 CH->block_fnum = (blk<<11) | fn;
1705
1706 CH->SLOT[SLOT1].Incr=-1;
1707 }
1708 break;
1709 case 1: /* 0xa4-0xa6 : FNUM2,BLK */
1710 CH->fn_h = v&0x3f;
1711 ret = 0;
1712 break;
1713 case 2: /* 0xa8-0xaa : 3CH FNUM1 */
1714 if(r < 0x100)
1715 {
1716 UINT32 fn = (((UINT32)(ym2612.OPN.SL3.fn_h&7))<<8) + v;
1717 UINT8 blk = ym2612.OPN.SL3.fn_h>>3;
1718 /* keyscale code */
1719 ym2612.OPN.SL3.kcode[c]= (blk<<2) | opn_fktable[fn >> 7];
1720 /* phase increment counter */
1721 ym2612.OPN.SL3.fc[c] = fn_table[fn*2]>>(7-blk);
1722 ym2612.OPN.SL3.block_fnum[c] = (blk<<11) | fn;
1723 ym2612.CH[2].SLOT[SLOT1].Incr=-1;
1724 }
1725 break;
1726 case 3: /* 0xac-0xae : 3CH FNUM2,BLK */
1727 if(r < 0x100)
1728 ym2612.OPN.SL3.fn_h = v&0x3f;
1729 ret = 0;
1730 break;
1731 default:
1732 ret = 0;
1733 break;
1734 }
1735 break;
1736
1737 case 0xb0:
1738 switch( OPN_SLOT(r) ){
1739 case 0: /* 0xb0-0xb2 : FB,ALGO */
1740 {
1741 int feedback = (v>>3)&7;
1742 CH->ALGO = v&7;
1743 CH->FB = feedback ? feedback+6 : 0;
1744 }
1745 break;
1746 case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (YM2612/YM2610B/YM2610/YM2608) */
1747 {
1748 int panshift = c<<1;
1749
1750 /* b0-2 PMS */
1751 CH->pms = (v & 7) * 32; /* CH->pms = PM depth * 32 (index in lfo_pm_table) */
1752
1753 /* b4-5 AMS */
1754 CH->ams = lfo_ams_depth_shift[(v>>4) & 3];
1755
1756 /* PAN : b7 = L, b6 = R */
1757 ym2612.OPN.pan &= ~(3<<panshift);
1758 ym2612.OPN.pan |= ((v & 0xc0) >> 6) << panshift; // ..LRLR
1759 }
1760 break;
1761 default:
1762 ret = 0;
1763 break;
1764 }
1765 break;
1766 default:
1767 ret = 0;
1768 break;
1769 }
1770
1771 return ret;
1772 }
1773
1774
1775 /*******************************************************************************/
1776 /* YM2612 local section */
1777 /*******************************************************************************/
1778
1779 /* Generate samples for YM2612 */
YM2612UpdateOne_(int * buffer,int length,int stereo,int is_buf_empty)1780 int YM2612UpdateOne_(int *buffer, int length, int stereo, int is_buf_empty)
1781 {
1782 int pan;
1783 int active_chs = 0;
1784 int flags = stereo ? 1:0;
1785
1786 // if !is_buf_empty, it means it has valid samples to mix with, else it may contain trash
1787 if (is_buf_empty) memset32(buffer, 0, length<<stereo);
1788
1789 /*
1790 {
1791 int c, s;
1792 ppp();
1793 for (c = 0; c < 6; c++) {
1794 int slr = 0, slm;
1795 printf("%i: ", c);
1796 for (s = 0; s < 4; s++) {
1797 if (ym2612.CH[c].SLOT[s].state != EG_OFF) slr = 1;
1798 printf(" %i", ym2612.CH[c].SLOT[s].state != EG_OFF);
1799 }
1800 slm = (ym2612.slot_mask&(0xf<<(c*4))) ? 1 : 0;
1801 printf(" | %i", slm);
1802 printf(" | %i\n", ym2612.CH[c].SLOT[SLOT1].Incr==-1);
1803 if (slr != slm) exit(1);
1804 }
1805 }
1806 */
1807 /* refresh PG and EG */
1808 refresh_fc_eg_chan( &ym2612.CH[0] );
1809 refresh_fc_eg_chan( &ym2612.CH[1] );
1810 if( (ym2612.OPN.ST.mode & 0xc0) )
1811 /* 3SLOT MODE */
1812 refresh_fc_eg_chan_sl3();
1813 else
1814 refresh_fc_eg_chan( &ym2612.CH[2] );
1815 refresh_fc_eg_chan( &ym2612.CH[3] );
1816 refresh_fc_eg_chan( &ym2612.CH[4] );
1817 refresh_fc_eg_chan( &ym2612.CH[5] );
1818
1819 pan = ym2612.OPN.pan;
1820
1821 /* mix to 32bit dest */
1822 // flags: stereo, ssg_enabled, disabled, _, pan_r, pan_l
1823 chan_render_prep();
1824 #define BIT_IF(v,b,c) { v &= ~(1<<(b)); if (c) v |= 1<<(b); }
1825 BIT_IF(flags, 1, (ym2612.ssg_mask & 0x00000f) && (ym2612.OPN.ST.flags & 1));
1826 if (ym2612.slot_mask & 0x00000f) active_chs |= chan_render(buffer, length, 0, flags|((pan&0x003)<<4)) << 0;
1827 BIT_IF(flags, 1, (ym2612.ssg_mask & 0x0000f0) && (ym2612.OPN.ST.flags & 1));
1828 if (ym2612.slot_mask & 0x0000f0) active_chs |= chan_render(buffer, length, 1, flags|((pan&0x00c)<<2)) << 1;
1829 BIT_IF(flags, 1, (ym2612.ssg_mask & 0x000f00) && (ym2612.OPN.ST.flags & 1));
1830 if (ym2612.slot_mask & 0x000f00) active_chs |= chan_render(buffer, length, 2, flags|((pan&0x030) )) << 2;
1831 BIT_IF(flags, 1, (ym2612.ssg_mask & 0x00f000) && (ym2612.OPN.ST.flags & 1));
1832 if (ym2612.slot_mask & 0x00f000) active_chs |= chan_render(buffer, length, 3, flags|((pan&0x0c0)>>2)) << 3;
1833 BIT_IF(flags, 1, (ym2612.ssg_mask & 0x0f0000) && (ym2612.OPN.ST.flags & 1));
1834 if (ym2612.slot_mask & 0x0f0000) active_chs |= chan_render(buffer, length, 4, flags|((pan&0x300)>>4)) << 4;
1835 BIT_IF(flags, 1, (ym2612.ssg_mask & 0xf00000) && (ym2612.OPN.ST.flags & 1));
1836 if (ym2612.slot_mask & 0xf00000) active_chs |= chan_render(buffer, length, 5, flags|((pan&0xc00)>>6)|(!!ym2612.dacen<<2)) << 5;
1837 #undef BIT_IF
1838 chan_render_finish();
1839
1840 return active_chs; // 1 if buffer updated
1841 }
1842
1843
1844 /* initialize YM2612 emulator */
YM2612Init_(int clock,int rate,int ssg)1845 void YM2612Init_(int clock, int rate, int ssg)
1846 {
1847 memset(&ym2612, 0, sizeof(ym2612));
1848 init_tables();
1849
1850 ym2612.OPN.ST.clock = clock;
1851 ym2612.OPN.ST.rate = rate;
1852 ym2612.OPN.ST.flags = (ssg ? 1:0);
1853
1854 OPNSetPres( 6*24 );
1855
1856 /* Extend handler */
1857 YM2612ResetChip_();
1858 }
1859
1860
1861 /* reset */
YM2612ResetChip_(void)1862 void YM2612ResetChip_(void)
1863 {
1864 int i;
1865
1866 memset(ym2612.REGS, 0, sizeof(ym2612.REGS));
1867
1868 set_timers( 0x30 ); /* mode 0 , timer reset */
1869 ym2612.REGS[0x27] = 0x30;
1870
1871 ym2612.OPN.eg_timer = 0;
1872 ym2612.OPN.eg_cnt = 0;
1873 ym2612.OPN.lfo_inc = 0;
1874 ym2612.OPN.lfo_cnt = 0;
1875 g_lfo_ampm = 126 << 8;
1876 ym2612.OPN.ST.status = 0;
1877
1878 reset_channels( &ym2612.CH[0] );
1879 for(i = 0xb6 ; i >= 0xb4 ; i-- )
1880 {
1881 OPNWriteReg(i ,0xc0);
1882 OPNWriteReg(i|0x100,0xc0);
1883 ym2612.REGS[i ] = 0xc0;
1884 ym2612.REGS[i|0x100] = 0xc0;
1885 }
1886 for(i = 0xb2 ; i >= 0x30 ; i-- )
1887 {
1888 OPNWriteReg(i ,0);
1889 OPNWriteReg(i|0x100,0);
1890 }
1891 for(i = 0x26 ; i >= 0x20 ; i-- ) OPNWriteReg(i,0);
1892 /* DAC mode clear */
1893 ym2612.dacen = 0;
1894 ym2612.dacout = 0;
1895 ym2612.addr_A1 = 0;
1896 }
1897
1898
1899 /* YM2612 write */
1900 /* a = address */
1901 /* v = value */
1902 /* returns 1 if sample affecting state changed */
YM2612Write_(unsigned int a,unsigned int v)1903 int YM2612Write_(unsigned int a, unsigned int v)
1904 {
1905 int addr, ret=1;
1906
1907 v &= 0xff; /* adjust to 8 bit bus */
1908
1909 switch( a & 3 ){
1910 case 0: /* address port 0 */
1911 case 2: /* address port 1 */
1912 ym2612.OPN.ST.address = v;
1913 ym2612.addr_A1 = (a & 2) >> 1;
1914 ret = 0;
1915 break;
1916
1917 case 1:
1918 case 3: /* data port */
1919 addr = ym2612.OPN.ST.address | ((int)ym2612.addr_A1 << 8);
1920
1921 switch( addr & 0x1f0 )
1922 {
1923 case 0x20: /* 0x20-0x2f Mode */
1924 switch( addr )
1925 {
1926 case 0x22: /* LFO FREQ (YM2608/YM2610/YM2610B/YM2612) */
1927 if (v&0x08) /* LFO enabled ? */
1928 {
1929 ym2612.OPN.lfo_inc = ym2612.OPN.lfo_freq[v&7];
1930 }
1931 else
1932 {
1933 ym2612.OPN.lfo_inc = 0;
1934 ym2612.OPN.lfo_cnt = 0;
1935 g_lfo_ampm = 126 << 8;
1936 }
1937 break;
1938 #if 0 // handled elsewhere
1939 case 0x24: { // timer A High 8
1940 int TAnew = (ym2612.OPN.ST.TA & 0x03)|(((int)v)<<2);
1941 if(ym2612.OPN.ST.TA != TAnew) {
1942 // we should reset ticker only if new value is written. Outrun requires this.
1943 ym2612.OPN.ST.TA = TAnew;
1944 ym2612.OPN.ST.TAC = (1024-TAnew)*18;
1945 ym2612.OPN.ST.TAT = 0;
1946 }
1947 }
1948 ret=0;
1949 break;
1950 case 0x25: { // timer A Low 2
1951 int TAnew = (ym2612.OPN.ST.TA & 0x3fc)|(v&3);
1952 if(ym2612.OPN.ST.TA != TAnew) {
1953 ym2612.OPN.ST.TA = TAnew;
1954 ym2612.OPN.ST.TAC = (1024-TAnew)*18;
1955 ym2612.OPN.ST.TAT = 0;
1956 }
1957 }
1958 ret=0;
1959 break;
1960 case 0x26: // timer B
1961 if(ym2612.OPN.ST.TB != v) {
1962 ym2612.OPN.ST.TB = v;
1963 ym2612.OPN.ST.TBC = (256-v)<<4;
1964 ym2612.OPN.ST.TBC *= 18;
1965 ym2612.OPN.ST.TBT = 0;
1966 }
1967 ret=0;
1968 break;
1969 #endif
1970 case 0x27: /* mode, timer control */
1971 set_timers( v );
1972 ret=0;
1973 break;
1974 case 0x28: /* key on / off */
1975 {
1976 UINT8 c;
1977
1978 c = v & 0x03;
1979 if( c == 3 ) { ret=0; break; }
1980 if( v&0x04 ) c+=3;
1981 if(v&0x10) FM_KEYON(c,SLOT1); else FM_KEYOFF(c,SLOT1);
1982 if(v&0x20) FM_KEYON(c,SLOT2); else FM_KEYOFF(c,SLOT2);
1983 if(v&0x40) FM_KEYON(c,SLOT3); else FM_KEYOFF(c,SLOT3);
1984 if(v&0x80) FM_KEYON(c,SLOT4); else FM_KEYOFF(c,SLOT4);
1985 break;
1986 }
1987 case 0x2a: /* DAC data (YM2612) */
1988 ym2612.dacout = ((int)v - 0x80) << 6; /* level unknown (notaz: 8 seems to be too much) */
1989 ret=0;
1990 break;
1991 case 0x2b: /* DAC Sel (YM2612) */
1992 /* b7 = dac enable */
1993 ym2612.dacen = v & 0x80;
1994 ret=0;
1995 break;
1996 default:
1997 break;
1998 }
1999 break;
2000 default: /* 0x30-0xff OPN section */
2001 /* write register */
2002 ret = OPNWriteReg(addr,v);
2003 }
2004 break;
2005 }
2006
2007 return ret;
2008 }
2009
2010 #if 0
2011 UINT8 YM2612Read_(void)
2012 {
2013 return ym2612.OPN.ST.status;
2014 }
2015
2016 int YM2612PicoTick_(int n)
2017 {
2018 int ret = 0;
2019
2020 // timer A
2021 if(ym2612.OPN.ST.mode & 0x01 && (ym2612.OPN.ST.TAT+=64*n) >= ym2612.OPN.ST.TAC) {
2022 ym2612.OPN.ST.TAT -= ym2612.OPN.ST.TAC;
2023 if(ym2612.OPN.ST.mode & 0x04) ym2612.OPN.ST.status |= 1;
2024 // CSM mode total level latch and auto key on
2025 if(ym2612.OPN.ST.mode & 0x80) {
2026 CSMKeyControll( &(ym2612.CH[2]) ); // Vectorman2, etc.
2027 ret = 1;
2028 }
2029 }
2030
2031 // timer B
2032 if(ym2612.OPN.ST.mode & 0x02 && (ym2612.OPN.ST.TBT+=64*n) >= ym2612.OPN.ST.TBC) {
2033 ym2612.OPN.ST.TBT -= ym2612.OPN.ST.TBC;
2034 if(ym2612.OPN.ST.mode & 0x08) ym2612.OPN.ST.status |= 2;
2035 }
2036
2037 return ret;
2038 }
2039 #endif
2040
YM2612PicoStateLoad_(void)2041 void YM2612PicoStateLoad_(void)
2042 {
2043 reset_channels( &ym2612.CH[0] );
2044 ym2612.slot_mask = 0xffffff;
2045 }
2046
2047 /* rather stupid design because I wanted to fit in unused register "space" */
2048 typedef struct
2049 {
2050 UINT32 state_phase;
2051 INT16 volume;
2052 } ym_save_addon_slot;
2053
2054 typedef struct
2055 {
2056 UINT32 magic;
2057 UINT8 address;
2058 UINT8 status;
2059 UINT8 addr_A1;
2060 UINT8 unused;
2061 int TAT;
2062 int TBT;
2063 UINT32 eg_cnt; // 10
2064 UINT32 eg_timer;
2065 UINT32 lfo_cnt;
2066 UINT16 lfo_ampm;
2067 UINT16 unused2;
2068 UINT32 keyon_field; // 20
2069 UINT32 kcode_fc_sl3_3;
2070 UINT32 reserved[2];
2071 } ym_save_addon;
2072
2073 typedef struct
2074 {
2075 UINT16 block_fnum[6];
2076 UINT16 block_fnum_sl3[3];
2077 UINT16 reserved[7];
2078 } ym_save_addon2;
2079
2080
YM2612PicoStateSave2(int tat,int tbt)2081 void YM2612PicoStateSave2(int tat, int tbt)
2082 {
2083 ym_save_addon_slot ss;
2084 ym_save_addon2 sa2;
2085 ym_save_addon sa;
2086 unsigned char *ptr;
2087 int c, s;
2088
2089 memset(&sa, 0, sizeof(sa));
2090 memset(&sa2, 0, sizeof(sa2));
2091
2092 // chans 1,2,3
2093 ptr = &ym2612.REGS[0x0b8];
2094 for (c = 0; c < 3; c++)
2095 {
2096 for (s = 0; s < 4; s++) {
2097 ss.state_phase = (ym2612.CH[c].SLOT[s].state << 29) | (ym2612.CH[c].SLOT[s].phase >> 3);
2098 ss.volume = ym2612.CH[c].SLOT[s].volume;
2099 if (ym2612.CH[c].SLOT[s].key)
2100 sa.keyon_field |= 1 << (c*4 + s);
2101 memcpy(ptr, &ss, 6);
2102 ptr += 6;
2103 }
2104 sa2.block_fnum[c] = ym2612.CH[c].block_fnum;
2105 }
2106 // chans 4,5,6
2107 ptr = &ym2612.REGS[0x1b8];
2108 for (; c < 6; c++)
2109 {
2110 for (s = 0; s < 4; s++) {
2111 ss.state_phase = (ym2612.CH[c].SLOT[s].state << 29) | (ym2612.CH[c].SLOT[s].phase >> 3);
2112 ss.volume = ym2612.CH[c].SLOT[s].volume;
2113 if (ym2612.CH[c].SLOT[s].key)
2114 sa.keyon_field |= 1 << (c*4 + s);
2115 memcpy(ptr, &ss, 6);
2116 ptr += 6;
2117 }
2118 sa2.block_fnum[c] = ym2612.CH[c].block_fnum;
2119 }
2120 for (c = 0; c < 3; c++)
2121 {
2122 sa2.block_fnum_sl3[c] = ym2612.OPN.SL3.block_fnum[c];
2123 }
2124
2125 memcpy(&ym2612.REGS[0], &sa2, sizeof(sa2)); // 0x20 max
2126
2127 // other things
2128 ptr = &ym2612.REGS[0x100];
2129 sa.magic = 0x41534d59; // 'YMSA'
2130 sa.address = ym2612.OPN.ST.address;
2131 sa.status = ym2612.OPN.ST.status;
2132 sa.addr_A1 = ym2612.addr_A1;
2133 sa.TAT = tat;
2134 sa.TBT = tbt;
2135 sa.eg_cnt = ym2612.OPN.eg_cnt;
2136 sa.eg_timer = ym2612.OPN.eg_timer;
2137 sa.lfo_cnt = ym2612.OPN.lfo_cnt;
2138 sa.lfo_ampm = g_lfo_ampm;
2139 memcpy(ptr, &sa, sizeof(sa)); // 0x30 max
2140 }
2141
YM2612PicoStateLoad2(int * tat,int * tbt)2142 int YM2612PicoStateLoad2(int *tat, int *tbt)
2143 {
2144 ym_save_addon_slot ss;
2145 ym_save_addon2 sa2;
2146 ym_save_addon sa;
2147 unsigned char *ptr;
2148 UINT32 fn;
2149 UINT8 blk;
2150 int c, s;
2151
2152 ptr = &ym2612.REGS[0x100];
2153 memcpy(&sa, ptr, sizeof(sa)); // 0x30 max
2154 if (sa.magic != 0x41534d59) return -1;
2155
2156 ptr = &ym2612.REGS[0];
2157 memcpy(&sa2, ptr, sizeof(sa2));
2158
2159 ym2612.OPN.ST.address = sa.address;
2160 ym2612.OPN.ST.status = sa.status;
2161 ym2612.addr_A1 = sa.addr_A1;
2162 ym2612.OPN.eg_cnt = sa.eg_cnt;
2163 ym2612.OPN.eg_timer = sa.eg_timer;
2164 ym2612.OPN.lfo_cnt = sa.lfo_cnt;
2165 g_lfo_ampm = sa.lfo_ampm;
2166 if (tat != NULL) *tat = sa.TAT;
2167 if (tbt != NULL) *tbt = sa.TBT;
2168
2169 // chans 1,2,3
2170 ptr = &ym2612.REGS[0x0b8];
2171 for (c = 0; c < 3; c++)
2172 {
2173 for (s = 0; s < 4; s++) {
2174 memcpy(&ss, ptr, 6);
2175 ym2612.CH[c].SLOT[s].state = ss.state_phase >> 29;
2176 ym2612.CH[c].SLOT[s].phase = ss.state_phase << 3;
2177 ym2612.CH[c].SLOT[s].volume = ss.volume;
2178 ym2612.CH[c].SLOT[s].key = (sa.keyon_field & (1 << (c*4 + s))) ? 1 : 0;
2179 ym2612.CH[c].SLOT[s].ksr = (UINT8)-1;
2180 ptr += 6;
2181 }
2182 ym2612.CH[c].SLOT[SLOT1].Incr=-1;
2183 ym2612.CH[c].block_fnum = sa2.block_fnum[c];
2184 fn = ym2612.CH[c].block_fnum & 0x7ff;
2185 blk = ym2612.CH[c].block_fnum >> 11;
2186 ym2612.CH[c].kcode= (blk<<2) | opn_fktable[fn >> 7];
2187 ym2612.CH[c].fc = fn_table[fn*2]>>(7-blk);
2188 }
2189 // chans 4,5,6
2190 ptr = &ym2612.REGS[0x1b8];
2191 for (; c < 6; c++)
2192 {
2193 for (s = 0; s < 4; s++) {
2194 memcpy(&ss, ptr, 6);
2195 ym2612.CH[c].SLOT[s].state = ss.state_phase >> 29;
2196 ym2612.CH[c].SLOT[s].phase = ss.state_phase << 3;
2197 ym2612.CH[c].SLOT[s].volume = ss.volume;
2198 ym2612.CH[c].SLOT[s].key = (sa.keyon_field & (1 << (c*4 + s))) ? 1 : 0;
2199 ym2612.CH[c].SLOT[s].ksr = (UINT8)-1;
2200 ptr += 6;
2201 }
2202 ym2612.CH[c].SLOT[SLOT1].Incr=-1;
2203 ym2612.CH[c].block_fnum = sa2.block_fnum[c];
2204 fn = ym2612.CH[c].block_fnum & 0x7ff;
2205 blk = ym2612.CH[c].block_fnum >> 11;
2206 ym2612.CH[c].kcode= (blk<<2) | opn_fktable[fn >> 7];
2207 ym2612.CH[c].fc = fn_table[fn*2]>>(7-blk);
2208 }
2209 for (c = 0; c < 3; c++)
2210 {
2211 ym2612.OPN.SL3.block_fnum[c] = sa2.block_fnum_sl3[c];
2212 fn = ym2612.OPN.SL3.block_fnum[c] & 0x7ff;
2213 blk = ym2612.OPN.SL3.block_fnum[c] >> 11;
2214 ym2612.OPN.SL3.kcode[c]= (blk<<2) | opn_fktable[fn >> 7];
2215 ym2612.OPN.SL3.fc[c] = fn_table[fn*2]>>(7-blk);
2216 }
2217
2218 return 0;
2219 }
2220
YM2612GetRegs(void)2221 void *YM2612GetRegs(void)
2222 {
2223 return ym2612.REGS;
2224 }
2225
2226