1 /***************************************************************************** 2 * 3 * mcs51.h 4 * Portable MCS-51 Family Emulator 5 * 6 * Chips in the family: 7 * 8051 Product Line (8031,8051,8751) 8 * 8052 Product Line (8032,8052,8752) 9 * 8054 Product Line (8054) 10 * 8058 Product Line (8058) 11 * 12 * Copyright Steve Ellenoff, all rights reserved. 13 * 14 * - This source code is released as freeware for non-commercial purposes. 15 * - You are free to use and redistribute this code in modified or 16 * unmodified form, provided you list me in the credits. 17 * - If you modify this source code, you must add a notice to each modified 18 * source file that it has been changed. If you're a nice person, you 19 * will clearly mark each change too. :) 20 * - If you wish to use this for commercial purposes, please contact me at 21 * sellenoff@hotmail.com 22 * - The author of this copywritten work reserves the right to change the 23 * terms of its usage and license at any time, including retroactively 24 * - This entire notice must remain in the source code. 25 * 26 * This work is based on: 27 * #1) 'Intel(tm) MC51 Microcontroller Family Users Manual' and 28 * #2) 8051 simulator by Travis Marlatte 29 * #3) Portable UPI-41/8041/8741/8042/8742 emulator V0.1 by Juergen Buchmueller (MAME CORE) 30 * 31 * 2008, October, Couriersud 32 * - Rewrite of timer, interrupt and serial code 33 * - addition of CMOS features 34 * - internal memory maps 35 * - addition of new processor types 36 * - full emulation of 8xCx2 processors 37 *****************************************************************************/ 38 39 #pragma once 40 41 #ifndef __MCS51_H__ 42 #define __MCS51_H__ 43 44 45 enum 46 { 47 MCS51_PC=1, MCS51_SP, MCS51_PSW, MCS51_ACC, MCS51_B, MCS51_DPH, MCS51_DPL, MCS51_IE, 48 MCS51_R0, MCS51_R1, MCS51_R2, MCS51_R3, MCS51_R4, MCS51_R5, MCS51_R6, MCS51_R7, MCS51_RB 49 }; 50 51 enum 52 { 53 MCS51_INT0_LINE = 0, /* P3.2: External Interrupt 0 */ 54 MCS51_INT1_LINE, /* P3.3: External Interrupt 1 */ 55 MCS51_RX_LINE, /* P3.0: Serial Port Receive Line */ 56 MCS51_T0_LINE, /* P3,4: Timer 0 External Input */ 57 MCS51_T1_LINE, /* P3.5: Timer 1 External Input */ 58 MCS51_T2_LINE, /* P1.0: Timer 2 External Input */ 59 MCS51_T2EX_LINE, /* P1.1: Timer 2 Capture Reload Trigger */ 60 61 DS5002FP_PFI_LINE /* DS5002FP Power fail interrupt */ 62 }; 63 64 /* special I/O space ports */ 65 66 enum 67 { 68 MCS51_PORT_P0 = 0x20000, 69 MCS51_PORT_P1 = 0x20001, 70 MCS51_PORT_P2 = 0x20002, 71 MCS51_PORT_P3 = 0x20003, 72 MCS51_PORT_TX = 0x20004 /* P3.1 */ 73 }; 74 75 /*************************************************************************** 76 CONFIGURATION 77 ***************************************************************************/ 78 79 /* configuration of the DS5002FP */ 80 typedef struct _ds5002fp_config ds5002fp_config; 81 struct _ds5002fp_config 82 { 83 UINT8 mcon; /* bootstrap loader MCON register */ 84 UINT8 rpctl; /* bootstrap loader RPCTL register */ 85 UINT8 crc; /* bootstrap loader CRC register */ 86 }; 87 88 /*************************************************************************** 89 FUNCTION PROTOTYPES 90 ***************************************************************************/ 91 extern void mcs51_init(void); /* Initialize cpu */ 92 extern void mcs51_reset(void); /* Reset registers to the initial values */ 93 extern void mcs51_exit(void); /* Shut down CPU core */ 94 extern INT32 mcs51Run(int cycles); /* /12 ! Execute cycles - returns number of cycles actually run */ 95 extern void mcs51RunEnd(void); /* stop execution */ 96 extern void mcs51_set_irq_line(int irqline, int state); 97 void mcs51_iram_fill(UINT8 *src, UINT32 size); 98 void mcs51_iram_get(UINT8 *dst, UINT32 size); 99 void mcs51_set_write_handler(void (*pointer)(INT32,UINT8)); 100 void mcs51_set_read_handler(UINT8 (*pointer)(INT32)); 101 void mcs51_scan(INT32 nAction); 102 extern UINT8 *mcs51_program_data; 103 104 extern void ds5002fp_init(UINT8 mcon, UINT8 rpctl, UINT8 crc); // default: 0, 0, 0 105 #define ds5002fp_reset mcs51_reset 106 #define ds5002fp_exit mcs51_exit 107 #define ds5002fpRun mcs51Run 108 #define ds5002fpRunEnd mcs51RunEnd 109 #define ds5002fp_set_irq_line mcs51_set_irq_line 110 #define ds5002fp_set_write_handler mcs51_set_write_handler 111 #define ds5002fp_set_read_handler mcs51_set_read_handler 112 #define ds5002fp_scan mcs51_scan 113 #define ds5002fp_program_data mcs51_program_data 114 #define ds5002fp_iram_fill mcs51_iram_fill 115 #define ds5002fp_iram_get mcs51_iram_get 116 117 #if 0 118 typedef void (*mcs51_serial_tx_func)(device_t *device, int data); 119 typedef int (*mcs51_serial_rx_func)(device_t *device); 120 121 extern void i8051_set_serial_tx_callback(device_t *device, mcs51_serial_tx_func tx_func); 122 extern void i8051_set_serial_rx_callback(device_t *device, mcs51_serial_rx_func rx_func); 123 124 /* variants with no internal rom and 128 byte internal memory */ 125 DECLARE_LEGACY_CPU_DEVICE(I8031, i8031); 126 127 /* variants with no internal rom and 256 byte internal memory */ 128 DECLARE_LEGACY_CPU_DEVICE(I8032, i8032); 129 130 /* variants 4k internal rom and 128 byte internal memory */ 131 DECLARE_LEGACY_CPU_DEVICE(I8051, i8051); 132 DECLARE_LEGACY_CPU_DEVICE(I8751, i8751); 133 134 /* variants 8k internal rom and 256 byte internal memory and more registers */ 135 DECLARE_LEGACY_CPU_DEVICE(I8052, i8052); 136 DECLARE_LEGACY_CPU_DEVICE(I8752, i8752); 137 138 /* cmos variants */ 139 DECLARE_LEGACY_CPU_DEVICE(I80C31, i80c31); 140 DECLARE_LEGACY_CPU_DEVICE(I80C51, i80c51); 141 DECLARE_LEGACY_CPU_DEVICE(I87C51, i87c51); 142 143 DECLARE_LEGACY_CPU_DEVICE(I80C32, i80c32); 144 DECLARE_LEGACY_CPU_DEVICE(I80C52, i80c52); 145 DECLARE_LEGACY_CPU_DEVICE(I87C52, i87c52); 146 147 /* 4k internal perom and 128 internal ram and 2 analog comparators */ 148 DECLARE_LEGACY_CPU_DEVICE(AT89C4051, at89c4051); 149 150 /* 151 * The DS5002FP has 2 16 bits data address buses (the byte-wide bus and the expanded bus). The exact memory position accessed depends on the 152 * partition mode, the memory range and the expanded bus select. The partition mode and the expanded bus select can be changed at any time. 153 * 154 * In order to simplify memory mapping to the data address bus, the following address map is assumed for partitioned mode: 155 156 * 0x00000-0x0ffff -> data memory on the expanded bus 157 * 0x10000-0x1ffff -> data memory on the byte-wide bus 158 159 * For non-partitioned mode the following memory map is assumed: 160 161 * 0x0000-0xffff -> data memory (the bus used to access it does not matter) 162 * 163 * Internal ram 128k and security features 164 */ 165 166 DECLARE_LEGACY_CPU_DEVICE(DS5002FP, ds5002fp); 167 168 169 /**************************************************************************** 170 * Disassembler 171 ****************************************************************************/ 172 173 CPU_DISASSEMBLE( i8051 ); 174 CPU_DISASSEMBLE( i80c51 ); 175 CPU_DISASSEMBLE( i8052 ); 176 CPU_DISASSEMBLE( i80c52 ); 177 CPU_DISASSEMBLE( ds5002fp ); 178 #endif 179 180 #endif /* __MCS51_H__ */ 181