1 /* ======================================================================== */ 2 /* ============================= CONFIGURATION ============================ */ 3 /* ======================================================================== */ 4 5 #undef FLAG_SET_M 6 #undef FLAG_SET_X 7 8 #if EXECUTION_MODE == EXECUTION_MODE_M0X0 9 #define FLAG_SET_M 0 10 #define FLAG_SET_X 0 11 #elif EXECUTION_MODE == EXECUTION_MODE_M0X1 12 #define FLAG_SET_M 0 13 #define FLAG_SET_X 1 14 #elif EXECUTION_MODE == EXECUTION_MODE_M1X0 15 #define FLAG_SET_M 1 16 #define FLAG_SET_X 0 17 #elif EXECUTION_MODE == EXECUTION_MODE_M1X1 18 #define FLAG_SET_M 1 19 #define FLAG_SET_X 1 20 #endif 21 22 /* ======================================================================== */ 23 /* ============================ STATUS REGISTER =========================== */ 24 /* ======================================================================== */ 25 26 /* note: difference from 65816. when switching to 8-bit X/Y, X and Y are *not* truncated 27 to 8 bits! */ 28 29 30 /* ======================================================================== */ 31 /* =========================== OPERATION MACROS =========================== */ 32 /* ======================================================================== */ 33 34 /* M37710 Push all */ 35 #undef OP_PSH 36 37 #if FLAG_SET_M 38 #if FLAG_SET_X 39 #define OP_PSH(MODE) \ 40 SRC = OPER_8_##MODE(); \ 41 CLK(12); \ 42 if (SRC&0x1) \ 43 { m37710i_push_8(REG_A); CLK(2); } \ 44 if (SRC&0x2) \ 45 { m37710i_push_8(REG_BA); CLK(2); } \ 46 if (SRC&0x4) \ 47 { m37710i_push_8(REG_X); CLK(2); } \ 48 if (SRC&0x8) \ 49 { m37710i_push_8(REG_Y); CLK(2); } \ 50 if (SRC&0x10) \ 51 { m37710i_push_16(REG_D); CLK(2); } \ 52 if (SRC&0x20) \ 53 { m37710i_push_8(REG_DB>>16); CLK(1); } \ 54 if (SRC&0x40) \ 55 { m37710i_push_8(REG_PB>>16); CLK(1); } \ 56 if (SRC&0x80) \ 57 { m37710i_push_8(m377.ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } 58 #else // FLAG_SET_X 59 #define OP_PSH(MODE) \ 60 SRC = OPER_8_##MODE(); \ 61 CLK(12); \ 62 if (SRC&0x1) \ 63 { m37710i_push_8(REG_A); CLK(2); } \ 64 if (SRC&0x2) \ 65 { m37710i_push_8(REG_BA); CLK(2); } \ 66 if (SRC&0x4) \ 67 { m37710i_push_16(REG_X); CLK(2); } \ 68 if (SRC&0x8) \ 69 { m37710i_push_16(REG_Y); CLK(2); } \ 70 if (SRC&0x10) \ 71 { m37710i_push_16(REG_D); CLK(2); } \ 72 if (SRC&0x20) \ 73 { m37710i_push_8(REG_DB>>16); CLK(1); } \ 74 if (SRC&0x40) \ 75 { m37710i_push_8(REG_PB>>16); CLK(1); } \ 76 if (SRC&0x80) \ 77 { m37710i_push_8(m377.ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } 78 #endif // FLAG_SET_X 79 #else // FLAG_SET_M 80 #if FLAG_SET_X 81 #define OP_PSH(MODE) \ 82 SRC = OPER_8_##MODE(); \ 83 CLK(12); \ 84 if (SRC&0x1) \ 85 { m37710i_push_16(REG_A); CLK(2); } \ 86 if (SRC&0x2) \ 87 { m37710i_push_16(REG_BA); CLK(2); } \ 88 if (SRC&0x4) \ 89 { m37710i_push_8(REG_X); CLK(2); } \ 90 if (SRC&0x8) \ 91 { m37710i_push_8(REG_Y); CLK(2); } \ 92 if (SRC&0x10) \ 93 { m37710i_push_16(REG_D); CLK(2); } \ 94 if (SRC&0x20) \ 95 { m37710i_push_8(REG_DB>>16); CLK(1); } \ 96 if (SRC&0x40) \ 97 { m37710i_push_8(REG_PB>>16); CLK(1); } \ 98 if (SRC&0x80) \ 99 { m37710i_push_8(m377.ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } 100 #else // FLAG_SET_X 101 #define OP_PSH(MODE) \ 102 SRC = OPER_8_##MODE(); \ 103 CLK(12); \ 104 if (SRC&0x1) \ 105 { m37710i_push_16(REG_A); CLK(2); } \ 106 if (SRC&0x2) \ 107 { m37710i_push_16(REG_BA); CLK(2);} \ 108 if (SRC&0x4) \ 109 { m37710i_push_16(REG_X); CLK(2); } \ 110 if (SRC&0x8) \ 111 { m37710i_push_16(REG_Y); CLK(2); } \ 112 if (SRC&0x10) \ 113 { m37710i_push_16(REG_D); CLK(2); } \ 114 if (SRC&0x20) \ 115 { m37710i_push_8(REG_DB>>16); CLK(1); } \ 116 if (SRC&0x40) \ 117 { m37710i_push_8(REG_PB>>16); CLK(1); } \ 118 if (SRC&0x80) \ 119 { m37710i_push_8(m377.ipl); m37710i_push_8(m37710i_get_reg_p()); CLK(2); } 120 #endif // FLAG_SET_X 121 #endif // FLAG_SET_M 122 123 /* M37710 Pull all */ 124 /* Unusual behavior: bit 6 has no effect */ 125 #undef OP_PUL 126 #define OP_PUL(MODE) \ 127 SRC = OPER_8_##MODE(); \ 128 CLK(14); \ 129 if (SRC&0x80) \ 130 { m37710i_set_reg_p(m37710i_pull_8()); m37710i_set_reg_ipl(m37710i_pull_8()); CLK(3); } \ 131 if (SRC&0x20) \ 132 { REG_DB = m37710i_pull_8() << 16; CLK(3); } \ 133 if (SRC&0x10) \ 134 { REG_D = m37710i_pull_16(); CLK(4); } \ 135 if (m37710i_get_reg_p() & XFLAG_SET) \ 136 { \ 137 if (SRC&0x8) \ 138 { REG_Y = m37710i_pull_8(); CLK(3); } \ 139 if (SRC&0x4) \ 140 { REG_X = m37710i_pull_8(); CLK(3); } \ 141 } \ 142 else \ 143 { \ 144 if (SRC&0x8) \ 145 { REG_Y = m37710i_pull_16(); CLK(3); } \ 146 if (SRC&0x4) \ 147 { REG_X = m37710i_pull_16(); CLK(3); } \ 148 } \ 149 if (m37710i_get_reg_p() & MFLAG_SET) \ 150 { \ 151 if (SRC&0x2) \ 152 { REG_BA = m37710i_pull_8(); CLK(3); } \ 153 if (SRC&0x1) \ 154 { REG_A = m37710i_pull_8(); CLK(3); } \ 155 } \ 156 else \ 157 { \ 158 if (SRC&0x2) \ 159 { REG_BA = m37710i_pull_16(); CLK(3); } \ 160 if (SRC&0x1) \ 161 { REG_A = m37710i_pull_16(); CLK(3); } \ 162 } \ 163 m37710i_update_irqs() 164 165 /* M37710 Multiply */ 166 #undef OP_MPY 167 #if FLAG_SET_M 168 #define OP_MPY(MODE) \ 169 CLK(CLK_OP + CLK_R8 + CLK_##MODE + 14); \ 170 SRC = OPER_8_##MODE(); \ 171 { UINT16 temp = SRC * (REG_A&0xff); REG_A = temp & 0xff; REG_BA = (temp>>8)&0xff; FLAG_Z = temp; FLAG_N = (temp & 0x8000) ? 1 : 0; FLAG_C = 0; } 172 #else 173 #define OP_MPY(MODE) \ 174 CLK(CLK_OP + CLK_R16 + CLK_##MODE + 14+8); \ 175 SRC = OPER_16_##MODE(); \ 176 { UINT32 temp = SRC * REG_A; REG_A = temp & 0xffff; REG_BA = (temp>>16)&0xffff; FLAG_Z = temp; FLAG_N = (temp & 0x80000000) ? 1 : 0; FLAG_C = 0; } 177 #endif 178 179 /* M37710 Divide */ 180 #undef OP_DIV 181 #if FLAG_SET_M 182 #define OP_DIV(MODE) \ 183 CLK(CLK_OP + CLK_R8 + CLK_##MODE + 17); \ 184 SRC = (REG_BA&0xff)<<8 | (REG_A & 0xff); \ 185 DST = OPER_8_##MODE(); \ 186 if (DST != 0) \ 187 { \ 188 UINT16 tempa = SRC / DST; UINT16 tempb = SRC % DST; \ 189 FLAG_V = ((tempa | tempb) & 0xff00) ? VFLAG_SET : 0; \ 190 FLAG_C = FLAG_V ? CFLAG_SET : 0; \ 191 if (!FLAG_V) { FLAG_N = (tempa & 0x80) ? 1 : 0; } \ 192 FLAG_Z = REG_A = tempa & 0xff; REG_BA = tempb & 0xff; \ 193 CLK(8); \ 194 } else m37710i_interrupt_software(0xfffc) 195 #else 196 #define OP_DIV(MODE) \ 197 CLK(CLK_OP + CLK_R16 + CLK_##MODE + 17); \ 198 SRC = (REG_BA<<16) | REG_A; \ 199 DST = OPER_16_##MODE(); \ 200 if (DST != 0) \ 201 { \ 202 UINT32 tempa = SRC / DST; UINT32 tempb = SRC % DST; \ 203 FLAG_V = ((tempa | tempb) & 0xffff0000) ? VFLAG_SET : 0; \ 204 FLAG_C = FLAG_V ? CFLAG_SET : 0; \ 205 if (!FLAG_V) { FLAG_N = (tempa & 0x8000) ? 1 : 0; } \ 206 FLAG_Z = REG_A = tempa & 0xffff; REG_BA = tempb & 0xffff; \ 207 CLK(8+15); \ 208 } else m37710i_interrupt_software(0xfffc) 209 #endif 210 211 /* M37710 Add With Carry */ 212 #undef OP_ADC 213 #if FLAG_SET_M 214 #define OP_ADC(MODE) \ 215 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 216 SRC = OPER_8_##MODE(); \ 217 FLAG_C = REG_A + SRC + CFLAG_AS_1(); \ 218 if(FLAG_D) \ 219 { \ 220 if((FLAG_C & 0xf) > 9) \ 221 FLAG_C+=6; \ 222 if((FLAG_C & 0xf0) > 0x90) \ 223 FLAG_C+=0x60; \ 224 } \ 225 FLAG_V = VFLAG_ADD_8(SRC, REG_A, FLAG_C); \ 226 FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C) 227 #else 228 #define OP_ADC(MODE) \ 229 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 230 SRC = OPER_16_##MODE(); \ 231 if(!FLAG_D) \ 232 { \ 233 FLAG_C = REG_A + SRC + CFLAG_AS_1(); \ 234 FLAG_V = VFLAG_ADD_16(SRC, REG_A, FLAG_C); \ 235 FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \ 236 FLAG_N = NFLAG_16(REG_A); \ 237 FLAG_C = CFLAG_16(FLAG_C); \ 238 BREAKOUT; \ 239 } \ 240 FLAG_C = MAKE_UINT_8(REG_A) + MAKE_UINT_8(SRC) + CFLAG_AS_1(); \ 241 if((FLAG_C & 0xf) > 9) \ 242 FLAG_C+=6; \ 243 if((FLAG_C & 0xf0) > 0x90) \ 244 FLAG_C+=0x60; \ 245 FLAG_Z = MAKE_UINT_8(FLAG_C); \ 246 \ 247 FLAG_C = MAKE_UINT_8(REG_A>>8) + MAKE_UINT_8(SRC>>8) + CFLAG_AS_1(); \ 248 if((FLAG_C & 0xf) > 9) \ 249 FLAG_C+=6; \ 250 if((FLAG_C & 0xf0) > 0x90) \ 251 FLAG_C+=0x60; \ 252 FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \ 253 FLAG_N = NFLAG_16(FLAG_Z); \ 254 FLAG_V = VFLAG_ADD_16(SRC, REG_A, FLAG_C); \ 255 REG_A = FLAG_Z 256 #endif 257 258 /* M37710 Add With Carry - B accumulator*/ 259 #undef OP_ADCB 260 #if FLAG_SET_M 261 #define OP_ADCB(MODE) \ 262 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 263 SRC = OPER_8_##MODE(); \ 264 FLAG_C = REG_BA + SRC + CFLAG_AS_1(); \ 265 if(FLAG_D) \ 266 { \ 267 if((FLAG_C & 0xf) > 9) \ 268 FLAG_C+=6; \ 269 if((FLAG_C & 0xf0) > 0x90) \ 270 FLAG_C+=0x60; \ 271 } \ 272 FLAG_V = VFLAG_ADD_8(SRC, REG_BA, FLAG_C); \ 273 FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C) 274 #else 275 #define OP_ADCB(MODE) \ 276 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 277 SRC = OPER_16_##MODE(); \ 278 if(!FLAG_D) \ 279 { \ 280 FLAG_C = REG_BA + SRC + CFLAG_AS_1(); \ 281 FLAG_V = VFLAG_ADD_16(SRC, REG_BA, FLAG_C); \ 282 FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \ 283 FLAG_N = NFLAG_16(REG_BA); \ 284 FLAG_C = CFLAG_16(FLAG_C); \ 285 BREAKOUT; \ 286 } \ 287 FLAG_C = MAKE_UINT_8(REG_BA) + MAKE_UINT_8(SRC) + CFLAG_AS_1(); \ 288 if((FLAG_C & 0xf) > 9) \ 289 FLAG_C+=6; \ 290 if((FLAG_C & 0xf0) > 0x90) \ 291 FLAG_C+=0x60; \ 292 FLAG_Z = MAKE_UINT_8(FLAG_C); \ 293 \ 294 FLAG_C = MAKE_UINT_8(REG_BA>>8) + MAKE_UINT_8(SRC>>8) + CFLAG_AS_1(); \ 295 if((FLAG_C & 0xf) > 9) \ 296 FLAG_C+=6; \ 297 if((FLAG_C & 0xf0) > 0x90) \ 298 FLAG_C+=0x60; \ 299 FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \ 300 FLAG_N = NFLAG_16(FLAG_Z); \ 301 FLAG_V = VFLAG_ADD_16(SRC, REG_BA, FLAG_C); \ 302 REG_BA = FLAG_Z 303 #endif 304 305 /* M37710 Logical AND with accumulator */ 306 #undef OP_AND 307 #if FLAG_SET_M 308 #define OP_AND(MODE) \ 309 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 310 FLAG_N = FLAG_Z = REG_A &= OPER_8_##MODE() 311 #else 312 #define OP_AND(MODE) \ 313 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 314 FLAG_Z = REG_A &= OPER_16_##MODE(); \ 315 FLAG_N = NFLAG_16(REG_A) 316 #endif 317 318 /* M37710 Logical AND with B accumulator */ 319 #undef OP_ANDB 320 #if FLAG_SET_M 321 #define OP_ANDB(MODE) \ 322 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 323 FLAG_N = FLAG_Z = REG_BA &= OPER_8_##MODE() 324 #else 325 #define OP_ANDB(MODE) \ 326 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 327 FLAG_Z = REG_BA &= OPER_16_##MODE(); \ 328 FLAG_N = NFLAG_16(REG_BA) 329 #endif 330 331 /* M37710 Arithmetic Shift Left accumulator */ 332 #undef OP_ASL 333 #if FLAG_SET_M 334 #define OP_ASL() \ 335 CLK(CLK_OP + CLK_IMPLIED); \ 336 FLAG_C = REG_A << 1; \ 337 FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C) 338 #else 339 #define OP_ASL() \ 340 CLK(CLK_OP + CLK_IMPLIED); \ 341 FLAG_C = REG_A << 1; \ 342 FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \ 343 FLAG_N = NFLAG_16(FLAG_C); \ 344 FLAG_C = CFLAG_16(FLAG_C) 345 #endif 346 347 /* M37710 Arithmetic Shift Left B accumulator */ 348 #undef OP_BSL 349 #if FLAG_SET_M 350 #define OP_BSL() \ 351 CLK(CLK_OP + CLK_IMPLIED); \ 352 FLAG_C = REG_BA << 1; \ 353 FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C) 354 #else 355 #define OP_BSL() \ 356 CLK(CLK_OP + CLK_IMPLIED); \ 357 FLAG_C = REG_BA << 1; \ 358 FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \ 359 FLAG_N = NFLAG_16(FLAG_C); \ 360 FLAG_C = CFLAG_16(FLAG_C) 361 #endif 362 363 /* M37710 Arithmetic Shift Left operand */ 364 #undef OP_ASLM 365 #if FLAG_SET_M 366 #define OP_ASLM(MODE) \ 367 CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ 368 DST = EA_##MODE(); \ 369 FLAG_C = read_8_##MODE(DST) << 1; \ 370 FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ 371 write_8_##MODE(DST, FLAG_Z) 372 #else 373 #define OP_ASLM(MODE) \ 374 CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ 375 DST = EA_##MODE(); \ 376 FLAG_C = read_16_##MODE(DST) << 1; \ 377 FLAG_Z = MAKE_UINT_16(FLAG_C); \ 378 FLAG_N = NFLAG_16(FLAG_C); \ 379 FLAG_C = CFLAG_16(FLAG_C); \ 380 write_16_##MODE(DST, FLAG_Z) 381 #endif 382 383 /* M37710 Branch on Condition Code */ 384 #undef OP_BCC 385 #define OP_BCC(COND) \ 386 DST = OPER_8_IMM(); \ 387 if(COND) \ 388 { \ 389 CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ 390 m37710i_branch_8(DST); \ 391 BREAKOUT; \ 392 } \ 393 CLK(CLK_OP + CLK_RELATIVE_8); 394 /* M37710 Cause a Break interrupt */ 395 #undef OP_BRK 396 #define OP_BRK() \ 397 REG_PC++; CLK(CLK_OP + CLK_R8 + CLK_IMM); \ 398 logerror("error M37710: BRK at PC=%06x\n", REG_PB|REG_PC); \ 399 m37710i_interrupt_software(0xfffa) 400 401 /* M37710 Branch Always */ 402 #undef OP_BRA 403 #define OP_BRA() \ 404 CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_8); \ 405 m37710i_branch_8(OPER_8_IMM()) 406 407 /* M37710 Branch Always Long */ 408 #undef OP_BRL 409 #define OP_BRL() \ 410 CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_16); \ 411 m37710i_branch_16(OPER_16_IMM()) 412 413 /* M37710 Clear Carry flag */ 414 #undef OP_CLC 415 #define OP_CLC() \ 416 CLK(CLK_OP + CLK_IMPLIED); \ 417 FLAG_C = CFLAG_CLEAR 418 419 /* M37710 Clear Interrupt Mask flag */ 420 #undef OP_CLI 421 #define OP_CLI() \ 422 CLK(CLK_OP + CLK_IMPLIED); \ 423 FLAG_I = IFLAG_CLEAR; \ 424 m37710i_update_irqs() 425 426 /* M37710 Clear oVerflow flag */ 427 #undef OP_CLV 428 #define OP_CLV() \ 429 CLK(CLK_OP + CLK_IMPLIED); \ 430 FLAG_V = VFLAG_CLEAR 431 432 /* M37710 Compare operand to accumulator */ 433 /* Unusual behavior: C flag is inverted */ 434 #undef OP_CMP 435 #if FLAG_SET_M 436 #define OP_CMP(MODE) \ 437 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 438 FLAG_C = REG_A - OPER_8_##MODE(); \ 439 FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ 440 FLAG_C ^= CFLAG_SET 441 #else 442 #define OP_CMP(MODE) \ 443 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 444 FLAG_C = REG_A - OPER_16_##MODE(); \ 445 FLAG_Z = MAKE_UINT_16(FLAG_C); \ 446 FLAG_N = NFLAG_16(FLAG_C); \ 447 FLAG_C = ~CFLAG_16(FLAG_C) 448 #endif 449 450 /* M37710 Compare operand to B accumulator */ 451 /* Unusual behavior: C flag is inverted */ 452 #undef OP_CMPB 453 #if FLAG_SET_M 454 #define OP_CMPB(MODE) \ 455 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 456 FLAG_C = REG_BA - OPER_8_##MODE(); \ 457 FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ 458 FLAG_C ^= CFLAG_SET 459 #else 460 #define OP_CMPB(MODE) \ 461 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 462 FLAG_C = REG_BA - OPER_16_##MODE(); \ 463 FLAG_Z = MAKE_UINT_16(FLAG_C); \ 464 FLAG_N = NFLAG_16(FLAG_C); \ 465 FLAG_C = ~CFLAG_16(FLAG_C) 466 #endif 467 468 /* M37710 Compare operand to index register */ 469 /* Unusual behavior: C flag is inverted */ 470 #undef OP_CMPX 471 #if FLAG_SET_X 472 #define OP_CMPX(REG, MODE) \ 473 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 474 FLAG_C = REG - OPER_8_##MODE(); \ 475 FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ 476 FLAG_C ^= CFLAG_SET 477 #else 478 #define OP_CMPX(REG, MODE) \ 479 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 480 FLAG_C = REG - OPER_16_##MODE(); \ 481 FLAG_Z = MAKE_UINT_16(FLAG_C); \ 482 FLAG_N = NFLAG_16(FLAG_C); \ 483 FLAG_C = ~CFLAG_16(FLAG_C) 484 #endif 485 486 /* M37710 Decrement accumulator */ 487 #undef OP_DEC 488 #if FLAG_SET_M 489 #define OP_DEC() \ 490 CLK(CLK_OP + CLK_IMPLIED); \ 491 FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(REG_A - 1) 492 #else 493 #define OP_DEC() \ 494 CLK(CLK_OP + CLK_IMPLIED); \ 495 FLAG_Z = REG_A = MAKE_UINT_16(REG_A - 1); \ 496 FLAG_N = NFLAG_16(REG_A) 497 #endif 498 499 /* M37710 Decrement B accumulator */ 500 #undef OP_DECB 501 #if FLAG_SET_M 502 #define OP_DECB() \ 503 CLK(CLK_OP + CLK_IMPLIED); \ 504 FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(REG_BA - 1) 505 #else 506 #define OP_DECB() \ 507 CLK(CLK_OP + CLK_IMPLIED); \ 508 FLAG_Z = REG_BA = MAKE_UINT_16(REG_BA - 1); \ 509 FLAG_N = NFLAG_16(REG_BA) 510 #endif 511 512 /* M37710 Decrement operand */ 513 #undef OP_DECM 514 #if FLAG_SET_M 515 #define OP_DECM(MODE) \ 516 CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ 517 DST = EA_##MODE(); \ 518 FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) - 1); \ 519 write_8_##MODE(DST, FLAG_Z) 520 #else 521 #define OP_DECM(MODE) \ 522 CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ 523 DST = EA_##MODE(); \ 524 FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) - 1); \ 525 FLAG_N = NFLAG_16(FLAG_Z); \ 526 write_16_##MODE(DST, FLAG_Z) 527 #endif 528 529 /* M37710 Decrement index register */ 530 #undef OP_DECX 531 #if FLAG_SET_X 532 #define OP_DECX(REG) \ 533 CLK(CLK_OP + CLK_IMPLIED); \ 534 FLAG_N = FLAG_Z = REG = MAKE_UINT_8(REG - 1) 535 #else 536 #define OP_DECX(REG) \ 537 CLK(CLK_OP + CLK_IMPLIED); \ 538 FLAG_Z = REG = MAKE_UINT_16(REG - 1); \ 539 FLAG_N = NFLAG_16(REG) 540 #endif 541 542 /* M37710 Exclusive Or operand to accumulator */ 543 #undef OP_EOR 544 #if FLAG_SET_M 545 #define OP_EOR(MODE) \ 546 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 547 FLAG_N = FLAG_Z = REG_A ^= OPER_8_##MODE() 548 #else 549 #define OP_EOR(MODE) \ 550 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 551 FLAG_Z = REG_A ^= OPER_16_##MODE(); \ 552 FLAG_N = NFLAG_16(REG_A) 553 #endif 554 555 /* M37710 Exclusive Or operand to accumulator B */ 556 #undef OP_EORB 557 #if FLAG_SET_M 558 #define OP_EORB(MODE) \ 559 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 560 FLAG_N = FLAG_Z = REG_BA ^= OPER_8_##MODE() 561 #else 562 #define OP_EORB(MODE) \ 563 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 564 FLAG_Z = REG_BA ^= OPER_16_##MODE(); \ 565 FLAG_N = NFLAG_16(REG_BA) 566 #endif 567 568 /* M37710 Increment accumulator */ 569 #undef OP_INC 570 #if FLAG_SET_M 571 #define OP_INC() \ 572 CLK(CLK_OP + CLK_IMPLIED); \ 573 FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(REG_A + 1) 574 #else 575 #define OP_INC() \ 576 CLK(CLK_OP + CLK_IMPLIED); \ 577 FLAG_Z = REG_A = MAKE_UINT_16(REG_A + 1); \ 578 FLAG_N = NFLAG_16(REG_A) 579 #endif 580 581 /* M37710 Increment B accumulator */ 582 #undef OP_INCB 583 #if FLAG_SET_M 584 #define OP_INCB() \ 585 CLK(CLK_OP + CLK_IMPLIED); \ 586 FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(REG_BA + 1) 587 #else 588 #define OP_INCB() \ 589 CLK(CLK_OP + CLK_IMPLIED); \ 590 FLAG_Z = REG_BA = MAKE_UINT_16(REG_BA + 1); \ 591 FLAG_N = NFLAG_16(REG_BA) 592 #endif 593 594 /* M37710 Increment operand */ 595 #undef OP_INCM 596 #if FLAG_SET_M 597 #define OP_INCM(MODE) \ 598 CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ 599 DST = EA_##MODE(); \ 600 FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) + 1); \ 601 write_8_##MODE(DST, FLAG_Z) 602 #else 603 #define OP_INCM(MODE) \ 604 CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ 605 DST = EA_##MODE(); \ 606 FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) + 1); \ 607 FLAG_N = NFLAG_16(FLAG_Z); \ 608 write_16_##MODE(DST, FLAG_Z) 609 #endif 610 611 /* M37710 Increment index register */ 612 #undef OP_INCX 613 #if FLAG_SET_X 614 #define OP_INCX(REG) \ 615 CLK(CLK_OP + CLK_IMPLIED); \ 616 FLAG_N = FLAG_Z = REG = MAKE_UINT_8(REG + 1) 617 #else 618 #define OP_INCX(REG) \ 619 CLK(CLK_OP + CLK_IMPLIED); \ 620 FLAG_Z = REG = MAKE_UINT_16(REG + 1); \ 621 FLAG_N = NFLAG_16(REG) 622 #endif 623 624 /* M37710 Jump Long */ 625 #undef OP_JMLAI 626 #define OP_JMLAI() \ 627 CLK(CLK_OP + CLK_AI + 1); \ 628 m37710i_jump_24(read_24_A(OPER_16_IMM())) 629 630 /* M37710 Jump */ 631 #undef OP_JMP 632 #define OP_JMP(MODE) \ 633 CLK(CLK_OP + CLK_##MODE); \ 634 m37710i_jump_16(EA_##MODE()) 635 636 /* M37710 Jump absolute indexed indirect */ 637 #undef OP_JMPAXI 638 #define OP_JMPAXI() \ 639 CLK(CLK_OP + CLK_AXI); \ 640 m37710i_jump_16(read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM() + REG_X)))) 641 642 /* M37710 Jump absolute long */ 643 #undef OP_JMPAL 644 #define OP_JMPAL() \ 645 CLK(CLK_OP + CLK_AL); \ 646 m37710i_jump_24(EA_AL()) 647 648 /* M37710 Jump to Subroutine Long */ 649 #undef OP_JSL 650 #define OP_JSL(MODE) \ 651 CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \ 652 DST = EA_##MODE(); \ 653 m37710i_push_8(REG_PB>>16); \ 654 m37710i_push_16(REG_PC); \ 655 m37710i_jump_24(DST) 656 657 /* M37710 Jump to Subroutine */ 658 #undef OP_JSR 659 #define OP_JSR(MODE) \ 660 CLK(CLK_OP + CLK_W16 + CLK_##MODE); \ 661 DST = EA_##MODE(); \ 662 m37710i_push_16(REG_PC); \ 663 m37710i_jump_16(DST) 664 665 /* M37710 Jump to Subroutine */ 666 #undef OP_JSRAXI 667 #define OP_JSRAXI() \ 668 CLK(CLK_OP + CLK_W16 + CLK_AXI); \ 669 DST = read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM() + REG_X))); \ 670 m37710i_push_16(REG_PC); \ 671 m37710i_jump_16(DST) 672 673 /* M37710 Load accumulator with operand */ 674 #undef OP_LDA 675 #if FLAG_SET_M 676 #define OP_LDA(MODE) \ 677 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 678 FLAG_N = FLAG_Z = REG_A = OPER_8_##MODE() 679 #else 680 #define OP_LDA(MODE) \ 681 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 682 FLAG_Z = REG_A = OPER_16_##MODE(); \ 683 FLAG_N = NFLAG_16(REG_A) 684 #endif 685 686 /* M37710 Load B accumulator with operand */ 687 #undef OP_LDB 688 #if FLAG_SET_M 689 #define OP_LDB(MODE) \ 690 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 691 FLAG_N = FLAG_Z = REG_BA = OPER_8_##MODE() 692 #else 693 #define OP_LDB(MODE) \ 694 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 695 FLAG_Z = REG_BA = OPER_16_##MODE(); \ 696 FLAG_N = NFLAG_16(REG_BA) 697 #endif 698 699 /* M37710 Load memory with operand */ 700 #undef OP_LDM 701 #if FLAG_SET_M 702 #define OP_LDM(MODE) \ 703 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 704 REG_IM2 = EA_##MODE(); \ 705 REG_IM = read_8_IMM(REG_PB | REG_PC); \ 706 REG_PC++; \ 707 write_8_##MODE(REG_IM2, REG_IM) 708 #else 709 #define OP_LDM(MODE) \ 710 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 711 REG_IM2 = EA_##MODE(); \ 712 REG_IM = read_16_IMM(REG_PB | REG_PC); \ 713 REG_PC+=2; \ 714 write_16_##MODE(REG_IM2, REG_IM) 715 #endif 716 717 /* M37710 Branch if bits set */ 718 #undef OP_BBS 719 #if FLAG_SET_M 720 #define OP_BBS(MODE) \ 721 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 722 REG_IM2 = read_8_NORM(EA_##MODE()); \ 723 REG_IM = read_8_IMM(REG_PB | REG_PC); \ 724 REG_PC++; \ 725 DST = OPER_8_IMM(); \ 726 if ((REG_IM2 & REG_IM) == REG_IM) \ 727 { \ 728 CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ 729 m37710i_branch_8(DST); \ 730 BREAKOUT; \ 731 } 732 #else 733 #define OP_BBS(MODE) \ 734 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 735 REG_IM2 = read_16_NORM(EA_##MODE()); \ 736 REG_IM = read_16_IMM(REG_PB | REG_PC); \ 737 REG_PC++; \ 738 REG_PC++; \ 739 DST = OPER_8_IMM(); \ 740 if ((REG_IM2 & REG_IM) == REG_IM) \ 741 { \ 742 CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ 743 m37710i_branch_8(DST); \ 744 BREAKOUT; \ 745 } 746 #endif 747 748 /* M37710 Branch if bits clear */ 749 #undef OP_BBC 750 #if FLAG_SET_M 751 #define OP_BBC(MODE) \ 752 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 753 REG_IM2 = read_8_NORM(EA_##MODE()); \ 754 REG_IM = read_8_IMM(REG_PB | REG_PC); \ 755 REG_PC++; \ 756 DST = OPER_8_IMM(); \ 757 if ((REG_IM2 & REG_IM) == 0) \ 758 { \ 759 CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ 760 m37710i_branch_8(DST); \ 761 BREAKOUT; \ 762 } 763 #else 764 #define OP_BBC(MODE) \ 765 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 766 REG_IM2 = read_16_NORM(EA_##MODE()); \ 767 REG_IM = read_16_IMM(REG_PB | REG_PC); \ 768 REG_PC++; \ 769 REG_PC++; \ 770 DST = OPER_8_IMM(); \ 771 if ((REG_IM2 & REG_IM) == 0) \ 772 { \ 773 CLK(CLK_OP + CLK_RELATIVE_8 + 1); \ 774 m37710i_branch_8(DST); \ 775 BREAKOUT; \ 776 } 777 #endif 778 779 /* M37710 Swap accumulators */ 780 #undef OP_XAB 781 #if FLAG_SET_M 782 #define OP_XAB() \ 783 CLK(6); \ 784 DST = REG_A; \ 785 FLAG_N = FLAG_Z = REG_A = REG_BA; \ 786 REG_BA = DST; 787 #else 788 #define OP_XAB() \ 789 CLK(6); \ 790 DST = REG_A; \ 791 FLAG_Z = REG_A = REG_BA; \ 792 FLAG_N = NFLAG_16(REG_A); \ 793 REG_BA = DST; 794 #endif 795 796 /* M37710 Load index register with operand */ 797 #undef OP_LDX 798 #if FLAG_SET_X 799 #define OP_LDX(REG, MODE) \ 800 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 801 FLAG_N = FLAG_Z = REG = OPER_8_##MODE() 802 #else 803 #define OP_LDX(REG, MODE) \ 804 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 805 FLAG_Z = REG = OPER_16_##MODE(); \ 806 FLAG_N = NFLAG_16(REG) 807 #endif 808 809 /* M37710 Logical Shift Right accumulator */ 810 #undef OP_LSR 811 #if FLAG_SET_M 812 #define OP_LSR() \ 813 CLK(CLK_OP + CLK_IMPLIED); \ 814 FLAG_N = 0; \ 815 FLAG_C = REG_A << 8; \ 816 FLAG_Z = REG_A >>= 1 817 #else 818 #define OP_LSR() \ 819 CLK(CLK_OP + CLK_IMPLIED); \ 820 FLAG_N = 0; \ 821 FLAG_C = REG_A << 8; \ 822 FLAG_Z = REG_A >>= 1 823 #endif 824 825 /* M37710 Logical Shift Right B accumulator */ 826 #undef OP_LSRB 827 #if FLAG_SET_M 828 #define OP_LSRB() \ 829 CLK(CLK_OP + CLK_IMPLIED); \ 830 FLAG_N = 0; \ 831 FLAG_C = REG_BA << 8; \ 832 FLAG_Z = REG_BA >>= 1 833 #else 834 #define OP_LSRB() \ 835 CLK(CLK_OP + CLK_IMPLIED); \ 836 FLAG_N = 0; \ 837 FLAG_C = REG_BA << 8; \ 838 FLAG_Z = REG_BA >>= 1 839 #endif 840 841 /* M37710 Logical Shift Right operand */ 842 #undef OP_LSRM 843 #if FLAG_SET_M 844 #define OP_LSRM(MODE) \ 845 CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ 846 DST = EA_##MODE(); \ 847 FLAG_N = 0; \ 848 FLAG_Z = read_8_##MODE(DST); \ 849 FLAG_C = FLAG_Z << 8; \ 850 FLAG_Z >>= 1; \ 851 write_8_##MODE(DST, FLAG_Z) 852 #else 853 #define OP_LSRM(MODE) \ 854 CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ 855 DST = EA_##MODE(); \ 856 FLAG_N = 0; \ 857 FLAG_Z = read_16_##MODE(DST); \ 858 FLAG_C = FLAG_Z << 8; \ 859 FLAG_Z >>= 1; \ 860 write_16_##MODE(DST, FLAG_Z) 861 #endif 862 863 /* M37710 Move Block Negative */ 864 #undef OP_MVN 865 #if FLAG_SET_X 866 #define OP_MVN() \ 867 DST = OPER_8_IMM()<<16; \ 868 SRC = OPER_8_IMM()<<16; \ 869 REG_DB = DST; \ 870 REG_A |= REG_B; \ 871 CLK(7); \ 872 if (REG_A > 0) \ 873 { \ 874 write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \ 875 REG_X = MAKE_UINT_8(REG_X+1); \ 876 REG_Y = MAKE_UINT_8(REG_Y+1); \ 877 REG_A--; \ 878 if ((REG_A&0xffff) != 0) \ 879 {\ 880 REG_PC -= 3; \ 881 }\ 882 else \ 883 { \ 884 if (FLAG_M) \ 885 { \ 886 REG_A = 0xff; \ 887 REG_B = 0xff00; \ 888 } \ 889 else \ 890 { \ 891 REG_A = 0xffff; \ 892 } \ 893 } \ 894 } 895 #else 896 #define OP_MVN() \ 897 DST = OPER_8_IMM()<<16; \ 898 SRC = OPER_8_IMM()<<16; \ 899 REG_DB = DST; \ 900 REG_A |= REG_B; \ 901 CLK(7); \ 902 if (REG_A > 0) \ 903 { \ 904 write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \ 905 REG_X = MAKE_UINT_16(REG_X+1); \ 906 REG_Y = MAKE_UINT_16(REG_Y+1); \ 907 REG_A--; \ 908 if ((REG_A&0xffff) != 0) \ 909 {\ 910 REG_PC -= 3; \ 911 }\ 912 else \ 913 { \ 914 if (FLAG_M) \ 915 { \ 916 REG_A = 0xff; \ 917 REG_B = 0xff00; \ 918 } \ 919 else \ 920 { \ 921 REG_A = 0xffff; \ 922 } \ 923 } \ 924 } 925 #endif 926 927 /* M37710 Move Block Positive */ 928 #undef OP_MVP 929 #if FLAG_SET_X 930 #define OP_MVP() \ 931 DST = OPER_8_IMM()<<16; \ 932 SRC = OPER_8_IMM()<<16; \ 933 REG_DB = DST; \ 934 REG_A |= REG_B; \ 935 CLK(7); \ 936 if (REG_A > 0) \ 937 { \ 938 write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \ 939 REG_X = MAKE_UINT_8(REG_X-1); \ 940 REG_Y = MAKE_UINT_8(REG_Y-1); \ 941 REG_A--; \ 942 if ((REG_A&0xffff) != 0) \ 943 {\ 944 REG_PC -= 3; \ 945 }\ 946 else \ 947 { \ 948 if (FLAG_M) \ 949 { \ 950 REG_A = 0xff; \ 951 REG_B = 0xff00; \ 952 } \ 953 else \ 954 { \ 955 REG_A = 0xffff; \ 956 } \ 957 } \ 958 } 959 #else 960 #define OP_MVP() \ 961 DST = OPER_8_IMM()<<16; \ 962 SRC = OPER_8_IMM()<<16; \ 963 REG_DB = DST; \ 964 REG_A |= REG_B; \ 965 CLK(7); \ 966 if (REG_A > 0) \ 967 { \ 968 write_8_NORM(DST | REG_Y, read_8_NORM(SRC | REG_X)); \ 969 REG_X = MAKE_UINT_16(REG_X-1); \ 970 REG_Y = MAKE_UINT_16(REG_Y-1); \ 971 REG_A--; \ 972 if ((REG_A&0xffff) != 0) \ 973 {\ 974 REG_PC -= 3; \ 975 }\ 976 else \ 977 { \ 978 if (FLAG_M) \ 979 { \ 980 REG_A = 0xff; \ 981 REG_B = 0xff00; \ 982 } \ 983 else \ 984 { \ 985 REG_A = 0xffff; \ 986 } \ 987 } \ 988 } 989 #endif 990 991 /* M37710 No Operation */ 992 #undef OP_NOP 993 #define OP_NOP() \ 994 CLK(CLK_OP + CLK_IMPLIED) 995 996 /* M37710 Logical OR operand to accumulator */ 997 #undef OP_ORA 998 #if FLAG_SET_M 999 #define OP_ORA(MODE) \ 1000 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 1001 FLAG_N = FLAG_Z = REG_A |= OPER_8_ ## MODE() 1002 #else 1003 #define OP_ORA(MODE) \ 1004 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 1005 FLAG_Z = REG_A |= OPER_16_##MODE(); \ 1006 FLAG_N = NFLAG_16(REG_A) 1007 #endif 1008 1009 /* M37710 Logical OR operand to B accumulator */ 1010 #undef OP_ORB 1011 #if FLAG_SET_M 1012 #define OP_ORB(MODE) \ 1013 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 1014 FLAG_N = FLAG_Z = REG_BA |= OPER_8_ ## MODE() 1015 #else 1016 #define OP_ORB(MODE) \ 1017 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 1018 FLAG_Z = REG_BA |= OPER_16_##MODE(); \ 1019 FLAG_N = NFLAG_16(REG_BA) 1020 #endif 1021 1022 /* M37710 Push Effective Address */ 1023 #undef OP_PEA 1024 #define OP_PEA() \ 1025 CLK(CLK_OP + CLK_R16 + CLK_W16); \ 1026 m37710i_push_16(OPER_16_IMM()) 1027 1028 /* M37710 Push Effective Indirect Address */ 1029 #undef OP_PEI 1030 #define OP_PEI() \ 1031 CLK(CLK_OP + CLK_R16 + CLK_W16 + CLK_D); \ 1032 m37710i_push_16(EA_DI()) 1033 1034 /* M37710 Push Effective PC-Relative Address */ 1035 #undef OP_PER 1036 #define OP_PER() \ 1037 CLK(CLK_OP + CLK_R16 + CLK_W16 + 1); \ 1038 SRC = OPER_16_IMM(); \ 1039 m37710i_push_16(REG_PC + SRC) 1040 1041 /* M37710 Push accumulator to the stack */ 1042 #undef OP_PHA 1043 #if FLAG_SET_M 1044 #define OP_PHA() \ 1045 CLK(CLK_OP + CLK_W8 + 1); \ 1046 m37710i_push_8(REG_A) 1047 #else 1048 #define OP_PHA() \ 1049 CLK(CLK_OP + CLK_W16 + 1); \ 1050 m37710i_push_16(REG_A) 1051 #endif 1052 1053 /* M37710 Push B accumulator to the stack */ 1054 #undef OP_PHAB 1055 #if FLAG_SET_M 1056 #define OP_PHAB() \ 1057 CLK(CLK_OP + CLK_W8 + 1); \ 1058 m37710i_push_8(REG_BA) 1059 #else 1060 #define OP_PHAB() \ 1061 CLK(CLK_OP + CLK_W16 + 1); \ 1062 m37710i_push_16(REG_BA) 1063 #endif 1064 1065 /* M37710 Push index register to the stack */ 1066 #undef OP_PHX 1067 #if FLAG_SET_X 1068 #define OP_PHX(REG) \ 1069 CLK(CLK_OP + CLK_W8 + 1); \ 1070 m37710i_push_8(REG) 1071 #else 1072 #define OP_PHX(REG) \ 1073 CLK(CLK_OP + CLK_W16 + 1); \ 1074 m37710i_push_16(REG) 1075 #endif 1076 1077 /* M37710 Push data bank register */ 1078 #undef OP_PHT 1079 #define OP_PHT() \ 1080 CLK(CLK_OP + CLK_W8 + 1); \ 1081 m37710i_push_8(REG_DB>>16) 1082 1083 /* M37710 Push direct register */ 1084 #undef OP_PHD 1085 #define OP_PHD() \ 1086 CLK(CLK_OP + CLK_W16 + 1); \ 1087 m37710i_push_16(REG_D) 1088 1089 /* M37710 Push program bank register */ 1090 #undef OP_PHK 1091 #define OP_PHK() \ 1092 CLK(CLK_OP + CLK_W8 + 1); \ 1093 m37710i_push_8(REG_PB>>16) 1094 1095 /* M37710 Push the Processor Status Register to the stack */ 1096 #undef OP_PHP 1097 #define OP_PHP() \ 1098 CLK(CLK_OP + CLK_W8 + 1); \ 1099 m37710i_push_8(m377.ipl); \ 1100 m37710i_push_8(m37710i_get_reg_p()) 1101 1102 /* M37710 Pull accumulator from the stack */ 1103 #undef OP_PLA 1104 #if FLAG_SET_M 1105 #define OP_PLA() \ 1106 CLK(CLK_OP + CLK_R8 + 2); \ 1107 FLAG_N = FLAG_Z = REG_A = m37710i_pull_8() 1108 #else 1109 #define OP_PLA() \ 1110 CLK(CLK_OP + CLK_R16 + 2); \ 1111 FLAG_Z = REG_A = m37710i_pull_16(); \ 1112 FLAG_N = NFLAG_16(FLAG_Z) 1113 #endif 1114 1115 /* M37710 Pull B accumulator from the stack */ 1116 #undef OP_PLAB 1117 #if FLAG_SET_M 1118 #define OP_PLAB() \ 1119 CLK(CLK_OP + CLK_R8 + 2); \ 1120 FLAG_N = FLAG_Z = REG_BA = m37710i_pull_8() 1121 #else 1122 #define OP_PLAB() \ 1123 CLK(CLK_OP + CLK_R16 + 2); \ 1124 FLAG_Z = REG_BA = m37710i_pull_16(); \ 1125 FLAG_N = NFLAG_16(FLAG_Z) 1126 #endif 1127 1128 /* M37710 Pull index register from the stack */ 1129 #undef OP_PLX 1130 #if FLAG_SET_X 1131 #define OP_PLX(REG) \ 1132 CLK(CLK_OP + CLK_R8 + 2); \ 1133 FLAG_N = FLAG_Z = REG = m37710i_pull_8() 1134 #else 1135 #define OP_PLX(REG) \ 1136 CLK(CLK_OP + CLK_R16 + 2); \ 1137 FLAG_Z = REG = m37710i_pull_16(); \ 1138 FLAG_N = NFLAG_16(FLAG_Z) 1139 #endif 1140 1141 /* M37710 Pull data bank register */ 1142 #undef OP_PLT 1143 #define OP_PLT() \ 1144 CLK(CLK_OP + CLK_R8 + 2); \ 1145 FLAG_N = FLAG_Z = m37710i_pull_8(); \ 1146 REG_DB = FLAG_Z << 16 1147 1148 /* M37710 Pull direct register */ 1149 #undef OP_PLD 1150 #define OP_PLD() \ 1151 CLK(CLK_OP + CLK_R16 + 2); \ 1152 REG_D = m37710i_pull_16() 1153 1154 /* M37710 Pull the Processor Status Register from the stack */ 1155 #undef OP_PLP 1156 #define OP_PLP() \ 1157 CLK(CLK_OP + CLK_R8 + 2); \ 1158 m37710i_set_reg_p(m37710i_pull_8()); \ 1159 m37710i_set_reg_ipl(m37710i_pull_8()); \ 1160 m37710i_update_irqs() 1161 1162 /* M37710 Reset Program status word */ 1163 #undef OP_REP 1164 #define OP_REP() \ 1165 CLK(CLK_OP + CLK_R8 + 1); \ 1166 m37710i_set_reg_p(m37710i_get_reg_p() & ~OPER_8_IMM()); \ 1167 m37710i_update_irqs() 1168 1169 /* M37710 Clear "M" status bit */ 1170 #undef OP_CLM 1171 #define OP_CLM() \ 1172 CLK(CLK_OP + CLK_R8 + 1); \ 1173 m37710i_set_reg_p(m37710i_get_reg_p() & ~FLAGPOS_M) 1174 1175 /* M37710 Rotate Left the accumulator */ 1176 #undef OP_ROL 1177 #if FLAG_SET_M 1178 #define OP_ROL() \ 1179 CLK(CLK_OP + CLK_IMPLIED); \ 1180 FLAG_C = (REG_A<<1) | CFLAG_AS_1(); \ 1181 FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C) 1182 #else 1183 #define OP_ROL() \ 1184 CLK(CLK_OP + CLK_IMPLIED); \ 1185 FLAG_C = (REG_A<<1) | CFLAG_AS_1(); \ 1186 FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \ 1187 FLAG_N = NFLAG_16(FLAG_C); \ 1188 FLAG_C = CFLAG_16(FLAG_C) 1189 #endif 1190 1191 /* M37710 Rotate Left the B accumulator */ 1192 #undef OP_ROLB 1193 #if FLAG_SET_M 1194 #define OP_ROLB() \ 1195 CLK(CLK_OP + CLK_IMPLIED); \ 1196 FLAG_C = (REG_BA<<1) | CFLAG_AS_1(); \ 1197 FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C) 1198 #else 1199 #define OP_ROLB() \ 1200 CLK(CLK_OP + CLK_IMPLIED); \ 1201 FLAG_C = (REG_BA<<1) | CFLAG_AS_1(); \ 1202 FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \ 1203 FLAG_N = NFLAG_16(FLAG_C); \ 1204 FLAG_C = CFLAG_16(FLAG_C) 1205 #endif 1206 1207 /* M37710 Rotate Left the accumulator by a specified amount */ 1208 #undef OP_RLA 1209 #if FLAG_SET_M 1210 #define OP_RLA(MODE) \ 1211 { int cnt = OPER_8_##MODE(); while (cnt > 0) { CLK(6); REG_A=((REG_A<<1)|(REG_A>>7&1))&0xff; cnt--; } } 1212 #else 1213 #define OP_RLA(MODE) \ 1214 { int cnt = OPER_16_##MODE(); while (cnt > 0) { CLK(6); REG_A=((REG_A<<1)|(REG_A>>15&1))&0xffff; cnt--; } } 1215 #endif 1216 1217 /* M37710 Rotate Left an operand */ 1218 #undef OP_ROLM 1219 #if FLAG_SET_M 1220 #define OP_ROLM(MODE) \ 1221 CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ 1222 DST = EA_##MODE(); \ 1223 FLAG_C = (read_8_##MODE(DST)<<1) | CFLAG_AS_1(); \ 1224 FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \ 1225 write_8_##MODE(DST, FLAG_Z) 1226 #else 1227 #define OP_ROLM(MODE) \ 1228 CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ 1229 DST = EA_##MODE(); \ 1230 FLAG_C = (read_16_##MODE(DST)<<1) | CFLAG_AS_1(); \ 1231 FLAG_Z = MAKE_UINT_16(FLAG_C); \ 1232 FLAG_N = NFLAG_16(FLAG_C); \ 1233 FLAG_C = CFLAG_16(FLAG_C); \ 1234 write_16_##MODE(DST, FLAG_Z) 1235 #endif 1236 1237 /* M37710 Rotate Right the accumulator */ 1238 #undef OP_ROR 1239 #if FLAG_SET_M 1240 #define OP_ROR() \ 1241 CLK(CLK_OP + CLK_IMPLIED); \ 1242 REG_A |= FLAG_C & 0x100; \ 1243 FLAG_C = REG_A << 8; \ 1244 FLAG_N = FLAG_Z = REG_A >>= 1 1245 #else 1246 #define OP_ROR() \ 1247 CLK(CLK_OP + CLK_IMPLIED); \ 1248 REG_A |= (FLAG_C<<8) & 0x10000; \ 1249 FLAG_C = REG_A << 8; \ 1250 FLAG_Z = REG_A >>= 1; \ 1251 FLAG_N = NFLAG_16(REG_A) 1252 #endif 1253 1254 /* M37710 Rotate Right the B accumulator */ 1255 #undef OP_RORB 1256 #if FLAG_SET_M 1257 #define OP_RORB() \ 1258 CLK(CLK_OP + CLK_IMPLIED); \ 1259 REG_BA |= FLAG_C & 0x100; \ 1260 FLAG_C = REG_BA << 8; \ 1261 FLAG_N = FLAG_Z = REG_BA >>= 1 1262 #else 1263 #define OP_RORB() \ 1264 CLK(CLK_OP + CLK_IMPLIED); \ 1265 REG_BA |= (FLAG_C<<8) & 0x10000; \ 1266 FLAG_C = REG_BA << 8; \ 1267 FLAG_Z = REG_BA >>= 1; \ 1268 FLAG_N = NFLAG_16(REG_BA) 1269 #endif 1270 1271 /* M37710 Rotate Right an operand */ 1272 #undef OP_RORM 1273 #if FLAG_SET_M 1274 #define OP_RORM(MODE) \ 1275 CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ 1276 DST = EA_##MODE(); \ 1277 FLAG_Z = read_8_##MODE(DST) | (FLAG_C & 0x100); \ 1278 FLAG_C = FLAG_Z << 8; \ 1279 FLAG_N = FLAG_Z >>= 1; \ 1280 write_8_##MODE(DST, FLAG_Z) 1281 #else 1282 #define OP_RORM(MODE) \ 1283 CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ 1284 DST = EA_##MODE(); \ 1285 FLAG_Z = read_16_##MODE(DST) | ((FLAG_C<<8) & 0x10000); \ 1286 FLAG_C = FLAG_Z << 8; \ 1287 FLAG_Z >>= 1; \ 1288 FLAG_N = NFLAG_16(FLAG_Z); \ 1289 write_16_##MODE(DST, FLAG_Z) 1290 #endif 1291 1292 /* M37710 Return from Interrupt */ 1293 #undef OP_RTI 1294 #define OP_RTI() \ 1295 CLK(8); \ 1296 m37710i_set_reg_p(m37710i_pull_8()); \ 1297 m37710i_set_reg_ipl(m37710i_pull_8()); \ 1298 m37710i_jump_16(m37710i_pull_16()); \ 1299 REG_PB = m37710i_pull_8() << 16; \ 1300 m37710i_update_irqs() 1301 1302 /* M37710 Return from Subroutine Long */ 1303 #undef OP_RTL 1304 #define OP_RTL() \ 1305 CLK(6); \ 1306 m37710i_jump_24(m37710i_pull_24()) 1307 1308 /* M37710 Return from Subroutine */ 1309 #undef OP_RTS 1310 #define OP_RTS() \ 1311 CLK(6); \ 1312 DST = m37710i_pull_16(); \ 1313 m37710i_jump_16(DST) 1314 1315 /* M37710 Subtract with Carry */ 1316 /* Unusual behavior: C flag is inverted */ 1317 #undef OP_SBC 1318 #if FLAG_SET_M 1319 #define OP_SBC(MODE) \ 1320 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 1321 SRC = OPER_8_##MODE(); \ 1322 FLAG_C = ~FLAG_C; \ 1323 if(!FLAG_D) \ 1324 { \ 1325 FLAG_C = REG_A - SRC - CFLAG_AS_1(); \ 1326 FLAG_V = VFLAG_SUB_8(SRC, REG_A, FLAG_C); \ 1327 FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C); \ 1328 FLAG_C = ~FLAG_C; \ 1329 BREAKOUT; \ 1330 } \ 1331 DST = CFLAG_AS_1(); \ 1332 FLAG_C = REG_A - SRC - DST; \ 1333 FLAG_V = VFLAG_SUB_8(SRC, REG_A, FLAG_C); \ 1334 if((FLAG_C & 0xf) > 9) \ 1335 FLAG_C-=6; \ 1336 if((FLAG_C & 0xf0) > 0x90) \ 1337 FLAG_C-=0x60; \ 1338 FLAG_N = FLAG_Z = REG_A = MAKE_UINT_8(FLAG_C); \ 1339 FLAG_C = ~FLAG_C 1340 #else 1341 #define OP_SBC(MODE) \ 1342 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 1343 SRC = OPER_16_##MODE(); \ 1344 FLAG_C = ~FLAG_C; \ 1345 if(!FLAG_D) \ 1346 { \ 1347 FLAG_C = REG_A - SRC - CFLAG_AS_1(); \ 1348 FLAG_V = VFLAG_SUB_16(SRC, REG_A, FLAG_C); \ 1349 FLAG_Z = REG_A = MAKE_UINT_16(FLAG_C); \ 1350 FLAG_N = NFLAG_16(REG_A); \ 1351 FLAG_C = ~CFLAG_16(FLAG_C); \ 1352 BREAKOUT; \ 1353 } \ 1354 DST = CFLAG_AS_1(); \ 1355 FLAG_C = MAKE_UINT_8(REG_A) - MAKE_UINT_8(SRC) - DST; \ 1356 if((FLAG_C & 0xf) > 9) \ 1357 FLAG_C-=6; \ 1358 if((FLAG_C & 0xf0) > 0x90) \ 1359 FLAG_C-=0x60; \ 1360 FLAG_Z = MAKE_UINT_8(FLAG_C); \ 1361 DST = CFLAG_AS_1(); \ 1362 FLAG_C = MAKE_UINT_8(REG_A>>8) - MAKE_UINT_8(SRC>>8) - DST; \ 1363 if((FLAG_C & 0xf) > 9) \ 1364 FLAG_C-=6; \ 1365 if((FLAG_C & 0xf0) > 0x90) \ 1366 FLAG_C-=0x60; \ 1367 FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \ 1368 FLAG_N = NFLAG_16(FLAG_Z); \ 1369 FLAG_V = VFLAG_SUB_16(SRC, REG_A, FLAG_Z); \ 1370 REG_A = FLAG_Z; \ 1371 FLAG_C = ~FLAG_C 1372 #endif 1373 1374 /* M37710 Subtract with Carry - B accumulator */ 1375 /* Unusual behavior: C flag is inverted */ 1376 #undef OP_SBCB 1377 #if FLAG_SET_M 1378 #define OP_SBCB(MODE) \ 1379 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 1380 SRC = OPER_8_##MODE(); \ 1381 FLAG_C = ~FLAG_C; \ 1382 if(!FLAG_D) \ 1383 { \ 1384 FLAG_C = REG_BA - SRC - CFLAG_AS_1(); \ 1385 FLAG_V = VFLAG_SUB_8(SRC, REG_BA, FLAG_C); \ 1386 FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C); \ 1387 FLAG_C = ~FLAG_C; \ 1388 BREAKOUT; \ 1389 } \ 1390 DST = CFLAG_AS_1(); \ 1391 FLAG_C = REG_BA - SRC - DST; \ 1392 FLAG_V = VFLAG_SUB_8(SRC, REG_BA, FLAG_C); \ 1393 if((FLAG_C & 0xf) > 9) \ 1394 FLAG_C-=6; \ 1395 if((FLAG_C & 0xf0) > 0x90) \ 1396 FLAG_C-=0x60; \ 1397 FLAG_N = FLAG_Z = REG_BA = MAKE_UINT_8(FLAG_C); \ 1398 FLAG_C = ~FLAG_C 1399 #else 1400 #define OP_SBCB(MODE) \ 1401 CLK(CLK_OP + CLK_R16 + CLK_##MODE); \ 1402 SRC = OPER_16_##MODE(); \ 1403 FLAG_C = ~FLAG_C; \ 1404 if(!FLAG_D) \ 1405 { \ 1406 FLAG_C = REG_BA - SRC - CFLAG_AS_1(); \ 1407 FLAG_V = VFLAG_SUB_16(SRC, REG_BA, FLAG_C); \ 1408 FLAG_Z = REG_BA = MAKE_UINT_16(FLAG_C); \ 1409 FLAG_N = NFLAG_16(REG_BA); \ 1410 FLAG_C = ~CFLAG_16(FLAG_C); \ 1411 BREAKOUT; \ 1412 } \ 1413 DST = CFLAG_AS_1(); \ 1414 FLAG_C = MAKE_UINT_8(REG_BA) - MAKE_UINT_8(SRC) - DST; \ 1415 if((FLAG_C & 0xf) > 9) \ 1416 FLAG_C-=6; \ 1417 if((FLAG_C & 0xf0) > 0x90) \ 1418 FLAG_C-=0x60; \ 1419 FLAG_Z = MAKE_UINT_8(FLAG_C); \ 1420 DST = CFLAG_AS_1(); \ 1421 FLAG_C = MAKE_UINT_8(REG_A>>8) - MAKE_UINT_8(SRC>>8) - DST; \ 1422 if((FLAG_C & 0xf) > 9) \ 1423 FLAG_C-=6; \ 1424 if((FLAG_C & 0xf0) > 0x90) \ 1425 FLAG_C-=0x60; \ 1426 FLAG_Z |= MAKE_UINT_8(FLAG_C) << 8; \ 1427 FLAG_N = NFLAG_16(FLAG_Z); \ 1428 FLAG_V = VFLAG_SUB_16(SRC, REG_BA, FLAG_Z); \ 1429 REG_BA = FLAG_Z; \ 1430 FLAG_C = ~FLAG_C 1431 #endif 1432 1433 /* M37710 Set Carry flag */ 1434 #undef OP_SEC 1435 #define OP_SEC() \ 1436 CLK(CLK_OP + CLK_IMPLIED); \ 1437 FLAG_C = CFLAG_SET 1438 1439 /* M37710 Set Interrupt Mask flag */ 1440 #undef OP_SEI 1441 #define OP_SEI() \ 1442 CLK(CLK_OP + CLK_IMPLIED); \ 1443 FLAG_I = IFLAG_SET 1444 1445 /* M37710 Set Program status word */ 1446 #undef OP_SEP 1447 #define OP_SEP() \ 1448 CLK(CLK_OP + CLK_R8 + 1); \ 1449 m37710i_set_reg_p(m37710i_get_reg_p() | OPER_8_IMM()) 1450 1451 /* M37710 Set "M" status bit */ 1452 #undef OP_SEM 1453 #define OP_SEM() \ 1454 CLK(CLK_OP + CLK_R8 + 1); \ 1455 m37710i_set_reg_p(m37710i_get_reg_p() | FLAGPOS_M) 1456 1457 /* M37710 Store accumulator to memory */ 1458 #undef OP_STA 1459 #if FLAG_SET_M 1460 #define OP_STA(MODE) \ 1461 CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ 1462 write_8_##MODE(EA_##MODE(), REG_A) 1463 #else 1464 #define OP_STA(MODE) \ 1465 CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ 1466 write_16_##MODE(EA_##MODE(), REG_A) 1467 #endif 1468 1469 /* M37710 Store B accumulator to memory */ 1470 #undef OP_STB 1471 #if FLAG_SET_M 1472 #define OP_STB(MODE) \ 1473 CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ 1474 write_8_##MODE(EA_##MODE(), REG_BA) 1475 #else 1476 #define OP_STB(MODE) \ 1477 CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ 1478 write_16_##MODE(EA_##MODE(), REG_BA) 1479 #endif 1480 1481 /* M37710 Store index register to memory */ 1482 #undef OP_STX 1483 #if FLAG_SET_X 1484 #define OP_STX(REG, MODE) \ 1485 CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \ 1486 write_8_##MODE(EA_##MODE(), REG) 1487 #else 1488 #define OP_STX(REG, MODE) \ 1489 CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \ 1490 write_16_##MODE(EA_##MODE(), REG) 1491 #endif 1492 1493 /* M37710 Stop the clock */ 1494 #undef OP_STP 1495 #define OP_STP() \ 1496 USE_ALL_CLKS(); \ 1497 CPU_STOPPED |= STOP_LEVEL_STOP 1498 1499 /* M37710 Transfer accumulator to index */ 1500 #undef OP_TAX 1501 #if FLAG_SET_M 1502 #if FLAG_SET_X 1503 #define OP_TAX(REG) \ 1504 CLK(CLK_OP + CLK_IMPLIED); \ 1505 FLAG_Z = REG = REG_A; \ 1506 FLAG_N = NFLAG_8(FLAG_Z) 1507 #else /* FLAG_SET_X */ 1508 #define OP_TAX(REG) \ 1509 CLK(CLK_OP + CLK_IMPLIED); \ 1510 FLAG_Z = REG = REG_B | REG_A; \ 1511 FLAG_N = NFLAG_16(FLAG_Z) 1512 #endif /* FLAG_SET_X */ 1513 #else /* FLAG_SET_M */ 1514 #if FLAG_SET_X 1515 #define OP_TAX(REG) \ 1516 CLK(CLK_OP + CLK_IMPLIED); \ 1517 FLAG_Z = REG = MAKE_UINT_8(REG_A); \ 1518 FLAG_N = NFLAG_8(FLAG_Z) 1519 #else /* FLAG_SET_X */ 1520 #define OP_TAX(REG) \ 1521 CLK(CLK_OP + CLK_IMPLIED); \ 1522 FLAG_Z = REG = REG_A; \ 1523 FLAG_N = NFLAG_16(FLAG_Z) 1524 #endif /* FLAG_SET_X */ 1525 #endif /* FLAG_SET_M */ 1526 1527 1528 /* M37710 Transfer accumulator B to index */ 1529 #undef OP_TBX 1530 #if FLAG_SET_M 1531 #if FLAG_SET_X 1532 #define OP_TBX(REG) \ 1533 CLK(CLK_OP + CLK_IMPLIED); \ 1534 FLAG_Z = REG = REG_BA; \ 1535 FLAG_N = NFLAG_8(FLAG_Z) 1536 #else /* FLAG_SET_X */ 1537 #define OP_TBX(REG) \ 1538 CLK(CLK_OP + CLK_IMPLIED); \ 1539 FLAG_Z = REG = REG_BB | REG_BA; \ 1540 FLAG_N = NFLAG_16(FLAG_Z) 1541 #endif /* FLAG_SET_X */ 1542 #else /* FLAG_SET_M */ 1543 #if FLAG_SET_X 1544 #define OP_TBX(REG) \ 1545 CLK(CLK_OP + CLK_IMPLIED); \ 1546 FLAG_Z = REG = MAKE_UINT_8(REG_BA); \ 1547 FLAG_N = NFLAG_8(FLAG_Z) 1548 #else /* FLAG_SET_X */ 1549 #define OP_TBX(REG) \ 1550 CLK(CLK_OP + CLK_IMPLIED); \ 1551 FLAG_Z = REG = REG_BA; \ 1552 FLAG_N = NFLAG_16(FLAG_Z) 1553 #endif /* FLAG_SET_X */ 1554 #endif /* FLAG_SET_M */ 1555 1556 /* M37710 Transfer index to accumulator */ 1557 #undef OP_TXA 1558 #if FLAG_SET_M 1559 #define OP_TXA(REG) \ 1560 CLK(CLK_OP + CLK_IMPLIED); \ 1561 FLAG_Z = REG_A = MAKE_UINT_8(REG); \ 1562 FLAG_N = NFLAG_8(FLAG_Z) 1563 #else 1564 #define OP_TXA(REG) \ 1565 CLK(CLK_OP + CLK_IMPLIED); \ 1566 FLAG_Z = REG_A = REG; \ 1567 FLAG_N = NFLAG_16(FLAG_Z) 1568 #endif 1569 1570 /* M37710 Transfer index to accumulator B */ 1571 #undef OP_TXB 1572 #if FLAG_SET_M 1573 #define OP_TXB(REG) \ 1574 CLK(CLK_OP + CLK_IMPLIED); \ 1575 FLAG_Z = REG_BA = MAKE_UINT_8(REG); \ 1576 FLAG_N = NFLAG_8(FLAG_Z) 1577 #else 1578 #define OP_TXB(REG) \ 1579 CLK(CLK_OP + CLK_IMPLIED); \ 1580 FLAG_Z = REG_BA = REG; \ 1581 FLAG_N = NFLAG_16(FLAG_Z) 1582 #endif 1583 1584 /* M37710 Transfer accumulator to direct register */ 1585 #undef OP_TAD 1586 #if FLAG_SET_M 1587 #define OP_TAD() \ 1588 CLK(CLK_OP + CLK_IMPLIED); \ 1589 REG_D = REG_A | REG_B 1590 #else 1591 #define OP_TAD() \ 1592 CLK(CLK_OP + CLK_IMPLIED); \ 1593 REG_D = REG_A 1594 #endif 1595 1596 /* M37710 Transfer accumulator B to direct register */ 1597 #undef OP_TBD 1598 #if FLAG_SET_M 1599 #define OP_TBD() \ 1600 CLK(CLK_OP + CLK_IMPLIED); \ 1601 REG_D = REG_BA | REG_BB 1602 #else 1603 #define OP_TBD() \ 1604 CLK(CLK_OP + CLK_IMPLIED); \ 1605 REG_D = REG_BA 1606 #endif 1607 1608 /* M37710 Transfer direct register to accumulator */ 1609 #undef OP_TDA 1610 #if FLAG_SET_M 1611 #define OP_TDA() \ 1612 CLK(CLK_OP + CLK_IMPLIED); \ 1613 FLAG_Z = REG_D; \ 1614 FLAG_N = NFLAG_16(FLAG_Z); \ 1615 REG_A = MAKE_UINT_8(REG_D); \ 1616 REG_B = REG_D & 0xff00 1617 #else 1618 #define OP_TDA() \ 1619 CLK(CLK_OP + CLK_IMPLIED); \ 1620 FLAG_Z = REG_A = REG_D; \ 1621 FLAG_N = NFLAG_16(FLAG_Z) 1622 #endif 1623 1624 /* M37710 Transfer direct register to accumulator B */ 1625 #undef OP_TDB 1626 #if FLAG_SET_M 1627 #define OP_TDB() \ 1628 CLK(CLK_OP + CLK_IMPLIED); \ 1629 FLAG_Z = REG_D; \ 1630 FLAG_N = NFLAG_16(FLAG_Z); \ 1631 REG_BA = MAKE_UINT_8(REG_D); \ 1632 REG_BB = REG_D & 0xff00 1633 #else 1634 #define OP_TDB() \ 1635 CLK(CLK_OP + CLK_IMPLIED); \ 1636 FLAG_Z = REG_BA = REG_D; \ 1637 FLAG_N = NFLAG_16(FLAG_Z) 1638 #endif 1639 1640 /* M37710 Transfer accumulator to stack pointer */ 1641 #undef OP_TAS 1642 #if FLAG_SET_M 1643 #define OP_TAS() \ 1644 CLK(CLK_OP + CLK_IMPLIED); \ 1645 REG_S = REG_A | REG_B 1646 #else 1647 #define OP_TAS() \ 1648 CLK(CLK_OP + CLK_IMPLIED); \ 1649 REG_S = REG_A 1650 #endif 1651 1652 /* M37710 Transfer accumulator B to stack pointer */ 1653 #undef OP_TBS 1654 #if FLAG_SET_M 1655 #define OP_TBS() \ 1656 CLK(CLK_OP + CLK_IMPLIED); \ 1657 REG_S = REG_BA | REG_BB 1658 #else 1659 #define OP_TBS() \ 1660 CLK(CLK_OP + CLK_IMPLIED); \ 1661 REG_S = REG_BA 1662 #endif 1663 1664 /* M37710 Transfer stack pointer to accumulator */ 1665 #undef OP_TSA 1666 #if FLAG_SET_M 1667 #define OP_TSA() \ 1668 CLK(CLK_OP + CLK_IMPLIED); \ 1669 FLAG_Z = REG_S; \ 1670 FLAG_N = NFLAG_16(FLAG_Z); \ 1671 REG_A = MAKE_UINT_8(REG_S); \ 1672 REG_B = REG_S & 0xff00 1673 #else 1674 #define OP_TSA() \ 1675 CLK(CLK_OP + CLK_IMPLIED); \ 1676 FLAG_Z = REG_A = REG_S; \ 1677 FLAG_N = NFLAG_16(FLAG_Z) 1678 #endif 1679 1680 /* M37710 Transfer stack pointer to accumulator B */ 1681 #undef OP_TSB 1682 #if FLAG_SET_M 1683 #define OP_TSB() \ 1684 CLK(CLK_OP + CLK_IMPLIED); \ 1685 FLAG_Z = REG_S; \ 1686 FLAG_N = NFLAG_16(FLAG_Z); \ 1687 REG_BA = MAKE_UINT_8(REG_S); \ 1688 REG_BB = REG_S & 0xff00 1689 #else 1690 #define OP_TSB() \ 1691 CLK(CLK_OP + CLK_IMPLIED); \ 1692 FLAG_Z = REG_BA = REG_S; \ 1693 FLAG_N = NFLAG_16(FLAG_Z) 1694 #endif 1695 1696 /* M37710 Transfer stack pointer to X */ 1697 #undef OP_TSX 1698 #if FLAG_SET_X 1699 #define OP_TSX() \ 1700 CLK(CLK_OP + CLK_IMPLIED); \ 1701 FLAG_Z = REG_X = MAKE_UINT_8(REG_S); \ 1702 FLAG_N = NFLAG_8(FLAG_Z) 1703 #else 1704 #define OP_TSX() \ 1705 CLK(CLK_OP + CLK_IMPLIED); \ 1706 FLAG_Z = REG_X = REG_S; \ 1707 FLAG_N = NFLAG_16(FLAG_Z) 1708 #endif 1709 1710 /* M37710 Transfer X to stack pointer */ 1711 #undef OP_TXS 1712 #if FLAG_SET_X 1713 #define OP_TXS() \ 1714 CLK(CLK_OP + CLK_IMPLIED); \ 1715 REG_S = MAKE_UINT_8(REG_X) 1716 #else 1717 #define OP_TXS() \ 1718 CLK(CLK_OP + CLK_IMPLIED); \ 1719 REG_S = REG_X 1720 #endif 1721 1722 /* M37710 Transfer X to Y */ 1723 #undef OP_TXY 1724 #if FLAG_SET_X 1725 #define OP_TXY() \ 1726 CLK(CLK_OP + CLK_IMPLIED); \ 1727 FLAG_Z = REG_Y = REG_X; \ 1728 FLAG_N = NFLAG_8(FLAG_Z) 1729 #else 1730 #define OP_TXY() \ 1731 CLK(CLK_OP + CLK_IMPLIED); \ 1732 FLAG_Z = REG_Y = REG_X; \ 1733 FLAG_N = NFLAG_16(FLAG_Z) 1734 #endif 1735 1736 /* M37710 Transfer Y to X */ 1737 #undef OP_TYX 1738 #if FLAG_SET_X 1739 #define OP_TYX() \ 1740 CLK(CLK_OP + CLK_IMPLIED); \ 1741 FLAG_Z = REG_X = REG_Y; \ 1742 FLAG_N = NFLAG_8(FLAG_Z) 1743 #else 1744 #define OP_TYX() \ 1745 CLK(CLK_OP + CLK_IMPLIED); \ 1746 FLAG_Z = REG_X = REG_Y; \ 1747 FLAG_N = NFLAG_16(FLAG_Z) 1748 #endif 1749 1750 /* M37710 clear bit */ 1751 #undef OP_CLB 1752 #if FLAG_SET_M 1753 #define OP_CLB(MODE) \ 1754 CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ 1755 DST = EA_##MODE(); \ 1756 REG_IM = read_8_##MODE(DST); \ 1757 REG_IM2 = read_8_IMM(REG_PB | REG_PC); \ 1758 REG_PC++; \ 1759 write_8_##MODE(DST, REG_IM & ~REG_IM2); 1760 #else 1761 #define OP_CLB(MODE) \ 1762 CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ 1763 DST = EA_##MODE(); \ 1764 REG_IM = read_16_##MODE(DST); \ 1765 REG_IM2 = read_16_IMM(REG_PB | REG_PC); \ 1766 REG_PC+=2; \ 1767 write_16_##MODE(DST, REG_IM & ~REG_IM2); 1768 #endif 1769 1770 /* M37710 set bit */ 1771 #undef OP_SEB 1772 #if FLAG_SET_M 1773 #define OP_SEB(MODE) \ 1774 CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \ 1775 DST = EA_##MODE(); \ 1776 REG_IM = read_8_##MODE(DST); \ 1777 REG_IM2 = read_8_IMM(REG_PB | REG_PC); \ 1778 REG_PC++; \ 1779 write_8_##MODE(DST, REG_IM | REG_IM2); 1780 #else 1781 #define OP_SEB(MODE) \ 1782 CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \ 1783 DST = EA_##MODE(); \ 1784 REG_IM = read_16_##MODE(DST); \ 1785 REG_IM2 = read_16_IMM(REG_PB | REG_PC); \ 1786 REG_PC+=2; \ 1787 write_16_##MODE(DST, REG_IM | REG_IM2); 1788 #endif 1789 1790 /* M37710 Wait for interrupt */ 1791 #undef OP_WAI 1792 #define OP_WAI() \ 1793 USE_ALL_CLKS(); \ 1794 CPU_STOPPED |= STOP_LEVEL_WAI 1795 1796 /* M37710 load data bank register */ 1797 #undef OP_LDT 1798 #define OP_LDT(MODE) \ 1799 CLK(CLK_OP + CLK_R8 + CLK_##MODE); \ 1800 REG_DB = OPER_8_##MODE()<<16; 1801 1802 1803 /* M37710 prefix for B accumulator (0x42) */ 1804 /* There is a 2 cycle penalty for all instructions using this prefix */ 1805 #undef OP_PFB 1806 #define OP_PFB() \ 1807 CLK(2); \ 1808 REG_IR = read_8_IMM(REG_PB | REG_PC); \ 1809 REG_PC++; \ 1810 (*m_opcodes42[REG_IR])(); 1811 1812 1813 /* M37710 prefix for multiply / divide instructions (0x89) */ 1814 #undef OP_PFXM 1815 #define OP_PFXM() \ 1816 REG_IR = read_8_IMM(REG_PB | REG_PC); \ 1817 REG_PC++; \ 1818 (*m_opcodes89[REG_IR])(); 1819 1820 1821 /* M37710 unimplemented opcode */ 1822 #undef OP_UNIMP 1823 #define OP_UNIMP() \ 1824 bprintf(0, _T("error M37710: UNIMPLEMENTED OPCODE! K=%x PC=%x PPC=%x\n"), REG_PB, REG_PC, REG_PPC); 1825 1826 /* ======================================================================== */ 1827 /* ======================== OPCODE & FUNCTION TABLES ====================== */ 1828 /* ======================================================================== */ 1829 1830 #undef OP 1831 #undef O 1832 #undef TABLE_OPCODES 1833 #undef TABLE_OPCODES2 1834 #undef TABLE_OPCODES3 1835 #undef TABLE_FUNCTION 1836 1837 #if !FLAG_SET_M && !FLAG_SET_X 1838 #define OP(CODE, OPERATION) void m37710i_ ## CODE ## _M0X0() {OPERATION;} 1839 #define O(CODE) &m37710i_ ## CODE ## _M0X0 1840 #define TABLE_OPCODES const opcode_func m37710i_opcodes_M0X0[256] 1841 #define TABLE_OPCODES2 const opcode_func m37710i_opcodes42_M0X0[256] 1842 #define TABLE_OPCODES3 const opcode_func m37710i_opcodes89_M0X0[256] 1843 #define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M0X0 ARGS 1844 1845 #elif !FLAG_SET_M && FLAG_SET_X 1846 1847 #define OP(CODE, OPERATION) void m37710i_ ## CODE ## _M0X1() {OPERATION;} 1848 #define O(CODE) &m37710i_ ## CODE ## _M0X1 1849 #define TABLE_OPCODES const opcode_func m37710i_opcodes_M0X1[256] 1850 #define TABLE_OPCODES2 const opcode_func m37710i_opcodes42_M0X1[256] 1851 #define TABLE_OPCODES3 const opcode_func m37710i_opcodes89_M0X1[256] 1852 #define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M0X1 ARGS 1853 1854 #elif FLAG_SET_M && !FLAG_SET_X 1855 1856 #define OP(CODE, OPERATION) void m37710i_ ## CODE ## _M1X0() {OPERATION;} 1857 #define O(CODE) &m37710i_ ## CODE ## _M1X0 1858 #define TABLE_OPCODES const opcode_func m37710i_opcodes_M1X0[256] 1859 #define TABLE_OPCODES2 const opcode_func m37710i_opcodes42_M1X0[256] 1860 #define TABLE_OPCODES3 const opcode_func m37710i_opcodes89_M1X0[256] 1861 #define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M1X0 ARGS 1862 1863 #elif FLAG_SET_M && FLAG_SET_X 1864 1865 #define OP(CODE, OPERATION) void m37710i_ ## CODE ## _M1X1() {OPERATION;} 1866 #define O(CODE) &m37710i_ ## CODE ## _M1X1 1867 #define TABLE_OPCODES const opcode_func m37710i_opcodes_M1X1[256] 1868 #define TABLE_OPCODES2 const opcode_func m37710i_opcodes42_M1X1[256] 1869 #define TABLE_OPCODES3 const opcode_func m37710i_opcodes89_M1X1[256] 1870 #define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE m37710i_ ## NAME ## _M1X1 ARGS 1871 1872 #endif 1873 1874 #define BREAKOUT return 1875 1876 /* OP FUNCTION Comment */ 1877 OP(00, OP_BRK ( ) ) /* BRK */ 1878 OP(01, OP_ORA ( DXI ) ) /* ORA dxi */ 1879 OP(02, OP_NOP ( ) ) /* unused */ 1880 OP(03, OP_ORA ( S ) ) /* ORA s (G) */ 1881 OP(04, OP_SEB ( D ) ) /* SEB d (C) */ 1882 OP(05, OP_ORA ( D ) ) /* ORA d */ 1883 OP(06, OP_ASLM ( D ) ) /* ASL d */ 1884 OP(07, OP_ORA ( DLI ) ) /* ORA dli (G) */ 1885 OP(08, OP_PHP ( ) ) /* PHP */ 1886 OP(09, OP_ORA ( IMM ) ) /* ORA imm */ 1887 OP(0a, OP_ASL ( ) ) /* ASL acc */ 1888 OP(0b, OP_PHD ( ) ) /* PHD (G) */ 1889 OP(0c, OP_SEB ( A ) ) /* SEB a (C) */ 1890 OP(0d, OP_ORA ( A ) ) /* ORA a */ 1891 OP(0e, OP_ASLM ( A ) ) /* ASL a */ 1892 OP(0f, OP_ORA ( AL ) ) /* ORA al (G) */ 1893 OP(10, OP_BCC ( COND_PL() ) ) /* BPL */ 1894 OP(11, OP_ORA ( DIY ) ) /* ORA diy */ 1895 OP(12, OP_ORA ( DI ) ) /* ORA di (C) */ 1896 OP(13, OP_ORA ( SIY ) ) /* ORA siy (G) */ 1897 OP(14, OP_CLB ( D ) ) /* CLB d (C) */ 1898 OP(15, OP_ORA ( DX ) ) /* ORA dx */ 1899 OP(16, OP_ASLM ( DX ) ) /* ASL dx */ 1900 OP(17, OP_ORA ( DLIY ) ) /* ORA dliy(C) */ 1901 OP(18, OP_CLC ( ) ) /* CLC */ 1902 OP(19, OP_ORA ( AY ) ) /* ORA ay */ 1903 OP(1a, OP_DEC ( ) ) /* DEA (C) */ 1904 OP(1b, OP_TAS ( ) ) /* TAS (G) */ 1905 OP(1c, OP_CLB ( A ) ) /* CLB a (C) */ 1906 OP(1d, OP_ORA ( AX ) ) /* ORA ax */ 1907 OP(1e, OP_ASLM ( AX ) ) /* ASL ax */ 1908 OP(1f, OP_ORA ( ALX ) ) /* ORA alx (G) */ 1909 OP(20, OP_JSR ( A ) ) /* JSR a */ 1910 OP(21, OP_AND ( DXI ) ) /* AND dxi */ 1911 OP(22, OP_JSL ( AL ) ) /* JSL al (G) */ 1912 OP(23, OP_AND ( S ) ) /* AND s (G) */ 1913 OP(24, OP_BBS ( D ) ) /* BBS d */ 1914 OP(25, OP_AND ( D ) ) /* AND d */ 1915 OP(26, OP_ROLM ( D ) ) /* ROL d */ 1916 OP(27, OP_AND ( DLI ) ) /* AND dli (G) */ 1917 OP(28, OP_PLP ( ) ) /* PLP */ 1918 OP(29, OP_AND ( IMM ) ) /* AND imm */ 1919 OP(2a, OP_ROL ( ) ) /* ROL acc */ 1920 OP(2b, OP_PLD ( ) ) /* PLD (G) */ 1921 OP(2c, OP_BBS ( A ) ) /* BBS a */ 1922 OP(2d, OP_AND ( A ) ) /* AND a */ 1923 OP(2e, OP_ROLM ( A ) ) /* ROL a */ 1924 OP(2f, OP_AND ( AL ) ) /* AND al (G) */ 1925 OP(30, OP_BCC ( COND_MI() ) ) /* BMI */ 1926 OP(31, OP_AND ( DIY ) ) /* AND diy */ 1927 OP(32, OP_AND ( DI ) ) /* AND di (C) */ 1928 OP(33, OP_AND ( SIY ) ) /* AND siy */ 1929 OP(34, OP_BBC ( D ) ) /* BBC d */ 1930 OP(35, OP_AND ( DX ) ) /* AND dx */ 1931 OP(36, OP_ROLM ( DX ) ) /* ROL dx */ 1932 OP(37, OP_AND ( DLIY ) ) /* AND dliy(G) */ 1933 OP(38, OP_SEC ( ) ) /* SEC */ 1934 OP(39, OP_AND ( AY ) ) /* AND ay */ 1935 OP(3a, OP_INC ( ) ) /* INA (C) */ 1936 OP(3b, OP_TSA ( ) ) /* TSA (G) */ 1937 OP(3c, OP_BBC ( A ) ) /* BBC a */ 1938 OP(3d, OP_AND ( AX ) ) /* AND ax */ 1939 OP(3e, OP_ROLM ( AX ) ) /* ROL ax */ 1940 OP(3f, OP_AND ( ALX ) ) /* AND alx (G) */ 1941 OP(40, OP_RTI ( ) ) /* RTI */ 1942 OP(41, OP_EOR ( DXI ) ) /* EOR dxi */ 1943 OP(42, OP_PFB ( ) ) /* prefix for "B" accumulator */ 1944 OP(43, OP_EOR ( S ) ) /* EOR s (G) */ 1945 OP(44, OP_MVP ( ) ) /* MVP (G) */ 1946 OP(45, OP_EOR ( D ) ) /* EOR d */ 1947 OP(46, OP_LSRM ( D ) ) /* LSR d */ 1948 OP(47, OP_EOR ( DLI ) ) /* EOR dli (G) */ 1949 OP(48, OP_PHA ( ) ) /* PHA */ 1950 OP(49, OP_EOR ( IMM ) ) /* EOR imm */ 1951 OP(4a, OP_LSR ( ) ) /* LSR acc */ 1952 OP(4b, OP_PHK ( ) ) /* PHK (G) */ 1953 OP(4c, OP_JMP ( A ) ) /* JMP a */ 1954 OP(4d, OP_EOR ( A ) ) /* EOR a */ 1955 OP(4e, OP_LSRM ( A ) ) /* LSR a */ 1956 OP(4f, OP_EOR ( AL ) ) /* EOR al (G) */ 1957 OP(50, OP_BCC ( COND_VC() ) ) /* BVC */ 1958 OP(51, OP_EOR ( DIY ) ) /* EOR diy */ 1959 OP(52, OP_EOR ( DI ) ) /* EOR di (C) */ 1960 OP(53, OP_EOR ( SIY ) ) /* EOR siy (G) */ 1961 OP(54, OP_MVN ( ) ) /* MVN (G) */ 1962 OP(55, OP_EOR ( DX ) ) /* EOR dx */ 1963 OP(56, OP_LSRM ( DX ) ) /* LSR dx */ 1964 OP(57, OP_EOR ( DLIY ) ) /* EOR dliy(G) */ 1965 OP(58, OP_CLI ( ) ) /* CLI */ 1966 OP(59, OP_EOR ( AY ) ) /* EOR ay */ 1967 OP(5a, OP_PHX ( REG_Y ) ) /* PHY (C) */ 1968 OP(5b, OP_TAD ( ) ) /* TAD (G) */ 1969 OP(5c, OP_JMPAL( ) ) /* JMP al (G) */ 1970 OP(5d, OP_EOR ( AX ) ) /* EOR ax */ 1971 OP(5e, OP_LSRM ( AX ) ) /* LSR ax */ 1972 OP(5f, OP_EOR ( ALX ) ) /* EOR alx (G) */ 1973 OP(60, OP_RTS ( ) ) /* RTS */ 1974 OP(61, OP_ADC ( DXI ) ) /* ADC dxi */ 1975 OP(62, OP_PER ( ) ) /* PER (G) */ 1976 OP(63, OP_ADC ( S ) ) /* ADC s (G) */ 1977 OP(64, OP_LDM ( D ) ) /* LDM d (C) */ 1978 OP(65, OP_ADC ( D ) ) /* ADC d */ 1979 OP(66, OP_RORM ( D ) ) /* ROR d */ 1980 OP(67, OP_ADC ( DLI ) ) /* ADC dli (G) */ 1981 OP(68, OP_PLA ( ) ) /* PLA */ 1982 OP(69, OP_ADC ( IMM ) ) /* ADC imm */ 1983 OP(6a, OP_ROR ( ) ) /* ROR acc */ 1984 OP(6b, OP_RTL ( ) ) /* RTL (G) */ 1985 OP(6c, OP_JMP ( AI ) ) /* JMP ai */ 1986 OP(6d, OP_ADC ( A ) ) /* ADC a */ 1987 OP(6e, OP_RORM ( A ) ) /* ROR a */ 1988 OP(6f, OP_ADC ( AL ) ) /* ADC al (G) */ 1989 OP(70, OP_BCC ( COND_VS() ) ) /* BVS */ 1990 OP(71, OP_ADC ( DIY ) ) /* ADC diy */ 1991 OP(72, OP_ADC ( DI ) ) /* ADC di (G) */ 1992 OP(73, OP_ADC ( SIY ) ) /* ADC siy (G) */ 1993 OP(74, OP_LDM ( DX ) ) /* LDM dx (C) */ 1994 OP(75, OP_ADC ( DX ) ) /* ADC dx */ 1995 OP(76, OP_RORM ( DX ) ) /* ROR dx */ 1996 OP(77, OP_ADC ( DLIY ) ) /* ADC dliy(G) */ 1997 OP(78, OP_SEI ( ) ) /* SEI */ 1998 OP(79, OP_ADC ( AY ) ) /* ADC ay */ 1999 OP(7a, OP_PLX ( REG_Y ) ) /* PLY (C) */ 2000 OP(7b, OP_TDA ( ) ) /* TDA (G) */ 2001 OP(7c, OP_JMPAXI( ) ) /* JMP axi (C) */ 2002 OP(7d, OP_ADC ( AX ) ) /* ADC ax */ 2003 OP(7e, OP_RORM ( AX ) ) /* ROR ax */ 2004 OP(7f, OP_ADC ( ALX ) ) /* ADC alx (G) */ 2005 OP(80, OP_BRA ( ) ) /* BRA (C) */ 2006 OP(81, OP_STA ( DXI ) ) /* STA dxi */ 2007 OP(82, OP_BRL ( ) ) /* BRL (G) */ 2008 OP(83, OP_STA ( S ) ) /* STA s (G) */ 2009 OP(84, OP_STX ( REG_Y, D ) ) /* STY d */ 2010 OP(85, OP_STA ( D ) ) /* STA d */ 2011 OP(86, OP_STX ( REG_X, D ) ) /* STX d */ 2012 OP(87, OP_STA ( DLI ) ) /* STA dli (G) */ 2013 OP(88, OP_DECX ( REG_Y ) ) /* DEY */ 2014 OP(89, OP_PFXM ( ) ) /* prefix for mul/div insns */ 2015 OP(8a, OP_TXA ( REG_X ) ) /* TXA */ 2016 OP(8b, OP_PHT ( ) ) /* PHT (G) */ 2017 OP(8c, OP_STX ( REG_Y, A ) ) /* STY a */ 2018 OP(8d, OP_STA ( A ) ) /* STA a */ 2019 OP(8e, OP_STX ( REG_X, A ) ) /* STX a */ 2020 OP(8f, OP_STA ( AL ) ) /* STA al (G) */ 2021 OP(90, OP_BCC ( COND_CC() ) ) /* BCC */ 2022 OP(91, OP_STA ( DIY ) ) /* STA diy */ 2023 OP(92, OP_STA ( DI ) ) /* STA di (C) */ 2024 OP(93, OP_STA ( SIY ) ) /* STA siy (G) */ 2025 OP(94, OP_STX ( REG_Y, DX ) ) /* STY dx */ 2026 OP(95, OP_STA ( DX ) ) /* STA dx */ 2027 OP(96, OP_STX ( REG_X, DY ) ) /* STX dy */ 2028 OP(97, OP_STA ( DLIY ) ) /* STA dliy(G) */ 2029 OP(98, OP_TXA ( REG_Y ) ) /* TYA */ 2030 OP(99, OP_STA ( AY ) ) /* STA ay */ 2031 OP(9a, OP_TXS ( ) ) /* TXS */ 2032 OP(9b, OP_TXY ( ) ) /* TXY (G) */ 2033 OP(9c, OP_LDM ( A ) ) /* LDM a (C) */ 2034 OP(9d, OP_STA ( AX ) ) /* STA ax */ 2035 OP(9e, OP_LDM ( AX ) ) /* LDM ax (C) */ 2036 OP(9f, OP_STA ( ALX ) ) /* STA alx (G) */ 2037 OP(a0, OP_LDX ( REG_Y, IMM ) ) /* LDY imm */ 2038 OP(a1, OP_LDA ( DXI ) ) /* LDA dxi */ 2039 OP(a2, OP_LDX ( REG_X, IMM ) ) /* LDX imm */ 2040 OP(a3, OP_LDA ( S ) ) /* LDA s (G) */ 2041 OP(a4, OP_LDX ( REG_Y, D ) ) /* LDY d */ 2042 OP(a5, OP_LDA ( D ) ) /* LDA d */ 2043 OP(a6, OP_LDX ( REG_X, D ) ) /* LDX d */ 2044 OP(a7, OP_LDA ( DLI ) ) /* LDA dli (G) */ 2045 OP(a8, OP_TAX ( REG_Y ) ) /* TAY */ 2046 OP(a9, OP_LDA ( IMM ) ) /* LDA imm */ 2047 OP(aa, OP_TAX ( REG_X ) ) /* TAX */ 2048 OP(ab, OP_PLT ( ) ) /* PLT (G) */ 2049 OP(ac, OP_LDX ( REG_Y, A ) ) /* LDY a */ 2050 OP(ad, OP_LDA ( A ) ) /* LDA a */ 2051 OP(ae, OP_LDX ( REG_X, A ) ) /* LDX a */ 2052 OP(af, OP_LDA ( AL ) ) /* LDA al (G) */ 2053 OP(b0, OP_BCC ( COND_CS() ) ) /* BCS */ 2054 OP(b1, OP_LDA ( DIY ) ) /* LDA diy */ 2055 OP(b2, OP_LDA ( DI ) ) /* LDA di (C) */ 2056 OP(b3, OP_LDA ( SIY ) ) /* LDA siy (G) */ 2057 OP(b4, OP_LDX ( REG_Y, DX ) ) /* LDY dx */ 2058 OP(b5, OP_LDA ( DX ) ) /* LDA dx */ 2059 OP(b6, OP_LDX ( REG_X, DY ) ) /* LDX dy */ 2060 OP(b7, OP_LDA ( DLIY ) ) /* LDA dliy(G) */ 2061 OP(b8, OP_CLV ( ) ) /* CLV */ 2062 OP(b9, OP_LDA ( AY ) ) /* LDA ay */ 2063 OP(ba, OP_TSX ( ) ) /* TSX */ 2064 OP(bb, OP_TYX ( ) ) /* TYX (G) */ 2065 OP(bc, OP_LDX ( REG_Y, AX ) ) /* LDY ax */ 2066 OP(bd, OP_LDA ( AX ) ) /* LDA ax */ 2067 OP(be, OP_LDX ( REG_X, AY ) ) /* LDX ay */ 2068 OP(bf, OP_LDA ( ALX ) ) /* LDA alx (G) */ 2069 OP(c0, OP_CMPX ( REG_Y, IMM ) ) /* CPY imm */ 2070 OP(c1, OP_CMP ( DXI ) ) /* CMP dxi */ 2071 OP(c2, OP_REP ( ) ) /* REP (G) */ 2072 OP(c3, OP_CMP ( S ) ) /* CMP s (G) */ 2073 OP(c4, OP_CMPX ( REG_Y, D ) ) /* CPY d */ 2074 OP(c5, OP_CMP ( D ) ) /* CMP d */ 2075 OP(c6, OP_DECM ( D ) ) /* DEC d */ 2076 OP(c7, OP_CMP ( DLI ) ) /* CMP dli (G) */ 2077 OP(c8, OP_INCX ( REG_Y ) ) /* INY */ 2078 OP(c9, OP_CMP ( IMM ) ) /* CMP imm */ 2079 OP(ca, OP_DECX ( REG_X ) ) /* DEX */ 2080 OP(cb, OP_WAI ( ) ) /* WAI (G) */ 2081 OP(cc, OP_CMPX ( REG_Y, A ) ) /* CPY a */ 2082 OP(cd, OP_CMP ( A ) ) /* CMP a */ 2083 OP(ce, OP_DECM ( A ) ) /* DEC a */ 2084 OP(cf, OP_CMP ( AL ) ) /* CMP al (G) */ 2085 OP(d0, OP_BCC ( COND_NE() ) ) /* BNE */ 2086 OP(d1, OP_CMP ( DIY ) ) /* CMP diy */ 2087 OP(d2, OP_CMP ( DI ) ) /* CMP di (C) */ 2088 OP(d3, OP_CMP ( SIY ) ) /* CMP siy (G) */ 2089 OP(d4, OP_PEI ( ) ) /* PEI (G) */ 2090 OP(d5, OP_CMP ( DX ) ) /* CMP dx */ 2091 OP(d6, OP_DECM ( DX ) ) /* DEC dx */ 2092 OP(d7, OP_CMP ( DLIY ) ) /* CMP dliy(G) */ 2093 OP(d8, OP_CLM ( ) ) /* CLM */ 2094 OP(d9, OP_CMP ( AY ) ) /* CMP ay */ 2095 OP(da, OP_PHX ( REG_X ) ) /* PHX (C) */ 2096 OP(db, OP_STP ( ) ) /* STP (G) */ 2097 OP(dc, OP_JMLAI( ) ) /* JML ai (G) */ 2098 OP(dd, OP_CMP ( AX ) ) /* CMP ax */ 2099 OP(de, OP_DECM ( AX ) ) /* DEC ax */ 2100 OP(df, OP_CMP ( ALX ) ) /* CMP alx (G) */ 2101 OP(e0, OP_CMPX ( REG_X, IMM ) ) /* CPX imm */ 2102 OP(e1, OP_SBC ( DXI ) ) /* SBC dxi */ 2103 OP(e2, OP_SEP ( ) ) /* SEP imm (G) */ 2104 OP(e3, OP_SBC ( S ) ) /* SBC s (G) */ 2105 OP(e4, OP_CMPX ( REG_X, D ) ) /* CPX d */ 2106 OP(e5, OP_SBC ( D ) ) /* SBC d */ 2107 OP(e6, OP_INCM ( D ) ) /* INC d */ 2108 OP(e7, OP_SBC ( DLI ) ) /* SBC dli (G) */ 2109 OP(e8, OP_INCX ( REG_X ) ) /* INX */ 2110 OP(e9, OP_SBC ( IMM ) ) /* SBC imm */ 2111 OP(ea, OP_NOP ( ) ) /* NOP */ 2112 OP(eb, OP_PSH ( IMM ) ) /* PSH imm */ 2113 OP(ec, OP_CMPX ( REG_X, A ) ) /* CPX a */ 2114 OP(ed, OP_SBC ( A ) ) /* SBC a */ 2115 OP(ee, OP_INCM ( A ) ) /* INC a */ 2116 OP(ef, OP_SBC ( AL ) ) /* SBC al (G) */ 2117 OP(f0, OP_BCC ( COND_EQ() ) ) /* BEQ */ 2118 OP(f1, OP_SBC ( DIY ) ) /* SBC diy */ 2119 OP(f2, OP_SBC ( DI ) ) /* SBC di (C) */ 2120 OP(f3, OP_SBC ( SIY ) ) /* SBC siy (G) */ 2121 OP(f4, OP_PEA ( ) ) /* PEA (G) */ 2122 OP(f5, OP_SBC ( DX ) ) /* SBC dx */ 2123 OP(f6, OP_INCM ( DX ) ) /* INC dx */ 2124 OP(f7, OP_SBC ( DLIY ) ) /* SBC dliy(G) */ 2125 OP(f8, OP_SEM ( ) ) /* SEM */ 2126 OP(f9, OP_SBC ( AY ) ) /* SBC ay */ 2127 OP(fa, OP_PLX ( REG_X ) ) /* PLX (C) */ 2128 OP(fb, OP_PUL ( IMM ) ) /* PUL imm */ 2129 OP(fc, OP_JSRAXI( ) ) /* JSR axi (G) */ 2130 OP(fd, OP_SBC ( AX ) ) /* SBC ax */ 2131 OP(fe, OP_INCM ( AX ) ) /* INC ax */ 2132 OP(ff, OP_SBC ( ALX ) ) /* SBC alx (G) */ 2133 2134 /* B accumulator */ 2135 OP(101,OP_ORB ( DXI ) ) /* ORB dxi */ 2136 OP(103,OP_ORB ( S ) ) /* ORB s */ 2137 OP(105,OP_ORB ( D ) ) /* ORB d */ 2138 OP(107,OP_ORB ( DLI ) ) /* ORB dli */ 2139 OP(109,OP_ORB ( IMM ) ) /* ORB imm */ 2140 OP(10a,OP_BSL ( ) ) /* BSL acc */ 2141 OP(10d,OP_ORB ( A ) ) /* ORB a */ 2142 OP(10f,OP_ORB ( AL ) ) /* ORB al */ 2143 OP(111,OP_ORB ( DIY ) ) /* ORB diy */ 2144 OP(112,OP_ORB ( DI ) ) /* ORB di */ 2145 OP(113,OP_ORB ( SIY ) ) /* ORB siy */ 2146 OP(115,OP_ORB ( DX ) ) /* ORB dx */ 2147 OP(117,OP_ORB ( DLIY ) ) /* ORB dliy */ 2148 OP(119,OP_ORB ( AY ) ) /* ORB ay */ 2149 OP(11a,OP_DECB ( ) ) /* DEB */ 2150 OP(11b,OP_TBS ( ) ) /* TBS */ 2151 OP(11d,OP_ORB ( AX ) ) /* ORB ax */ 2152 OP(11f,OP_ORB ( ALX ) ) /* ORB alx */ 2153 OP(121,OP_ANDB ( DXI ) ) /* ANDB dxi */ 2154 OP(123,OP_ANDB ( S ) ) /* ANDB s */ 2155 OP(125,OP_ANDB ( D ) ) /* ANDB d */ 2156 OP(127,OP_ANDB ( DLI ) ) /* ANDB dli */ 2157 OP(129,OP_ANDB ( IMM ) ) /* ANDB imm */ 2158 OP(12a,OP_ROLB ( ) ) /* ROL Bacc */ 2159 OP(12d,OP_ANDB ( A ) ) /* ANDB a */ 2160 OP(12f,OP_ANDB ( AL ) ) /* ANDB al */ 2161 OP(131,OP_ANDB ( DIY ) ) /* ANDB diy */ 2162 OP(132,OP_ANDB ( DI ) ) /* ANDB di */ 2163 OP(133,OP_ANDB ( SIY ) ) /* ANDB siy */ 2164 OP(135,OP_ANDB ( DX ) ) /* ANDB dx */ 2165 OP(137,OP_ANDB ( DLIY ) ) /* ANDB dliy */ 2166 OP(139,OP_ANDB ( AY ) ) /* ANDB ay */ 2167 OP(13a,OP_INCB ( ) ) /* INB */ 2168 OP(13b,OP_TSB ( ) ) /* TSB */ 2169 OP(13d,OP_ANDB ( AX ) ) /* ANDB ax */ 2170 OP(13f,OP_ANDB ( ALX ) ) /* ANDB alx */ 2171 OP(141,OP_EORB ( DXI ) ) /* EORB dxi */ 2172 OP(143,OP_EORB ( S ) ) /* EORB s */ 2173 OP(145,OP_EORB ( D ) ) /* EORB d */ 2174 OP(147,OP_EORB ( DLI ) ) /* EORB dli */ 2175 OP(148,OP_PHAB ( ) ) /* PHB */ 2176 OP(149,OP_EORB ( IMM ) ) /* EORB imm */ 2177 OP(14a,OP_LSRB ( ) ) /* LSRB acc */ 2178 OP(14d,OP_EORB ( A ) ) /* EORB a */ 2179 OP(14f,OP_EORB ( AL ) ) /* EORB al */ 2180 OP(151,OP_EORB ( DIY ) ) /* EORB diy */ 2181 OP(152,OP_EORB ( DI ) ) /* EORB di */ 2182 OP(153,OP_EORB ( SIY ) ) /* EORB siy */ 2183 OP(155,OP_EORB ( DX ) ) /* EORB dx */ 2184 OP(157,OP_EORB ( DLIY ) ) /* EORB dliy */ 2185 OP(159,OP_EORB ( AY ) ) /* EORB ay */ 2186 OP(15b,OP_TBD ( ) ) /* TBD */ 2187 OP(15d,OP_EORB ( AX ) ) /* EORB ax */ 2188 OP(15f,OP_EORB ( ALX ) ) /* EORB alx */ 2189 OP(161,OP_ADCB ( DXI ) ) /* ADCB dxi */ 2190 OP(163,OP_ADCB ( S ) ) /* ADCB s */ 2191 OP(165,OP_ADCB ( D ) ) /* ADCB d */ 2192 OP(167,OP_ADCB ( DLI ) ) /* ADCB dli */ 2193 OP(168,OP_PLAB ( ) ) /* PLB */ 2194 OP(169,OP_ADCB ( IMM ) ) /* ADCB imm */ 2195 OP(16a,OP_RORB ( ) ) /* ROR Bacc */ 2196 OP(16d,OP_ADCB ( A ) ) /* ADCB a */ 2197 OP(16f,OP_ADCB ( AL ) ) /* ADCB al */ 2198 OP(171,OP_ADCB ( DIY ) ) /* ADCB diy */ 2199 OP(172,OP_ADCB ( DI ) ) /* ADCB di */ 2200 OP(173,OP_ADCB ( SIY ) ) /* ADCB siy */ 2201 OP(175,OP_ADCB ( DX ) ) /* ADCB dx */ 2202 OP(177,OP_ADCB ( DLIY ) ) /* ADCB dliy */ 2203 OP(179,OP_ADCB ( AY ) ) /* ADCB ay */ 2204 OP(17b,OP_TDB ( ) ) /* TDB */ 2205 OP(17d,OP_ADCB ( AX ) ) /* ADCB ax */ 2206 OP(17f,OP_ADCB ( ALX ) ) /* ADCB alx */ 2207 OP(181,OP_STB ( DXI ) ) /* STB dxi */ 2208 OP(183,OP_STB ( S ) ) /* STB s */ 2209 OP(185,OP_STB ( D ) ) /* STB d */ 2210 OP(187,OP_STB ( DLI ) ) /* STB dli */ 2211 OP(18a,OP_TXB ( REG_X ) ) /* TXB */ 2212 OP(18d,OP_STB ( A ) ) /* STB a */ 2213 OP(18f,OP_STB ( AL ) ) /* STB al */ 2214 OP(191,OP_STB ( DIY ) ) /* STB diy */ 2215 OP(192,OP_STB ( DI ) ) /* STB di */ 2216 OP(193,OP_STB ( SIY ) ) /* STB siy */ 2217 OP(195,OP_STB ( DX ) ) /* STB dx */ 2218 OP(197,OP_STB ( DLIY ) ) /* STB dliy */ 2219 OP(198,OP_TXB ( REG_Y ) ) /* TYB */ 2220 OP(199,OP_STB ( AY ) ) /* STB ay */ 2221 OP(19d,OP_STB ( AX ) ) /* STB ax */ 2222 OP(19f,OP_STB ( ALX ) ) /* STB alx */ 2223 OP(1a1,OP_LDB ( DXI ) ) /* LDB dxi */ 2224 OP(1a3,OP_LDB ( S ) ) /* LDB s */ 2225 OP(1a5,OP_LDB ( D ) ) /* LDB d */ 2226 OP(1a7,OP_LDB ( DLI ) ) /* LDB dli */ 2227 OP(1a8,OP_TBX ( REG_Y ) ) /* TBY */ 2228 OP(1a9,OP_LDB ( IMM ) ) /* LDB imm */ 2229 OP(1aa,OP_TBX ( REG_X ) ) /* TBX */ 2230 OP(1ad,OP_LDB ( A ) ) /* LDB a */ 2231 OP(1af,OP_LDB ( AL ) ) /* LDB al */ 2232 OP(1b1,OP_LDB ( DIY ) ) /* LDB diy */ 2233 OP(1b2,OP_LDB ( DI ) ) /* LDB di */ 2234 OP(1b3,OP_LDB ( SIY ) ) /* LDB siy */ 2235 OP(1b5,OP_LDB ( DX ) ) /* LDB dx */ 2236 OP(1b7,OP_LDB ( DLIY ) ) /* LDB dliy */ 2237 OP(1b9,OP_LDB ( AY ) ) /* LDB ay */ 2238 OP(1bd,OP_LDB ( AX ) ) /* LDB ax */ 2239 OP(1bf,OP_LDB ( ALX ) ) /* LDB alx */ 2240 OP(1c1,OP_CMPB ( DXI ) ) /* CMPB dxi */ 2241 OP(1c3,OP_CMPB ( S ) ) /* CMPB s */ 2242 OP(1c5,OP_CMPB ( D ) ) /* CMPB d */ 2243 OP(1c7,OP_CMPB ( DLI ) ) /* CMPB dli */ 2244 OP(1c9,OP_CMPB ( IMM ) ) /* CMPB imm */ 2245 OP(1cd,OP_CMPB ( A ) ) /* CMPB a */ 2246 OP(1cf,OP_CMPB ( AL ) ) /* CMPB al */ 2247 OP(1d1,OP_CMPB ( DIY ) ) /* CMPB diy */ 2248 OP(1d2,OP_CMPB ( DI ) ) /* CMPB di */ 2249 OP(1d3,OP_CMPB ( SIY ) ) /* CMPB siy */ 2250 OP(1d5,OP_CMPB ( DX ) ) /* CMPB dx */ 2251 OP(1d7,OP_CMPB ( DLIY ) ) /* CMPB dliy */ 2252 OP(1d9,OP_CMPB ( AY ) ) /* CMPB ay */ 2253 OP(1dd,OP_CMPB ( AX ) ) /* CMPB ax */ 2254 OP(1df,OP_CMPB ( ALX ) ) /* CMPB alx */ 2255 OP(1e1,OP_SBCB ( DXI ) ) /* SBCB dxi */ 2256 OP(1e3,OP_SBCB ( S ) ) /* SBCB s */ 2257 OP(1e5,OP_SBCB ( D ) ) /* SBCB d */ 2258 OP(1e7,OP_SBCB ( DLI ) ) /* SBCB dli */ 2259 OP(1e9,OP_SBCB ( IMM ) ) /* SBCB imm */ 2260 OP(1ed,OP_SBCB ( A ) ) /* SBCB a */ 2261 OP(1ef,OP_SBCB ( AL ) ) /* SBCB al */ 2262 OP(1f1,OP_SBCB ( DIY ) ) /* SBCB diy */ 2263 OP(1f2,OP_SBCB ( DI ) ) /* SBCB di */ 2264 OP(1f3,OP_SBCB ( SIY ) ) /* SBCB siy */ 2265 OP(1f5,OP_SBCB ( DX ) ) /* SBCB dx */ 2266 OP(1f7,OP_SBCB ( DLIY ) ) /* SBCB dliy */ 2267 OP(1f9,OP_SBCB ( AY ) ) /* SBCB ay */ 2268 OP(1fd,OP_SBCB ( AX ) ) /* SBCB ax */ 2269 OP(1ff,OP_SBCB ( ALX ) ) /* SBCB alx */ 2270 2271 OP(200,OP_UNIMP( ) ) /* unimplemented */ 2272 2273 /* multiply/divide */ 2274 OP(201,OP_MPY ( DXI ) ) /* MPY dxi */ 2275 OP(203,OP_MPY ( S ) ) /* MPY s */ 2276 OP(205,OP_MPY ( D ) ) /* MPY d */ 2277 OP(207,OP_MPY ( DLI ) ) /* MPY dli */ 2278 OP(209,OP_MPY ( IMM ) ) /* MPY imm */ 2279 OP(20d,OP_MPY ( A ) ) /* MPY a */ 2280 OP(20f,OP_MPY ( AL ) ) /* MPY al */ 2281 OP(211,OP_MPY ( DIY ) ) /* MPY diy */ 2282 OP(212,OP_MPY ( DI ) ) /* MPY di */ 2283 OP(213,OP_MPY ( SIY ) ) /* MPY siy */ 2284 OP(215,OP_MPY ( DX ) ) /* MPY dx */ 2285 OP(217,OP_MPY ( DLIY ) ) /* MPY dliy */ 2286 OP(219,OP_MPY ( AY ) ) /* MPY ay */ 2287 OP(21d,OP_MPY ( AX ) ) /* MPY ax */ 2288 OP(21f,OP_MPY ( ALX ) ) /* MPY alx */ 2289 OP(221,OP_DIV ( DXI ) ) /* DIV dxi */ 2290 OP(223,OP_DIV ( S ) ) /* DIV s */ 2291 OP(225,OP_DIV ( D ) ) /* DIV d */ 2292 OP(227,OP_DIV ( DLI ) ) /* DIV dli */ 2293 OP(228,OP_XAB ( ) ) /* XAB */ 2294 OP(229,OP_DIV ( IMM ) ) /* DIV imm */ 2295 OP(22d,OP_DIV ( A ) ) /* DIV a */ 2296 OP(22f,OP_DIV ( AL ) ) /* DIV al */ 2297 OP(231,OP_DIV ( DIY ) ) /* DIV diy */ 2298 OP(232,OP_DIV ( DI ) ) /* DIV di */ 2299 OP(233,OP_DIV ( SIY ) ) /* DIV siy */ 2300 OP(235,OP_DIV ( DX ) ) /* DIV dx */ 2301 OP(237,OP_DIV ( DLIY ) ) /* DIV dliy */ 2302 OP(239,OP_DIV ( AY ) ) /* DIV ay */ 2303 OP(23d,OP_DIV ( AX ) ) /* DIV ax */ 2304 OP(23f,OP_DIV ( ALX ) ) /* DIV alx */ 2305 OP(249,OP_RLA ( IMM ) ) /* RLA imm */ 2306 OP(2c2,OP_LDT ( IMM ) ) /* LDT imm */ 2307 // note: block 28x-2bx is for 7750 opcodes, not implemented yet 2308 2309 TABLE_OPCODES = 2310 // 00 01 02 03 04 05 06 07 2311 // 08 09 0a 0b 0c 0d 0e 0f 2312 { 2313 O(00), O(01), O(02), O(03), O(04), O(05), O(06), O(07), // 00 2314 O(08), O(09), O(0a), O(0b), O(0c), O(0d), O(0e), O(0f), 2315 O(10), O(11), O(12), O(13), O(14), O(15), O(16), O(17), // 10 2316 O(18), O(19), O(1a), O(1b), O(1c), O(1d), O(1e), O(1f), 2317 O(20), O(21), O(22), O(23), O(24), O(25), O(26), O(27), // 20 2318 O(28), O(29), O(2a), O(2b), O(2c), O(2d), O(2e), O(2f), 2319 O(30), O(31), O(32), O(33), O(34), O(35), O(36), O(37), // 30 2320 O(38), O(39), O(3a), O(3b), O(3c), O(3d), O(3e), O(3f), 2321 O(40), O(41), O(42), O(43), O(44), O(45), O(46), O(47), // 40 2322 O(48), O(49), O(4a), O(4b), O(4c), O(4d), O(4e), O(4f), 2323 O(50), O(51), O(52), O(53), O(54), O(55), O(56), O(57), // 50 2324 O(58), O(59), O(5a), O(5b), O(5c), O(5d), O(5e), O(5f), 2325 O(60), O(61), O(62), O(63), O(64), O(65), O(66), O(67), // 60 2326 O(68), O(69), O(6a), O(6b), O(6c), O(6d), O(6e), O(6f), 2327 O(70), O(71), O(72), O(73), O(74), O(75), O(76), O(77), // 70 2328 O(78), O(79), O(7a), O(7b), O(7c), O(7d), O(7e), O(7f), 2329 O(80), O(81), O(82), O(83), O(84), O(85), O(86), O(87), // 80 2330 O(88), O(89), O(8a), O(8b), O(8c), O(8d), O(8e), O(8f), 2331 O(90), O(91), O(92), O(93), O(94), O(95), O(96), O(97), // 90 2332 O(98), O(99), O(9a), O(9b), O(9c), O(9d), O(9e), O(9f), 2333 O(a0), O(a1), O(a2), O(a3), O(a4), O(a5), O(a6), O(a7), // a0 2334 O(a8), O(a9), O(aa), O(ab), O(ac), O(ad), O(ae), O(af), 2335 O(b0), O(b1), O(b2), O(b3), O(b4), O(b5), O(b6), O(b7), // b0 2336 O(b8), O(b9), O(ba), O(bb), O(bc), O(bd), O(be), O(bf), 2337 O(c0), O(c1), O(c2), O(c3), O(c4), O(c5), O(c6), O(c7), // c0 2338 O(c8), O(c9), O(ca), O(cb), O(cc), O(cd), O(ce), O(cf), 2339 O(d0), O(d1), O(d2), O(d3), O(d4), O(d5), O(d6), O(d7), // d0 2340 O(d8), O(d9), O(da), O(db), O(dc), O(dd), O(de), O(df), 2341 O(e0), O(e1), O(e2), O(e3), O(e4), O(e5), O(e6), O(e7), // e0 2342 O(e8), O(e9), O(ea), O(eb), O(ec), O(ed), O(ee), O(ef), 2343 O(f0), O(f1), O(f2), O(f3), O(f4), O(f5), O(f6), O(f7), // f0 2344 O(f8), O(f9), O(fa), O(fb), O(fc), O(fd), O(fe), O(ff) 2345 }; 2346 2347 TABLE_OPCODES2 = 2348 // 00 01 02 03 04 05 06 07 2349 // 08 09 0a 0b 0c 0d 0e 0f 2350 { 2351 O(200),O(101),O(200),O(103),O(200),O(105),O(200),O(107), // 00 2352 O(200),O(109),O(10a),O(200),O(200),O(10d),O(200),O(10f), 2353 O(200),O(111),O(112),O(113),O(200),O(115),O(200),O(117), // 10 2354 O(200),O(119),O(11a),O(11b),O(200),O(11d),O(200),O(11f), 2355 O(200),O(121),O(200),O(123),O(200),O(125),O(200),O(127), // 20 2356 O(200),O(129),O(12a),O(200),O(200),O(12d),O(200),O(12f), 2357 O(200),O(131),O(132),O(133),O(200),O(135),O(200),O(137), // 30 2358 O(200),O(139),O(13a),O(13b),O(200),O(13d),O(200),O(13f), 2359 O(200),O(141),O(200),O(143),O(200),O(145),O(200),O(147), // 40 2360 O(148),O(149),O(14a),O(200),O(200),O(14d),O(200),O(14f), 2361 O(200),O(151),O(152),O(153),O(200),O(155),O(200),O(157), // 50 2362 O(200),O(159),O(200),O(15b),O(200),O(15d),O(200),O(15f), 2363 O(200),O(161),O(200),O(163),O(200),O(165),O(200),O(167), // 60 2364 O(168),O(169),O(16a),O(200),O(200),O(16d),O(200),O(16f), 2365 O(200),O(171),O(172),O(173),O(200),O(175),O(200),O(177), // 70 2366 O(200),O(179),O(200),O(17b),O(200),O(17d),O(200),O(17f), 2367 O(200),O(181),O(200),O(183),O(200),O(185),O(200),O(187), // 80 2368 O(200),O(200),O(18a),O(200),O(200),O(18d),O(200),O(18f), 2369 O(200),O(191),O(192),O(193),O(200),O(195),O(200),O(197), // 90 2370 O(198),O(199),O(200),O(200),O(200),O(19d),O(200),O(19f), 2371 O(200),O(1a1),O(200),O(1a3),O(200),O(1a5),O(200),O(1a7), // a0 2372 O(1a8),O(1a9),O(1aa),O(200),O(200),O(1ad),O(200),O(1af), 2373 O(200),O(1b1),O(1b2),O(1b3),O(200),O(1b5),O(200),O(1b7), // b0 2374 O(200),O(1b9),O(200),O(200),O(200),O(1bd),O(200),O(1bf), 2375 O(200),O(1c1),O(200),O(1c3),O(200),O(1c5),O(200),O(1c7), // c0 2376 O(200),O(1c9),O(200),O(200),O(200),O(1cd),O(200),O(1cf), 2377 O(200),O(1d1),O(1d2),O(1d3),O(200),O(1d5),O(200),O(1d7), // d0 2378 O(200),O(1d9),O(200),O(200),O(200),O(1dd),O(200),O(1df), 2379 O(200),O(1e1),O(200),O(1e3),O(200),O(1e5),O(200),O(1e7), // e0 2380 O(200),O(1e9),O(200),O(200),O(200),O(1ed),O(200),O(1ef), 2381 O(200),O(1f1),O(1f2),O(1f3),O(200),O(1f5),O(200),O(1f7), // f0 2382 O(200),O(1f9),O(200),O(200),O(200),O(1fd),O(200),O(1ff) 2383 }; 2384 2385 TABLE_OPCODES3 = 2386 // 00 01 02 03 04 05 06 07 2387 // 08 09 0a 0b 0c 0d 0e 0f 2388 { 2389 O(200),O(201),O(200),O(203),O(200),O(205),O(200),O(207), // 00 2390 O(200),O(209),O(200),O(200),O(200),O(20d),O(200),O(20f), 2391 O(200),O(211),O(212),O(213),O(200),O(215),O(200),O(217), // 10 2392 O(200),O(219),O(200),O(200),O(200),O(21d),O(200),O(21f), 2393 O(200),O(221),O(200),O(223),O(200),O(225),O(200),O(227), // 20 2394 O(228),O(229),O(200),O(200),O(200),O(22d),O(200),O(22f), 2395 O(200),O(231),O(232),O(233),O(200),O(235),O(200),O(237), // 30 2396 O(200),O(239),O(200),O(200),O(200),O(23d),O(200),O(23f), 2397 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 40 2398 O(200),O(249),O(200),O(200),O(200),O(200),O(200),O(200), 2399 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 50 2400 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2401 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 60 2402 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2403 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 70 2404 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2405 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 80 2406 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2407 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // 90 2408 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2409 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // a0 2410 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2411 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // b0 2412 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2413 O(200),O(200),O(2c2),O(200),O(200),O(200),O(200),O(200), // c0 2414 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2415 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // d0 2416 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2417 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // e0 2418 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), 2419 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200), // f0 2420 O(200),O(200),O(200),O(200),O(200),O(200),O(200),O(200) 2421 }; 2422 2423 2424 /* Assert or clear a line on the CPU */ 2425 TABLE_FUNCTION(void, set_line, (int line, int state)) 2426 { 2427 switch(line) 2428 { 2429 // maskable interrupts 2430 case M37710_LINE_ADC: 2431 case M37710_LINE_UART1XMIT: 2432 case M37710_LINE_UART1RECV: 2433 case M37710_LINE_UART0XMIT: 2434 case M37710_LINE_UART0RECV: 2435 case M37710_LINE_TIMERB2: 2436 case M37710_LINE_TIMERB1: 2437 case M37710_LINE_TIMERB0: 2438 case M37710_LINE_TIMERA4: 2439 case M37710_LINE_TIMERA3: 2440 case M37710_LINE_TIMERA2: 2441 case M37710_LINE_TIMERA1: 2442 case M37710_LINE_TIMERA0: 2443 case M37710_LINE_IRQ2: 2444 case M37710_LINE_IRQ1: 2445 case M37710_LINE_IRQ0: 2446 switch(state) 2447 { 2448 case CLEAR_LINE: 2449 LINE_IRQ &= ~(1 << line); 2450 if (m37710_irq_levels[line]) 2451 { 2452 m377.m37710_regs[m37710_irq_levels[line]] &= ~8; 2453 } 2454 break; 2455 2456 case ASSERT_LINE: 2457 case PULSE_LINE: 2458 case HOLD_LINE: 2459 case CPU_IRQSTATUS_HOLD: 2460 LINE_IRQ |= (1 << line); 2461 if (m37710_irq_levels[line]) 2462 { 2463 m377.m37710_regs[m37710_irq_levels[line]] |= 8; 2464 } 2465 break; 2466 2467 default: break; 2468 } 2469 break; 2470 2471 default: break; 2472 } 2473 } 2474 2475 2476 2477 /* Get a register from the CPU core */ 2478 TABLE_FUNCTION(UINT32, get_reg, (int regnum)) 2479 { 2480 switch(regnum) 2481 { 2482 case M37710_A: return REG_B | REG_A; 2483 case M37710_B: return REG_BB | REG_BA; 2484 case M37710_X: return REG_X; 2485 case M37710_Y: return REG_Y; 2486 case M37710_S: return REG_S; 2487 case M37710_PC: return REG_PC; 2488 case M37710_PB: return REG_PB >> 16; 2489 case M37710_DB: return REG_DB >> 16; 2490 case M37710_D: return REG_D; 2491 case M37710_P: return m37710i_get_reg_p(); 2492 case M37710_IRQ_STATE: return LINE_IRQ; 2493 case STATE_GENPCBASE: return REG_PPC; 2494 } 2495 return 0; 2496 } 2497 2498 TABLE_FUNCTION(void, set_reg, (int regnum, UINT32 val)) 2499 { 2500 switch(regnum) 2501 { 2502 case M37710_PC: REG_PC = MAKE_UINT_16(val); break; 2503 case M37710_S: REG_S = MAKE_UINT_16(val); break; 2504 case M37710_P: m37710i_set_reg_p(val); break; 2505 #if FLAG_SET_M 2506 case M37710_A: REG_A = MAKE_UINT_8(val); REG_B = val&0xff00; break; 2507 case M37710_B: REG_BA = MAKE_UINT_8(val); REG_BB = val&0xff00; break; 2508 #else 2509 case M37710_A: REG_A = MAKE_UINT_16(val); break; 2510 case M37710_B: REG_BA = MAKE_UINT_16(val); break; 2511 #endif 2512 #if FLAG_SET_X 2513 case M37710_X: REG_X = MAKE_UINT_8(val); break; 2514 case M37710_Y: REG_Y = MAKE_UINT_8(val); break; 2515 #else 2516 case M37710_X: REG_X = MAKE_UINT_16(val); break; 2517 case M37710_Y: REG_Y = MAKE_UINT_16(val); break; 2518 #endif 2519 case M37710_IRQ_STATE: (*FTABLE_SET_LINE)(M37710_LINE_IRQ0, val == 0 ? CLEAR_LINE : ASSERT_LINE); break; 2520 } 2521 } 2522 2523 TABLE_FUNCTION(int, execute, (int clocks)) 2524 { 2525 if(!CPU_STOPPED) 2526 { 2527 //extern int counter; 2528 do 2529 { 2530 m37710i_update_irqs(); 2531 REG_PPC = REG_PC; 2532 //M37710_CALL_DEBUGGER(REG_PB | REG_PC); 2533 REG_PC++; 2534 REG_IR = read_8_IMM(REG_PB | REG_PPC); 2535 (*m_opcodes[REG_IR])(); 2536 //if (counter) bprintf(0, _T("pc: %x\tppc: %x\n"),REG_PB | REG_PC, REG_PB | REG_PPC); 2537 } while(CLOCKS > 0 && !m377.end_run); 2538 return CLOCKS; // CLOCKS is m377.ICount 2539 } 2540 CLOCKS = 0; 2541 return 0; 2542 } 2543 2544 2545 /* ======================================================================== */ 2546 /* ================================== EOF ================================= */ 2547 /* ======================================================================== */ 2548