1 /*****************************************************************************
2 *
3 * tbl65c02.c
4 * 65c02 opcode functions and function pointer table
5 *
6 * Copyright Juergen Buchmueller, all rights reserved.
7 *
8 * - This source code is released as freeware for non-commercial purposes.
9 * - You are free to use and redistribute this code in modified or
10 * unmodified form, provided you list me in the credits.
11 * - If you modify this source code, you must add a notice to each modified
12 * source file that it has been changed. If you're a nice person, you
13 * will clearly mark each change too. :)
14 * - If you wish to use this for commercial purposes, please contact me at
15 * pullmoll@t-online.de
16 * - The author of this copywritten work reserves the right to change the
17 * terms of its usage and license at any time, including retroactively
18 * - This entire notice must remain in the source code.
19 *
20 * Not sure about the timing of all the extra (undocumented) NOP instructions.
21 * Core may need to be split up into two 65c02 core. Not all versions supported
22 * the bit operation RMB/SMB/etc.
23 *
24 *****************************************************************************/
25
26 #undef OP
27 #define OP(nn) M6502_INLINE void m65c02_##nn(void)
28 #define RD_IMM_DISCARD RDOPARG()
29 #define RD_ZPG_DISCARD EA_ZPG; RDMEM(EAD)
30 #define RD_ZPX_DISCARD EA_ZPX; RDMEM(EAD)
31
32 /*****************************************************************************
33 *****************************************************************************
34 *
35 * Implementations for 65C02 opcodes
36 *
37 * There are a few slight differences between Rockwell and WDC 65C02 CPUs.
38 * The absolute indexed addressing mode RMW instructions take 6 cycles on
39 * WDC 65C02 CPU but 7 cycles on a regular 6502 and a Rockwell 65C02 CPU.
40 * TODO: Implement STP and WAI for wdc65c02.
41 *
42 *****************************************************************************
43 * op temp cycles rdmem opc wrmem ********************/
44 OP(00) { BRK_C02; } /* 7 BRK */
45 OP(20) { JSR; } /* 6 JSR */
46 OP(40) { RTI; } /* 6 RTI */
47 OP(60) { RTS; } /* 6 RTS */
48 OP(80) { int tmp; BRA_C02( 1 ); } /* 3-4 BRA REL */
OP(a0)49 OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */
OP(c0)50 OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */
OP(e0)51 OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */
52
53 OP(10) { int tmp; BRA_C02( ! ( P & F_N ) ); } /* 2-4 BPL REL */
54 OP(30) { int tmp; BRA_C02( ( P & F_N ) ); } /* 2-4 BMI REL */
55 OP(50) { int tmp; BRA_C02( ! ( P & F_V ) ); } /* 2-4 BVC REL */
56 OP(70) { int tmp; BRA_C02( ( P & F_V ) ); } /* 2-4 BVS REL */
57 OP(90) { int tmp; BRA_C02( ! ( P & F_C ) ); } /* 2-4 BCC REL */
OP(b0)58 OP(b0) { int tmp; BRA_C02( ( P & F_C ) ); } /* 2-4 BCS REL */
OP(d0)59 OP(d0) { int tmp; BRA_C02( ! ( P & F_Z ) ); } /* 2-4 BNE REL */
OP(f0)60 OP(f0) { int tmp; BRA_C02( ( P & F_Z ) ); } /* 2-4 BEQ REL */
61
62 OP(01) { int tmp; RD_IDX; ORA; } /* 6 ORA IDX */
63 OP(21) { int tmp; RD_IDX; AND; } /* 6 AND IDX */
64 OP(41) { int tmp; RD_IDX; EOR; } /* 6 EOR IDX */
65 OP(61) { int tmp; RD_IDX; ADC_C02; } /* 6/7 ADC IDX */
66 OP(81) { int tmp; STA; WR_IDX; } /* 6 STA IDX */
OP(a1)67 OP(a1) { int tmp; RD_IDX; LDA; } /* 6 LDA IDX */
OP(c1)68 OP(c1) { int tmp; RD_IDX; CMP; } /* 6 CMP IDX */
OP(e1)69 OP(e1) { int tmp; RD_IDX; SBC_C02; } /* 6/7 SBC IDX */
70
71 OP(11) { int tmp; RD_IDY_C02_P; ORA; } /* 5 ORA IDY page penalty */
72 OP(31) { int tmp; RD_IDY_C02_P; AND; } /* 5 AND IDY page penalty */
73 OP(51) { int tmp; RD_IDY_C02_P; EOR; } /* 5 EOR IDY page penalty */
74 OP(71) { int tmp; RD_IDY_C02_P; ADC_C02; } /* 5/6 ADC IDY page penalty */
75 OP(91) { int tmp; STA; WR_IDY_C02_NP; } /* 6 STA IDY */
OP(b1)76 OP(b1) { int tmp; RD_IDY_C02_P; LDA; } /* 5 LDA IDY page penalty */
OP(d1)77 OP(d1) { int tmp; RD_IDY_C02_P; CMP; } /* 5 CMP IDY page penalty */
OP(f1)78 OP(f1) { int tmp; RD_IDY_C02_P; SBC_C02; } /* 5/6 SBC IDY page penalty */
79
80 OP(02) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
81 OP(22) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
82 OP(42) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
83 OP(62) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
84 OP(82) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
OP(a2)85 OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */
OP(c2)86 OP(c2) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
OP(e2)87 OP(e2) { RD_IMM_DISCARD; NOP; } /* 2 NOP not sure for rockwell */
88
89 OP(12) { int tmp; RD_ZPI; ORA; } /* 5 ORA ZPI */
90 OP(32) { int tmp; RD_ZPI; AND; } /* 5 AND ZPI */
91 OP(52) { int tmp; RD_ZPI; EOR; } /* 5 EOR ZPI */
92 OP(72) { int tmp; RD_ZPI; ADC_C02; } /* 5/6 ADC ZPI */
93 OP(92) { int tmp; STA; WR_ZPI; } /* 5 STA ZPI */
OP(b2)94 OP(b2) { int tmp; RD_ZPI; LDA; } /* 5 LDA ZPI */
OP(d2)95 OP(d2) { int tmp; RD_ZPI; CMP; } /* 5 CMP ZPI */
OP(f2)96 OP(f2) { int tmp; RD_ZPI; SBC_C02; } /* 5/6 SBC ZPI */
97
98 OP(03) { NOP; } /* 1 NOP not sure for rockwell */
99 OP(23) { NOP; } /* 1 NOP not sure for rockwell */
100 OP(43) { NOP; } /* 1 NOP not sure for rockwell */
101 OP(63) { NOP; } /* 1 NOP not sure for rockwell */
102 OP(83) { NOP; } /* 1 NOP not sure for rockwell */
OP(a3)103 OP(a3) { NOP; } /* 1 NOP not sure for rockwell */
OP(c3)104 OP(c3) { NOP; } /* 1 NOP not sure for rockwell */
OP(e3)105 OP(e3) { NOP; } /* 1 NOP not sure for rockwell */
106
107 OP(13) { NOP; } /* 1 NOP not sure for rockwell */
108 OP(33) { NOP; } /* 1 NOP not sure for rockwell */
109 OP(53) { NOP; } /* 1 NOP not sure for rockwell */
110 OP(73) { NOP; } /* 1 NOP not sure for rockwell */
111 OP(93) { NOP; } /* 1 NOP not sure for rockwell */
OP(b3)112 OP(b3) { NOP; } /* 1 NOP not sure for rockwell */
OP(d3)113 OP(d3) { NOP; } /* 1 NOP not sure for rockwell */
OP(f3)114 OP(f3) { NOP; } /* 1 NOP not sure for rockwell */
115
116 OP(04) { int tmp; RD_ZPG; RD_EA; TSB; WB_EA; } /* 5 TSB ZPG */
117 OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */
118 OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP not sure for rockwell */
119 OP(64) { int tmp; STZ; WR_ZPG; } /* 3 STZ ZPG */
120 OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */
OP(a4)121 OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */
OP(c4)122 OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */
OP(e4)123 OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */
124
125 OP(14) { int tmp; RD_ZPG; RD_EA; TRB; WB_EA; } /* 5 TRB ZPG */
126 OP(34) { int tmp; RD_ZPX; BIT; } /* 4 BIT ZPX */
127 OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP not sure for rockwell */
128 OP(74) { int tmp; STZ; WR_ZPX; } /* 4 STZ ZPX */
129 OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */
OP(b4)130 OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */
OP(d4)131 OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP not sure for rockwell */
OP(f4)132 OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP not sure for rockwell */
133
134 OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */
135 OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */
136 OP(45) { int tmp; RD_ZPG; EOR; } /* 3 EOR ZPG */
137 OP(65) { int tmp; RD_ZPG; ADC_C02; } /* 3/4 ADC ZPG */
138 OP(85) { int tmp; STA; WR_ZPG; } /* 3 STA ZPG */
OP(a5)139 OP(a5) { int tmp; RD_ZPG; LDA; } /* 3 LDA ZPG */
OP(c5)140 OP(c5) { int tmp; RD_ZPG; CMP; } /* 3 CMP ZPG */
OP(e5)141 OP(e5) { int tmp; RD_ZPG; SBC_C02; } /* 3/4 SBC ZPG */
142
143 OP(15) { int tmp; RD_ZPX; ORA; } /* 4 ORA ZPX */
144 OP(35) { int tmp; RD_ZPX; AND; } /* 4 AND ZPX */
145 OP(55) { int tmp; RD_ZPX; EOR; } /* 4 EOR ZPX */
146 OP(75) { int tmp; RD_ZPX; ADC_C02; } /* 4/5 ADC ZPX */
147 OP(95) { int tmp; STA; WR_ZPX; } /* 4 STA ZPX */
OP(b5)148 OP(b5) { int tmp; RD_ZPX; LDA; } /* 4 LDA ZPX */
OP(d5)149 OP(d5) { int tmp; RD_ZPX; CMP; } /* 4 CMP ZPX */
OP(f5)150 OP(f5) { int tmp; RD_ZPX; SBC_C02; } /* 4/5 SBC ZPX */
151
152 OP(06) { int tmp; RD_ZPG, RD_EA; ASL; WB_EA; } /* 5 ASL ZPG */
153 OP(26) { int tmp; RD_ZPG; RD_EA; ROL; WB_EA; } /* 5 ROL ZPG */
154 OP(46) { int tmp; RD_ZPG; RD_EA; LSR; WB_EA; } /* 5 LSR ZPG */
155 OP(66) { int tmp; RD_ZPG; RD_EA; ROR; WB_EA; } /* 5 ROR ZPG */
156 OP(86) { int tmp; STX; WR_ZPG; } /* 3 STX ZPG */
OP(a6)157 OP(a6) { int tmp; RD_ZPG; LDX; } /* 3 LDX ZPG */
OP(c6)158 OP(c6) { int tmp; RD_ZPG; RD_EA; DEC; WB_EA; } /* 5 DEC ZPG */
OP(e6)159 OP(e6) { int tmp; RD_ZPG; RD_EA; INC; WB_EA; } /* 5 INC ZPG */
160
161 OP(16) { int tmp; RD_ZPX; RD_EA; ASL; WB_EA; } /* 6 ASL ZPX */
162 OP(36) { int tmp; RD_ZPX; RD_EA; ROL; WB_EA; } /* 6 ROL ZPX */
163 OP(56) { int tmp; RD_ZPX; RD_EA; LSR; WB_EA; } /* 6 LSR ZPX */
164 OP(76) { int tmp; RD_ZPX; RD_EA; ROR; WB_EA; } /* 6 ROR ZPX */
165 OP(96) { int tmp; STX; WR_ZPY; } /* 4 STX ZPY */
OP(b6)166 OP(b6) { int tmp; RD_ZPY; LDX; } /* 4 LDX ZPY */
OP(d6)167 OP(d6) { int tmp; RD_ZPX; RD_EA; DEC; WB_EA; } /* 6 DEC ZPX */
OP(f6)168 OP(f6) { int tmp; RD_ZPX; RD_EA; INC; WB_EA; } /* 6 INC ZPX */
169
170 OP(07) { int tmp; RD_ZPG; RD_EA; RMB(0);WB_EA; } /* 5 RMB0 ZPG */
171 OP(27) { int tmp; RD_ZPG; RD_EA; RMB(2);WB_EA; } /* 5 RMB2 ZPG */
172 OP(47) { int tmp; RD_ZPG; RD_EA; RMB(4);WB_EA; } /* 5 RMB4 ZPG */
173 OP(67) { int tmp; RD_ZPG; RD_EA; RMB(6);WB_EA; } /* 5 RMB6 ZPG */
174 OP(87) { int tmp; RD_ZPG; RD_EA; SMB(0);WB_EA; } /* 5 SMB0 ZPG */
OP(a7)175 OP(a7) { int tmp; RD_ZPG; RD_EA; SMB(2);WB_EA; } /* 5 SMB2 ZPG */
OP(c7)176 OP(c7) { int tmp; RD_ZPG; RD_EA; SMB(4);WB_EA; } /* 5 SMB4 ZPG */
OP(e7)177 OP(e7) { int tmp; RD_ZPG; RD_EA; SMB(6);WB_EA; } /* 5 SMB6 ZPG */
178
179 OP(17) { int tmp; RD_ZPG; RD_EA; RMB(1);WB_EA; } /* 5 RMB1 ZPG */
180 OP(37) { int tmp; RD_ZPG; RD_EA; RMB(3);WB_EA; } /* 5 RMB3 ZPG */
181 OP(57) { int tmp; RD_ZPG; RD_EA; RMB(5);WB_EA; } /* 5 RMB5 ZPG */
182 OP(77) { int tmp; RD_ZPG; RD_EA; RMB(7);WB_EA; } /* 5 RMB7 ZPG */
183 OP(97) { int tmp; RD_ZPG; RD_EA; SMB(1);WB_EA; } /* 5 SMB1 ZPG */
OP(b7)184 OP(b7) { int tmp; RD_ZPG; RD_EA; SMB(3);WB_EA; } /* 5 SMB3 ZPG */
OP(d7)185 OP(d7) { int tmp; RD_ZPG; RD_EA; SMB(5);WB_EA; } /* 5 SMB5 ZPG */
OP(f7)186 OP(f7) { int tmp; RD_ZPG; RD_EA; SMB(7);WB_EA; } /* 5 SMB7 ZPG */
187
188 OP(08) { RD_DUM; PHP; } /* 3 PHP */
189 OP(28) { RD_DUM; PLP; } /* 4 PLP */
190 OP(48) { RD_DUM; PHA; } /* 3 PHA */
191 OP(68) { RD_DUM; PLA; } /* 4 PLA */
192 OP(88) { RD_DUM; DEY; } /* 2 DEY */
OP(a8)193 OP(a8) { RD_DUM; TAY; } /* 2 TAY */
OP(c8)194 OP(c8) { RD_DUM; INY; } /* 2 INY */
OP(e8)195 OP(e8) { RD_DUM; INX; } /* 2 INX */
196
197 OP(18) { RD_DUM; CLC; } /* 2 CLC */
198 OP(38) { RD_DUM; SEC; } /* 2 SEC */
199 OP(58) { RD_DUM; CLI; } /* 2 CLI */
200 OP(78) { RD_DUM; SEI; } /* 2 SEI */
201 OP(98) { RD_DUM; TYA; } /* 2 TYA */
OP(b8)202 OP(b8) { RD_DUM; CLV; } /* 2 CLV */
OP(d8)203 OP(d8) { RD_DUM; CLD; } /* 2 CLD */
OP(f8)204 OP(f8) { RD_DUM; SED; } /* 2 SED */
205
206 OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */
207 OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */
208 OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */
209 OP(69) { int tmp; RD_IMM; ADC_C02; } /* 2/3 ADC IMM */
210 OP(89) { int tmp; RD_IMM; BIT_IMM_C02; } /* 2 BIT IMM */
OP(a9)211 OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */
OP(c9)212 OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */
OP(e9)213 OP(e9) { int tmp; RD_IMM; SBC_C02; } /* 2/3 SBC IMM */
214
215 OP(19) { int tmp; RD_ABY_C02_P; ORA; } /* 4 ORA ABY page penalty */
216 OP(39) { int tmp; RD_ABY_C02_P; AND; } /* 4 AND ABY page penalty */
217 OP(59) { int tmp; RD_ABY_C02_P; EOR; } /* 4 EOR ABY page penalty */
218 OP(79) { int tmp; RD_ABY_C02_P; ADC_C02; } /* 4/5 ADC ABY page penalty */
219 OP(99) { int tmp; STA; WR_ABY_C02_NP; } /* 5 STA ABY */
OP(b9)220 OP(b9) { int tmp; RD_ABY_C02_P; LDA; } /* 4 LDA ABY page penalty */
OP(d9)221 OP(d9) { int tmp; RD_ABY_C02_P; CMP; } /* 4 CMP ABY page penalty */
OP(f9)222 OP(f9) { int tmp; RD_ABY_C02_P; SBC_C02; } /* 4/5 SBC ABY page penalty */
223
224 OP(0a) { int tmp; RD_DUM; RD_ACC; ASL; WB_ACC; } /* 2 ASL A */
225 OP(2a) { int tmp; RD_DUM; RD_ACC; ROL; WB_ACC; } /* 2 ROL A */
226 OP(4a) { int tmp; RD_DUM; RD_ACC; LSR; WB_ACC; } /* 2 LSR A */
227 OP(6a) { int tmp; RD_DUM; RD_ACC; ROR; WB_ACC; } /* 2 ROR A */
228 OP(8a) { RD_DUM; TXA; } /* 2 TXA */
OP(aa)229 OP(aa) { RD_DUM; TAX; } /* 2 TAX */
OP(ca)230 OP(ca) { RD_DUM; DEX; } /* 2 DEX */
OP(ea)231 OP(ea) { RD_DUM; NOP; } /* 2 NOP */
232
233 OP(1a) { RD_DUM;INA; } /* 2 INA */
234 OP(3a) { RD_DUM;DEA; } /* 2 DEA */
235 OP(5a) { RD_DUM;PHY; } /* 3 PHY */
236 OP(7a) { RD_DUM;PLY; } /* 4 PLY */
237 OP(9a) { RD_DUM; TXS; } /* 2 TXS */
OP(ba)238 OP(ba) { RD_DUM; TSX; } /* 2 TSX */
OP(da)239 OP(da) { RD_DUM;PHX; } /* 3 PHX */
OP(fa)240 OP(fa) { RD_DUM;PLX; } /* 4 PLX */
241
242 OP(0b) { NOP; } /* 1 NOP not sure for rockwell */
243 OP(2b) { NOP; } /* 1 NOP not sure for rockwell */
244 OP(4b) { NOP; } /* 1 NOP not sure for rockwell */
245 OP(6b) { NOP; } /* 1 NOP not sure for rockwell */
246 OP(8b) { NOP; } /* 1 NOP not sure for rockwell */
OP(ab)247 OP(ab) { NOP; } /* 1 NOP not sure for rockwell */
OP(cb)248 OP(cb) { NOP; } /* 1 NOP not sure for rockwell */
OP(eb)249 OP(eb) { NOP; } /* 1 NOP not sure for rockwell */
250
251 OP(1b) { NOP; } /* 1 NOP not sure for rockwell */
252 OP(3b) { NOP; } /* 1 NOP not sure for rockwell */
253 OP(5b) { NOP; } /* 1 NOP not sure for rockwell */
254 OP(7b) { NOP; } /* 1 NOP not sure for rockwell */
255 OP(9b) { NOP; } /* 1 NOP not sure for rockwell */
OP(bb)256 OP(bb) { NOP; } /* 1 NOP not sure for rockwell */
OP(db)257 OP(db) { NOP; } /* 1 NOP not sure for rockwell */
OP(fb)258 OP(fb) { NOP; } /* 1 NOP not sure for rockwell */
259
260 OP(0c) { int tmp; RD_ABS; RD_EA; TSB; WB_EA; } /* 6 TSB ABS */
261 OP(2c) { int tmp; RD_ABS; BIT; } /* 4 BIT ABS */
262 OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */
263 OP(6c) { int tmp; EA_IND_C02; JMP; } /* 6 JMP IND */
264 OP(8c) { int tmp; STY; WR_ABS; } /* 4 STY ABS */
OP(ac)265 OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */
OP(cc)266 OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */
OP(ec)267 OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */
268
269 OP(1c) { int tmp; RD_ABS; RD_EA; TRB; WB_EA; } /* 6 TRB ABS */
270 OP(3c) { int tmp; RD_ABX_C02_P; BIT; } /* 4 BIT ABX page penalty */
271 OP(5c) { RD_ABX_C02_NP_DISCARD; RD_DUM; RD_DUM; RD_DUM; RD_DUM; } /* 8 NOP ABX not sure for rockwell. Page penalty not sure */
272 OP(7c) { int tmp; EA_IAX; JMP; } /* 6 JMP IAX page penalty */
273 OP(9c) { int tmp; STZ; WR_ABS; } /* 4 STZ ABS */
OP(bc)274 OP(bc) { int tmp; RD_ABX_C02_P; LDY; } /* 4 LDY ABX page penalty */
OP(dc)275 OP(dc) { RD_ABX_C02_NP_DISCARD; NOP; } /* 4 NOP ABX not sure for rockwell. Page penalty not sure */
OP(fc)276 OP(fc) { RD_ABX_C02_NP_DISCARD; NOP; } /* 4 NOP ABX not sure for rockwell. Page penalty not sure */
277
278 OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */
279 OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */
280 OP(4d) { int tmp; RD_ABS; EOR; } /* 4 EOR ABS */
281 OP(6d) { int tmp; RD_ABS; ADC_C02; } /* 4/5 ADC ABS */
282 OP(8d) { int tmp; STA; WR_ABS; } /* 4 STA ABS */
OP(ad)283 OP(ad) { int tmp; RD_ABS; LDA; } /* 4 LDA ABS */
OP(cd)284 OP(cd) { int tmp; RD_ABS; CMP; } /* 4 CMP ABS */
OP(ed)285 OP(ed) { int tmp; RD_ABS; SBC_C02; } /* 4/5 SBC ABS */
286
287 OP(1d) { int tmp; RD_ABX_C02_P; ORA; } /* 4 ORA ABX page penalty */
288 OP(3d) { int tmp; RD_ABX_C02_P; AND; } /* 4 AND ABX page penalty */
289 OP(5d) { int tmp; RD_ABX_C02_P; EOR; } /* 4 EOR ABX page penalty */
290 OP(7d) { int tmp; RD_ABX_C02_P; ADC_C02; } /* 4/5 ADC ABX page penalty */
291 OP(9d) { int tmp; STA; WR_ABX_C02_NP; } /* 5 STA ABX */
OP(bd)292 OP(bd) { int tmp; RD_ABX_C02_P; LDA; } /* 4 LDA ABX page penalty */
OP(dd)293 OP(dd) { int tmp; RD_ABX_C02_P; CMP; } /* 4 CMP ABX page penalty */
OP(fd)294 OP(fd) { int tmp; RD_ABX_C02_P; SBC_C02; } /* 4/5 SBC ABX page penalty */
295
296 OP(0e) { int tmp; RD_ABS; RD_EA; ASL; WB_EA; } /* 6 ASL ABS */
297 OP(2e) { int tmp; RD_ABS; RD_EA; ROL; WB_EA; } /* 6 ROL ABS */
298 OP(4e) { int tmp; RD_ABS; RD_EA; LSR; WB_EA; } /* 6 LSR ABS */
299 OP(6e) { int tmp; RD_ABS; RD_EA; ROR; WB_EA; } /* 6 ROR ABS */
300 OP(8e) { int tmp; STX; WR_ABS; } /* 4 STX ABS */
OP(ae)301 OP(ae) { int tmp; RD_ABS; LDX; } /* 4 LDX ABS */
OP(ce)302 OP(ce) { int tmp; RD_ABS; RD_EA; DEC; WB_EA; } /* 6 DEC ABS */
OP(ee)303 OP(ee) { int tmp; RD_ABS; RD_EA; INC; WB_EA; } /* 6 INC ABS */
304
305 OP(1e) { int tmp; RD_ABX_C02_NP; RD_EA; ASL; WB_EA; } /* 7 ASL ABX */
306 OP(3e) { int tmp; RD_ABX_C02_NP; RD_EA; ROL; WB_EA; } /* 7 ROL ABX */
307 OP(5e) { int tmp; RD_ABX_C02_NP; RD_EA; LSR; WB_EA; } /* 7 LSR ABX */
308 OP(7e) { int tmp; RD_ABX_C02_NP; RD_EA; ROR; WB_EA; } /* 7 ROR ABX */
309 OP(9e) { int tmp; STZ; WR_ABX_C02_NP; } /* 5 STZ ABX */
OP(be)310 OP(be) { int tmp; RD_ABY_C02_P; LDX; } /* 4 LDX ABY page penalty */
OP(de)311 OP(de) { int tmp; RD_ABX_C02_NP; RD_EA; DEC; WB_EA; } /* 7 DEC ABX */
OP(fe)312 OP(fe) { int tmp; RD_ABX_C02_NP; RD_EA; INC; WB_EA; } /* 7 INC ABX */
313
314 OP(0f) { int tmp; RD_ZPG; BBR(0); } /* 5-7 BBR0 ZPG */
315 OP(2f) { int tmp; RD_ZPG; BBR(2); } /* 5-7 BBR2 ZPG */
316 OP(4f) { int tmp; RD_ZPG; BBR(4); } /* 5-7 BBR4 ZPG */
317 OP(6f) { int tmp; RD_ZPG; BBR(6); } /* 5-7 BBR6 ZPG */
318 OP(8f) { int tmp; RD_ZPG; BBS(0); } /* 5-7 BBS0 ZPG */
OP(af)319 OP(af) { int tmp; RD_ZPG; BBS(2); } /* 5-7 BBS2 ZPG */
OP(cf)320 OP(cf) { int tmp; RD_ZPG; BBS(4); } /* 5-7 BBS4 ZPG */
OP(ef)321 OP(ef) { int tmp; RD_ZPG; BBS(6); } /* 5-7 BBS6 ZPG */
322
323 OP(1f) { int tmp; RD_ZPG; BBR(1); } /* 5-7 BBR1 ZPG */
324 OP(3f) { int tmp; RD_ZPG; BBR(3); } /* 5-7 BBR3 ZPG */
325 OP(5f) { int tmp; RD_ZPG; BBR(5); } /* 5-7 BBR5 ZPG */
326 OP(7f) { int tmp; RD_ZPG; BBR(7); } /* 5-7 BBR7 ZPG */
327 OP(9f) { int tmp; RD_ZPG; BBS(1); } /* 5-7 BBS1 ZPG */
OP(bf)328 OP(bf) { int tmp; RD_ZPG; BBS(3); } /* 5-7 BBS3 ZPG */
OP(df)329 OP(df) { int tmp; RD_ZPG; BBS(5); } /* 5-7 BBS5 ZPG */
OP(ff)330 OP(ff) { int tmp; RD_ZPG; BBS(7); } /* 5-7 BBS7 ZPG */
331
332 static void (*const insn65c02[0x100])(void) = {
333 m65c02_00,m65c02_01,m65c02_02,m65c02_03,m65c02_04,m65c02_05,m65c02_06,m65c02_07,
334 m65c02_08,m65c02_09,m65c02_0a,m65c02_0b,m65c02_0c,m65c02_0d,m65c02_0e,m65c02_0f,
335 m65c02_10,m65c02_11,m65c02_12,m65c02_13,m65c02_14,m65c02_15,m65c02_16,m65c02_17,
336 m65c02_18,m65c02_19,m65c02_1a,m65c02_1b,m65c02_1c,m65c02_1d,m65c02_1e,m65c02_1f,
337 m65c02_20,m65c02_21,m65c02_22,m65c02_23,m65c02_24,m65c02_25,m65c02_26,m65c02_27,
338 m65c02_28,m65c02_29,m65c02_2a,m65c02_2b,m65c02_2c,m65c02_2d,m65c02_2e,m65c02_2f,
339 m65c02_30,m65c02_31,m65c02_32,m65c02_33,m65c02_34,m65c02_35,m65c02_36,m65c02_37,
340 m65c02_38,m65c02_39,m65c02_3a,m65c02_3b,m65c02_3c,m65c02_3d,m65c02_3e,m65c02_3f,
341 m65c02_40,m65c02_41,m65c02_42,m65c02_43,m65c02_44,m65c02_45,m65c02_46,m65c02_47,
342 m65c02_48,m65c02_49,m65c02_4a,m65c02_4b,m65c02_4c,m65c02_4d,m65c02_4e,m65c02_4f,
343 m65c02_50,m65c02_51,m65c02_52,m65c02_53,m65c02_54,m65c02_55,m65c02_56,m65c02_57,
344 m65c02_58,m65c02_59,m65c02_5a,m65c02_5b,m65c02_5c,m65c02_5d,m65c02_5e,m65c02_5f,
345 m65c02_60,m65c02_61,m65c02_62,m65c02_63,m65c02_64,m65c02_65,m65c02_66,m65c02_67,
346 m65c02_68,m65c02_69,m65c02_6a,m65c02_6b,m65c02_6c,m65c02_6d,m65c02_6e,m65c02_6f,
347 m65c02_70,m65c02_71,m65c02_72,m65c02_73,m65c02_74,m65c02_75,m65c02_76,m65c02_77,
348 m65c02_78,m65c02_79,m65c02_7a,m65c02_7b,m65c02_7c,m65c02_7d,m65c02_7e,m65c02_7f,
349 m65c02_80,m65c02_81,m65c02_82,m65c02_83,m65c02_84,m65c02_85,m65c02_86,m65c02_87,
350 m65c02_88,m65c02_89,m65c02_8a,m65c02_8b,m65c02_8c,m65c02_8d,m65c02_8e,m65c02_8f,
351 m65c02_90,m65c02_91,m65c02_92,m65c02_93,m65c02_94,m65c02_95,m65c02_96,m65c02_97,
352 m65c02_98,m65c02_99,m65c02_9a,m65c02_9b,m65c02_9c,m65c02_9d,m65c02_9e,m65c02_9f,
353 m65c02_a0,m65c02_a1,m65c02_a2,m65c02_a3,m65c02_a4,m65c02_a5,m65c02_a6,m65c02_a7,
354 m65c02_a8,m65c02_a9,m65c02_aa,m65c02_ab,m65c02_ac,m65c02_ad,m65c02_ae,m65c02_af,
355 m65c02_b0,m65c02_b1,m65c02_b2,m65c02_b3,m65c02_b4,m65c02_b5,m65c02_b6,m65c02_b7,
356 m65c02_b8,m65c02_b9,m65c02_ba,m65c02_bb,m65c02_bc,m65c02_bd,m65c02_be,m65c02_bf,
357 m65c02_c0,m65c02_c1,m65c02_c2,m65c02_c3,m65c02_c4,m65c02_c5,m65c02_c6,m65c02_c7,
358 m65c02_c8,m65c02_c9,m65c02_ca,m65c02_cb,m65c02_cc,m65c02_cd,m65c02_ce,m65c02_cf,
359 m65c02_d0,m65c02_d1,m65c02_d2,m65c02_d3,m65c02_d4,m65c02_d5,m65c02_d6,m65c02_d7,
360 m65c02_d8,m65c02_d9,m65c02_da,m65c02_db,m65c02_dc,m65c02_dd,m65c02_de,m65c02_df,
361 m65c02_e0,m65c02_e1,m65c02_e2,m65c02_e3,m65c02_e4,m65c02_e5,m65c02_e6,m65c02_e7,
362 m65c02_e8,m65c02_e9,m65c02_ea,m65c02_eb,m65c02_ec,m65c02_ed,m65c02_ee,m65c02_ef,
363 m65c02_f0,m65c02_f1,m65c02_f2,m65c02_f3,m65c02_f4,m65c02_f5,m65c02_f6,m65c02_f7,
364 m65c02_f8,m65c02_f9,m65c02_fa,m65c02_fb,m65c02_fc,m65c02_fd,m65c02_fe,m65c02_ff
365 };
366
367 #ifdef WDC65C02
OP(cb_wdc)368 OP(cb_wdc) { RD_DUM; RD_DUM; } /* 3 WAI, TODO: Implement HALT mode */
OP(db_wdc)369 OP(db_wdc) { RD_DUM; RD_DUM; } /* 3 STP, TODO: Implement STP mode */
370 OP(1e_wdc) { int tmp; RD_ABX_P; RD_EA; ASL; WB_EA; } /* 6 ASL ABX page penalty */
371 OP(3e_wdc) { int tmp; RD_ABX_P; RD_EA; ROL; WB_EA; } /* 6 ROL ABX page penalty */
372 OP(5e_wdc) { int tmp; RD_ABX_P; RD_EA; LSR; WB_EA; } /* 6 LSR ABX page penalty */
373 OP(7e_wdc) { int tmp; RD_ABX_P; RD_EA; ROR; WB_EA; } /* 6 ROR ABX page penalty */
OP(de_wdc)374 OP(de_wdc) { int tmp; RD_ABX_P; RD_EA; DEC; WB_EA; } /* 6 DEC ABX page penalty */
OP(fe_wdc)375 OP(fe_wdc) { int tmp; RD_ABX_P; RD_EA; INC; WB_EA; } /* 6 INC ABX page penalty */
376
377 static void (*const insnwdc65c02[0x100])(m6502_Regs *cpustate) = {
378 m65c02_00,m65c02_01,m65c02_02,m65c02_03,m65c02_04,m65c02_05,m65c02_06,m65c02_07,
379 m65c02_08,m65c02_09,m65c02_0a,m65c02_0b,m65c02_0c,m65c02_0d,m65c02_0e,m65c02_0f,
380 m65c02_10,m65c02_11,m65c02_12,m65c02_13,m65c02_14,m65c02_15,m65c02_16,m65c02_17,
381 m65c02_18,m65c02_19,m65c02_1a,m65c02_1b,m65c02_1c,m65c02_1d,m65c02_1e_wdc,m65c02_1f,
382 m65c02_20,m65c02_21,m65c02_22,m65c02_23,m65c02_24,m65c02_25,m65c02_26,m65c02_27,
383 m65c02_28,m65c02_29,m65c02_2a,m65c02_2b,m65c02_2c,m65c02_2d,m65c02_2e,m65c02_2f,
384 m65c02_30,m65c02_31,m65c02_32,m65c02_33,m65c02_34,m65c02_35,m65c02_36,m65c02_37,
385 m65c02_38,m65c02_39,m65c02_3a,m65c02_3b,m65c02_3c,m65c02_3d,m65c02_3e_wdc,m65c02_3f,
386 m65c02_40,m65c02_41,m65c02_42,m65c02_43,m65c02_44,m65c02_45,m65c02_46,m65c02_47,
387 m65c02_48,m65c02_49,m65c02_4a,m65c02_4b,m65c02_4c,m65c02_4d,m65c02_4e,m65c02_4f,
388 m65c02_50,m65c02_51,m65c02_52,m65c02_53,m65c02_54,m65c02_55,m65c02_56,m65c02_57,
389 m65c02_58,m65c02_59,m65c02_5a,m65c02_5b,m65c02_5c,m65c02_5d,m65c02_5e_wdc,m65c02_5f,
390 m65c02_60,m65c02_61,m65c02_62,m65c02_63,m65c02_64,m65c02_65,m65c02_66,m65c02_67,
391 m65c02_68,m65c02_69,m65c02_6a,m65c02_6b,m65c02_6c,m65c02_6d,m65c02_6e,m65c02_6f,
392 m65c02_70,m65c02_71,m65c02_72,m65c02_73,m65c02_74,m65c02_75,m65c02_76,m65c02_77,
393 m65c02_78,m65c02_79,m65c02_7a,m65c02_7b,m65c02_7c,m65c02_7d,m65c02_7e_wdc,m65c02_7f,
394 m65c02_80,m65c02_81,m65c02_82,m65c02_83,m65c02_84,m65c02_85,m65c02_86,m65c02_87,
395 m65c02_88,m65c02_89,m65c02_8a,m65c02_8b,m65c02_8c,m65c02_8d,m65c02_8e,m65c02_8f,
396 m65c02_90,m65c02_91,m65c02_92,m65c02_93,m65c02_94,m65c02_95,m65c02_96,m65c02_97,
397 m65c02_98,m65c02_99,m65c02_9a,m65c02_9b,m65c02_9c,m65c02_9d,m65c02_9e,m65c02_9f,
398 m65c02_a0,m65c02_a1,m65c02_a2,m65c02_a3,m65c02_a4,m65c02_a5,m65c02_a6,m65c02_a7,
399 m65c02_a8,m65c02_a9,m65c02_aa,m65c02_ab,m65c02_ac,m65c02_ad,m65c02_ae,m65c02_af,
400 m65c02_b0,m65c02_b1,m65c02_b2,m65c02_b3,m65c02_b4,m65c02_b5,m65c02_b6,m65c02_b7,
401 m65c02_b8,m65c02_b9,m65c02_ba,m65c02_bb,m65c02_bc,m65c02_bd,m65c02_be,m65c02_bf,
402 m65c02_c0,m65c02_c1,m65c02_c2,m65c02_c3,m65c02_c4,m65c02_c5,m65c02_c6,m65c02_c7,
403 m65c02_c8,m65c02_c9,m65c02_ca,m65c02_cb_wdc,m65c02_cc,m65c02_cd,m65c02_ce,m65c02_cf,
404 m65c02_d0,m65c02_d1,m65c02_d2,m65c02_d3,m65c02_d4,m65c02_d5,m65c02_d6,m65c02_d7,
405 m65c02_d8,m65c02_d9,m65c02_da,m65c02_db_wdc,m65c02_dc,m65c02_dd,m65c02_de_wdc,m65c02_df,
406 m65c02_e0,m65c02_e1,m65c02_e2,m65c02_e3,m65c02_e4,m65c02_e5,m65c02_e6,m65c02_e7,
407 m65c02_e8,m65c02_e9,m65c02_ea,m65c02_eb,m65c02_ec,m65c02_ed,m65c02_ee,m65c02_ef,
408 m65c02_f0,m65c02_f1,m65c02_f2,m65c02_f3,m65c02_f4,m65c02_f5,m65c02_f6,m65c02_f7,
409 m65c02_f8,m65c02_f9,m65c02_fa,m65c02_fb,m65c02_fc,m65c02_fd,m65c02_fe_wdc,m65c02_ff
410 };
411 #endif
412
413
414