1 #ifdef HAVE_YM3438_CORE
2 /*
3 * Copyright (C) 2017 Alexey Khokholov (Nuke.YKT)
4 *
5 * Redistribution and use of this code or any derivative works are permitted
6 * provided that the following conditions are met:
7 *
8 * - Redistributions may not be sold, nor may they be used in a commercial
9 * product or activity.
10 *
11 * - Redistributions that are modified from the original source must include the
12 * complete source code, including the source code for all components used by a
13 * binary built from the modified sources. However, as a special exception, the
14 * source code distributed need not include anything that is normally distributed
15 * (in either source or binary form) with the major components (compiler, kernel,
16 * and so on) of the operating system on which the executable runs, unless that
17 * component itself accompanies the executable.
18 *
19 * - Redistributions must reproduce the above copyright notice, this list of
20 * conditions and the following disclaimer in the documentation and/or other
21 * materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 *
35 *
36 * Nuked OPN2(Yamaha YM3438) emulator.
37 * Thanks:
38 * Silicon Pr0n:
39 * Yamaha YM3438 decap and die shot(digshadow).
40 * OPLx decapsulated(Matthew Gambrell, Olli Niemitalo):
41 * OPL2 ROMs.
42 *
43 * version: 1.0.8
44 */
45
46 #include <string.h>
47 #include "ym3438.h"
48
49 enum {
50 eg_num_attack = 0,
51 eg_num_decay = 1,
52 eg_num_sustain = 2,
53 eg_num_release = 3
54 };
55
56 /* logsin table */
57 static const Bit16u logsinrom[256] = {
58 0x859, 0x6c3, 0x607, 0x58b, 0x52e, 0x4e4, 0x4a6, 0x471,
59 0x443, 0x41a, 0x3f5, 0x3d3, 0x3b5, 0x398, 0x37e, 0x365,
60 0x34e, 0x339, 0x324, 0x311, 0x2ff, 0x2ed, 0x2dc, 0x2cd,
61 0x2bd, 0x2af, 0x2a0, 0x293, 0x286, 0x279, 0x26d, 0x261,
62 0x256, 0x24b, 0x240, 0x236, 0x22c, 0x222, 0x218, 0x20f,
63 0x206, 0x1fd, 0x1f5, 0x1ec, 0x1e4, 0x1dc, 0x1d4, 0x1cd,
64 0x1c5, 0x1be, 0x1b7, 0x1b0, 0x1a9, 0x1a2, 0x19b, 0x195,
65 0x18f, 0x188, 0x182, 0x17c, 0x177, 0x171, 0x16b, 0x166,
66 0x160, 0x15b, 0x155, 0x150, 0x14b, 0x146, 0x141, 0x13c,
67 0x137, 0x133, 0x12e, 0x129, 0x125, 0x121, 0x11c, 0x118,
68 0x114, 0x10f, 0x10b, 0x107, 0x103, 0x0ff, 0x0fb, 0x0f8,
69 0x0f4, 0x0f0, 0x0ec, 0x0e9, 0x0e5, 0x0e2, 0x0de, 0x0db,
70 0x0d7, 0x0d4, 0x0d1, 0x0cd, 0x0ca, 0x0c7, 0x0c4, 0x0c1,
71 0x0be, 0x0bb, 0x0b8, 0x0b5, 0x0b2, 0x0af, 0x0ac, 0x0a9,
72 0x0a7, 0x0a4, 0x0a1, 0x09f, 0x09c, 0x099, 0x097, 0x094,
73 0x092, 0x08f, 0x08d, 0x08a, 0x088, 0x086, 0x083, 0x081,
74 0x07f, 0x07d, 0x07a, 0x078, 0x076, 0x074, 0x072, 0x070,
75 0x06e, 0x06c, 0x06a, 0x068, 0x066, 0x064, 0x062, 0x060,
76 0x05e, 0x05c, 0x05b, 0x059, 0x057, 0x055, 0x053, 0x052,
77 0x050, 0x04e, 0x04d, 0x04b, 0x04a, 0x048, 0x046, 0x045,
78 0x043, 0x042, 0x040, 0x03f, 0x03e, 0x03c, 0x03b, 0x039,
79 0x038, 0x037, 0x035, 0x034, 0x033, 0x031, 0x030, 0x02f,
80 0x02e, 0x02d, 0x02b, 0x02a, 0x029, 0x028, 0x027, 0x026,
81 0x025, 0x024, 0x023, 0x022, 0x021, 0x020, 0x01f, 0x01e,
82 0x01d, 0x01c, 0x01b, 0x01a, 0x019, 0x018, 0x017, 0x017,
83 0x016, 0x015, 0x014, 0x014, 0x013, 0x012, 0x011, 0x011,
84 0x010, 0x00f, 0x00f, 0x00e, 0x00d, 0x00d, 0x00c, 0x00c,
85 0x00b, 0x00a, 0x00a, 0x009, 0x009, 0x008, 0x008, 0x007,
86 0x007, 0x007, 0x006, 0x006, 0x005, 0x005, 0x005, 0x004,
87 0x004, 0x004, 0x003, 0x003, 0x003, 0x002, 0x002, 0x002,
88 0x002, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001,
89 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000
90 };
91
92 /* exp table */
93 static const Bit16u exprom[256] = {
94 0x000, 0x003, 0x006, 0x008, 0x00b, 0x00e, 0x011, 0x014,
95 0x016, 0x019, 0x01c, 0x01f, 0x022, 0x025, 0x028, 0x02a,
96 0x02d, 0x030, 0x033, 0x036, 0x039, 0x03c, 0x03f, 0x042,
97 0x045, 0x048, 0x04b, 0x04e, 0x051, 0x054, 0x057, 0x05a,
98 0x05d, 0x060, 0x063, 0x066, 0x069, 0x06c, 0x06f, 0x072,
99 0x075, 0x078, 0x07b, 0x07e, 0x082, 0x085, 0x088, 0x08b,
100 0x08e, 0x091, 0x094, 0x098, 0x09b, 0x09e, 0x0a1, 0x0a4,
101 0x0a8, 0x0ab, 0x0ae, 0x0b1, 0x0b5, 0x0b8, 0x0bb, 0x0be,
102 0x0c2, 0x0c5, 0x0c8, 0x0cc, 0x0cf, 0x0d2, 0x0d6, 0x0d9,
103 0x0dc, 0x0e0, 0x0e3, 0x0e7, 0x0ea, 0x0ed, 0x0f1, 0x0f4,
104 0x0f8, 0x0fb, 0x0ff, 0x102, 0x106, 0x109, 0x10c, 0x110,
105 0x114, 0x117, 0x11b, 0x11e, 0x122, 0x125, 0x129, 0x12c,
106 0x130, 0x134, 0x137, 0x13b, 0x13e, 0x142, 0x146, 0x149,
107 0x14d, 0x151, 0x154, 0x158, 0x15c, 0x160, 0x163, 0x167,
108 0x16b, 0x16f, 0x172, 0x176, 0x17a, 0x17e, 0x181, 0x185,
109 0x189, 0x18d, 0x191, 0x195, 0x199, 0x19c, 0x1a0, 0x1a4,
110 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc, 0x1c0, 0x1c4,
111 0x1c8, 0x1cc, 0x1d0, 0x1d4, 0x1d8, 0x1dc, 0x1e0, 0x1e4,
112 0x1e8, 0x1ec, 0x1f0, 0x1f5, 0x1f9, 0x1fd, 0x201, 0x205,
113 0x209, 0x20e, 0x212, 0x216, 0x21a, 0x21e, 0x223, 0x227,
114 0x22b, 0x230, 0x234, 0x238, 0x23c, 0x241, 0x245, 0x249,
115 0x24e, 0x252, 0x257, 0x25b, 0x25f, 0x264, 0x268, 0x26d,
116 0x271, 0x276, 0x27a, 0x27f, 0x283, 0x288, 0x28c, 0x291,
117 0x295, 0x29a, 0x29e, 0x2a3, 0x2a8, 0x2ac, 0x2b1, 0x2b5,
118 0x2ba, 0x2bf, 0x2c4, 0x2c8, 0x2cd, 0x2d2, 0x2d6, 0x2db,
119 0x2e0, 0x2e5, 0x2e9, 0x2ee, 0x2f3, 0x2f8, 0x2fd, 0x302,
120 0x306, 0x30b, 0x310, 0x315, 0x31a, 0x31f, 0x324, 0x329,
121 0x32e, 0x333, 0x338, 0x33d, 0x342, 0x347, 0x34c, 0x351,
122 0x356, 0x35b, 0x360, 0x365, 0x36a, 0x370, 0x375, 0x37a,
123 0x37f, 0x384, 0x38a, 0x38f, 0x394, 0x399, 0x39f, 0x3a4,
124 0x3a9, 0x3ae, 0x3b4, 0x3b9, 0x3bf, 0x3c4, 0x3c9, 0x3cf,
125 0x3d4, 0x3da, 0x3df, 0x3e4, 0x3ea, 0x3ef, 0x3f5, 0x3fa
126 };
127
128 /* Note table */
129 static const Bit32u fn_note[16] = {
130 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 3, 3, 3, 3, 3, 3
131 };
132
133 /* Envelope generator */
134 static const Bit32u eg_stephi[4][4] = {
135 { 0, 0, 0, 0 },
136 { 1, 0, 0, 0 },
137 { 1, 0, 1, 0 },
138 { 1, 1, 1, 0 }
139 };
140
141 static const Bit8u eg_am_shift[4] = {
142 7, 3, 1, 0
143 };
144
145 /* Phase generator */
146 static const Bit32u pg_detune[8] = { 16, 17, 19, 20, 22, 24, 27, 29 };
147
148 static const Bit32u pg_lfo_sh1[8][8] = {
149 { 7, 7, 7, 7, 7, 7, 7, 7 },
150 { 7, 7, 7, 7, 7, 7, 7, 7 },
151 { 7, 7, 7, 7, 7, 7, 1, 1 },
152 { 7, 7, 7, 7, 1, 1, 1, 1 },
153 { 7, 7, 7, 1, 1, 1, 1, 0 },
154 { 7, 7, 1, 1, 0, 0, 0, 0 },
155 { 7, 7, 1, 1, 0, 0, 0, 0 },
156 { 7, 7, 1, 1, 0, 0, 0, 0 }
157 };
158
159 static const Bit32u pg_lfo_sh2[8][8] = {
160 { 7, 7, 7, 7, 7, 7, 7, 7 },
161 { 7, 7, 7, 7, 2, 2, 2, 2 },
162 { 7, 7, 7, 2, 2, 2, 7, 7 },
163 { 7, 7, 2, 2, 7, 7, 2, 2 },
164 { 7, 7, 2, 7, 7, 7, 2, 7 },
165 { 7, 7, 7, 2, 7, 7, 2, 1 },
166 { 7, 7, 7, 2, 7, 7, 2, 1 },
167 { 7, 7, 7, 2, 7, 7, 2, 1 }
168 };
169
170 /* Address decoder */
171 static const Bit32u op_offset[12] = {
172 0x000, /* Ch1 OP1/OP2 */
173 0x001, /* Ch2 OP1/OP2 */
174 0x002, /* Ch3 OP1/OP2 */
175 0x100, /* Ch4 OP1/OP2 */
176 0x101, /* Ch5 OP1/OP2 */
177 0x102, /* Ch6 OP1/OP2 */
178 0x004, /* Ch1 OP3/OP4 */
179 0x005, /* Ch2 OP3/OP4 */
180 0x006, /* Ch3 OP3/OP4 */
181 0x104, /* Ch4 OP3/OP4 */
182 0x105, /* Ch5 OP3/OP4 */
183 0x106 /* Ch6 OP3/OP4 */
184 };
185
186 static const Bit32u ch_offset[6] = {
187 0x000, /* Ch1 */
188 0x001, /* Ch2 */
189 0x002, /* Ch3 */
190 0x100, /* Ch4 */
191 0x101, /* Ch5 */
192 0x102 /* Ch6 */
193 };
194
195 /* LFO */
196 static const Bit32u lfo_cycles[8] = {
197 108, 77, 71, 67, 62, 44, 8, 5
198 };
199
200 /* FM algorithm */
201 static const Bit32u fm_algorithm[4][6][8] = {
202 {
203 { 1, 1, 1, 1, 1, 1, 1, 1 }, /* OP1_0 */
204 { 1, 1, 1, 1, 1, 1, 1, 1 }, /* OP1_1 */
205 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP2 */
206 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
207 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
208 { 0, 0, 0, 0, 0, 0, 0, 1 } /* Out */
209 },
210 {
211 { 0, 1, 0, 0, 0, 1, 0, 0 }, /* OP1_0 */
212 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */
213 { 1, 1, 1, 0, 0, 0, 0, 0 }, /* OP2 */
214 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
215 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
216 { 0, 0, 0, 0, 0, 1, 1, 1 } /* Out */
217 },
218 {
219 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_0 */
220 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */
221 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP2 */
222 { 1, 0, 0, 1, 1, 1, 1, 0 }, /* Last operator */
223 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
224 { 0, 0, 0, 0, 1, 1, 1, 1 } /* Out */
225 },
226 {
227 { 0, 0, 1, 0, 0, 1, 0, 0 }, /* OP1_0 */
228 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */
229 { 0, 0, 0, 1, 0, 0, 0, 0 }, /* OP2 */
230 { 1, 1, 0, 1, 1, 0, 0, 0 }, /* Last operator */
231 { 0, 0, 1, 0, 0, 0, 0, 0 }, /* Last operator */
232 { 1, 1, 1, 1, 1, 1, 1, 1 } /* Out */
233 }
234 };
235
236 static Bit32u chip_type = ym3438_mode_readmode;
237
OPN2_DoIO(ym3438_t * chip)238 void OPN2_DoIO(ym3438_t *chip)
239 {
240 /* Write signal check */
241 chip->write_a_en = (chip->write_a & 0x03) == 0x01;
242 chip->write_d_en = (chip->write_d & 0x03) == 0x01;
243 chip->write_a <<= 1;
244 chip->write_d <<= 1;
245 /* Busy counter */
246 chip->busy = chip->write_busy;
247 chip->write_busy_cnt += chip->write_busy;
248 chip->write_busy = (chip->write_busy && !(chip->write_busy_cnt >> 5)) || chip->write_d_en;
249 chip->write_busy_cnt &= 0x1f;
250 }
251
OPN2_DoRegWrite(ym3438_t * chip)252 void OPN2_DoRegWrite(ym3438_t *chip)
253 {
254 Bit32u i;
255 Bit32u slot = chip->slot % 12;
256 Bit32u address;
257 Bit32u channel = chip->channel;
258 /* Update registers */
259 if (chip->write_fm_data)
260 {
261 /* Slot */
262 if (op_offset[slot] == (chip->address & 0x107))
263 {
264 if (chip->address & 0x08)
265 {
266 /* OP2, OP4 */
267 slot += 12;
268 }
269 address = chip->address & 0xf0;
270 switch (address)
271 {
272 case 0x30: /* DT, MULTI */
273 chip->multi[slot] = chip->data & 0x0f;
274 if (!chip->multi[slot])
275 {
276 chip->multi[slot] = 1;
277 }
278 else
279 {
280 chip->multi[slot] <<= 1;
281 }
282 chip->dt[slot] = (chip->data >> 4) & 0x07;
283 break;
284 case 0x40: /* TL */
285 chip->tl[slot] = chip->data & 0x7f;
286 break;
287 case 0x50: /* KS, AR */
288 chip->ar[slot] = chip->data & 0x1f;
289 chip->ks[slot] = (chip->data >> 6) & 0x03;
290 break;
291 case 0x60: /* AM, DR */
292 chip->dr[slot] = chip->data & 0x1f;
293 chip->am[slot] = (chip->data >> 7) & 0x01;
294 break;
295 case 0x70: /* SR */
296 chip->sr[slot] = chip->data & 0x1f;
297 break;
298 case 0x80: /* SL, RR */
299 chip->rr[slot] = chip->data & 0x0f;
300 chip->sl[slot] = (chip->data >> 4) & 0x0f;
301 chip->sl[slot] |= (chip->sl[slot] + 1) & 0x10;
302 break;
303 case 0x90: /* SSG-EG */
304 chip->ssg_eg[slot] = chip->data & 0x0f;
305 break;
306 default:
307 break;
308 }
309 }
310
311 /* Channel */
312 if (ch_offset[channel] == (chip->address & 0x103))
313 {
314 address = chip->address & 0xfc;
315 switch (address)
316 {
317 case 0xa0:
318 chip->fnum[channel] = (chip->data & 0xff) | ((chip->reg_a4 & 0x07) << 8);
319 chip->block[channel] = (chip->reg_a4 >> 3) & 0x07;
320 chip->kcode[channel] = (chip->block[channel] << 2) | fn_note[chip->fnum[channel] >> 7];
321 break;
322 case 0xa4:
323 chip->reg_a4 = chip->data & 0xff;
324 break;
325 case 0xa8:
326 chip->fnum_3ch[channel] = (chip->data & 0xff) | ((chip->reg_ac & 0x07) << 8);
327 chip->block_3ch[channel] = (chip->reg_ac >> 3) & 0x07;
328 chip->kcode_3ch[channel] = (chip->block_3ch[channel] << 2) | fn_note[chip->fnum_3ch[channel] >> 7];
329 break;
330 case 0xac:
331 chip->reg_ac = chip->data & 0xff;
332 break;
333 case 0xb0:
334 chip->connect[channel] = chip->data & 0x07;
335 chip->fb[channel] = (chip->data >> 3) & 0x07;
336 break;
337 case 0xb4:
338 chip->pms[channel] = chip->data & 0x07;
339 chip->ams[channel] = (chip->data >> 4) & 0x03;
340 chip->pan_l[channel] = (chip->data >> 7) & 0x01;
341 chip->pan_r[channel] = (chip->data >> 6) & 0x01;
342 break;
343 default:
344 break;
345 }
346 }
347 }
348
349 if (chip->write_a_en || chip->write_d_en)
350 {
351 /* Data */
352 if (chip->write_a_en)
353 {
354 chip->write_fm_data = 0;
355 }
356
357 if (chip->write_fm_address && chip->write_d_en)
358 {
359 chip->write_fm_data = 1;
360 }
361
362 /* Address */
363 if (chip->write_a_en)
364 {
365 if ((chip->write_data & 0xf0) != 0x00)
366 {
367 /* FM Write */
368 chip->address = chip->write_data;
369 chip->write_fm_address = 1;
370 }
371 else
372 {
373 /* SSG write */
374 chip->write_fm_address = 0;
375 }
376 }
377
378 /* FM Mode */
379 /* Data */
380 if (chip->write_d_en && (chip->write_data & 0x100) == 0)
381 {
382 switch (chip->address)
383 {
384 case 0x21: /* LSI test 1 */
385 for (i = 0; i < 8; i++)
386 {
387 chip->mode_test_21[i] = (chip->write_data >> i) & 0x01;
388 }
389 break;
390 case 0x22: /* LFO control */
391 if ((chip->write_data >> 3) & 0x01)
392 {
393 chip->lfo_en = 0x7f;
394 }
395 else
396 {
397 chip->lfo_en = 0;
398 }
399 chip->lfo_freq = chip->write_data & 0x07;
400 break;
401 case 0x24: /* Timer A */
402 chip->timer_a_reg &= 0x03;
403 chip->timer_a_reg |= (chip->write_data & 0xff) << 2;
404 break;
405 case 0x25:
406 chip->timer_a_reg &= 0x3fc;
407 chip->timer_a_reg |= chip->write_data & 0x03;
408 break;
409 case 0x26: /* Timer B */
410 chip->timer_b_reg = chip->write_data & 0xff;
411 break;
412 case 0x27: /* CSM, Timer control */
413 chip->mode_ch3 = (chip->write_data & 0xc0) >> 6;
414 chip->mode_csm = chip->mode_ch3 == 2;
415 chip->timer_a_load = chip->write_data & 0x01;
416 chip->timer_a_enable = (chip->write_data >> 2) & 0x01;
417 chip->timer_a_reset = (chip->write_data >> 4) & 0x01;
418 chip->timer_b_load = (chip->write_data >> 1) & 0x01;
419 chip->timer_b_enable = (chip->write_data >> 3) & 0x01;
420 chip->timer_b_reset = (chip->write_data >> 5) & 0x01;
421 break;
422 case 0x28: /* Key on/off */
423 for (i = 0; i < 4; i++)
424 {
425 chip->mode_kon_operator[i] = (chip->write_data >> (4 + i)) & 0x01;
426 }
427 if ((chip->write_data & 0x03) == 0x03)
428 {
429 /* Invalid address */
430 chip->mode_kon_channel = 0xff;
431 }
432 else
433 {
434 chip->mode_kon_channel = (chip->write_data & 0x03) + ((chip->write_data >> 2) & 1) * 3;
435 }
436 break;
437 case 0x2a: /* DAC data */
438 chip->dacdata &= 0x01;
439 chip->dacdata |= (chip->write_data ^ 0x80) << 1;
440 break;
441 case 0x2b: /* DAC enable */
442 chip->dacen = chip->write_data >> 7;
443 break;
444 case 0x2c: /* LSI test 2 */
445 for (i = 0; i < 8; i++)
446 {
447 chip->mode_test_2c[i] = (chip->write_data >> i) & 0x01;
448 }
449 chip->dacdata &= 0x1fe;
450 chip->dacdata |= chip->mode_test_2c[3];
451 chip->eg_custom_timer = !chip->mode_test_2c[7] && chip->mode_test_2c[6];
452 break;
453 default:
454 break;
455 }
456 }
457
458 /* Address */
459 if (chip->write_a_en)
460 {
461 chip->write_fm_mode_a = chip->write_data & 0xff;
462 }
463 }
464
465 if (chip->write_fm_data)
466 {
467 chip->data = chip->write_data & 0xff;
468 }
469 }
470
OPN2_PhaseCalcIncrement(ym3438_t * chip)471 void OPN2_PhaseCalcIncrement(ym3438_t *chip)
472 {
473 Bit32u fnum = chip->pg_fnum;
474 Bit32u fnum_h = fnum >> 4;
475 Bit32u fm;
476 Bit32u basefreq;
477 Bit8u lfo = chip->lfo_pm;
478 Bit8u lfo_l = lfo & 0x0f;
479 Bit8u pms = chip->pms[chip->channel];
480 Bit8u dt = chip->dt[chip->slot];
481 Bit8u dt_l = dt & 0x03;
482 Bit8u detune = 0;
483 Bit8u block, note;
484 Bit8u sum, sum_h, sum_l;
485 Bit8u kcode = chip->pg_kcode;
486
487 fnum <<= 1;
488 /* Apply LFO */
489 if (lfo_l & 0x08)
490 {
491 lfo_l ^= 0x0f;
492 }
493 fm = (fnum_h >> pg_lfo_sh1[pms][lfo_l]) + (fnum_h >> pg_lfo_sh2[pms][lfo_l]);
494 if (pms > 5)
495 {
496 fm <<= pms - 5;
497 }
498 fm >>= 2;
499 if (lfo & 0x10)
500 {
501 fnum -= fm;
502 }
503 else
504 {
505 fnum += fm;
506 }
507 fnum &= 0xfff;
508
509 basefreq = (fnum << chip->pg_block) >> 2;
510
511 /* Apply detune */
512 if (dt_l)
513 {
514 if (kcode > 0x1c)
515 {
516 kcode = 0x1c;
517 }
518 block = kcode >> 2;
519 note = kcode & 0x03;
520 sum = block + 9 + ((dt_l == 3) | (dt_l & 0x02));
521 sum_h = sum >> 1;
522 sum_l = sum & 0x01;
523 detune = pg_detune[(sum_l << 2) | note] >> (9 - sum_h);
524 }
525 if (dt & 0x04)
526 {
527 basefreq -= detune;
528 }
529 else
530 {
531 basefreq += detune;
532 }
533 basefreq &= 0x1ffff;
534 chip->pg_inc[chip->slot] = (basefreq * chip->multi[chip->slot]) >> 1;
535 chip->pg_inc[chip->slot] &= 0xfffff;
536 }
537
OPN2_PhaseGenerate(ym3438_t * chip)538 void OPN2_PhaseGenerate(ym3438_t *chip)
539 {
540 Bit32u slot;
541 /* Mask increment */
542 slot = (chip->slot + 20) % 24;
543 if (chip->pg_reset[slot])
544 {
545 chip->pg_inc[slot] = 0;
546 }
547 /* Phase step */
548 slot = (chip->slot + 19) % 24;
549 chip->pg_phase[slot] += chip->pg_inc[slot];
550 chip->pg_phase[slot] &= 0xfffff;
551 if (chip->pg_reset[slot] || chip->mode_test_21[3])
552 {
553 chip->pg_phase[slot] = 0;
554 }
555 }
556
OPN2_EnvelopeSSGEG(ym3438_t * chip)557 void OPN2_EnvelopeSSGEG(ym3438_t *chip)
558 {
559 Bit32u slot = chip->slot;
560 Bit8u direction = 0;
561 chip->eg_ssg_pgrst_latch[slot] = 0;
562 chip->eg_ssg_repeat_latch[slot] = 0;
563 chip->eg_ssg_hold_up_latch[slot] = 0;
564 chip->eg_ssg_inv[slot] = 0;
565 if (chip->ssg_eg[slot] & 0x08)
566 {
567 direction = chip->eg_ssg_dir[slot];
568 if (chip->eg_level[slot] & 0x200)
569 {
570 /* Reset */
571 if ((chip->ssg_eg[slot] & 0x03) == 0x00)
572 {
573 chip->eg_ssg_pgrst_latch[slot] = 1;
574 }
575 /* Repeat */
576 if ((chip->ssg_eg[slot] & 0x01) == 0x00)
577 {
578 chip->eg_ssg_repeat_latch[slot] = 1;
579 }
580 /* Inverse */
581 if ((chip->ssg_eg[slot] & 0x03) == 0x02)
582 {
583 direction ^= 1;
584 }
585 if ((chip->ssg_eg[slot] & 0x03) == 0x03)
586 {
587 direction = 1;
588 }
589 }
590 /* Hold up */
591 if (chip->eg_kon_latch[slot]
592 && ((chip->ssg_eg[slot] & 0x07) == 0x05 || (chip->ssg_eg[slot] & 0x07) == 0x03))
593 {
594 chip->eg_ssg_hold_up_latch[slot] = 1;
595 }
596 direction &= chip->eg_kon[slot];
597 chip->eg_ssg_inv[slot] = (chip->eg_ssg_dir[slot] ^ ((chip->ssg_eg[slot] >> 2) & 0x01))
598 & chip->eg_kon[slot];
599 }
600 chip->eg_ssg_dir[slot] = direction;
601 chip->eg_ssg_enable[slot] = (chip->ssg_eg[slot] >> 3) & 0x01;
602 }
603
OPN2_EnvelopeADSR(ym3438_t * chip)604 void OPN2_EnvelopeADSR(ym3438_t *chip)
605 {
606 Bit32u slot = (chip->slot + 22) % 24;
607
608 Bit8u nkon = chip->eg_kon_latch[slot];
609 Bit8u okon = chip->eg_kon[slot];
610 Bit8u kon_event;
611 Bit8u koff_event;
612 Bit8u eg_off;
613 Bit16s level;
614 Bit16s nextlevel = 0;
615 Bit16s ssg_level;
616 Bit8u nextstate = chip->eg_state[slot];
617 Bit16s inc = 0;
618 chip->eg_read[0] = chip->eg_read_inc;
619 chip->eg_read_inc = chip->eg_inc > 0;
620
621 /* Reset phase generator */
622 chip->pg_reset[slot] = (nkon && !okon) || chip->eg_ssg_pgrst_latch[slot];
623
624 /* KeyOn/Off */
625 kon_event = (nkon && !okon) || (okon && chip->eg_ssg_repeat_latch[slot]);
626 koff_event = okon && !nkon;
627
628 ssg_level = level = (Bit16s)chip->eg_level[slot];
629
630 if (chip->eg_ssg_inv[slot])
631 {
632 /* Inverse */
633 ssg_level = 512 - level;
634 ssg_level &= 0x3ff;
635 }
636 if (koff_event)
637 {
638 level = ssg_level;
639 }
640 if (chip->eg_ssg_enable[slot])
641 {
642 eg_off = level >> 9;
643 }
644 else
645 {
646 eg_off = (level & 0x3f0) == 0x3f0;
647 }
648 nextlevel = level;
649 if (kon_event)
650 {
651 nextstate = eg_num_attack;
652 /* Instant attack */
653 if (chip->eg_ratemax)
654 {
655 nextlevel = 0;
656 }
657 else if (chip->eg_state[slot] == eg_num_attack && level != 0 && chip->eg_inc && nkon)
658 {
659 inc = (~level << chip->eg_inc) >> 5;
660 }
661 }
662 else
663 {
664 switch (chip->eg_state[slot])
665 {
666 case eg_num_attack:
667 if (level == 0)
668 {
669 nextstate = eg_num_decay;
670 }
671 else if(chip->eg_inc && !chip->eg_ratemax && nkon)
672 {
673 inc = (~level << chip->eg_inc) >> 5;
674 }
675 break;
676 case eg_num_decay:
677 if ((level >> 5) == chip->eg_sl[1])
678 {
679 nextstate = eg_num_sustain;
680 }
681 else if (!eg_off && chip->eg_inc)
682 {
683 inc = 1 << (chip->eg_inc - 1);
684 if (chip->eg_ssg_enable[slot])
685 {
686 inc <<= 2;
687 }
688 }
689 break;
690 case eg_num_sustain:
691 case eg_num_release:
692 if (!eg_off && chip->eg_inc)
693 {
694 inc = 1 << (chip->eg_inc - 1);
695 if (chip->eg_ssg_enable[slot])
696 {
697 inc <<= 2;
698 }
699 }
700 break;
701 default:
702 break;
703 }
704 if (!nkon)
705 {
706 nextstate = eg_num_release;
707 }
708 }
709 if (chip->eg_kon_csm[slot])
710 {
711 nextlevel |= chip->eg_tl[1] << 3;
712 }
713
714 /* Envelope off */
715 if (!kon_event && !chip->eg_ssg_hold_up_latch[slot] && chip->eg_state[slot] != eg_num_attack && eg_off)
716 {
717 nextstate = eg_num_release;
718 nextlevel = 0x3ff;
719 }
720
721 nextlevel += inc;
722
723 chip->eg_kon[slot] = chip->eg_kon_latch[slot];
724 chip->eg_level[slot] = (Bit16u)nextlevel & 0x3ff;
725 chip->eg_state[slot] = nextstate;
726 }
727
OPN2_EnvelopePrepare(ym3438_t * chip)728 void OPN2_EnvelopePrepare(ym3438_t *chip)
729 {
730 Bit8u rate;
731 Bit8u sum;
732 Bit8u inc = 0;
733 Bit32u slot = chip->slot;
734 Bit8u rate_sel;
735
736 /* Prepare increment */
737 rate = (chip->eg_rate << 1) + chip->eg_ksv;
738
739 if (rate > 0x3f)
740 {
741 rate = 0x3f;
742 }
743
744 sum = ((rate >> 2) + chip->eg_shift_lock) & 0x0f;
745 if (chip->eg_rate != 0 && chip->eg_quotient == 2)
746 {
747 if (rate < 48)
748 {
749 switch (sum)
750 {
751 case 12:
752 inc = 1;
753 break;
754 case 13:
755 inc = (rate >> 1) & 0x01;
756 break;
757 case 14:
758 inc = rate & 0x01;
759 break;
760 default:
761 break;
762 }
763 }
764 else
765 {
766 inc = eg_stephi[rate & 0x03][chip->eg_timer_low_lock] + (rate >> 2) - 11;
767 if (inc > 4)
768 {
769 inc = 4;
770 }
771 }
772 }
773 chip->eg_inc = inc;
774 chip->eg_ratemax = (rate >> 1) == 0x1f;
775
776 /* Prepare rate & ksv */
777 rate_sel = chip->eg_state[slot];
778 if ((chip->eg_kon[slot] && chip->eg_ssg_repeat_latch[slot])
779 || (!chip->eg_kon[slot] && chip->eg_kon_latch[slot]))
780 {
781 rate_sel = eg_num_attack;
782 }
783 switch (rate_sel)
784 {
785 case eg_num_attack:
786 chip->eg_rate = chip->ar[slot];
787 break;
788 case eg_num_decay:
789 chip->eg_rate = chip->dr[slot];
790 break;
791 case eg_num_sustain:
792 chip->eg_rate = chip->sr[slot];
793 break;
794 case eg_num_release:
795 chip->eg_rate = (chip->rr[slot] << 1) | 0x01;
796 break;
797 default:
798 break;
799 }
800 chip->eg_ksv = chip->pg_kcode >> (chip->ks[slot] ^ 0x03);
801 if (chip->am[slot])
802 {
803 chip->eg_lfo_am = chip->lfo_am >> eg_am_shift[chip->ams[chip->channel]];
804 }
805 else
806 {
807 chip->eg_lfo_am = 0;
808 }
809 /* Delay TL & SL value */
810 chip->eg_tl[1] = chip->eg_tl[0];
811 chip->eg_tl[0] = chip->tl[slot];
812 chip->eg_sl[1] = chip->eg_sl[0];
813 chip->eg_sl[0] = chip->sl[slot];
814 }
815
OPN2_EnvelopeGenerate(ym3438_t * chip)816 void OPN2_EnvelopeGenerate(ym3438_t *chip)
817 {
818 Bit32u slot = (chip->slot + 23) % 24;
819 Bit16u level;
820
821 level = chip->eg_level[slot];
822
823 if (chip->eg_ssg_inv[slot])
824 {
825 /* Inverse */
826 level = 512 - level;
827 }
828 if (chip->mode_test_21[5])
829 {
830 level = 0;
831 }
832 level &= 0x3ff;
833
834 /* Apply AM LFO */
835 level += chip->eg_lfo_am;
836
837 /* Apply TL */
838 if (!(chip->mode_csm && chip->channel == 2 + 1))
839 {
840 level += chip->eg_tl[0] << 3;
841 }
842 if (level > 0x3ff)
843 {
844 level = 0x3ff;
845 }
846 chip->eg_out[slot] = level;
847 }
848
OPN2_UpdateLFO(ym3438_t * chip)849 void OPN2_UpdateLFO(ym3438_t *chip)
850 {
851 if ((chip->lfo_quotient & lfo_cycles[chip->lfo_freq]) == lfo_cycles[chip->lfo_freq])
852 {
853 chip->lfo_quotient = 0;
854 chip->lfo_cnt++;
855 }
856 else
857 {
858 chip->lfo_quotient += chip->lfo_inc;
859 }
860 chip->lfo_cnt &= chip->lfo_en;
861 }
862
OPN2_FMPrepare(ym3438_t * chip)863 void OPN2_FMPrepare(ym3438_t *chip)
864 {
865 Bit32u slot = (chip->slot + 6) % 24;
866 Bit32u channel = chip->channel;
867 Bit16s mod, mod1, mod2;
868 Bit32u op = slot / 6;
869 Bit8u connect = chip->connect[channel];
870 Bit32u prevslot = (chip->slot + 18) % 24;
871
872 /* Calculate modulation */
873 mod1 = mod2 = 0;
874
875 if (fm_algorithm[op][0][connect])
876 {
877 mod2 |= chip->fm_op1[channel][0];
878 }
879 if (fm_algorithm[op][1][connect])
880 {
881 mod1 |= chip->fm_op1[channel][1];
882 }
883 if (fm_algorithm[op][2][connect])
884 {
885 mod1 |= chip->fm_op2[channel];
886 }
887 if (fm_algorithm[op][3][connect])
888 {
889 mod2 |= chip->fm_out[prevslot];
890 }
891 if (fm_algorithm[op][4][connect])
892 {
893 mod1 |= chip->fm_out[prevslot];
894 }
895 mod = mod1 + mod2;
896 if (op == 0)
897 {
898 /* Feedback */
899 mod = mod >> (10 - chip->fb[channel]);
900 if (!chip->fb[channel])
901 {
902 mod = 0;
903 }
904 }
905 else
906 {
907 mod >>= 1;
908 }
909 chip->fm_mod[slot] = mod;
910
911 slot = (chip->slot + 18) % 24;
912 /* OP1 */
913 if (slot / 6 == 0)
914 {
915 chip->fm_op1[channel][1] = chip->fm_op1[channel][0];
916 chip->fm_op1[channel][0] = chip->fm_out[slot];
917 }
918 /* OP2 */
919 if (slot / 6 == 2)
920 {
921 chip->fm_op2[channel] = chip->fm_out[slot];
922 }
923 }
924
OPN2_ChGenerate(ym3438_t * chip)925 void OPN2_ChGenerate(ym3438_t *chip)
926 {
927 Bit32u slot = (chip->slot + 18) % 24;
928 Bit32u channel = chip->channel;
929 Bit32u op = slot / 6;
930 Bit32u test_dac = chip->mode_test_2c[5];
931 Bit16s acc = chip->ch_acc[channel];
932 Bit16s add = test_dac;
933 Bit16s sum = 0;
934 if (op == 0 && !test_dac)
935 {
936 acc = 0;
937 }
938 if (fm_algorithm[op][5][chip->connect[channel]] && !test_dac)
939 {
940 add += chip->fm_out[slot] >> 5;
941 }
942 sum = acc + add;
943 /* Clamp */
944 if (sum > 255)
945 {
946 sum = 255;
947 }
948 else if(sum < -256)
949 {
950 sum = -256;
951 }
952
953 if (op == 0 || test_dac)
954 {
955 chip->ch_out[channel] = chip->ch_acc[channel];
956 }
957 chip->ch_acc[channel] = sum;
958 }
959
OPN2_ChOutput(ym3438_t * chip)960 void OPN2_ChOutput(ym3438_t *chip)
961 {
962 Bit32u cycles = chip->cycles;
963 Bit32u channel = chip->channel;
964 Bit32u test_dac = chip->mode_test_2c[5];
965 Bit16s out;
966 Bit16s sign;
967 Bit32u out_en;
968 chip->ch_read = chip->ch_lock;
969 if (chip->slot < 12)
970 {
971 /* Ch 4,5,6 */
972 channel++;
973 }
974 if ((cycles & 3) == 0)
975 {
976 if (!test_dac)
977 {
978 /* Lock value */
979 chip->ch_lock = chip->ch_out[channel];
980 }
981 chip->ch_lock_l = chip->pan_l[channel];
982 chip->ch_lock_r = chip->pan_r[channel];
983 }
984 /* Ch 6 */
985 if (((cycles >> 2) == 1 && chip->dacen) || test_dac)
986 {
987 out = (Bit16s)chip->dacdata;
988 out <<= 7;
989 out >>= 7;
990 }
991 else
992 {
993 out = chip->ch_lock;
994 }
995 chip->mol = 0;
996 chip->mor = 0;
997
998 if (chip_type & ym3438_mode_ym2612)
999 {
1000 out_en = ((cycles & 3) == 3) || test_dac;
1001 /* YM2612 DAC emulation(not verified) */
1002 sign = out >> 8;
1003 if (out >= 0)
1004 {
1005 out++;
1006 sign++;
1007 }
1008 if (chip->ch_lock_l && out_en)
1009 {
1010 chip->mol = out;
1011 }
1012 else
1013 {
1014 chip->mol = sign;
1015 }
1016 if (chip->ch_lock_r && out_en)
1017 {
1018 chip->mor = out;
1019 }
1020 else
1021 {
1022 chip->mor = sign;
1023 }
1024 /* Amplify signal */
1025 chip->mol *= 3;
1026 chip->mor *= 3;
1027 }
1028 else
1029 {
1030 out_en = ((cycles & 3) != 0) || test_dac;
1031 if (chip->ch_lock_l && out_en)
1032 {
1033 chip->mol = out;
1034 }
1035 if (chip->ch_lock_r && out_en)
1036 {
1037 chip->mor = out;
1038 }
1039 }
1040 }
1041
OPN2_FMGenerate(ym3438_t * chip)1042 void OPN2_FMGenerate(ym3438_t *chip)
1043 {
1044 Bit32u slot = (chip->slot + 19) % 24;
1045 /* Calculate phase */
1046 Bit16u phase = (chip->fm_mod[slot] + (chip->pg_phase[slot] >> 10)) & 0x3ff;
1047 Bit16u quarter;
1048 Bit16u level;
1049 Bit16s output;
1050 if (phase & 0x100)
1051 {
1052 quarter = (phase ^ 0xff) & 0xff;
1053 }
1054 else
1055 {
1056 quarter = phase & 0xff;
1057 }
1058 level = logsinrom[quarter];
1059 /* Apply envelope */
1060 level += chip->eg_out[slot] << 2;
1061 /* Transform */
1062 if (level > 0x1fff)
1063 {
1064 level = 0x1fff;
1065 }
1066 output = ((exprom[(level & 0xff) ^ 0xff] | 0x400) << 2) >> (level >> 8);
1067 if (phase & 0x200)
1068 {
1069 output = ((~output) ^ (chip->mode_test_21[4] << 13)) + 1;
1070 }
1071 else
1072 {
1073 output = output ^ (chip->mode_test_21[4] << 13);
1074 }
1075 output <<= 2;
1076 output >>= 2;
1077 chip->fm_out[slot] = output;
1078 }
1079
OPN2_DoTimerA(ym3438_t * chip)1080 void OPN2_DoTimerA(ym3438_t *chip)
1081 {
1082 Bit16u time;
1083 Bit8u load;
1084 load = chip->timer_a_overflow;
1085 if (chip->cycles == 2)
1086 {
1087 /* Lock load value */
1088 load |= (!chip->timer_a_load_lock && chip->timer_a_load);
1089 chip->timer_a_load_lock = chip->timer_a_load;
1090 if (chip->mode_csm)
1091 {
1092 /* CSM KeyOn */
1093 chip->mode_kon_csm = load;
1094 }
1095 else
1096 {
1097 chip->mode_kon_csm = 0;
1098 }
1099 }
1100 /* Load counter */
1101 if (chip->timer_a_load_latch)
1102 {
1103 time = chip->timer_a_reg;
1104 }
1105 else
1106 {
1107 time = chip->timer_a_cnt;
1108 }
1109 chip->timer_a_load_latch = load;
1110 /* Increase counter */
1111 if ((chip->cycles == 1 && chip->timer_a_load_lock) || chip->mode_test_21[2])
1112 {
1113 time++;
1114 }
1115 /* Set overflow flag */
1116 if (chip->timer_a_reset)
1117 {
1118 chip->timer_a_reset = 0;
1119 chip->timer_a_overflow_flag = 0;
1120 }
1121 else
1122 {
1123 chip->timer_a_overflow_flag |= chip->timer_a_overflow & chip->timer_a_enable;
1124 }
1125 chip->timer_a_overflow = (time >> 10);
1126 chip->timer_a_cnt = time & 0x3ff;
1127 }
1128
OPN2_DoTimerB(ym3438_t * chip)1129 void OPN2_DoTimerB(ym3438_t *chip)
1130 {
1131 Bit16u time;
1132 Bit8u load;
1133 load = chip->timer_b_overflow;
1134 if (chip->cycles == 2)
1135 {
1136 /* Lock load value */
1137 load |= (!chip->timer_b_load_lock && chip->timer_b_load);
1138 chip->timer_b_load_lock = chip->timer_b_load;
1139 }
1140 /* Load counter */
1141 if (chip->timer_b_load_latch)
1142 {
1143 time = chip->timer_b_reg;
1144 }
1145 else
1146 {
1147 time = chip->timer_b_cnt;
1148 }
1149 chip->timer_b_load_latch = load;
1150 /* Increase counter */
1151 if (chip->cycles == 1)
1152 {
1153 chip->timer_b_subcnt++;
1154 }
1155 if ((chip->timer_b_subcnt == 0x10 && chip->timer_b_load_lock) || chip->mode_test_21[2])
1156 {
1157 time++;
1158 }
1159 chip->timer_b_subcnt &= 0x0f;
1160 /* Set overflow flag */
1161 if (chip->timer_b_reset)
1162 {
1163 chip->timer_b_reset = 0;
1164 chip->timer_b_overflow_flag = 0;
1165 }
1166 else
1167 {
1168 chip->timer_b_overflow_flag |= chip->timer_b_overflow & chip->timer_b_enable;
1169 }
1170 chip->timer_b_overflow = (time >> 8);
1171 chip->timer_b_cnt = time & 0xff;
1172 }
1173
OPN2_KeyOn(ym3438_t * chip)1174 void OPN2_KeyOn(ym3438_t*chip)
1175 {
1176 /* Key On */
1177 chip->eg_kon_latch[chip->slot] = chip->mode_kon[chip->slot];
1178 chip->eg_kon_csm[chip->slot] = 0;
1179 if (chip->channel == 2 && chip->mode_kon_csm)
1180 {
1181 /* CSM Key On */
1182 chip->eg_kon_latch[chip->slot] = 1;
1183 chip->eg_kon_csm[chip->slot] = 1;
1184 }
1185 if (chip->cycles == chip->mode_kon_channel)
1186 {
1187 /* OP1 */
1188 chip->mode_kon[chip->channel] = chip->mode_kon_operator[0];
1189 /* OP2 */
1190 chip->mode_kon[chip->channel + 12] = chip->mode_kon_operator[1];
1191 /* OP3 */
1192 chip->mode_kon[chip->channel + 6] = chip->mode_kon_operator[2];
1193 /* OP4 */
1194 chip->mode_kon[chip->channel + 18] = chip->mode_kon_operator[3];
1195 }
1196 }
1197
OPN2_Reset(ym3438_t * chip)1198 void OPN2_Reset(ym3438_t *chip)
1199 {
1200 Bit32u i;
1201 memset(chip, 0, sizeof(ym3438_t));
1202 for (i = 0; i < 24; i++)
1203 {
1204 chip->eg_out[i] = 0x3ff;
1205 chip->eg_level[i] = 0x3ff;
1206 chip->eg_state[i] = eg_num_release;
1207 chip->multi[i] = 1;
1208 }
1209 for (i = 0; i < 6; i++)
1210 {
1211 chip->pan_l[i] = 1;
1212 chip->pan_r[i] = 1;
1213 }
1214 }
1215
OPN2_SetChipType(Bit32u type)1216 void OPN2_SetChipType(Bit32u type)
1217 {
1218 chip_type = type;
1219 }
1220
OPN2_Clock(ym3438_t * chip,Bit16s * buffer)1221 void OPN2_Clock(ym3438_t *chip, Bit16s *buffer)
1222 {
1223 chip->lfo_inc = chip->mode_test_21[1];
1224 chip->pg_read >>= 1;
1225 chip->eg_read[1] >>= 1;
1226 chip->eg_cycle++;
1227 /* Lock envelope generator timer value */
1228 if (chip->cycles == 1 && chip->eg_quotient == 2)
1229 {
1230 if (chip->eg_cycle_stop)
1231 {
1232 chip->eg_shift_lock = 0;
1233 }
1234 else
1235 {
1236 chip->eg_shift_lock = chip->eg_shift + 1;
1237 }
1238 chip->eg_timer_low_lock = chip->eg_timer & 0x03;
1239 }
1240 /* Cycle specific functions */
1241 switch (chip->cycles)
1242 {
1243 case 0:
1244 chip->lfo_pm = chip->lfo_cnt >> 2;
1245 if (chip->lfo_cnt & 0x40)
1246 {
1247 chip->lfo_am = chip->lfo_cnt & 0x3f;
1248 }
1249 else
1250 {
1251 chip->lfo_am = chip->lfo_cnt ^ 0x3f;
1252 }
1253 chip->lfo_am <<= 1;
1254 break;
1255 case 1:
1256 chip->eg_quotient++;
1257 chip->eg_quotient %= 3;
1258 chip->eg_cycle = 0;
1259 chip->eg_cycle_stop = 1;
1260 chip->eg_shift = 0;
1261 chip->eg_timer_inc |= chip->eg_quotient >> 1;
1262 chip->eg_timer = chip->eg_timer + chip->eg_timer_inc;
1263 chip->eg_timer_inc = chip->eg_timer >> 12;
1264 chip->eg_timer &= 0xfff;
1265 break;
1266 case 2:
1267 chip->pg_read = chip->pg_phase[21] & 0x3ff;
1268 chip->eg_read[1] = chip->eg_out[0];
1269 break;
1270 case 13:
1271 chip->eg_cycle = 0;
1272 chip->eg_cycle_stop = 1;
1273 chip->eg_shift = 0;
1274 chip->eg_timer = chip->eg_timer + chip->eg_timer_inc;
1275 chip->eg_timer_inc = chip->eg_timer >> 12;
1276 chip->eg_timer &= 0xfff;
1277 break;
1278 case 23:
1279 chip->lfo_inc |= 1;
1280 break;
1281 }
1282 chip->eg_timer &= ~(chip->mode_test_21[5] << chip->eg_cycle);
1283 if (((chip->eg_timer >> chip->eg_cycle) | (chip->pin_test_in & chip->eg_custom_timer)) & chip->eg_cycle_stop)
1284 {
1285 chip->eg_shift = chip->eg_cycle;
1286 chip->eg_cycle_stop = 0;
1287 }
1288
1289 OPN2_DoIO(chip);
1290
1291 OPN2_DoTimerA(chip);
1292 OPN2_DoTimerB(chip);
1293 OPN2_KeyOn(chip);
1294
1295 OPN2_ChOutput(chip);
1296 OPN2_ChGenerate(chip);
1297
1298 OPN2_FMPrepare(chip);
1299 OPN2_FMGenerate(chip);
1300
1301 OPN2_PhaseGenerate(chip);
1302 OPN2_PhaseCalcIncrement(chip);
1303
1304 OPN2_EnvelopeADSR(chip);
1305 OPN2_EnvelopeGenerate(chip);
1306 OPN2_EnvelopeSSGEG(chip);
1307 OPN2_EnvelopePrepare(chip);
1308
1309 /* Prepare fnum & block */
1310 if (chip->mode_ch3)
1311 {
1312 /* Channel 3 special mode */
1313 switch (chip->slot)
1314 {
1315 case 1: /* OP1 */
1316 chip->pg_fnum = chip->fnum_3ch[1];
1317 chip->pg_block = chip->block_3ch[1];
1318 chip->pg_kcode = chip->kcode_3ch[1];
1319 break;
1320 case 7: /* OP3 */
1321 chip->pg_fnum = chip->fnum_3ch[0];
1322 chip->pg_block = chip->block_3ch[0];
1323 chip->pg_kcode = chip->kcode_3ch[0];
1324 break;
1325 case 13: /* OP2 */
1326 chip->pg_fnum = chip->fnum_3ch[2];
1327 chip->pg_block = chip->block_3ch[2];
1328 chip->pg_kcode = chip->kcode_3ch[2];
1329 break;
1330 case 19: /* OP4 */
1331 default:
1332 chip->pg_fnum = chip->fnum[(chip->channel + 1) % 6];
1333 chip->pg_block = chip->block[(chip->channel + 1) % 6];
1334 chip->pg_kcode = chip->kcode[(chip->channel + 1) % 6];
1335 break;
1336 }
1337 }
1338 else
1339 {
1340 chip->pg_fnum = chip->fnum[(chip->channel + 1) % 6];
1341 chip->pg_block = chip->block[(chip->channel + 1) % 6];
1342 chip->pg_kcode = chip->kcode[(chip->channel + 1) % 6];
1343 }
1344
1345 OPN2_UpdateLFO(chip);
1346 OPN2_DoRegWrite(chip);
1347 chip->cycles = (chip->cycles + 1) % 24;
1348 chip->slot = chip->cycles;
1349 chip->channel = chip->cycles % 6;
1350
1351 buffer[0] = chip->mol;
1352 buffer[1] = chip->mor;
1353
1354 if (chip->status_time)
1355 chip->status_time--;
1356 }
1357
OPN2_Write(ym3438_t * chip,Bit32u port,Bit8u data)1358 void OPN2_Write(ym3438_t *chip, Bit32u port, Bit8u data)
1359 {
1360 port &= 3;
1361 chip->write_data = ((port << 7) & 0x100) | data;
1362 if (port & 1)
1363 {
1364 /* Data */
1365 chip->write_d |= 1;
1366 }
1367 else
1368 {
1369 /* Address */
1370 chip->write_a |= 1;
1371 }
1372 }
1373
OPN2_SetTestPin(ym3438_t * chip,Bit32u value)1374 void OPN2_SetTestPin(ym3438_t *chip, Bit32u value)
1375 {
1376 chip->pin_test_in = value & 1;
1377 }
1378
OPN2_ReadTestPin(ym3438_t * chip)1379 Bit32u OPN2_ReadTestPin(ym3438_t *chip)
1380 {
1381 if (!chip->mode_test_2c[7])
1382 {
1383 return 0;
1384 }
1385 return chip->cycles == 23;
1386 }
1387
OPN2_ReadIRQPin(ym3438_t * chip)1388 Bit32u OPN2_ReadIRQPin(ym3438_t *chip)
1389 {
1390 return chip->timer_a_overflow_flag | chip->timer_b_overflow_flag;
1391 }
1392
OPN2_Read(ym3438_t * chip,Bit32u port)1393 Bit8u OPN2_Read(ym3438_t *chip, Bit32u port)
1394 {
1395 if ((port & 3) == 0 || (chip_type & ym3438_mode_readmode))
1396 {
1397 if (chip->mode_test_21[6])
1398 {
1399 /* Read test data */
1400 Bit16u testdata = ((chip->pg_read & 0x01) << 15)
1401 | ((chip->eg_read[chip->mode_test_21[0]] & 0x01) << 14);
1402 if (chip->mode_test_2c[4])
1403 {
1404 testdata |= chip->ch_read & 0x1ff;
1405 }
1406 else
1407 {
1408 testdata |= chip->fm_out[(chip->slot + 18) % 24] & 0x3fff;
1409 }
1410 if (chip->mode_test_21[7])
1411 {
1412 chip->status = testdata & 0xff;
1413 }
1414 else
1415 {
1416 chip->status = testdata >> 8;
1417 }
1418 }
1419 else
1420 {
1421 chip->status = (chip->busy << 7) | (chip->timer_b_overflow_flag << 1)
1422 | chip->timer_a_overflow_flag;
1423 }
1424 if (chip_type & ym3438_mode_ym2612)
1425 {
1426 chip->status_time = 300000;
1427 }
1428 else
1429 {
1430 chip->status_time = 40000000;
1431 }
1432 }
1433 if (chip->status_time)
1434 {
1435 return chip->status;
1436 }
1437 return 0;
1438 }
1439 #endif /* HAVE_YM3438_CORE */
1440