1 #include "../vidhrdw/gberet.c"
2
3 /***************************************************************************
4
5 Green Beret memory map (preliminary)
6
7 gberetb is a bootleg hacked to run on different hardware.
8
9 driver by Nicola Salmoria
10
11
12 0000-bfff ROM
13 c000-c7ff Color RAM
14 c800-cfff Video RAM
15 d000-d0c0 Sprites (bank 0)
16 d100-d1c0 Sprites (bank 1)
17 d200-dfff RAM
18 e000-e01f ZRAM1 line scroll registers
19 e020-e03f ZRAM2 bit 8 of line scroll registers
20
21 read:
22 f200 DSW1
23 bit 0-1 lives
24 bit 2 cocktail/upright cabinet (0 = upright)
25 bit 3-4 bonus
26 bit 5-6 difficulty
27 bit 7 demo sounds
28 f400 DSW2
29 bit 0 = screen flip
30 bit 1 = single/dual upright controls
31 f600 DSW0
32 bit 0-1-2-3 coins per play Coin1
33 bit 4-5-6-7 coins per play Coin2
34 f601 IN1 player 2 controls
35 f602 IN0 player 1 controls
36 f603 IN2
37 bit 0-1-2 coin bit 3 1 player start bit 4 2 players start
38
39 write:
40 e040 ?
41 e041 ?
42 e042 ?
43 e043 bit 3 = sprite RAM bank select; other bits = ?
44 e044 bit 0 = nmi enable, bit 3 = flip screen, other bits = ?
45 f000 ?
46 f200 SN76496 command
47 f400 SN76496 trigger (write command to f200, then write to this location
48 to cause the chip to read it)
49 f600 watchdog reset (?)
50
51 interrupts:
52 The game uses both IRQ (mode 1) and NMI.
53
54
55 TODO:
56 gberetb:
57 - cocktail mode
58 mrgoemon:
59 - flickering rogue sprites
60 - it resets during the first boot sequence, but works afterwards
61
62 ***************************************************************************/
63
64 #include "driver.h"
65 #include "vidhrdw/generic.h"
66
67
68
69 extern unsigned char *gberet_videoram,*gberet_colorram;
70 extern unsigned char *gberet_spritebank;
71 extern unsigned char *gberet_scrollram;
72 WRITE_HANDLER( gberet_videoram_w );
73 WRITE_HANDLER( gberet_colorram_w );
74 WRITE_HANDLER( gberet_e044_w );
75 WRITE_HANDLER( gberet_scroll_w );
76 WRITE_HANDLER( gberetb_scroll_w );
77 void gberet_vh_convert_color_prom(unsigned char *palette, unsigned short *colortable,const unsigned char *color_prom);
78 int gberet_vh_start(void);
79 void init_gberet(void);
80 void init_gberetb(void);
81 void gberet_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
82
83 int gberet_interrupt(void);
84
85
WRITE_HANDLER(gberet_coincounter_w)86 static WRITE_HANDLER( gberet_coincounter_w )
87 {
88 /* bits 0/1 = coin counters */
89 coin_counter_w(0,data & 1);
90 coin_counter_w(1,data & 2);
91 }
92
WRITE_HANDLER(mrgoemon_bankswitch_w)93 static WRITE_HANDLER( mrgoemon_bankswitch_w )
94 {
95 unsigned char *RAM = memory_region(REGION_CPU1);
96 int offs;
97
98 /* bits 0/1 = coin counters */
99 coin_counter_w(0,data & 1);
100 coin_counter_w(1,data & 2);
101
102 /* bits 5-7 = ROM bank select */
103 offs = 0x10000 + ((data & 0xe0) >> 5) * 0x800;
104 cpu_setbank(1,&RAM[offs]);
105 }
106
107
108
109 static struct MemoryReadAddress readmem[] =
110 {
111 { 0x0000, 0xbfff, MRA_ROM },
112 { 0xc000, 0xe03f, MRA_RAM },
113 { 0xf200, 0xf200, input_port_4_r }, /* DSW1 */
114 { 0xf400, 0xf400, input_port_5_r }, /* DSW2 */
115 { 0xf600, 0xf600, input_port_3_r }, /* DSW0 */
116 { 0xf601, 0xf601, input_port_1_r }, /* IN1 */
117 { 0xf602, 0xf602, input_port_0_r }, /* IN0 */
118 { 0xf603, 0xf603, input_port_2_r }, /* IN2 */
119 { 0xf800, 0xf800, MRA_NOP }, /* gberetb only - IRQ acknowledge */
120 { -1 } /* end of table */
121 };
122
123 static struct MemoryWriteAddress writemem[] =
124 {
125 { 0x0000, 0xbfff, MWA_ROM },
126 { 0xc000, 0xc7ff, gberet_colorram_w, &gberet_colorram },
127 { 0xc800, 0xcfff, gberet_videoram_w, &gberet_videoram },
128 { 0xd000, 0xd0bf, MWA_RAM, &spriteram_2 },
129 { 0xd100, 0xd1bf, MWA_RAM, &spriteram, &spriteram_size },
130 { 0xd200, 0xdfff, MWA_RAM },
131 { 0xe000, 0xe03f, gberet_scroll_w, &gberet_scrollram },
132 { 0xe043, 0xe043, MWA_RAM, &gberet_spritebank },
133 { 0xe044, 0xe044, gberet_e044_w },
134 { 0xf000, 0xf000, gberet_coincounter_w },
135 { 0xf200, 0xf200, MWA_NOP }, /* Loads the snd command into the snd latch */
136 { 0xf400, 0xf400, SN76496_0_w }, /* This address triggers the SN chip to read the data port. */
137 // { 0xf600, 0xf600, MWA_NOP },
138 { -1 } /* end of table */
139 };
140
141 static struct MemoryWriteAddress gberetb_writemem[] =
142 {
143 { 0x0000, 0xbfff, MWA_ROM },
144 { 0xc000, 0xc7ff, gberet_colorram_w, &gberet_colorram },
145 { 0xc800, 0xcfff, gberet_videoram_w, &gberet_videoram },
146 { 0xd000, 0xd0ff, MWA_RAM },
147 { 0xd100, 0xd1ff, MWA_RAM },
148 { 0xd200, 0xdfff, MWA_RAM },
149 { 0xe000, 0xe03f, MWA_RAM },
150 // { 0xe800, 0xe8ff, MWA_RAM },
151 { 0xe900, 0xe9ff, MWA_RAM, &spriteram, &spriteram_size },
152 { 0xf800, 0xf800, MWA_NOP }, /* NMI acknowledge */
153 { 0xf900, 0xf901, gberetb_scroll_w },
154 // { 0xe043, 0xe043, MWA_RAM, &gberet_spritebank },
155 { 0xe044, 0xe044, gberet_e044_w },
156 { 0xf400, 0xf400, SN76496_0_w },
157 { -1 } /* end of table */
158 };
159
160 static struct MemoryReadAddress mrgoemon_readmem[] =
161 {
162 { 0x0000, 0xbfff, MRA_ROM },
163 { 0xc000, 0xe03f, MRA_RAM },
164 { 0xf200, 0xf200, input_port_4_r }, /* DSW1 */
165 { 0xf400, 0xf400, input_port_5_r }, /* DSW2 */
166 { 0xf600, 0xf600, input_port_3_r }, /* DSW0 */
167 { 0xf601, 0xf601, input_port_1_r }, /* IN1 */
168 { 0xf602, 0xf602, input_port_0_r }, /* IN0 */
169 { 0xf603, 0xf603, input_port_2_r }, /* IN2 */
170 { 0xf800, 0xffff, MRA_BANK1 },
171 { -1 } /* end of table */
172 };
173
174 static struct MemoryWriteAddress mrgoemon_writemem[] =
175 {
176 { 0x0000, 0xbfff, MWA_ROM },
177 { 0xc000, 0xc7ff, gberet_colorram_w, &gberet_colorram },
178 { 0xc800, 0xcfff, gberet_videoram_w, &gberet_videoram },
179 { 0xd000, 0xd0bf, MWA_RAM, &spriteram_2 },
180 { 0xd100, 0xd1bf, MWA_RAM, &spriteram, &spriteram_size },
181 { 0xd200, 0xdfff, MWA_RAM },
182 { 0xe000, 0xe03f, gberet_scroll_w, &gberet_scrollram },
183 { 0xe043, 0xe043, MWA_RAM, &gberet_spritebank },
184 { 0xe044, 0xe044, gberet_e044_w },
185 { 0xf000, 0xf000, mrgoemon_bankswitch_w }, /* + coin counters */
186 { 0xf200, 0xf200, MWA_NOP }, /* Loads the snd command into the snd latch */
187 { 0xf400, 0xf400, SN76496_0_w }, /* This address triggers the SN chip to read the data port. */
188 { 0xf800, 0xffff, MWA_ROM },
189 { -1 } /* end of table */
190 };
191
192
193
194 INPUT_PORTS_START( gberet )
195 PORT_START /* IN0 */
196 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
197 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
198 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
199 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
200 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
201 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
202 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
203 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
204
205 PORT_START /* IN1 */
206 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
207 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
208 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
209 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
210 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
211 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_COCKTAIL )
212 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
213 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
214
215 PORT_START /* IN2 */
216 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
217 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
218 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
219 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
220 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
221 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
222 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
223 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
224
225 PORT_START /* DSW0 */
226 PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
227 PORT_DIPSETTING( 0x02, DEF_STR( 4C_1C ) )
228 PORT_DIPSETTING( 0x05, DEF_STR( 3C_1C ) )
229 PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
230 PORT_DIPSETTING( 0x04, DEF_STR( 3C_2C ) )
231 PORT_DIPSETTING( 0x01, DEF_STR( 4C_3C ) )
232 PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
233 PORT_DIPSETTING( 0x03, DEF_STR( 3C_4C ) )
234 PORT_DIPSETTING( 0x07, DEF_STR( 2C_3C ) )
235 PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
236 PORT_DIPSETTING( 0x06, DEF_STR( 2C_5C ) )
237 PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
238 PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
239 PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
240 PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) )
241 PORT_DIPSETTING( 0x09, DEF_STR( 1C_7C ) )
242 PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
243 PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_B ) )
244 PORT_DIPSETTING( 0x20, DEF_STR( 4C_1C ) )
245 PORT_DIPSETTING( 0x50, DEF_STR( 3C_1C ) )
246 PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
247 PORT_DIPSETTING( 0x40, DEF_STR( 3C_2C ) )
248 PORT_DIPSETTING( 0x10, DEF_STR( 4C_3C ) )
249 PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
250 PORT_DIPSETTING( 0x30, DEF_STR( 3C_4C ) )
251 PORT_DIPSETTING( 0x70, DEF_STR( 2C_3C ) )
252 PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
253 PORT_DIPSETTING( 0x60, DEF_STR( 2C_5C ) )
254 PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
255 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
256 PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
257 PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
258 PORT_DIPSETTING( 0x90, DEF_STR( 1C_7C ) )
259 /* 0x00 is invalid */
260
261 PORT_START /* DSW1 */
262 PORT_DIPNAME( 0x03, 0x02, DEF_STR( Lives ) )
263 PORT_DIPSETTING( 0x03, "2" )
264 PORT_DIPSETTING( 0x02, "3" )
265 PORT_DIPSETTING( 0x01, "5" )
266 PORT_DIPSETTING( 0x00, "7" )
267 PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) )
268 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
269 PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
270 PORT_DIPNAME( 0x18, 0x18, DEF_STR( Bonus_Life ) )
271 PORT_DIPSETTING( 0x18, "30000 70000" )
272 PORT_DIPSETTING( 0x10, "40000 80000" )
273 PORT_DIPSETTING( 0x08, "50000 100000" )
274 PORT_DIPSETTING( 0x00, "50000 200000" )
275 PORT_DIPNAME( 0x60, 0x60, DEF_STR( Difficulty ) )
276 PORT_DIPSETTING( 0x60, "Easy" )
277 PORT_DIPSETTING( 0x40, "Medium" )
278 PORT_DIPSETTING( 0x20, "Hard" )
279 PORT_DIPSETTING( 0x00, "Hardest" )
280 PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) )
281 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
282 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
283
284 PORT_START /* DSW2 */
285 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
286 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
287 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
288 PORT_DIPNAME( 0x02, 0x02, "Controls" )
289 PORT_DIPSETTING( 0x02, "Single" )
290 PORT_DIPSETTING( 0x00, "Dual" )
291 PORT_DIPNAME( 0x04, 0x04, DEF_STR ( Unknown ) )
292 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
293 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
294 PORT_DIPNAME( 0x08, 0x08, DEF_STR ( Unknown ) )
295 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
296 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
297 PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
298 INPUT_PORTS_END
299
300 /* IN2 is different and IN1 and DSW0 are swapped */
301 INPUT_PORTS_START( gberetb )
302 PORT_START /* IN0 */
303 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
304 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
305 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
306 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
307 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
308 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
309 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
310 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
311
312 PORT_START /* DSW0 */
313 PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
314 PORT_DIPSETTING( 0x02, DEF_STR( 4C_1C ) )
315 PORT_DIPSETTING( 0x05, DEF_STR( 3C_1C ) )
316 PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
317 PORT_DIPSETTING( 0x04, DEF_STR( 3C_2C ) )
318 PORT_DIPSETTING( 0x01, DEF_STR( 4C_3C ) )
319 PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
320 PORT_DIPSETTING( 0x03, DEF_STR( 3C_4C ) )
321 PORT_DIPSETTING( 0x07, DEF_STR( 2C_3C ) )
322 PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
323 PORT_DIPSETTING( 0x06, DEF_STR( 2C_5C ) )
324 PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
325 PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
326 PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
327 PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) )
328 PORT_DIPSETTING( 0x09, DEF_STR( 1C_7C ) )
329 PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
330 PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_B ) )
331 PORT_DIPSETTING( 0x20, DEF_STR( 4C_1C ) )
332 PORT_DIPSETTING( 0x50, DEF_STR( 3C_1C ) )
333 PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
334 PORT_DIPSETTING( 0x40, DEF_STR( 3C_2C ) )
335 PORT_DIPSETTING( 0x10, DEF_STR( 4C_3C ) )
336 PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
337 PORT_DIPSETTING( 0x30, DEF_STR( 3C_4C ) )
338 PORT_DIPSETTING( 0x70, DEF_STR( 2C_3C ) )
339 PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
340 PORT_DIPSETTING( 0x60, DEF_STR( 2C_5C ) )
341 PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
342 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
343 PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
344 PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
345 PORT_DIPSETTING( 0x90, DEF_STR( 1C_7C ) )
346 /* 0x00 is invalid */
347
348 PORT_START /* IN2 */
349 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
350 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
351 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
352 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
353 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
354 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
355 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
356 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
357
358 PORT_START /* IN1 */
359 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
360 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
361 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
362 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
363 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
364 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_COCKTAIL )
365 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
366 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
367
368 PORT_START /* DSW1 */
369 PORT_DIPNAME( 0x03, 0x02, DEF_STR( Lives ) )
370 PORT_DIPSETTING( 0x03, "2" )
371 PORT_DIPSETTING( 0x02, "3" )
372 PORT_DIPSETTING( 0x01, "5" )
373 PORT_DIPSETTING( 0x00, "7" )
374 PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) )
375 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
376 PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
377 PORT_DIPNAME( 0x18, 0x18, DEF_STR( Bonus_Life ) )
378 PORT_DIPSETTING( 0x18, "30000 70000" )
379 PORT_DIPSETTING( 0x10, "40000 80000" )
380 PORT_DIPSETTING( 0x08, "50000 100000" )
381 PORT_DIPSETTING( 0x00, "50000 200000" )
382 PORT_DIPNAME( 0x60, 0x60, DEF_STR( Difficulty ) )
383 PORT_DIPSETTING( 0x60, "Easy" )
384 PORT_DIPSETTING( 0x40, "Medium" )
385 PORT_DIPSETTING( 0x20, "Hard" )
386 PORT_DIPSETTING( 0x00, "Hardest" )
387 PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) )
388 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
389 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
390
391 PORT_START /* DSW2 */
392 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
393 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
394 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
395 PORT_DIPNAME( 0x02, 0x02, "Controls" )
396 PORT_DIPSETTING( 0x02, "Single" )
397 PORT_DIPSETTING( 0x00, "Dual" )
398 PORT_DIPNAME( 0x04, 0x04, DEF_STR ( Unknown ) )
399 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
400 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
401 PORT_DIPNAME( 0x08, 0x08, DEF_STR ( Unknown ) )
402 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
403 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
404 PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
405 INPUT_PORTS_END
406
407 INPUT_PORTS_START( mrgoemon )
408 PORT_START /* IN0 */
409 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_4WAY )
410 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_4WAY )
411 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_4WAY )
412 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_4WAY )
413 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
414 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
415 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
416 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
417
418 PORT_START /* IN1 */
419 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_4WAY | IPF_COCKTAIL )
420 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_4WAY | IPF_COCKTAIL )
421 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_4WAY | IPF_COCKTAIL )
422 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_4WAY | IPF_COCKTAIL )
423 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
424 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_COCKTAIL )
425 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
426 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
427
428 PORT_START /* IN2 */
429 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
430 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
431 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
432 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
433 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
434 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
435 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
436 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
437
438 PORT_START /* DSW0 */
439 PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
440 PORT_DIPSETTING( 0x02, DEF_STR( 4C_1C ) )
441 PORT_DIPSETTING( 0x05, DEF_STR( 3C_1C ) )
442 PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
443 PORT_DIPSETTING( 0x04, DEF_STR( 3C_2C ) )
444 PORT_DIPSETTING( 0x01, DEF_STR( 4C_3C ) )
445 PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
446 PORT_DIPSETTING( 0x03, DEF_STR( 3C_4C ) )
447 PORT_DIPSETTING( 0x07, DEF_STR( 2C_3C ) )
448 PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
449 PORT_DIPSETTING( 0x06, DEF_STR( 2C_5C ) )
450 PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
451 PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
452 PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
453 PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) )
454 PORT_DIPSETTING( 0x09, DEF_STR( 1C_7C ) )
455 PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
456 PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_B ) )
457 PORT_DIPSETTING( 0x20, DEF_STR( 4C_1C ) )
458 PORT_DIPSETTING( 0x50, DEF_STR( 3C_1C ) )
459 PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
460 PORT_DIPSETTING( 0x40, DEF_STR( 3C_2C ) )
461 PORT_DIPSETTING( 0x10, DEF_STR( 4C_3C ) )
462 PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
463 PORT_DIPSETTING( 0x30, DEF_STR( 3C_4C ) )
464 PORT_DIPSETTING( 0x70, DEF_STR( 2C_3C ) )
465 PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
466 PORT_DIPSETTING( 0x60, DEF_STR( 2C_5C ) )
467 PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
468 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
469 PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
470 PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
471 PORT_DIPSETTING( 0x90, DEF_STR( 1C_7C ) )
472 /* 0x00 is invalid */
473
474 PORT_START /* DSW1 */
475 PORT_DIPNAME( 0x03, 0x02, DEF_STR( Lives ) )
476 PORT_DIPSETTING( 0x03, "2" )
477 PORT_DIPSETTING( 0x02, "3" )
478 PORT_DIPSETTING( 0x01, "5" )
479 PORT_DIPSETTING( 0x00, "7" )
480 PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) )
481 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
482 PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
483 PORT_DIPNAME( 0x18, 0x18, DEF_STR( Bonus_Life ) )
484 PORT_DIPSETTING( 0x18, "20000 and every 60000" )
485 PORT_DIPSETTING( 0x10, "30000 and every 70000" )
486 PORT_DIPSETTING( 0x08, "40000 and every 80000" )
487 PORT_DIPSETTING( 0x00, "50000 and every 90000" )
488 PORT_DIPNAME( 0x60, 0x60, DEF_STR( Difficulty ) )
489 PORT_DIPSETTING( 0x60, "Easy" )
490 PORT_DIPSETTING( 0x40, "Medium" )
491 PORT_DIPSETTING( 0x20, "Hard" )
492 PORT_DIPSETTING( 0x00, "Hardest" )
493 PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) )
494 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
495 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
496
497 PORT_START /* DSW2 */
498 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) )
499 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
500 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
501 PORT_DIPNAME( 0x02, 0x02, "Controls" )
502 PORT_DIPSETTING( 0x02, "Single" )
503 PORT_DIPSETTING( 0x00, "Dual" )
504 PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
505 PORT_DIPNAME( 0x08, 0x08, DEF_STR ( Unknown ) )
506 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
507 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
508 PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
509 INPUT_PORTS_END
510
511
512
513 static struct GfxLayout charlayout =
514 {
515 8,8, /* 8*8 characters */
516 512, /* 512 characters */
517 4, /* 4 bits per pixel */
518 { 0, 1, 2, 3 }, /* the four bitplanes are packed in one nibble */
519 { 0*4, 1*4, 2*4, 3*4, 4*4, 5*4, 6*4, 7*4 },
520 { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 },
521 32*8 /* every char takes 8 consecutive bytes */
522 };
523
524 static struct GfxLayout spritelayout =
525 {
526 16,16, /* 16*16 sprites */
527 512, /* 512 sprites */
528 4, /* 4 bits per pixel */
529 { 0, 1, 2, 3 }, /* the four bitplanes are packed in one nibble */
530 { 0*4, 1*4, 2*4, 3*4, 4*4, 5*4, 6*4, 7*4,
531 32*8+0*4, 32*8+1*4, 32*8+2*4, 32*8+3*4, 32*8+4*4, 32*8+5*4, 32*8+6*4, 32*8+7*4 },
532 { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32,
533 64*8+0*32, 64*8+1*32, 64*8+2*32, 64*8+3*32, 64*8+4*32, 64*8+5*32, 64*8+6*32, 64*8+7*32 },
534 128*8 /* every sprite takes 128 consecutive bytes */
535 };
536
537 static struct GfxLayout gberetb_charlayout =
538 {
539 8,8, /* 8*8 characters */
540 512, /* 512 characters */
541 4, /* 4 bits per pixel */
542 { 0, 1, 2, 3 }, /* the four bitplanes are packed in one nibble */
543 { 6*4, 7*4, 0*4, 1*4, 2*4, 3*4, 4*4, 5*4 },
544 { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 },
545 32*8 /* every char takes 8 consecutive bytes */
546 };
547
548 static struct GfxLayout gberetb_spritelayout =
549 {
550 16,16, /* 16*16 sprites */
551 512, /* 512 sprites */
552 4, /* 4 bits per pixel */
553 { 0*0x4000*8, 1*0x4000*8, 2*0x4000*8, 3*0x4000*8 },
554 { 0, 1, 2, 3, 4, 5, 6, 7,
555 16*8+0, 16*8+1, 16*8+2, 16*8+3, 16*8+4, 16*8+5, 16*8+6, 16*8+7 },
556 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
557 8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8 },
558 32*8 /* every sprite takes 32 consecutive bytes */
559 };
560
561
562 static struct GfxDecodeInfo gfxdecodeinfo[] =
563 {
564 { REGION_GFX1, 0, &charlayout, 0, 16 },
565 { REGION_GFX2, 0, &spritelayout, 16*16, 16 },
566 { -1 } /* end of array */
567 };
568
569 static struct GfxDecodeInfo gberetb_gfxdecodeinfo[] =
570 {
571 { REGION_GFX1, 0, &gberetb_charlayout, 0, 16 },
572 { REGION_GFX2, 0, &gberetb_spritelayout, 16*16, 16 },
573 { -1 } /* end of array */
574 };
575
576
577
578 static struct SN76496interface sn76496_interface =
579 {
580 1, /* 1 chip */
581 { 18432000/12 }, /* 2H (generated by a custom IC) */
582 { 100 }
583 };
584
585
586
587 static struct MachineDriver machine_driver_gberet =
588 {
589 /* basic machine hardware */
590 {
591 {
592 CPU_Z80,
593 18432000/6, /* X1S (generated by a custom IC) */
594 readmem,writemem,0,0,
595 gberet_interrupt,32 /* 1 IRQ + 16 NMI (generated by a custom IC) */
596 }
597 },
598 30, DEFAULT_30HZ_VBLANK_DURATION, /* frames per second, vblank duration */
599 1, /* single CPU, no need for interleaving */
600 0,
601
602 /* video hardware */
603 32*8, 32*8, { 1*8, 31*8-1, 2*8, 30*8-1 },
604 gfxdecodeinfo,
605 32,2*16*16,
606 gberet_vh_convert_color_prom,
607
608 VIDEO_TYPE_RASTER,
609 0,
610 gberet_vh_start,
611 0,
612 gberet_vh_screenrefresh,
613
614 /* sound hardware */
615 0,0,0,0,
616 {
617 {
618 SOUND_SN76496,
619 &sn76496_interface
620 }
621 }
622 };
623
624 static struct MachineDriver machine_driver_gberetb =
625 {
626 /* basic machine hardware */
627 {
628 {
629 CPU_Z80,
630 3072000, /* 3.072 MHz ?? */
631 readmem,gberetb_writemem,0,0,
632 gberet_interrupt,16 /* 1 IRQ + 8 NMI */
633 }
634 },
635 60, DEFAULT_60HZ_VBLANK_DURATION, /* frames per second, vblank duration */
636 1, /* single CPU, no need for interleaving */
637 0,
638
639 /* video hardware */
640 32*8, 32*8, { 1*8, 31*8-1, 2*8, 30*8-1 },
641 gberetb_gfxdecodeinfo,
642 32,2*16*16,
643 gberet_vh_convert_color_prom,
644
645 VIDEO_TYPE_RASTER,
646 0,
647 gberet_vh_start,
648 0,
649 gberet_vh_screenrefresh,
650
651 /* sound hardware */
652 0,0,0,0,
653 {
654 {
655 SOUND_SN76496,
656 &sn76496_interface
657 }
658 }
659 };
660
661 static struct MachineDriver machine_driver_mrgoemon =
662 {
663 /* basic machine hardware */
664 {
665 {
666 CPU_Z80,
667 18432000/6, /* X1S (generated by a custom IC) */
668 mrgoemon_readmem,mrgoemon_writemem,0,0,
669 gberet_interrupt,16 /* 1 IRQ + 8 NMI */
670 }
671 },
672 60, DEFAULT_60HZ_VBLANK_DURATION, /* frames per second, vblank duration */
673 1, /* single CPU, no need for interleaving */
674 0,
675
676 /* video hardware */
677 32*8, 32*8, { 1*8, 31*8-1, 2*8, 30*8-1 },
678 gfxdecodeinfo,
679 32,2*16*16,
680 gberet_vh_convert_color_prom,
681
682 VIDEO_TYPE_RASTER,
683 0,
684 gberet_vh_start,
685 0,
686 gberet_vh_screenrefresh,
687
688 /* sound hardware */
689 0,0,0,0,
690 {
691 {
692 SOUND_SN76496,
693 &sn76496_interface
694 }
695 }
696 };
697
698
699
700 /***************************************************************************
701
702 Game driver(s)
703
704 ***************************************************************************/
705
706 ROM_START( gberet )
707 ROM_REGION( 0x10000, REGION_CPU1 ) /* 64k for code */
708 ROM_LOAD( "c10_l03.bin", 0x0000, 0x4000, 0xae29e4ff )
709 ROM_LOAD( "c08_l02.bin", 0x4000, 0x4000, 0x240836a5 )
710 ROM_LOAD( "c07_l01.bin", 0x8000, 0x4000, 0x41fa3e1f )
711
712 ROM_REGION( 0x04000, REGION_GFX1 | REGIONFLAG_DISPOSE )
713 ROM_LOAD( "f03_l07.bin", 0x00000, 0x4000, 0x4da7bd1b )
714
715 ROM_REGION( 0x10000, REGION_GFX2 | REGIONFLAG_DISPOSE )
716 ROM_LOAD( "e05_l06.bin", 0x00000, 0x4000, 0x0f1cb0ca )
717 ROM_LOAD( "e04_l05.bin", 0x04000, 0x4000, 0x523a8b66 )
718 ROM_LOAD( "f04_l08.bin", 0x08000, 0x4000, 0x883933a4 )
719 ROM_LOAD( "e03_l04.bin", 0x0c000, 0x4000, 0xccecda4c )
720
721 ROM_REGION( 0x0220, REGION_PROMS )
722 ROM_LOAD( "577h09", 0x0000, 0x0020, 0xc15e7c80 ) /* palette */
723 ROM_LOAD( "577h10", 0x0020, 0x0100, 0xe9de1e53 ) /* sprites */
724 ROM_LOAD( "577h11", 0x0120, 0x0100, 0x2a1a992b ) /* characters */
725 ROM_END
726
727 ROM_START( rushatck )
728 ROM_REGION( 0x10000, REGION_CPU1 ) /* 64k for code */
729 ROM_LOAD( "rush_h03.10c", 0x0000, 0x4000, 0x4d276b52 )
730 ROM_LOAD( "rush_h02.8c", 0x4000, 0x4000, 0xb5802806 )
731 ROM_LOAD( "rush_h01.7c", 0x8000, 0x4000, 0xda7c8f3d )
732
733 ROM_REGION( 0x04000, REGION_GFX1 | REGIONFLAG_DISPOSE )
734 ROM_LOAD( "rush_h07.3f", 0x00000, 0x4000, 0x03f9815f )
735
736 ROM_REGION( 0x10000, REGION_GFX2 | REGIONFLAG_DISPOSE )
737 ROM_LOAD( "e05_l06.bin", 0x00000, 0x4000, 0x0f1cb0ca )
738 ROM_LOAD( "rush_h05.4e", 0x04000, 0x4000, 0x9d028e8f )
739 ROM_LOAD( "f04_l08.bin", 0x08000, 0x4000, 0x883933a4 )
740 ROM_LOAD( "e03_l04.bin", 0x0c000, 0x4000, 0xccecda4c )
741
742 ROM_REGION( 0x0220, REGION_PROMS )
743 ROM_LOAD( "577h09", 0x0000, 0x0020, 0xc15e7c80 ) /* palette */
744 ROM_LOAD( "577h10", 0x0020, 0x0100, 0xe9de1e53 ) /* sprites */
745 ROM_LOAD( "577h11", 0x0120, 0x0100, 0x2a1a992b ) /* characters */
746 ROM_END
747
748 ROM_START( gberetb )
749 ROM_REGION( 0x10000, REGION_CPU1 ) /* 64k for code */
750 ROM_LOAD( "2-ic82.10g", 0x0000, 0x8000, 0x6d6fb494 )
751 ROM_LOAD( "3-ic81.10f", 0x8000, 0x4000, 0xf1520a0a )
752
753 ROM_REGION( 0x04000, REGION_GFX1 | REGIONFLAG_DISPOSE )
754 ROM_LOAD( "1-ic92.12c", 0x00000, 0x4000, 0xb0189c87 )
755
756 ROM_REGION( 0x10000, REGION_GFX2 | REGIONFLAG_DISPOSE )
757 ROM_LOAD( "7-1c8.2b", 0x00000, 0x4000, 0x86334522 )
758 ROM_LOAD( "6-ic9.2c", 0x04000, 0x4000, 0xbda50d3e )
759 ROM_LOAD( "5-ic10.2d", 0x08000, 0x4000, 0x6a7b3881 )
760 ROM_LOAD( "4-ic11.2e", 0x0c000, 0x4000, 0x3fb186c9 )
761
762 ROM_REGION( 0x0220, REGION_PROMS )
763 ROM_LOAD( "577h09", 0x0000, 0x0020, 0xc15e7c80 ) /* palette */
764 ROM_LOAD( "577h10", 0x0020, 0x0100, 0xe9de1e53 ) /* sprites */
765 ROM_LOAD( "577h11", 0x0120, 0x0100, 0x2a1a992b ) /* characters */
766 ROM_END
767
768 ROM_START( mrgoemon )
769 ROM_REGION( 0x14000, REGION_CPU1 ) /* 64k for code + banked ROM */
770 ROM_LOAD( "621d01.10c", 0x00000, 0x8000, 0xb2219c56 )
771 ROM_LOAD( "621d02.12c", 0x08000, 0x4000, 0xc3337a97 )
772 ROM_CONTINUE( 0x10000, 0x4000 )
773
774 ROM_REGION( 0x04000, REGION_GFX1 | REGIONFLAG_DISPOSE )
775 ROM_LOAD( "621a05.6d", 0x00000, 0x4000, 0xf0a6dfc5 )
776
777 ROM_REGION( 0x10000, REGION_GFX2 | REGIONFLAG_DISPOSE )
778 ROM_LOAD( "621d03.4d", 0x00000, 0x8000, 0x66f2b973 )
779 ROM_LOAD( "621d04.5d", 0x08000, 0x8000, 0x47df6301 )
780
781 ROM_REGION( 0x0220, REGION_PROMS )
782 ROM_LOAD( "621a06.5f", 0x0000, 0x0020, 0x7c90de5f ) /* palette */
783 ROM_LOAD( "621a07.6f", 0x0020, 0x0100, 0x3980acdc ) /* sprites */
784 ROM_LOAD( "621a08.7f", 0x0120, 0x0100, 0x2fb244dd ) /* characters */
785 ROM_END
786
787
788
789 GAME( 1985, gberet, 0, gberet, gberet, gberet, ROT0, "Konami", "Green Beret" )
790 GAME( 1985, rushatck, gberet, gberet, gberet, gberet, ROT0, "Konami", "Rush'n Attack" )
791 GAME( 1985, gberetb, gberet, gberetb, gberetb, gberetb, ROT0, "bootleg", "Green Beret (bootleg)" )
792 GAME( 1986, mrgoemon, 0, mrgoemon, mrgoemon, gberet, ROT0, "Konami", "Mr. Goemon (Japan)" )
793
794