1 #include "../vidhrdw/shisen.c"
2
3 /***************************************************************************
4
5 Shisen
6
7 driver by Nicola Salmoria
8
9 ***************************************************************************/
10 #include "driver.h"
11 #include "vidhrdw/generic.h"
12 #include "sndhrdw/m72.h"
13
14 /* in vidhrdw/sichuan2.c */
15 WRITE_HANDLER( sichuan2_bankswitch_w );
16 WRITE_HANDLER( sichuan2_paletteram_w );
17 void sichuan2_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
18
19
20
READ_HANDLER(sichuan2_dsw1_r)21 static READ_HANDLER( sichuan2_dsw1_r )
22 {
23 int ret = input_port_3_r(0);
24
25 /* Based on the coin mode fill in the upper bits */
26 if (input_port_4_r(0) & 0x04)
27 {
28 /* Mode 1 */
29 ret |= (input_port_5_r(0) << 4);
30 }
31 else
32 {
33 /* Mode 2 */
34 ret |= (input_port_5_r(0) & 0xf0);
35 }
36
37 return ret;
38 }
39
WRITE_HANDLER(sichuan2_coin_w)40 static WRITE_HANDLER( sichuan2_coin_w )
41 {
42 //if ((data & 0xf9) != 0x01) logerror("coin ctrl = %02x\n",data);
43
44 coin_counter_w(0,data & 2);
45 coin_counter_w(1,data & 4);
46 }
47
48
49
50 static struct MemoryReadAddress readmem[] =
51 {
52 { 0x0000, 0x7fff, MRA_ROM },
53 { 0x8000, 0xbfff, MRA_BANK1 },
54 { 0xc800, 0xcaff, MRA_RAM },
55 { 0xd000, 0xffff, MRA_RAM },
56 { -1 } /* end of table */
57 };
58
59 static struct MemoryWriteAddress writemem[] =
60 {
61 { 0x0000, 0xbfff, MWA_ROM },
62 { 0xc800, 0xcaff, sichuan2_paletteram_w, &paletteram },
63 { 0xd000, 0xdfff, videoram_w, &videoram, &videoram_size },
64 { 0xe000, 0xffff, MWA_RAM },
65 { -1 } /* end of table */
66 };
67
68 static struct IOReadPort readport[] =
69 {
70 { 0x00, 0x00, sichuan2_dsw1_r },
71 { 0x01, 0x01, input_port_4_r },
72 { 0x02, 0x02, input_port_0_r },
73 { 0x03, 0x03, input_port_1_r },
74 { 0x04, 0x04, input_port_2_r },
75 { -1 } /* end of table */
76 };
77
78 static struct IOWritePort writeport[] =
79 {
80 { 0x00, 0x00, sichuan2_coin_w },
81 { 0x01, 0x01, m72_sound_command_w },
82 { 0x02, 0x02, sichuan2_bankswitch_w },
83 { -1 } /* end of table */
84 };
85
86 static struct MemoryReadAddress sound_readmem[] =
87 {
88 { 0x0000, 0x3fff, MRA_ROM },
89 { 0xfd00, 0xffff, MRA_RAM },
90 { -1 } /* end of table */
91 };
92
93 static struct MemoryWriteAddress sound_writemem[] =
94 {
95 { 0x0000, 0x3fff, MWA_ROM },
96 { 0xfd00, 0xffff, MWA_RAM },
97 { -1 } /* end of table */
98 };
99
100 static struct IOReadPort sound_readport[] =
101 {
102 { 0x01, 0x01, YM2151_status_port_0_r },
103 { 0x80, 0x80, soundlatch_r },
104 { 0x84, 0x84, m72_sample_r },
105 { -1 } /* end of table */
106 };
107
108 static struct IOWritePort sound_writeport[] =
109 {
110 { 0x00, 0x00, YM2151_register_port_0_w },
111 { 0x01, 0x01, YM2151_data_port_0_w },
112 { 0x80, 0x81, shisen_sample_addr_w },
113 { 0x82, 0x82, m72_sample_w },
114 { 0x83, 0x83, m72_sound_irq_ack_w },
115 { -1 } /* end of table */
116 };
117
118
119
120 INPUT_PORTS_START( shisen )
121 PORT_START /* IN0 */
122 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
123 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
124 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
125 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
126 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
127 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
128 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
129 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
130
131 PORT_START /* IN1 */
132 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
133 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
134 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
135 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
136 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
137 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_COCKTAIL )
138 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_COCKTAIL )
139 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
140
141 PORT_START /* COIN */
142 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
143 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
144 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
145 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
146 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN3 )
147 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
148 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
149 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
150
151 PORT_START /* DSW1 */
152 PORT_DIPNAME( 0x03, 0x03, "Timer" )
153 PORT_DIPSETTING( 0x03, "1" )
154 PORT_DIPSETTING( 0x02, "2" )
155 PORT_DIPSETTING( 0x01, "3" )
156 PORT_DIPSETTING( 0x00, "4" )
157 PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Difficulty ) )
158 PORT_DIPSETTING( 0x0c, "1" )
159 PORT_DIPSETTING( 0x08, "2" )
160 PORT_DIPSETTING( 0x04, "3" )
161 PORT_DIPSETTING( 0x00, "4" )
162 PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNUSED ) /* Gets filled in based on the coin mode */
163
164 PORT_START /* DSW2 */
165 PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ) )
166 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
167 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
168 PORT_DIPNAME( 0x02, 0x00, DEF_STR( Demo_Sounds ) )
169 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
170 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
171 PORT_DIPNAME( 0x04, 0x04, "Coin Mode" )
172 PORT_DIPSETTING( 0x04, "Mode 1" )
173 PORT_DIPSETTING( 0x00, "Mode 2" )
174 PORT_DIPNAME( 0x08, 0x08, "Naughty Pics" )
175 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
176 PORT_DIPSETTING( 0x08, DEF_STR( On ) )
177 PORT_DIPNAME( 0x10, 0x10, "Gal Select" )
178 PORT_DIPSETTING( 0x00, DEF_STR( No ) )
179 PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
180 /* In stop mode, press 2 to stop and 1 to restart */
181 PORT_BITX ( 0x20, 0x20, IPT_DIPSWITCH_NAME | IPF_CHEAT, "Stop Mode", IP_KEY_NONE, IP_JOY_NONE )
182 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
183 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
184 PORT_DIPNAME( 0x40, 0x40, "Max Players" )
185 PORT_DIPSETTING( 0x00, "1" )
186 PORT_DIPSETTING( 0x40, "2" )
187 PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
188
189 /* Fake port to support the two different coin modes */
190 PORT_START
191 PORT_DIPNAME( 0x0f, 0x0f, "Coinage Mode 1" ) /* mapped on coin mode 1 */
192 PORT_DIPSETTING( 0x0a, DEF_STR( 6C_1C ) )
193 PORT_DIPSETTING( 0x0b, DEF_STR( 5C_1C ) )
194 PORT_DIPSETTING( 0x0c, DEF_STR( 4C_1C ) )
195 PORT_DIPSETTING( 0x0d, DEF_STR( 3C_1C ) )
196 PORT_DIPSETTING( 0x01, DEF_STR( 8C_3C ) )
197 PORT_DIPSETTING( 0x0e, DEF_STR( 2C_1C ) )
198 PORT_DIPSETTING( 0x02, DEF_STR( 5C_3C ) )
199 PORT_DIPSETTING( 0x03, DEF_STR( 3C_2C ) )
200 PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
201 PORT_DIPSETTING( 0x04, DEF_STR( 2C_3C ) )
202 PORT_DIPSETTING( 0x09, DEF_STR( 1C_2C ) )
203 PORT_DIPSETTING( 0x08, DEF_STR( 1C_3C ) )
204 PORT_DIPSETTING( 0x07, DEF_STR( 1C_4C ) )
205 PORT_DIPSETTING( 0x06, DEF_STR( 1C_5C ) )
206 PORT_DIPSETTING( 0x05, DEF_STR( 1C_6C ) )
207 PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
208 PORT_DIPNAME( 0x30, 0x30, "Coin A Mode 2" ) /* mapped on coin mode 2 */
209 PORT_DIPSETTING( 0x00, DEF_STR( 5C_1C ) )
210 PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) )
211 PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) )
212 PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
213 PORT_DIPNAME( 0xc0, 0xc0, "Coin B Mode 2" )
214 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_2C ) )
215 PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) )
216 PORT_DIPSETTING( 0x40, DEF_STR( 1C_5C ) )
217 PORT_DIPSETTING( 0x00, DEF_STR( 1C_6C ) )
218 INPUT_PORTS_END
219
220
221
222 static struct GfxLayout charlayout =
223 {
224 8,8,
225 4096*8,
226 4,
227 { 0, 4, 0x80000*8+0, 0x80000*8+4 },
228 { 0, 1, 2, 3, 8*8+0, 8*8+1, 8*8+2, 8*8+3 },
229 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
230 16*8
231 };
232
233
234 static struct GfxDecodeInfo gfxdecodeinfo[] =
235 {
236 { REGION_GFX1, 0x00000, &charlayout, 0, 16 },
237 { -1 } /* end of array */
238 };
239
240
241
242 static struct YM2151interface ym2151_interface =
243 {
244 1, /* 1 chip */
245 3579645, /* 3.579645 MHz */
246 { YM3012_VOL(100,MIXER_PAN_LEFT,100,MIXER_PAN_RIGHT) },
247 { m72_ym2151_irq_handler },
248 { 0 }
249 };
250
251 static struct DACinterface dac_interface =
252 {
253 1, /* 1 channel */
254 { 50 }
255 };
256
257
258
259 static struct MachineDriver machine_driver_shisen =
260 {
261 /* basic machine hardware */
262 {
263 {
264 CPU_Z80,
265 6000000, /* 6 Mhz ? */
266 readmem,writemem,readport,writeport,
267 interrupt,1
268 },
269 {
270 CPU_Z80 | CPU_AUDIO_CPU,
271 3579645, /* 3.579645 MHz? (Vigilante) */
272 sound_readmem,sound_writemem,sound_readport,sound_writeport,
273 nmi_interrupt,128 /* clocked by V1? (Vigilante) */
274 /* IRQs are generated by main Z80 and YM2151 */
275 }
276 },
277 55, DEFAULT_60HZ_VBLANK_DURATION, /* frames per second, vblank duration */
278 1, /* 1 CPU slice per frame - interleaving is forced when a sound command is written */ \
279 m72_init_sound,
280
281 /* video hardware */
282 64*8, 32*8, { 0*8, 64*8-1, 0*8, 32*8-1 },
283 gfxdecodeinfo,
284 256, 256,
285 0,
286
287 VIDEO_TYPE_RASTER|VIDEO_MODIFIES_PALETTE|VIDEO_SUPPORTS_DIRTY|VIDEO_PIXEL_ASPECT_RATIO_1_2,
288 0,
289 generic_vh_start,
290 generic_vh_stop,
291 sichuan2_vh_screenrefresh,
292
293 /* sound hardware */
294 SOUND_SUPPORTS_STEREO,0,0,0,
295 {
296 {
297 SOUND_YM2151,
298 &ym2151_interface
299 },
300 {
301 SOUND_DAC,
302 &dac_interface
303 }
304 }
305 };
306
307
308
309 /***************************************************************************
310
311 Game driver(s)
312
313 ***************************************************************************/
314
315 ROM_START( sichuan2 )
316 ROM_REGION( 0x30000, REGION_CPU1 ) /* 64k+128k for main CPU */
317 ROM_LOAD( "ic06.06", 0x00000, 0x10000, 0x98a2459b )
318 ROM_RELOAD( 0x10000, 0x10000 )
319 ROM_LOAD( "ic07.03", 0x20000, 0x10000, 0x0350f6e2 )
320
321 ROM_REGION( 0x10000, REGION_CPU2 ) /* 64k for the audio CPU */
322 ROM_LOAD( "ic01.01", 0x00000, 0x10000, 0x51b0a26c )
323
324 ROM_REGION( 0x100000, REGION_GFX1 | REGIONFLAG_DISPOSE )
325 ROM_LOAD( "ic08.04", 0x00000, 0x10000, 0x1c0e221c )
326 ROM_LOAD( "ic09.05", 0x10000, 0x10000, 0x8a7d8284 )
327 ROM_LOAD( "ic12.08", 0x20000, 0x10000, 0x48e1d043 )
328 ROM_LOAD( "ic13.09", 0x30000, 0x10000, 0x3feff3f2 )
329 ROM_LOAD( "ic14.10", 0x40000, 0x10000, 0xb76a517d )
330 ROM_LOAD( "ic15.11", 0x50000, 0x10000, 0x8ff5ee7a )
331 ROM_LOAD( "ic16.12", 0x60000, 0x10000, 0x64e5d837 )
332 ROM_LOAD( "ic17.13", 0x70000, 0x10000, 0x02c1b2c4 )
333 ROM_LOAD( "ic18.14", 0x80000, 0x10000, 0xf5a8370e )
334 ROM_LOAD( "ic19.15", 0x90000, 0x10000, 0x7a9b7671 )
335 ROM_LOAD( "ic20.16", 0xa0000, 0x10000, 0x7fb396ad )
336 ROM_LOAD( "ic21.17", 0xb0000, 0x10000, 0xfb83c652 )
337 ROM_LOAD( "ic22.18", 0xc0000, 0x10000, 0xd8b689e9 )
338 ROM_LOAD( "ic23.19", 0xd0000, 0x10000, 0xe6611947 )
339 ROM_LOAD( "ic10.06", 0xe0000, 0x10000, 0x473b349a )
340 ROM_LOAD( "ic11.07", 0xf0000, 0x10000, 0xd9a60285 )
341
342 ROM_REGION( 0x40000, REGION_SOUND1 ) /* samples */
343 ROM_LOAD( "ic02.02", 0x00000, 0x10000, 0x92f0093d )
344 ROM_LOAD( "ic03.03", 0x10000, 0x10000, 0x116a049c )
345 ROM_LOAD( "ic04.04", 0x20000, 0x10000, 0x6840692b )
346 ROM_LOAD( "ic05.05", 0x30000, 0x10000, 0x92ffe22a )
347 ROM_END
348
349 ROM_START( sichuana )
350 ROM_REGION( 0x30000, REGION_CPU1 ) /* 64k+128k for main CPU */
351 ROM_LOAD( "sichuan.a6", 0x00000, 0x10000, 0xf8ac05ef )
352 ROM_RELOAD( 0x10000, 0x10000 )
353 ROM_LOAD( "ic07.03", 0x20000, 0x10000, 0x0350f6e2 )
354
355 ROM_REGION( 0x10000, REGION_CPU2 ) /* 64k for the audio CPU */
356 ROM_LOAD( "ic01.01", 0x00000, 0x10000, 0x51b0a26c )
357
358 ROM_REGION( 0x100000, REGION_GFX1 | REGIONFLAG_DISPOSE )
359 ROM_LOAD( "ic08.04", 0x00000, 0x10000, 0x1c0e221c )
360 ROM_LOAD( "ic09.05", 0x10000, 0x10000, 0x8a7d8284 )
361 ROM_LOAD( "ic12.08", 0x20000, 0x10000, 0x48e1d043 )
362 ROM_LOAD( "ic13.09", 0x30000, 0x10000, 0x3feff3f2 )
363 ROM_LOAD( "ic14.10", 0x40000, 0x10000, 0xb76a517d )
364 ROM_LOAD( "ic15.11", 0x50000, 0x10000, 0x8ff5ee7a )
365 ROM_LOAD( "ic16.12", 0x60000, 0x10000, 0x64e5d837 )
366 ROM_LOAD( "ic17.13", 0x70000, 0x10000, 0x02c1b2c4 )
367 ROM_LOAD( "ic18.14", 0x80000, 0x10000, 0xf5a8370e )
368 ROM_LOAD( "ic19.15", 0x90000, 0x10000, 0x7a9b7671 )
369 ROM_LOAD( "ic20.16", 0xa0000, 0x10000, 0x7fb396ad )
370 ROM_LOAD( "ic21.17", 0xb0000, 0x10000, 0xfb83c652 )
371 ROM_LOAD( "ic22.18", 0xc0000, 0x10000, 0xd8b689e9 )
372 ROM_LOAD( "ic23.19", 0xd0000, 0x10000, 0xe6611947 )
373 ROM_LOAD( "ic10.06", 0xe0000, 0x10000, 0x473b349a )
374 ROM_LOAD( "ic11.07", 0xf0000, 0x10000, 0xd9a60285 )
375
376 ROM_REGION( 0x40000, REGION_SOUND1 ) /* samples */
377 ROM_LOAD( "ic02.02", 0x00000, 0x10000, 0x92f0093d )
378 ROM_LOAD( "ic03.03", 0x10000, 0x10000, 0x116a049c )
379 ROM_LOAD( "ic04.04", 0x20000, 0x10000, 0x6840692b )
380 ROM_LOAD( "ic05.05", 0x30000, 0x10000, 0x92ffe22a )
381 ROM_END
382
383 ROM_START( shisen )
384 ROM_REGION( 0x30000, REGION_CPU1 ) /* 64k+128k for main CPU */
385 ROM_LOAD( "a-27-a.rom", 0x00000, 0x20000, 0xde2ecf05 )
386 ROM_RELOAD( 0x10000, 0x20000 )
387
388 ROM_REGION( 0x10000, REGION_CPU2 ) /* 64k for the audio CPU */
389 ROM_LOAD( "ic01.01", 0x00000, 0x10000, 0x51b0a26c )
390
391 ROM_REGION( 0x100000, REGION_GFX1 | REGIONFLAG_DISPOSE )
392 ROM_LOAD( "ic08.04", 0x00000, 0x10000, 0x1c0e221c )
393 ROM_LOAD( "ic09.05", 0x10000, 0x10000, 0x8a7d8284 )
394 ROM_LOAD( "ic12.08", 0x20000, 0x10000, 0x48e1d043 )
395 ROM_LOAD( "ic13.09", 0x30000, 0x10000, 0x3feff3f2 )
396 ROM_LOAD( "ic14.10", 0x40000, 0x10000, 0xb76a517d )
397 ROM_LOAD( "ic15.11", 0x50000, 0x10000, 0x8ff5ee7a )
398 ROM_LOAD( "ic16.12", 0x60000, 0x10000, 0x64e5d837 )
399 ROM_LOAD( "ic17.13", 0x70000, 0x10000, 0x02c1b2c4 )
400 ROM_LOAD( "ic18.14", 0x80000, 0x10000, 0xf5a8370e )
401 ROM_LOAD( "ic19.15", 0x90000, 0x10000, 0x7a9b7671 )
402 ROM_LOAD( "ic20.16", 0xa0000, 0x10000, 0x7fb396ad )
403 ROM_LOAD( "ic21.17", 0xb0000, 0x10000, 0xfb83c652 )
404 ROM_LOAD( "ic22.18", 0xc0000, 0x10000, 0xd8b689e9 )
405 ROM_LOAD( "ic23.19", 0xd0000, 0x10000, 0xe6611947 )
406 ROM_LOAD( "ic10.06", 0xe0000, 0x10000, 0x473b349a )
407 ROM_LOAD( "ic11.07", 0xf0000, 0x10000, 0xd9a60285 )
408
409 ROM_REGION( 0x40000, REGION_SOUND1 ) /* samples */
410 ROM_LOAD( "ic02.02", 0x00000, 0x10000, 0x92f0093d )
411 ROM_LOAD( "ic03.03", 0x10000, 0x10000, 0x116a049c )
412 ROM_LOAD( "ic04.04", 0x20000, 0x10000, 0x6840692b )
413 ROM_LOAD( "ic05.05", 0x30000, 0x10000, 0x92ffe22a )
414 ROM_END
415
416
417
418 GAME( 1989, sichuan2, 0, shisen, shisen, 0, ROT0, "Tamtex", "Sichuan II (hack?) (set 1)" )
419 GAME( 1989, sichuana, sichuan2, shisen, shisen, 0, ROT0, "Tamtex", "Sichuan II (hack ?) (set 2)" )
420 GAME( 1989, shisen, sichuan2, shisen, shisen, 0, ROT0, "Tamtex", "Shisensho - Joshiryo-Hen (Japan)" )
421