1 #ifndef E132XS_H 2 #define E132XS_H 3 4 /* Functions */ 5 extern void e132xs_init(void); 6 extern void e132xs_reset(void *param); 7 extern void e132xs_exit(void); 8 extern int e132xs_execute(int cycles); 9 extern unsigned e132xs_get_context(void *regs); 10 extern void e132xs_set_context(void *regs); 11 extern unsigned e132xs_get_reg(int regnum); 12 extern void e132xs_set_reg(int regnum, unsigned val); 13 extern void e132xs_set_irq_line(int irqline, int state); 14 extern void e132xs_set_irq_callback(int (*callback)(int irqline)); 15 extern const char *e132xs_info(void *context, int regnum); 16 extern unsigned e132xs_dasm(char *buffer, unsigned pc); 17 18 #ifdef MAME_DEBUG 19 extern unsigned dasm_e132xs(char *buffer, unsigned pc); 20 #endif 21 22 23 /* Variables */ 24 extern int e132xs_ICount; 25 26 /* read byte */ 27 #define READ_B(addr) (cpu_readmem32bedw(addr)) 28 /* read half-word */ 29 #define READ_HW(addr) (cpu_readmem32bedw_word(addr)) 30 /* read word */ 31 #define READ_W(addr) (cpu_readmem32bedw_dword(addr)) 32 33 /* write byte */ 34 #define WRITE_B(addr, val) (cpu_writemem32bedw(addr, val)) 35 /* write half-word */ 36 #define WRITE_HW(addr, val) (cpu_writemem32bedw_word(addr, val)) 37 /* write word */ 38 #define WRITE_W(addr, val) (cpu_writemem32bedw_dword(addr, val)) 39 40 #define READ_OP(addr) READ_HW(addr) 41 //#define READ_OP(addr) (cpu_readop16(addr)) 42 43 44 #define PC_CODE 0 45 #define SR_CODE 1 46 47 #define X_CODE(val) ((val & 0x7000) >> 12) 48 #define E_BIT(val) ((val & 0x8000) >> 15) 49 #define S_BIT_CONST(val) ((val & 0x4000) >> 14) 50 #define DD(val) ((val & 0x3000) >> 12) 51 52 53 /* Extended DSP instructions */ 54 #define EMUL 0x102 55 #define EMULU 0x104 56 #define EMULS 0x106 57 #define EMAC 0x10a 58 #define EMACD 0x10e 59 #define EMSUB 0x11a 60 #define EMSUBD 0x11e 61 #define EHMAC 0x02a 62 #define EHMACD 0x02e 63 #define EHCMULD 0x046 64 #define EHCMACD 0x04e 65 #define EHCSUMD 0x086 66 #define EHCFFTD 0x096 67 #define EHCFFTSD 0x296 68 69 /* Delay values */ 70 #define NO_DELAY 0 71 #define DELAY_EXECUTE 1 72 #define DELAY_TAKEN 2 73 74 /* Trap numbers */ 75 #define IO2 48 76 #define IO1 49 77 #define INT4 50 78 #define INT3 51 79 #define INT2 52 80 #define INT1 53 81 #define IO3 54 82 #define TIMER 55 83 #define RESERVED1 56 84 #define TRACE_EXCEPTION 57 85 #define PARITY_ERROR 58 86 #define EXTENDED_OVERFLOW 59 87 #define RANGE_ERROR 60 88 #define PRIVILEGE_ERROR RANGE_ERROR 89 #define FRAME_ERROR RANGE_ERROR 90 #define RESERVED2 61 91 #define RESET 62 // reserved if not mapped @ MEM3 92 #define ERROR_ENTRY 63 // for instruction code of all ones 93 94 /* Traps code */ 95 #define TRAPLE 4 96 #define TRAPGT 5 97 #define TRAPLT 6 98 #define TRAPGE 7 99 #define TRAPSE 8 100 #define TRAPHT 9 101 #define TRAPST 10 102 #define TRAPHE 11 103 #define TRAPE 12 104 #define TRAPNE 13 105 #define TRAPV 14 106 #define TRAP 15 107 108 /* Entry point to get trap locations or emulated code associated */ 109 #define E132XS_ENTRY_MEM0 0 110 #define E132XS_ENTRY_MEM1 1 111 #define E132XS_ENTRY_MEM2 2 112 #define E132XS_ENTRY_MEM3 3 113 #define E132XS_ENTRY_IRAM 4 114 115 #endif /* E132XS_H */ 116