1 /*****************************************************************************
2 *
3 * tbl6510.c
4 * 6510 opcode functions and function pointer table
5 *
6 * Copyright (c) 1998,1999,2000 Juergen Buchmueller, all rights reserved.
7 *
8 * - This source code is released as freeware for non-commercial purposes.
9 * - You are free to use and redistribute this code in modified or
10 * unmodified form, provided you list me in the credits.
11 * - If you modify this source code, you must add a notice to each modified
12 * source file that it has been changed. If you're a nice person, you
13 * will clearly mark each change too. :)
14 * - If you wish to use this for commercial purposes, please contact me at
15 * pullmoll@t-online.de
16 * - The author of this copywritten work reserves the right to change the
17 * terms of its usage and license at any time, including retroactively
18 * - This entire notice must remain in the source code.
19 *
20 * - Opcode information based on an Intel 386 '6510.asm' core
21 * written by R.F. van Ee (1993)
22 * - Cycle counts are guesswork :-)
23 *
24 *****************************************************************************/
25 /*
26 PeT 11.August 2000
27 added NMOS rw opcodes address access behaviour
28 emulation of this currently NOT in NMOS 6502, N2A03, M6509
29 only done in the official opcodes
30 (inofficial are too hard to guess and test)
31 NMOS does rw opcodes
32 (inc 00) as read 00 into alu, write alu into 00, inc alu, write alu into 00
33 CMOS
34 (inc 00) as read 00 into alu, read alu into 00, inc alu, write alu into 00
35 needed in many C64,c16 games
36 c16 lone07 does asl ff09, 1st write cycles quits interrupt
37 */
38
39
40 #undef OP
41 #define OP(nn) static INLINE void m6510_##nn(void)
42
43 /*****************************************************************************
44 *****************************************************************************
45 *
46 * overrides for 6510 opcodes
47 *
48 *****************************************************************************
49 ********** insn temp cycles rdmem opc wrmem **********/
50 #define m6510_00 m6502_00 /* 7 BRK */
51 #define m6510_20 m6502_20 /* 6 JSR */
52 #define m6510_40 m6502_40 /* 6 RTI */
53 #define m6510_60 m6502_60 /* 6 RTS */
54 OP(80) { m6502_ICount -= 2; DOP; } /* 2 DOP */
55 #define m6510_a0 m6502_a0 /* 2 LDY IMM */
56 #define m6510_c0 m6502_c0 /* 2 CPY IMM */
57 #define m6510_e0 m6502_e0 /* 2 CPX IMM */
58
59 #define m6510_10 m6502_10 /* 2 BPL */
60 #define m6510_30 m6502_30 /* 2 BMI */
61 #define m6510_50 m6502_50 /* 2 BVC */
62 #define m6510_70 m6502_70 /* 2 BVS */
63 #define m6510_90 m6502_90 /* 2 BCC */
64 #define m6510_b0 m6502_b0 /* 2 BCS */
65 #define m6510_d0 m6502_d0 /* 2 BNE */
66 #define m6510_f0 m6502_f0 /* 2 BEQ */
67
68 #define m6510_01 m6502_01 /* 6 ORA IDX */
69 #define m6510_21 m6502_21 /* 6 AND IDX */
70 #define m6510_41 m6502_41 /* 6 EOR IDX */
71 #define m6510_61 m6502_61 /* 6 ADC IDX */
72 #define m6510_81 m6502_81 /* 6 STA IDX */
73 #define m6510_a1 m6502_a1 /* 6 LDA IDX */
74 #define m6510_c1 m6502_c1 /* 6 CMP IDX */
75 #define m6510_e1 m6502_e1 /* 6 SBC IDX */
76
77 #define m6510_11 m6502_11 /* 5 ORA IDY */
78 #define m6510_31 m6502_31 /* 5 AND IDY */
79 #define m6510_51 m6502_51 /* 5 EOR IDY */
80 #define m6510_71 m6502_71 /* 5 ADC IDY */
81 #define m6510_91 m6502_91 /* 6 STA IDY */
82 #define m6510_b1 m6502_b1 /* 5 LDA IDY */
83 #define m6510_d1 m6502_d1 /* 5 CMP IDY */
84 #define m6510_f1 m6502_f1 /* 5 SBC IDY */
85
86 OP(02) { m6502_ICount -= 2; KIL; } /* 2 KIL */
87 OP(22) { m6502_ICount -= 2; KIL; } /* 2 KIL */
88 OP(42) { m6502_ICount -= 2; KIL; } /* 2 KIL */
89 OP(62) { m6502_ICount -= 2; KIL; } /* 2 KIL */
90 OP(82) { m6502_ICount -= 2; DOP; } /* 2 DOP */
91 #define m6510_a2 m6502_a2 /* 2 LDX IMM */
OP(c2)92 OP(c2) { m6502_ICount -= 2; DOP; } /* 2 DOP */
OP(e2)93 OP(e2) { m6502_ICount -= 2; DOP; } /* 2 DOP */
94
95 OP(12) { m6502_ICount -= 2; KIL; } /* 2 KIL */
96 OP(32) { m6502_ICount -= 2; KIL; } /* 2 KIL */
97 OP(52) { m6502_ICount -= 2; KIL; } /* 2 KIL */
98 OP(72) { m6502_ICount -= 2; KIL; } /* 2 KIL */
99 OP(92) { m6502_ICount -= 2; KIL; } /* 2 KIL */
OP(b2)100 OP(b2) { m6502_ICount -= 2; KIL; } /* 2 KIL */
OP(d2)101 OP(d2) { m6502_ICount -= 2; KIL; } /* 2 KIL */
OP(f2)102 OP(f2) { m6502_ICount -= 2; KIL; } /* 2 KIL */
103
104 OP(03) { int tmp; m6502_ICount -= 7; RD_IDX; SLO; WB_EA; } /* 7 SLO IDX */
105 OP(23) { int tmp; m6502_ICount -= 7; RD_IDX; RLA; WB_EA; } /* 7 RLA IDX */
106 OP(43) { int tmp; m6502_ICount -= 7; RD_IDX; SRE; WB_EA; } /* 7 SRE IDX */
107 OP(63) { int tmp; m6502_ICount -= 7; RD_IDX; RRA; WB_EA; } /* 7 RRA IDX */
108 OP(83) { int tmp; m6502_ICount -= 6; SAX; WR_IDX; } /* 6 SAX IDX */
OP(a3)109 OP(a3) { int tmp; m6502_ICount -= 6; RD_IDX; LAX; } /* 6 LAX IDX */
OP(c3)110 OP(c3) { int tmp; m6502_ICount -= 7; RD_IDX; DCP; WB_EA; } /* 7 DCP IDX */
OP(e3)111 OP(e3) { int tmp; m6502_ICount -= 7; RD_IDX; ISB; WB_EA; } /* 7 ISB IDX */
112
113 OP(13) { int tmp; m6502_ICount -= 6; RD_IDY; SLO; WB_EA; } /* 6 SLO IDY */
114 OP(33) { int tmp; m6502_ICount -= 6; RD_IDY; RLA; WB_EA; } /* 6 RLA IDY */
115 OP(53) { int tmp; m6502_ICount -= 6; RD_IDY; SRE; WB_EA; } /* 6 SRE IDY */
116 OP(73) { int tmp; m6502_ICount -= 6; RD_IDY; RRA; WB_EA; } /* 6 RRA IDY */
117 OP(93) { int tmp; m6502_ICount -= 5; EA_IDY; SAH; WB_EA; } /* 5 SAH IDY */
OP(b3)118 OP(b3) { int tmp; m6502_ICount -= 5; RD_IDY; LAX; } /* 5 LAX IDY */
OP(d3)119 OP(d3) { int tmp; m6502_ICount -= 6; RD_IDY; DCP; WB_EA; } /* 6 DCP IDY */
OP(f3)120 OP(f3) { int tmp; m6502_ICount -= 6; RD_IDY; ISB; WB_EA; } /* 6 ISB IDY */
121
122 OP(04) { m6502_ICount -= 2; DOP; } /* 2 DOP */
123 #define m6510_24 m6502_24 /* 3 BIT ZPG */
124 OP(44) { m6502_ICount -= 2; DOP; } /* 2 DOP */
125 OP(64) { m6502_ICount -= 2; DOP; } /* 2 DOP */
126 #define m6510_84 m6502_84 /* 3 STY ZPG */
127 #define m6510_a4 m6502_a4 /* 3 LDY ZPG */
128 #define m6510_c4 m6502_c4 /* 3 CPY ZPG */
129 #define m6510_e4 m6502_e4 /* 3 CPX ZPG */
130
131 OP(14) { m6502_ICount -= 2; DOP; } /* 2 DOP */
132 OP(34) { m6502_ICount -= 2; DOP; } /* 2 DOP */
133 OP(54) { m6502_ICount -= 2; DOP; } /* 2 DOP */
134 OP(74) { m6502_ICount -= 2; DOP; } /* 2 DOP */
135 #define m6510_94 m6502_94 /* 4 STY ZP_X */
136 #define m6510_b4 m6502_b4 /* 4 LDY ZP_X */
OP(d4)137 OP(d4) { m6502_ICount -= 2; DOP; } /* 2 DOP */
OP(f4)138 OP(f4) { m6502_ICount -= 2; DOP; } /* 2 DOP */
139
140 #define m6510_05 m6502_05 /* 3 ORA ZPG */
141 #define m6510_25 m6502_25 /* 3 AND ZPG */
142 #define m6510_45 m6502_45 /* 3 EOR ZPG */
143 #define m6510_65 m6502_65 /* 3 ADC ZPG */
144 #define m6510_85 m6502_85 /* 3 STA ZPG */
145 #define m6510_a5 m6502_a5 /* 3 LDA ZPG */
146 #define m6510_c5 m6502_c5 /* 3 CMP ZPG */
147 #define m6510_e5 m6502_e5 /* 3 SBC ZPG */
148
149 #define m6510_15 m6502_15 /* 4 ORA ZPX */
150 #define m6510_35 m6502_35 /* 4 AND ZPX */
151 #define m6510_55 m6502_55 /* 4 EOR ZPX */
152 #define m6510_75 m6502_75 /* 4 ADC ZPX */
153 #define m6510_95 m6502_95 /* 4 STA ZPX */
154 #define m6510_b5 m6502_b5 /* 4 LDA ZPX */
155 #define m6510_d5 m6502_d5 /* 4 CMP ZPX */
156 #define m6510_f5 m6502_f5 /* 4 SBC ZPX */
157
158 OP(06) { int tmp; m6502_ICount -= 5; RD_ZPG; WB_EA; ASL; WB_EA; } /* 5 ASL ZPG */
159 OP(26) { int tmp; m6502_ICount -= 5; RD_ZPG; WB_EA; ROL; WB_EA; } /* 5 ROL ZPG */
160 OP(46) { int tmp; m6502_ICount -= 5; RD_ZPG; WB_EA; LSR; WB_EA; } /* 5 LSR ZPG */
161 OP(66) { int tmp; m6502_ICount -= 5; RD_ZPG; WB_EA; ROR; WB_EA; } /* 5 ROR ZPG */
162 #define m6510_86 m6502_86 /* 3 STX ZPG */
163 #define m6510_a6 m6502_a6 /* 3 LDX ZPG */
OP(c6)164 OP(c6) { int tmp; m6502_ICount -= 5; RD_ZPG; WB_EA; DEC; WB_EA; } /* 5 DEC ZPG */
OP(e6)165 OP(e6) { int tmp; m6502_ICount -= 5; RD_ZPG; WB_EA; INC; WB_EA; } /* 5 INC ZPG */
166
167 OP(16) { int tmp; m6502_ICount -= 6; RD_ZPX; WB_EA; ASL; WB_EA; } /* 6 ASL ZPX */
168 OP(36) { int tmp; m6502_ICount -= 6; RD_ZPX; WB_EA; ROL; WB_EA; } /* 6 ROL ZPX */
169 OP(56) { int tmp; m6502_ICount -= 6; RD_ZPX; WB_EA; LSR; WB_EA; } /* 6 LSR ZPX */
170 OP(76) { int tmp; m6502_ICount -= 6; RD_ZPX; WB_EA; ROR; WB_EA; } /* 6 ROR ZPX */
171 #define m6510_96 m6502_96 /* 4 STX ZPY */
172 #define m6510_b6 m6502_b6 /* 4 LDX ZPY */
OP(d6)173 OP(d6) { int tmp; m6502_ICount -= 6; RD_ZPX; WB_EA; DEC; WB_EA; } /* 6 DEC ZPX */
OP(f6)174 OP(f6) { int tmp; m6502_ICount -= 6; RD_ZPX; WB_EA; INC; WB_EA; } /* 6 INC ZPX */
175
176 OP(07) { int tmp; m6502_ICount -= 5; RD_ZPG; SLO; WB_EA; } /* 5 SLO ZPG */
177 OP(27) { int tmp; m6502_ICount -= 5; RD_ZPG; RLA; WB_EA; } /* 5 RLA ZPG */
178 OP(47) { int tmp; m6502_ICount -= 5; RD_ZPG; SRE; WB_EA; } /* 5 SRE ZPG */
179 OP(67) { int tmp; m6502_ICount -= 5; RD_ZPG; RRA; WB_EA; } /* 5 RRA ZPG */
180 OP(87) { int tmp; m6502_ICount -= 3; SAX; WR_ZPG; } /* 3 SAX ZPG */
OP(a7)181 OP(a7) { int tmp; m6502_ICount -= 3; RD_ZPG; LAX; } /* 3 LAX ZPG */
OP(c7)182 OP(c7) { int tmp; m6502_ICount -= 5; RD_ZPG; DCP; WB_EA; } /* 5 DCP ZPG */
OP(e7)183 OP(e7) { int tmp; m6502_ICount -= 5; RD_ZPG; ISB; WB_EA; } /* 5 ISB ZPG */
184
185 OP(17) { int tmp; m6502_ICount -= 6; RD_ZPX; SLO; WB_EA; } /* 4 SLO ZPX */
186 OP(37) { int tmp; m6502_ICount -= 6; RD_ZPX; RLA; WB_EA; } /* 4 RLA ZPX */
187 OP(57) { int tmp; m6502_ICount -= 6; RD_ZPX; SRE; WB_EA; } /* 4 SRE ZPX */
188 OP(77) { int tmp; m6502_ICount -= 6; RD_ZPX; RRA; WB_EA; } /* 4 RRA ZPX */
189 OP(97) { int tmp; m6502_ICount -= 4; SAX; WR_ZPY; } /* 4 SAX ZPY */
OP(b7)190 OP(b7) { int tmp; m6502_ICount -= 4; RD_ZPY; LAX; } /* 4 LAX ZPY */
OP(d7)191 OP(d7) { int tmp; m6502_ICount -= 6; RD_ZPX; DCP; WB_EA; } /* 6 DCP ZPX */
OP(f7)192 OP(f7) { int tmp; m6502_ICount -= 6; RD_ZPX; ISB; WB_EA; } /* 6 ISB ZPX */
193
194 #define m6510_08 m6502_08 /* 2 PHP */
195 #define m6510_28 m6502_28 /* 2 PLP */
196 #define m6510_48 m6502_48 /* 2 PHA */
197 #define m6510_68 m6502_68 /* 2 PLA */
198 #define m6510_88 m6502_88 /* 2 DEY */
199 #define m6510_a8 m6502_a8 /* 2 TAY */
200 #define m6510_c8 m6502_c8 /* 2 INY */
201 #define m6510_e8 m6502_e8 /* 2 INX */
202
203 #define m6510_18 m6502_18 /* 2 CLC */
204 #define m6510_38 m6502_38 /* 2 SEC */
205 #define m6510_58 m6502_58 /* 2 CLI */
206 #define m6510_78 m6502_78 /* 2 SEI */
207 #define m6510_98 m6502_98 /* 2 TYA */
208 #define m6510_b8 m6502_b8 /* 2 CLV */
209 #define m6510_d8 m6502_d8 /* 2 CLD */
210 #define m6510_f8 m6502_f8 /* 2 SED */
211
212 #define m6510_09 m6502_09 /* 2 ORA IMM */
213 #define m6510_29 m6502_29 /* 2 AND IMM */
214 #define m6510_49 m6502_49 /* 2 EOR IMM */
215 #define m6510_69 m6502_69 /* 2 ADC IMM */
216 OP(89) { m6502_ICount -= 2; DOP; } /* 2 DOP */
217 #define m6510_a9 m6502_a9 /* 2 LDA IMM */
218 #define m6510_c9 m6502_c9 /* 2 CMP IMM */
219 #define m6510_e9 m6502_e9 /* 2 SBC IMM */
220
221 #define m6510_19 m6502_19 /* 4 ORA ABY */
222 #define m6510_39 m6502_39 /* 4 AND ABY */
223 #define m6510_59 m6502_59 /* 4 EOR ABY */
224 #define m6510_79 m6502_79 /* 4 ADC ABY */
225 #define m6510_99 m6502_99 /* 5 STA ABY */
226 #define m6510_b9 m6502_b9 /* 4 LDA ABY */
227 #define m6510_d9 m6502_d9 /* 4 CMP ABY */
228 #define m6510_f9 m6502_f9 /* 4 SBC ABY */
229
230 #define m6510_0a m6502_0a /* 2 ASL A */
231 #define m6510_2a m6502_2a /* 2 ROL A */
232 #define m6510_4a m6502_4a /* 2 LSR A */
233 #define m6510_6a m6502_6a /* 2 ROR A */
234 #define m6510_8a m6502_8a /* 2 TXA */
235 #define m6510_aa m6502_aa /* 2 TAX */
236 #define m6510_ca m6502_ca /* 2 DEX */
237 #define m6510_ea m6502_ea /* 2 NOP */
238
239 OP(1a) { m6502_ICount -= 2; NOP; } /* 2 NOP */
240 OP(3a) { m6502_ICount -= 2; NOP; } /* 2 NOP */
241 OP(5a) { m6502_ICount -= 2; NOP; } /* 2 NOP */
242 OP(7a) { m6502_ICount -= 2; NOP; } /* 2 NOP */
243 #define m6510_9a m6502_9a /* 2 TXS */
244 #define m6510_ba m6502_ba /* 2 TSX */
OP(da)245 OP(da) { m6502_ICount -= 2; NOP; } /* 2 NOP */
OP(fa)246 OP(fa) { m6502_ICount -= 2; NOP; } /* 2 NOP */
247
248 OP(0b) { int tmp; m6502_ICount -= 2; RD_IMM; ANC; } /* 2 ANC IMM */
249 OP(2b) { int tmp; m6502_ICount -= 2; RD_IMM; ANC; } /* 2 ANC IMM */
250 OP(4b) { int tmp; m6502_ICount -= 2; RD_IMM; ASR; WB_ACC; } /* 2 ASR IMM */
251 OP(6b) { int tmp; m6502_ICount -= 2; RD_IMM; ARR; WB_ACC; } /* 2 ARR IMM */
252 OP(8b) { int tmp; m6502_ICount -= 2; RD_IMM; AXA; } /* 2 AXA IMM */
OP(ab)253 OP(ab) { int tmp; m6502_ICount -= 2; RD_IMM; OAL; } /* 2 OAL IMM */
OP(cb)254 OP(cb) { int tmp; m6502_ICount -= 2; RD_IMM; ASX; } /* 2 ASX IMM */
OP(eb)255 OP(eb) { int tmp; m6502_ICount -= 2; RD_IMM; SBC; } /* 2 SBC IMM */
256
257 OP(1b) { int tmp; m6502_ICount -= 4; RD_ABY; SLO; WB_EA; } /* 4 SLO ABY */
258 OP(3b) { int tmp; m6502_ICount -= 4; RD_ABY; RLA; WB_EA; } /* 4 RLA ABY */
259 OP(5b) { int tmp; m6502_ICount -= 4; RD_ABY; SRE; WB_EA; } /* 4 SRE ABY */
260 OP(7b) { int tmp; m6502_ICount -= 4; RD_ABY; RRA; WB_EA; } /* 4 RRA ABY */
261 OP(9b) { int tmp; m6502_ICount -= 5; EA_ABY; SSH; WB_EA; } /* 5 SSH ABY */
OP(bb)262 OP(bb) { int tmp; m6502_ICount -= 4; RD_ABY; AST; } /* 4 AST ABY */
OP(db)263 OP(db) { int tmp; m6502_ICount -= 6; RD_ABY; DCP; WB_EA; } /* 6 DCP ABY */
OP(fb)264 OP(fb) { int tmp; m6502_ICount -= 6; RD_ABY; ISB; WB_EA; } /* 6 ISB ABY */
265
266 OP(0c) { m6502_ICount -= 2; TOP; } /* 2 TOP */
267 #define m6510_2c m6502_2c /* 4 BIT ABS */
268 #define m6510_4c m6502_4c /* 3 JMP ABS */
269 #define m6510_6c m6502_6c /* 5 JMP IND */
270 #define m6510_8c m6502_8c /* 4 STY ABS */
271 #define m6510_ac m6502_ac /* 4 LDY ABS */
272 #define m6510_cc m6502_cc /* 4 CPY ABS */
273 #define m6510_ec m6502_ec /* 4 CPX ABS */
274
275 OP(1c) { m6502_ICount -= 2; TOP; } /* 2 TOP */
276 OP(3c) { m6502_ICount -= 2; TOP; } /* 2 TOP */
277 OP(5c) { m6502_ICount -= 2; TOP; } /* 2 TOP */
278 OP(7c) { m6502_ICount -= 2; TOP; } /* 2 TOP */
279 OP(9c) { int tmp; m6502_ICount -= 5; EA_ABX; SYH; WB_EA; } /* 5 SYH ABX */
280 #define m6510_bc m6502_bc /* 4 LDY ABX */
OP(dc)281 OP(dc) { m6502_ICount -= 2; TOP; } /* 2 TOP */
OP(fc)282 OP(fc) { m6502_ICount -= 2; TOP; } /* 2 TOP */
283
284 #define m6510_0d m6502_0d /* 4 ORA ABS */
285 #define m6510_2d m6502_2d /* 4 AND ABS */
286 #define m6510_4d m6502_4d /* 4 EOR ABS */
287 #define m6510_6d m6502_6d /* 4 ADC ABS */
288 #define m6510_8d m6502_8d /* 4 STA ABS */
289 #define m6510_ad m6502_ad /* 4 LDA ABS */
290 #define m6510_cd m6502_cd /* 4 CMP ABS */
291 #define m6510_ed m6502_ed /* 4 SBC ABS */
292
293 #define m6510_1d m6502_1d /* 4 ORA ABX */
294 #define m6510_3d m6502_3d /* 4 AND ABX */
295 #define m6510_5d m6502_5d /* 4 EOR ABX */
296 #define m6510_7d m6502_7d /* 4 ADC ABX */
297 #define m6510_9d m6502_9d /* 5 STA ABX */
298 #define m6510_bd m6502_bd /* 4 LDA ABX */
299 #define m6510_dd m6502_dd /* 4 CMP ABX */
300 #define m6510_fd m6502_fd /* 4 SBC ABX */
301
302
303 OP(0e) { int tmp; m6502_ICount -= 6; RD_ABS; WB_EA; ASL; WB_EA; } /* 6 ASL ABS */
304 OP(2e) { int tmp; m6502_ICount -= 6; RD_ABS; WB_EA; ROL; WB_EA; } /* 6 ROL ABS */
305 OP(4e) { int tmp; m6502_ICount -= 6; RD_ABS; WB_EA; LSR; WB_EA; } /* 6 LSR ABS */
306 OP(6e) { int tmp; m6502_ICount -= 6; RD_ABS; WB_EA; ROR; WB_EA; } /* 6 ROR ABS */
307 #define m6510_8e m6502_8e /* 5 STX ABS */
308 #define m6510_ae m6502_ae /* 4 LDX ABS */
OP(ce)309 OP(ce) { int tmp; m6502_ICount -= 6; RD_ABS; WB_EA; DEC; WB_EA; } /* 6 DEC ABS */
OP(ee)310 OP(ee) { int tmp; m6502_ICount -= 6; RD_ABS; WB_EA; INC; WB_EA; } /* 6 INC ABS */
311
312 OP(1e) { int tmp; m6502_ICount -= 7; RD_ABX; WB_EA; ASL; WB_EA; } /* 7 ASL ABX */
313 OP(3e) { int tmp; m6502_ICount -= 7; RD_ABX; WB_EA; ROL; WB_EA; } /* 7 ROL ABX */
314 OP(5e) { int tmp; m6502_ICount -= 7; RD_ABX; WB_EA; LSR; WB_EA; } /* 7 LSR ABX */
315 OP(7e) { int tmp; m6502_ICount -= 7; RD_ABX; WB_EA; ROR; WB_EA; } /* 7 ROR ABX */
316 OP(9e) { int tmp; m6502_ICount -= 2; EA_ABY; SXH; WB_EA; } /* 2 SXH ABY */
317 #define m6510_be m6502_be /* 4 LDX ABY */
OP(de)318 OP(de) { int tmp; m6502_ICount -= 7; RD_ABX; WB_EA; DEC; WB_EA; } /* 7 DEC ABX */
OP(fe)319 OP(fe) { int tmp; m6502_ICount -= 7; RD_ABX; WB_EA; INC; WB_EA; } /* 7 INC ABX */
320
321 OP(0f) { int tmp; m6502_ICount -= 6; RD_ABS; SLO; WB_EA; } /* 4 SLO ABS */
322 OP(2f) { int tmp; m6502_ICount -= 6; RD_ABS; RLA; WB_EA; } /* 4 RLA ABS */
323 OP(4f) { int tmp; m6502_ICount -= 6; RD_ABS; SRE; WB_EA; } /* 4 SRE ABS */
324 OP(6f) { int tmp; m6502_ICount -= 6; RD_ABS; RRA; WB_EA; } /* 4 RRA ABS */
325 OP(8f) { int tmp; m6502_ICount -= 4; SAX; WR_ABS; } /* 4 SAX ABS */
OP(af)326 OP(af) { int tmp; m6502_ICount -= 5; RD_ABS; LAX; } /* 4 LAX ABS */
OP(cf)327 OP(cf) { int tmp; m6502_ICount -= 6; RD_ABS; DCP; WB_EA; } /* 6 DCP ABS */
OP(ef)328 OP(ef) { int tmp; m6502_ICount -= 6; RD_ABS; ISB; WB_EA; } /* 6 ISB ABS */
329
330 OP(1f) { int tmp; m6502_ICount -= 4; RD_ABX; SLO; WB_EA; } /* 4 SLO ABX */
331 OP(3f) { int tmp; m6502_ICount -= 4; RD_ABX; RLA; WB_EA; } /* 4 RLA ABX */
332 OP(5f) { int tmp; m6502_ICount -= 4; RD_ABX; SRE; WB_EA; } /* 4 SRE ABX */
333 OP(7f) { int tmp; m6502_ICount -= 4; RD_ABX; RRA; WB_EA; } /* 4 RRA ABX */
334 OP(9f) { int tmp; m6502_ICount -= 6; EA_ABY; SAH; WB_EA; } /* 5 SAH ABY */
OP(bf)335 OP(bf) { int tmp; m6502_ICount -= 6; RD_ABY; LAX; } /* 4 LAX ABY */
OP(df)336 OP(df) { int tmp; m6502_ICount -= 7; RD_ABX; DCP; WB_EA; } /* 7 DCP ABX */
OP(ff)337 OP(ff) { int tmp; m6502_ICount -= 7; RD_ABX; ISB; WB_EA; } /* 7 ISB ABX */
338
339 static void (*insn6510[0x100])(void) = {
340 m6510_00,m6510_01,m6510_02,m6510_03,m6510_04,m6510_05,m6510_06,m6510_07,
341 m6510_08,m6510_09,m6510_0a,m6510_0b,m6510_0c,m6510_0d,m6510_0e,m6510_0f,
342 m6510_10,m6510_11,m6510_12,m6510_13,m6510_14,m6510_15,m6510_16,m6510_17,
343 m6510_18,m6510_19,m6510_1a,m6510_1b,m6510_1c,m6510_1d,m6510_1e,m6510_1f,
344 m6510_20,m6510_21,m6510_22,m6510_23,m6510_24,m6510_25,m6510_26,m6510_27,
345 m6510_28,m6510_29,m6510_2a,m6510_2b,m6510_2c,m6510_2d,m6510_2e,m6510_2f,
346 m6510_30,m6510_31,m6510_32,m6510_33,m6510_34,m6510_35,m6510_36,m6510_37,
347 m6510_38,m6510_39,m6510_3a,m6510_3b,m6510_3c,m6510_3d,m6510_3e,m6510_3f,
348 m6510_40,m6510_41,m6510_42,m6510_43,m6510_44,m6510_45,m6510_46,m6510_47,
349 m6510_48,m6510_49,m6510_4a,m6510_4b,m6510_4c,m6510_4d,m6510_4e,m6510_4f,
350 m6510_50,m6510_51,m6510_52,m6510_53,m6510_54,m6510_55,m6510_56,m6510_57,
351 m6510_58,m6510_59,m6510_5a,m6510_5b,m6510_5c,m6510_5d,m6510_5e,m6510_5f,
352 m6510_60,m6510_61,m6510_62,m6510_63,m6510_64,m6510_65,m6510_66,m6510_67,
353 m6510_68,m6510_69,m6510_6a,m6510_6b,m6510_6c,m6510_6d,m6510_6e,m6510_6f,
354 m6510_70,m6510_71,m6510_72,m6510_73,m6510_74,m6510_75,m6510_76,m6510_77,
355 m6510_78,m6510_79,m6510_7a,m6510_7b,m6510_7c,m6510_7d,m6510_7e,m6510_7f,
356 m6510_80,m6510_81,m6510_82,m6510_83,m6510_84,m6510_85,m6510_86,m6510_87,
357 m6510_88,m6510_89,m6510_8a,m6510_8b,m6510_8c,m6510_8d,m6510_8e,m6510_8f,
358 m6510_90,m6510_91,m6510_92,m6510_93,m6510_94,m6510_95,m6510_96,m6510_97,
359 m6510_98,m6510_99,m6510_9a,m6510_9b,m6510_9c,m6510_9d,m6510_9e,m6510_9f,
360 m6510_a0,m6510_a1,m6510_a2,m6510_a3,m6510_a4,m6510_a5,m6510_a6,m6510_a7,
361 m6510_a8,m6510_a9,m6510_aa,m6510_ab,m6510_ac,m6510_ad,m6510_ae,m6510_af,
362 m6510_b0,m6510_b1,m6510_b2,m6510_b3,m6510_b4,m6510_b5,m6510_b6,m6510_b7,
363 m6510_b8,m6510_b9,m6510_ba,m6510_bb,m6510_bc,m6510_bd,m6510_be,m6510_bf,
364 m6510_c0,m6510_c1,m6510_c2,m6510_c3,m6510_c4,m6510_c5,m6510_c6,m6510_c7,
365 m6510_c8,m6510_c9,m6510_ca,m6510_cb,m6510_cc,m6510_cd,m6510_ce,m6510_cf,
366 m6510_d0,m6510_d1,m6510_d2,m6510_d3,m6510_d4,m6510_d5,m6510_d6,m6510_d7,
367 m6510_d8,m6510_d9,m6510_da,m6510_db,m6510_dc,m6510_dd,m6510_de,m6510_df,
368 m6510_e0,m6510_e1,m6510_e2,m6510_e3,m6510_e4,m6510_e5,m6510_e6,m6510_e7,
369 m6510_e8,m6510_e9,m6510_ea,m6510_eb,m6510_ec,m6510_ed,m6510_ee,m6510_ef,
370 m6510_f0,m6510_f1,m6510_f2,m6510_f3,m6510_f4,m6510_f5,m6510_f6,m6510_f7,
371 m6510_f8,m6510_f9,m6510_fa,m6510_fb,m6510_fc,m6510_fd,m6510_fe,m6510_ff
372 };
373
374