1 #ifndef _MIPS_H
2 #define _MIPS_H
3 
4 #include "osd_cpu.h"
5 
6 enum
7 {
8 	MIPS_PC = 1,
9 	MIPS_DELAYV, MIPS_DELAYR,
10 	MIPS_HI, MIPS_LO,
11 	MIPS_R0, MIPS_R1,
12 	MIPS_R2, MIPS_R3,
13 	MIPS_R4, MIPS_R5,
14 	MIPS_R6, MIPS_R7,
15 	MIPS_R8, MIPS_R9,
16 	MIPS_R10, MIPS_R11,
17 	MIPS_R12, MIPS_R13,
18 	MIPS_R14, MIPS_R15,
19 	MIPS_R16, MIPS_R17,
20 	MIPS_R18, MIPS_R19,
21 	MIPS_R20, MIPS_R21,
22 	MIPS_R22, MIPS_R23,
23 	MIPS_R24, MIPS_R25,
24 	MIPS_R26, MIPS_R27,
25 	MIPS_R28, MIPS_R29,
26 	MIPS_R30, MIPS_R31,
27 	MIPS_CP0R0, MIPS_CP0R1,
28 	MIPS_CP0R2, MIPS_CP0R3,
29 	MIPS_CP0R4, MIPS_CP0R5,
30 	MIPS_CP0R6, MIPS_CP0R7,
31 	MIPS_CP0R8, MIPS_CP0R9,
32 	MIPS_CP0R10, MIPS_CP0R11,
33 	MIPS_CP0R12, MIPS_CP0R13,
34 	MIPS_CP0R14, MIPS_CP0R15,
35 	MIPS_CP0R16, MIPS_CP0R17,
36 	MIPS_CP0R18, MIPS_CP0R19,
37 	MIPS_CP0R20, MIPS_CP0R21,
38 	MIPS_CP0R22, MIPS_CP0R23,
39 	MIPS_CP0R24, MIPS_CP0R25,
40 	MIPS_CP0R26, MIPS_CP0R27,
41 	MIPS_CP0R28, MIPS_CP0R29,
42 	MIPS_CP0R30, MIPS_CP0R31,
43 	MIPS_CP2DR0, MIPS_CP2DR1,
44 	MIPS_CP2DR2, MIPS_CP2DR3,
45 	MIPS_CP2DR4, MIPS_CP2DR5,
46 	MIPS_CP2DR6, MIPS_CP2DR7,
47 	MIPS_CP2DR8, MIPS_CP2DR9,
48 	MIPS_CP2DR10, MIPS_CP2DR11,
49 	MIPS_CP2DR12, MIPS_CP2DR13,
50 	MIPS_CP2DR14, MIPS_CP2DR15,
51 	MIPS_CP2DR16, MIPS_CP2DR17,
52 	MIPS_CP2DR18, MIPS_CP2DR19,
53 	MIPS_CP2DR20, MIPS_CP2DR21,
54 	MIPS_CP2DR22, MIPS_CP2DR23,
55 	MIPS_CP2DR24, MIPS_CP2DR25,
56 	MIPS_CP2DR26, MIPS_CP2DR27,
57 	MIPS_CP2DR28, MIPS_CP2DR29,
58 	MIPS_CP2DR30, MIPS_CP2DR31,
59 	MIPS_CP2CR0, MIPS_CP2CR1,
60 	MIPS_CP2CR2, MIPS_CP2CR3,
61 	MIPS_CP2CR4, MIPS_CP2CR5,
62 	MIPS_CP2CR6, MIPS_CP2CR7,
63 	MIPS_CP2CR8, MIPS_CP2CR9,
64 	MIPS_CP2CR10, MIPS_CP2CR11,
65 	MIPS_CP2CR12, MIPS_CP2CR13,
66 	MIPS_CP2CR14, MIPS_CP2CR15,
67 	MIPS_CP2CR16, MIPS_CP2CR17,
68 	MIPS_CP2CR18, MIPS_CP2CR19,
69 	MIPS_CP2CR20, MIPS_CP2CR21,
70 	MIPS_CP2CR22, MIPS_CP2CR23,
71 	MIPS_CP2CR24, MIPS_CP2CR25,
72 	f1, f2, f3, f4,
73 	f5, f6, f7, f8,
74 	MIPS_CP2CR26, MIPS_CP2CR27,
75 	MIPS_CP2CR28, MIPS_CP2CR29,
76 	MIPS_CP2CR30, MIPS_CP2CR31
77 };
78 
79 extern int mips_ICount;
80 
81 #define MIPS_INT_NONE	( -1 )
82 
83 #define MIPS_IRQ0	( 0 )
84 #define MIPS_IRQ1	( 1 )
85 #define MIPS_IRQ2	( 2 )
86 #define MIPS_IRQ3	( 3 )
87 #define MIPS_IRQ4	( 4 )
88 #define MIPS_IRQ5	( 5 )
89 
90 #define MIPS_BYTE_EXTEND( a ) ( (INT32)(INT8)a )
91 #define MIPS_WORD_EXTEND( a ) ( (INT32)(INT16)a )
92 
93 #define INS_OP( op ) ( ( op >> 26 ) & 63 )
94 #define INS_RS( op ) ( ( op >> 21 ) & 31 )
95 #define INS_RT( op ) ( ( op >> 16 ) & 31 )
96 #define INS_IMMEDIATE( op ) ( op & 0xffff )
97 #define INS_TARGET( op ) ( op & 0x3ffffff )
98 #define INS_RD( op ) ( ( op >> 11 ) & 31 )
99 #define INS_SHAMT( op ) ( ( op >> 6 ) & 31 )
100 #define INS_FUNCT( op ) ( op & 63 )
101 #define INS_CODE( op ) ( ( op >> 6 ) & 0xfffff )
102 #define INS_CO( op ) ( ( op >> 25 ) & 1 )
103 #define INS_COFUN( op ) ( op & 0x1ffffff )
104 #define INS_CF( op ) ( op & 63 )
105 
106 #define GTE_OP( op ) ( ( op >> 20 ) & 0x1f )
107 #define GTE_SF( op ) ( ( op >> 19 ) & 1 )
108 #define GTE_MX( op ) ( ( op >> 17 ) & 3 )
109 #define GTE_V( op ) ( ( op >> 15 ) & 3 )
110 #define GTE_CV( op ) ( ( op >> 13 ) & 3 )
111 #define GTE_LM( op ) ( ( op >> 10 ) & 1 )
112 #define GTE_CT( op ) ( ( op ) & 0x7ff )
113 
114 #define OP_SPECIAL ( 0 )
115 #define OP_REGIMM ( 1 )
116 #define OP_J ( 2 )
117 #define OP_JAL ( 3 )
118 #define OP_BEQ ( 4 )
119 #define OP_BNE ( 5 )
120 #define OP_BLEZ ( 6 )
121 #define OP_BGTZ ( 7 )
122 #define OP_ADDI ( 8 )
123 #define OP_ADDIU ( 9 )
124 #define OP_SLTI ( 10 )
125 #define OP_SLTIU ( 11 )
126 #define OP_ANDI ( 12 )
127 #define OP_ORI ( 13 )
128 #define OP_XORI ( 14 )
129 #define OP_LUI ( 15 )
130 #define OP_COP0 ( 16 )
131 #define OP_COP1 ( 17 )
132 #define OP_COP2 ( 18 )
133 #define OP_LB ( 32 )
134 #define OP_LH ( 33 )
135 #define OP_LWL ( 34 )
136 #define OP_LW ( 35 )
137 #define OP_LBU ( 36 )
138 #define OP_LHU ( 37 )
139 #define OP_LWR ( 38 )
140 #define OP_SB ( 40 )
141 #define OP_SH ( 41 )
142 #define OP_SWL ( 42 )
143 #define OP_SW ( 43 )
144 #define OP_SWR ( 46 )
145 #define OP_LWC1 ( 49 )
146 #define OP_LWC2 ( 50 )
147 #define OP_SWC1 ( 57 )
148 #define OP_SWC2 ( 58 )
149 
150 /* OP_SPECIAL */
151 #define FUNCT_SLL ( 0 )
152 #define FUNCT_SRL ( 2 )
153 #define FUNCT_SRA ( 3 )
154 #define FUNCT_SLLV ( 4 )
155 #define FUNCT_SRLV ( 6 )
156 #define FUNCT_SRAV ( 7 )
157 #define FUNCT_JR ( 8 )
158 #define FUNCT_JALR ( 9 )
159 #define FUNCT_SYSCALL ( 12 )
160 #define FUNCT_BREAK ( 13 )
161 #define FUNCT_MFHI ( 16 )
162 #define FUNCT_MTHI ( 17 )
163 #define FUNCT_MFLO ( 18 )
164 #define FUNCT_MTLO ( 19 )
165 #define FUNCT_MULT ( 24 )
166 #define FUNCT_MULTU ( 25 )
167 #define FUNCT_DIV ( 26 )
168 #define FUNCT_DIVU ( 27 )
169 #define FUNCT_ADD ( 32 )
170 #define FUNCT_ADDU ( 33 )
171 #define FUNCT_SUB ( 34 )
172 #define FUNCT_SUBU ( 35 )
173 #define FUNCT_AND ( 36 )
174 #define FUNCT_OR ( 37 )
175 #define FUNCT_XOR ( 38 )
176 #define FUNCT_NOR ( 39 )
177 #define FUNCT_SLT ( 42 )
178 #define FUNCT_SLTU ( 43 )
179 
180 /* OP_REGIMM */
181 #define RT_BLTZ ( 0 )
182 #define RT_BGEZ ( 1 )
183 #define RT_BLTZAL ( 16 )
184 #define RT_BGEZAL ( 17 )
185 
186 /* OP_COP0/OP_COP1/OP_COP2 */
187 #define RS_MFC ( 0 )
188 #define RS_CFC ( 2 )
189 #define RS_MTC ( 4 )
190 #define RS_CTC ( 6 )
191 #define RS_BC ( 8 )
192 
193 /* RS_BC */
194 #define RT_BCF ( 0 )
195 #define RT_BCT ( 1 )
196 
197 /* OP_COP0 */
198 #define CF_RFE ( 16 )
199 
200 extern void mips_stop(void);
201 
202 extern void mips_init(void);
203 extern void mips_reset(void *param);
204 extern void mips_exit(void);
205 extern int mips_execute(int cycles);
206 extern unsigned mips_get_context(void *dst);
207 extern void mips_set_context(void *src);
208 extern unsigned mips_get_reg(int regnum);
209 extern void mips_set_reg(int regnum, unsigned val);
210 extern void mips_set_nmi_line(int linestate);
211 extern void mips_set_irq_line(int irqline, int linestate);
212 extern void mips_set_irq_callback(int (*callback)(int irqline));
213 extern const char *mips_info(void *context, int regnum);
214 extern unsigned mips_dasm(char *buffer, UINT32 pc);
215 
216 #ifdef MAME_DEBUG
217 extern unsigned DasmMIPS(char *buff, unsigned _pc);
218 #endif
219 
220 #if HAS_PSXCPU
221 
222 #define psxcpu_ICount mips_ICount
223 
224 #define psxcpu_init mips_init
225 #define psxcpu_reset mips_reset
226 #define psxcpu_exit mips_exit
227 #define psxcpu_execute mips_execute
228 #define psxcpu_get_context mips_get_context
229 #define psxcpu_set_context mips_set_context
230 #define psxcpu_get_pc mips_get_pc
231 #define psxcpu_set_pc mips_set_pc
232 #define psxcpu_get_sp mips_get_sp
233 #define psxcpu_set_sp mips_set_sp
234 #define psxcpu_get_reg mips_get_reg
235 #define psxcpu_set_reg mips_set_reg
236 #define psxcpu_set_nmi_line mips_set_nmi_line
237 #define psxcpu_set_irq_line mips_set_irq_line
238 #define psxcpu_set_irq_callback mips_set_irq_callback
239 #define psxcpu_state_save mips_state_save
240 #define psxcpu_state_load mips_state_load
241 #define psxcpu_info mips_info
242 #define psxcpu_dasm mips_dasm
243 
244 #endif
245 
246 #endif
247