1 /***************************************************************************
2
3 Pandora's Palace(GX328) (c) 1984 Konami/Interlogic
4
5 Driver by Manuel Abadia <manu@teleline.es>
6
7 Notes:
8 - Press 1P and 2P together to enter test mode.
9
10 TODO:
11 - CPU B continuously reads from 1e00. It seems to be important, could be a
12 scanline counter or something like that.
13
14 ***************************************************************************/
15
16 #include "driver.h"
17 #include "cpu/m6809/m6809.h"
18 #include "cpu/z80/z80.h"
19 #include "cpu/i8039/i8039.h"
20 #include "vidhrdw/generic.h"
21
22 static int irq_enable_a, irq_enable_b;
23 static int firq_old_data_a, firq_old_data_b;
24 static int i8039_status;
25
26 unsigned char *pandoras_sharedram;
27 static unsigned char *pandoras_sharedram2;
28
29 /* from vidhrdw */
30 PALETTE_INIT( pandoras );
31 READ_HANDLER( pandoras_vram_r );
32 READ_HANDLER( pandoras_cram_r );
33 WRITE_HANDLER( pandoras_vram_w );
34 WRITE_HANDLER( pandoras_cram_w );
35 WRITE_HANDLER( pandoras_flipscreen_w );
36 WRITE_HANDLER( pandoras_scrolly_w );
37 VIDEO_START( pandoras );
38 VIDEO_UPDATE( pandoras );
39
INTERRUPT_GEN(pandoras_interrupt_a)40 static INTERRUPT_GEN( pandoras_interrupt_a ){
41 if (irq_enable_a)
42 cpu_set_irq_line(0, M6809_IRQ_LINE, HOLD_LINE);
43 }
44
INTERRUPT_GEN(pandoras_interrupt_b)45 static INTERRUPT_GEN( pandoras_interrupt_b ){
46 if (irq_enable_b)
47 cpu_set_irq_line(1, M6809_IRQ_LINE, HOLD_LINE);
48 }
49
READ_HANDLER(pandoras_sharedram_r)50 static READ_HANDLER( pandoras_sharedram_r ){
51 return pandoras_sharedram[offset];
52 }
53
WRITE_HANDLER(pandoras_sharedram_w)54 static WRITE_HANDLER( pandoras_sharedram_w ){
55 pandoras_sharedram[offset] = data;
56 }
57
READ_HANDLER(pandoras_sharedram2_r)58 static READ_HANDLER( pandoras_sharedram2_r ){
59 return pandoras_sharedram2[offset];
60 }
61
WRITE_HANDLER(pandoras_sharedram2_w)62 static WRITE_HANDLER( pandoras_sharedram2_w ){
63 pandoras_sharedram2[offset] = data;
64 }
65
WRITE_HANDLER(pandoras_int_control_w)66 static WRITE_HANDLER( pandoras_int_control_w ){
67 /* byte 0: irq enable (CPU A)
68 byte 2: coin counter 1
69 byte 3: coin counter 2
70 byte 5: flip screen
71 byte 6: irq enable (CPU B)
72 byte 7: NMI to CPU B
73
74 other bytes unknown */
75
76 switch (offset){
77 case 0x00: if (!data) cpu_set_irq_line(0, M6809_IRQ_LINE, CLEAR_LINE);
78 irq_enable_a = data;
79 break;
80 case 0x02: coin_counter_w(0,data & 0x01);
81 break;
82 case 0x03: coin_counter_w(1,data & 0x01);
83 break;
84 case 0x05: pandoras_flipscreen_w(0, data);
85 break;
86 case 0x06: if (!data) cpu_set_irq_line(1, M6809_IRQ_LINE, CLEAR_LINE);
87 irq_enable_b = data;
88 break;
89 case 0x07: cpu_set_irq_line(1,IRQ_LINE_NMI,PULSE_LINE);
90 break;
91
92 default:
93 logerror("%04x: (irq_ctrl) write %02x to %02x\n",activecpu_get_pc(), data, offset);
94 }
95 }
96
WRITE_HANDLER(pandoras_cpua_irqtrigger_w)97 WRITE_HANDLER( pandoras_cpua_irqtrigger_w ){
98 if (!firq_old_data_a && data){
99 cpu_set_irq_line(0,M6809_FIRQ_LINE,HOLD_LINE);
100 }
101
102 firq_old_data_a = data;
103 }
104
WRITE_HANDLER(pandoras_cpub_irqtrigger_w)105 WRITE_HANDLER( pandoras_cpub_irqtrigger_w ){
106 if (!firq_old_data_b && data){
107 cpu_set_irq_line(1,M6809_FIRQ_LINE,HOLD_LINE);
108 }
109
110 firq_old_data_b = data;
111 }
112
WRITE_HANDLER(pandoras_i8039_irqtrigger_w)113 WRITE_HANDLER( pandoras_i8039_irqtrigger_w )
114 {
115 cpu_set_irq_line(3, 0, ASSERT_LINE);
116 }
117
WRITE_HANDLER(i8039_irqen_and_status_w)118 static WRITE_HANDLER( i8039_irqen_and_status_w )
119 {
120 /* bit 7 enables IRQ */
121 if ((data & 0x80) == 0)
122 cpu_set_irq_line(3, 0, CLEAR_LINE);
123
124 /* bit 5 goes to 8910 port A */
125 i8039_status = (data & 0x20) >> 5;
126 }
127
WRITE_HANDLER(pandoras_z80_irqtrigger_w)128 WRITE_HANDLER( pandoras_z80_irqtrigger_w )
129 {
130 cpu_set_irq_line_and_vector(2,0,HOLD_LINE,0xff);
131 }
132
133
134
MEMORY_READ_START(pandoras_readmem_a)135 static MEMORY_READ_START( pandoras_readmem_a )
136 { 0x0000, 0x0fff, pandoras_sharedram_r }, /* Work RAM (Shared with CPU B) */
137 { 0x1000, 0x13ff, pandoras_cram_r }, /* Color RAM (shared with CPU B) */
138 { 0x1400, 0x17ff, pandoras_vram_r }, /* Video RAM (shared with CPU B) */
139 { 0x4000, 0x5fff, MRA_ROM }, /* space for diagnostic ROM */
140 { 0x6000, 0x67ff, pandoras_sharedram2_r }, /* Shared RAM with CPU B */
141 { 0x8000, 0xffff, MRA_ROM }, /* ROM */
142 MEMORY_END
143
144 static MEMORY_WRITE_START( pandoras_writemem_a )
145 { 0x0000, 0x0fff, pandoras_sharedram_w, &pandoras_sharedram }, /* Work RAM (Shared with CPU B) */
146 { 0x1000, 0x13ff, pandoras_cram_w, &colorram }, /* Color RAM (shared with CPU B) */
147 { 0x1400, 0x17ff, pandoras_vram_w, &videoram }, /* Video RAM (shared with CPU B) */
148 { 0x1800, 0x1807, pandoras_int_control_w }, /* INT control */
149 { 0x1a00, 0x1a00, pandoras_scrolly_w }, /* bg scroll */
150 { 0x1c00, 0x1c00, pandoras_z80_irqtrigger_w }, /* cause INT on the Z80 */
151 { 0x1e00, 0x1e00, soundlatch_w }, /* sound command to the Z80 */
152 { 0x2000, 0x2000, pandoras_cpub_irqtrigger_w }, /* cause FIRQ on CPU B */
153 { 0x2001, 0x2001, watchdog_reset_w }, /* watchdog reset */
154 { 0x4000, 0x5fff, MWA_ROM }, /* see notes */
155 { 0x6000, 0x67ff, pandoras_sharedram2_w, &pandoras_sharedram2 },/* Shared RAM with CPU B */
156 { 0x8000, 0xffff, MWA_ROM }, /* ROM */
157 MEMORY_END
158
159 static MEMORY_READ_START( pandoras_readmem_b )
160 { 0x0000, 0x0fff, pandoras_sharedram_r }, /* Work RAM (Shared with CPU A) */
161 { 0x1000, 0x13ff, pandoras_cram_r }, /* Color RAM (shared with CPU A) */
162 { 0x1400, 0x17ff, pandoras_vram_r }, /* Video RAM (shared with CPU A) */
163 { 0x1800, 0x1800, input_port_0_r }, /* DIPSW #1 */
164 { 0x1a00, 0x1a00, input_port_3_r }, /* COINSW */
165 { 0x1a01, 0x1a01, input_port_4_r }, /* 1P inputs */
166 { 0x1a02, 0x1a02, input_port_5_r }, /* 2P inputs */
167 { 0x1a03, 0x1a03, input_port_2_r }, /* DIPSW #3 */
168 { 0x1c00, 0x1c00, input_port_1_r }, /* DISPW #2 */
169 // { 0x1e00, 0x1e00, MRA_NOP }, /* ??? seems to be important */
170 { 0xc000, 0xc7ff, pandoras_sharedram2_r }, /* Shared RAM with the CPU A */
171 { 0xe000, 0xffff, MRA_ROM }, /* ROM */
172 MEMORY_END
173
174 static MEMORY_WRITE_START( pandoras_writemem_b )
175 { 0x0000, 0x0fff, pandoras_sharedram_w }, /* Work RAM (Shared with CPU A) */
176 { 0x1000, 0x13ff, pandoras_cram_w }, /* Color RAM (shared with CPU A) */
177 { 0x1400, 0x17ff, pandoras_vram_w }, /* Video RAM (shared with CPU A) */
178 { 0x1800, 0x1807, pandoras_int_control_w }, /* INT control */
179 { 0x8000, 0x8000, watchdog_reset_w }, /* watchdog reset */
180 { 0xa000, 0xa000, pandoras_cpua_irqtrigger_w },/* cause FIRQ on CPU A */
181 { 0xc000, 0xc7ff, pandoras_sharedram2_w }, /* Shared RAM with the CPU A */
182 { 0xe000, 0xffff, MWA_ROM }, /* ROM */
183 MEMORY_END
184
185 static MEMORY_READ_START( pandoras_readmem_snd )
186 { 0x0000, 0x1fff, MRA_ROM }, /* ROM */
187 { 0x2000, 0x23ff, MRA_RAM }, /* RAM */
188 { 0x4000, 0x4000, soundlatch_r }, /* soundlatch_r */
189 { 0x6001, 0x6001, AY8910_read_port_0_r }, /* AY-8910 */
190 MEMORY_END
191
192 static MEMORY_WRITE_START( pandoras_writemem_snd )
193 { 0x0000, 0x1fff, MWA_ROM }, /* ROM */
194 { 0x2000, 0x23ff, MWA_RAM }, /* RAM */
195 { 0x6000, 0x6000, AY8910_control_port_0_w },/* AY-8910 */
196 { 0x6002, 0x6002, AY8910_write_port_0_w }, /* AY-8910 */
197 { 0x8000, 0x8000, pandoras_i8039_irqtrigger_w },/* cause INT on the 8039 */
198 { 0xa000, 0xa000, soundlatch2_w }, /* sound command to the 8039 */
199 MEMORY_END
200
201 static MEMORY_READ_START( i8039_readmem )
202 { 0x0000, 0x0fff, MRA_ROM },
203 MEMORY_END
204
205 static MEMORY_WRITE_START( i8039_writemem )
206 { 0x0000, 0x0fff, MWA_ROM },
207 MEMORY_END
208
209 static PORT_READ_START( i8039_readport )
210 { 0x00, 0xff, soundlatch2_r },
211 PORT_END
212
213 static PORT_WRITE_START( i8039_writeport )
214 { I8039_p1, I8039_p1, DAC_0_data_w },
215 { I8039_p2, I8039_p2, i8039_irqen_and_status_w },
216 PORT_END
217
218
219 /***************************************************************************
220
221 Input Ports
222
223 ***************************************************************************/
224
225 INPUT_PORTS_START( pandoras )
226 PORT_START /* DSW #1 */
227 PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
228 PORT_DIPSETTING( 0x02, DEF_STR( 4C_1C ) )
229 PORT_DIPSETTING( 0x05, DEF_STR( 3C_1C ) )
230 PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
231 PORT_DIPSETTING( 0x04, DEF_STR( 3C_2C ) )
232 PORT_DIPSETTING( 0x01, DEF_STR( 4C_3C ) )
233 PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
234 PORT_DIPSETTING( 0x03, DEF_STR( 3C_4C ) )
235 PORT_DIPSETTING( 0x07, DEF_STR( 2C_3C ) )
236 PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
237 PORT_DIPSETTING( 0x06, DEF_STR( 2C_5C ) )
238 PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
239 PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
240 PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
241 PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) )
242 PORT_DIPSETTING( 0x09, DEF_STR( 1C_7C ) )
243 PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
244 PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_B ) )
245 PORT_DIPSETTING( 0x20, DEF_STR( 4C_1C ) )
246 PORT_DIPSETTING( 0x50, DEF_STR( 3C_1C ) )
247 PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
248 PORT_DIPSETTING( 0x40, DEF_STR( 3C_2C ) )
249 PORT_DIPSETTING( 0x10, DEF_STR( 4C_3C ) )
250 PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
251 PORT_DIPSETTING( 0x30, DEF_STR( 3C_4C ) )
252 PORT_DIPSETTING( 0x70, DEF_STR( 2C_3C ) )
253 PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
254 PORT_DIPSETTING( 0x60, DEF_STR( 2C_5C ) )
255 PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
256 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
257 PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
258 PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
259 PORT_DIPSETTING( 0x90, DEF_STR( 1C_7C ) )
260 // PORT_DIPSETTING( 0x00, "Invalid" )
261
262 PORT_START /* DSW #2 */
263 PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )
264 PORT_DIPSETTING( 0x03, "3" )
265 PORT_DIPSETTING( 0x02, "4" )
266 PORT_DIPSETTING( 0x01, "5" )
267 PORT_DIPSETTING( 0x00, "7" )
268 PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) )
269 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
270 PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
271 PORT_DIPNAME( 0x18, 0x18, DEF_STR( Bonus_Life ) )
272 PORT_DIPSETTING( 0x18, "20k and every 60k" )
273 PORT_DIPSETTING( 0x10, "30k and every 70k" )
274 PORT_DIPSETTING( 0x08, "20k" )
275 PORT_DIPSETTING( 0x00, "30k" )
276 PORT_DIPNAME( 0x60, 0x40, DEF_STR( Difficulty ) )
277 PORT_DIPSETTING( 0x60, "Easy" )
278 PORT_DIPSETTING( 0x40, "Normal" )
279 PORT_DIPSETTING( 0x20, "Difficult" )
280 PORT_DIPSETTING( 0x00, "Very Difficult" )
281 PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) )
282 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
283 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
284
285 PORT_START /* DSW #3 */
286 PORT_DIPNAME( 0x01, 0x01, "Freeze" )
287 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
288 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
289 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
290 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
291 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
292 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
293 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
294 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
295 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
296 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
297 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
298 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
299 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
300 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
301 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
302 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
303 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
304 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
305 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
306 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
307 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
308 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
309 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
310
311 PORT_START /* COINSW */
312 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
313 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
314 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
315 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
316 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
317 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
318 PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
319
320 PORT_START /* PLAYER 1 INPUTS */
321 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
322 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
323 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
324 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
325 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
326 PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
327
328 PORT_START /* PLAYER 2 INPUTS */
329 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
330 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
331 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
332 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
333 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
334 PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
335 INPUT_PORTS_END
336
337
338
339 static struct GfxLayout charlayout =
340 {
341 8,8,
342 RGN_FRAC(1,1),
343 4,
344 { 0, 1, 2, 3 },
345 { 0*4, 1*4, 2*4, 3*4, 4*4, 5*4, 6*4, 7*4 },
346 { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 },
347 32*8
348 };
349
350 static struct GfxLayout spritelayout =
351 {
352 16,16,
353 RGN_FRAC(1,1),
354 4,
355 { 0, 1, 2, 3 },
356 { 15*4, 14*4, 13*4, 12*4, 11*4, 10*4, 9*4, 8*4,
357 7*4, 6*4, 5*4, 4*4, 3*4, 2*4, 1*4, 0*4 },
358 { 15*4*16, 14*4*16, 13*4*16, 12*4*16, 11*4*16, 10*4*16, 9*4*16, 8*4*16,
359 7*4*16, 6*4*16, 5*4*16, 4*4*16, 3*4*16, 2*4*16, 1*4*16, 0*4*16 },
360 32*4*8
361 };
362
363 static struct GfxDecodeInfo gfxdecodeinfo[] =
364 {
365 { REGION_GFX1, 0, &charlayout, 0, 16 },
366 { REGION_GFX2, 0, &spritelayout, 16*16, 16 },
367 { -1 } /* end of array */
368 };
369
370 /***************************************************************************
371
372 Machine Driver
373
374 ***************************************************************************/
375
MACHINE_INIT(pandoras)376 static MACHINE_INIT( pandoras )
377 {
378 firq_old_data_a = firq_old_data_b = 0;
379 irq_enable_a = irq_enable_b = 0;
380 }
381
READ_HANDLER(pandoras_portA_r)382 static READ_HANDLER( pandoras_portA_r )
383 {
384 return i8039_status;
385 }
386
READ_HANDLER(pandoras_portB_r)387 static READ_HANDLER( pandoras_portB_r )
388 {
389 return (activecpu_gettotalcycles() / 512) & 0x0f;
390 }
391
392 static struct AY8910interface ay8910_interface =
393 {
394 1, /* 1 chip */
395 14318000/8,
396 { 40 },
397 { pandoras_portA_r }, // not used
398 { pandoras_portB_r },
399 { 0 },
400 { 0 }
401 };
402
403 static struct DACinterface dac_interface =
404 {
405 1,
406 { 25 }
407 };
408
409 static MACHINE_DRIVER_START( pandoras )
410
411 /* basic machine hardware */
412 MDRV_CPU_ADD(M6809,18432000/6) /* CPU A */
413 MDRV_CPU_MEMORY(pandoras_readmem_a,pandoras_writemem_a)
414 MDRV_CPU_VBLANK_INT(pandoras_interrupt_a,1)
415
416 MDRV_CPU_ADD(M6809,18432000/6) /* CPU B */
417 MDRV_CPU_MEMORY(pandoras_readmem_b,pandoras_writemem_b)
418 MDRV_CPU_VBLANK_INT(pandoras_interrupt_b,1)
419
420 MDRV_CPU_ADD(Z80,14318000/8)
421 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
422 MDRV_CPU_MEMORY(pandoras_readmem_snd,pandoras_writemem_snd)
423
424 MDRV_CPU_ADD(I8039,(14318000/2)/I8039_CLOCK_DIVIDER)
425 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
426 MDRV_CPU_MEMORY(i8039_readmem,i8039_writemem)
427 MDRV_CPU_PORTS(i8039_readport,i8039_writeport)
428
429 MDRV_FRAMES_PER_SECOND(60)
430 MDRV_VBLANK_DURATION(DEFAULT_60HZ_VBLANK_DURATION)
431 MDRV_INTERLEAVE(50) /* slices per frame */
432
433 MDRV_MACHINE_INIT(pandoras)
434
435 /* video hardware */
436 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
437 MDRV_SCREEN_SIZE(32*8, 32*8)
438 MDRV_VISIBLE_AREA(0*8, 32*8-1, 2*8, 30*8-1)
439 MDRV_GFXDECODE(gfxdecodeinfo)
440 MDRV_PALETTE_LENGTH(32)
441 MDRV_COLORTABLE_LENGTH(16*16+16*16)
442
443 MDRV_PALETTE_INIT(pandoras)
444 MDRV_VIDEO_START(pandoras)
445 MDRV_VIDEO_UPDATE(pandoras)
446
447 /* sound hardware */
448 MDRV_SOUND_ADD(AY8910, ay8910_interface)
449 MDRV_SOUND_ADD(DAC, dac_interface)
450 MACHINE_DRIVER_END
451
452
453 /***************************************************************************
454
455 Game ROMs
456
457 ***************************************************************************/
458
459 ROM_START( pandoras )
460 ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64K for the CPU A */
461 ROM_LOAD( "pand_j13.cpu", 0x08000, 0x02000, CRC(7a0fe9c5) SHA1(e68c8d76d1abb69ac72b0e2cd8c1dfc540064ee3) )
462 ROM_LOAD( "pand_j12.cpu", 0x0a000, 0x02000, CRC(7dc4bfe1) SHA1(359c3051e5d7a34d0e49578e4c168fd19c73e202) )
463 ROM_LOAD( "pand_j10.cpu", 0x0c000, 0x02000, CRC(be3af3b7) SHA1(91321b53e17e58b674104cb95b1c35ee8fecae22) )
464 ROM_LOAD( "pand_j9.cpu", 0x0e000, 0x02000, CRC(e674a17a) SHA1(a4b096dc455425dd60298acf2203659ef6f8d857) )
465
466 ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* 64K for the CPU B */
467 ROM_LOAD( "pand_j5.cpu", 0x0e000, 0x02000, CRC(4aab190b) SHA1(d2204953d6b6b34cea851bfc9c2b31426e75f90b) )
468
469 ROM_REGION( 0x10000, REGION_CPU3, 0 ) /* 64K for the Sound CPU */
470 ROM_LOAD( "pand_6c.snd", 0x00000, 0x02000, CRC(0c1f109d) SHA1(4e6cdee99261764bd2fea5abbd49d800baba0dc5) )
471
472 ROM_REGION( 0x1000, REGION_CPU4, 0 ) /* 4K for the Sound CPU 2 */
473 ROM_LOAD( "pand_7e.snd", 0x00000, 0x01000, CRC(18b0f9d0) SHA1(2a6119423222577a4c2b99ed78f61ba387eec7f8) )
474
475 ROM_REGION( 0x4000, REGION_GFX1, ROMREGION_DISPOSE )
476 ROM_LOAD( "pand_a18.cpu", 0x00000, 0x02000, CRC(23706d4a) SHA1(cca92e6ff90e3006a79a214f1211fd659771de53) ) /* tiles */
477 ROM_LOAD( "pand_a19.cpu", 0x02000, 0x02000, CRC(a463b3f9) SHA1(549b7ee6e47325b80186441da11879fb8b1b47be) )
478
479 ROM_REGION( 0x6000, REGION_GFX2, ROMREGION_DISPOSE )
480 ROM_LOAD( "pand_j18.cpu", 0x00000, 0x02000, CRC(99a696c5) SHA1(35a27cd5ecc51a9a1acf01eb8078a1028f03be32) ) /* sprites */
481 ROM_LOAD( "pand_j17.cpu", 0x02000, 0x02000, CRC(38a03c21) SHA1(b0c8f642787bab3cd1d76657e56f07f4f6f9073c) )
482 ROM_LOAD( "pand_j16.cpu", 0x04000, 0x02000, CRC(e0708a78) SHA1(9dbd08b6ca8a66a61e128d1806888696273de848) )
483
484 ROM_REGION( 0x0220, REGION_PROMS, 0 )
485 ROM_LOAD( "pandora.2a", 0x0000, 0x020, CRC(4d56f939) SHA1(a8dac604bfdaf4b153b75dbf165de113152b6daa) ) /* palette */
486 ROM_LOAD( "pandora.17g", 0x0020, 0x100, CRC(c1a90cfc) SHA1(c6581f2d543e38f1de399774183cf0698e61dab5) ) /* sprite lookup table */
487 ROM_LOAD( "pandora.16b", 0x0120, 0x100, CRC(c89af0c3) SHA1(4072c8d61521b34ce4dbce1d48f546402e9539cd) ) /* character lookup table */
488 ROM_END
489
490
491
492 GAME( 1984, pandoras, 0, pandoras, pandoras, 0, ROT90, "Konami/Interlogic", "Pandora's Palace" )
493