1 /***************************************************************************
2
3 Generic (PC-style) IDE controller implementation
4
5 ***************************************************************************/
6
7 #include "idectrl.h"
8 #include "state.h"
9
10
11 /*************************************
12 *
13 * Debugging
14 *
15 *************************************/
16
17 #define VERBOSE 0
18 #define PRINTF_IDE_COMMANDS 0
19 #define PRINTF_IDE_PASSWORD 0
20
21 #if VERBOSE
22 #define LOG(x) logerror x
23 #else
24 #define LOG(X)
25 #endif
26
27 #if (VERBOSE && PRINTF_IDE_COMMANDS)
28 #define LOGPRINT(x) logerror x; printf x
29 #elif PRINTF_IDE_COMMANDS
30 #define LOGPRINT(x) printf x
31 #else
32 #define LOGPRINT(X)
33 #endif
34
35
36
37 /*************************************
38 *
39 * Constants
40 *
41 *************************************/
42
43 #define IDE_DISK_SECTOR_SIZE 512
44
45 #define MINIMUM_COMMAND_TIME (TIME_IN_USEC(10))
46
47 #define TIME_PER_SECTOR (TIME_IN_USEC(100))
48 #define TIME_PER_ROTATION (TIME_IN_HZ(5400/60))
49 #define TIME_SECURITY_ERROR (TIME_IN_MSEC(1000))
50
51 #define TIME_SEEK_MULTISECTOR (TIME_IN_MSEC(13))
52 #define TIME_NO_SEEK_MULTISECTOR (TIME_IN_USEC(16.3))
53
54 #define IDE_STATUS_ERROR 0x01
55 #define IDE_STATUS_HIT_INDEX 0x02
56 #define IDE_STATUS_BUFFER_READY 0x08
57 #define IDE_STATUS_SEEK_COMPLETE 0x10
58 #define IDE_STATUS_DRIVE_READY 0x40
59 #define IDE_STATUS_BUSY 0x80
60
61 #define IDE_CONFIG_REGISTERS 0x10
62
63 #define IDE_ADDR_CONFIG_UNK 0x034
64 #define IDE_ADDR_CONFIG_REGISTER 0x038
65 #define IDE_ADDR_CONFIG_DATA 0x03c
66
67 #define IDE_ADDR_DATA 0x1f0
68 #define IDE_ADDR_ERROR 0x1f1
69 #define IDE_ADDR_SECTOR_COUNT 0x1f2
70 #define IDE_ADDR_SECTOR_NUMBER 0x1f3
71 #define IDE_ADDR_CYLINDER_LSB 0x1f4
72 #define IDE_ADDR_CYLINDER_MSB 0x1f5
73 #define IDE_ADDR_HEAD_NUMBER 0x1f6
74 #define IDE_ADDR_STATUS_COMMAND 0x1f7
75
76 #define IDE_ADDR_STATUS_CONTROL 0x3f6
77
78 #define IDE_COMMAND_READ_MULTIPLE 0x20
79 #define IDE_COMMAND_READ_MULTIPLE_ONCE 0x21
80 #define IDE_COMMAND_WRITE_MULTIPLE 0x30
81 #define IDE_COMMAND_SET_CONFIG 0x91
82 #define IDE_COMMAND_READ_MULTIPLE_BLOCK 0xc4
83 #define IDE_COMMAND_WRITE_MULTIPLE_BLOCK 0xc5
84 #define IDE_COMMAND_SET_BLOCK_COUNT 0xc6
85 #define IDE_COMMAND_READ_DMA 0xc8
86 #define IDE_COMMAND_WRITE_DMA 0xca
87 #define IDE_COMMAND_GET_INFO 0xec
88 #define IDE_COMMAND_SET_FEATURES 0xef
89 #define IDE_COMMAND_SECURITY_UNLOCK 0xf2
90 #define IDE_COMMAND_UNKNOWN_F9 0xf9
91
92 #define IDE_ERROR_NONE 0x00
93 #define IDE_ERROR_DEFAULT 0x01
94 #define IDE_ERROR_UNKNOWN_COMMAND 0x04
95 #define IDE_ERROR_BAD_LOCATION 0x10
96 #define IDE_ERROR_BAD_SECTOR 0x80
97
98 #define IDE_BUSMASTER_STATUS_ACTIVE 0x01
99 #define IDE_BUSMASTER_STATUS_ERROR 0x02
100 #define IDE_BUSMASTER_STATUS_IRQ 0x04
101
102
103
104 /*************************************
105 *
106 * Type definitions
107 *
108 *************************************/
109
110 struct ide_state
111 {
112 UINT8 adapter_control;
113 UINT8 status;
114 UINT8 error;
115 UINT8 command;
116 UINT8 interrupt_pending;
117 UINT8 precomp_offset;
118
119 UINT8 buffer[IDE_DISK_SECTOR_SIZE];
120 UINT8 features[IDE_DISK_SECTOR_SIZE];
121 UINT16 buffer_offset;
122 UINT16 sector_count;
123
124 UINT16 block_count;
125 UINT16 sectors_until_int;
126
127 UINT8 dma_active;
128 UINT8 dma_cpu;
129 UINT8 dma_address_xor;
130 UINT8 dma_last_buffer;
131 offs_t dma_address;
132 offs_t dma_descriptor;
133 UINT32 dma_bytes_left;
134
135 UINT8 bus_master_command;
136 UINT8 bus_master_status;
137 UINT32 bus_master_descriptor;
138
139 UINT16 cur_cylinder;
140 UINT8 cur_sector;
141 UINT8 cur_head;
142 UINT8 cur_head_reg;
143
144 UINT32 cur_lba;
145
146 UINT16 num_cylinders;
147 UINT8 num_sectors;
148 UINT8 num_heads;
149
150 UINT8 config_unknown;
151 UINT8 config_register[IDE_CONFIG_REGISTERS];
152 UINT8 config_register_num;
153
154 struct ide_interface *intf;
155 struct hard_disk_file * disk;
156 void * last_status_timer;
157 void * reset_timer;
158
159 int master_password_enable;
160 int user_password_enable;
161 UINT8 * master_password;
162 UINT8 * user_password;
163 };
164
165
166
167 /*************************************
168 *
169 * Local variables
170 *
171 *************************************/
172
173 static struct ide_state idestate[MAX_IDE_CONTROLLERS];
174
175
176
177 /*************************************
178 *
179 * Prototypes
180 *
181 *************************************/
182
183 static void reset_callback(int param);
184
185 static void ide_build_features(struct ide_state *ide);
186
187 static void continue_read(struct ide_state *ide);
188 static void read_sector_done(int which);
189 static void read_first_sector(struct ide_state *ide);
190 static void read_next_sector(struct ide_state *ide);
191
192 static UINT32 ide_controller_read(struct ide_state *ide, offs_t offset, int size);
193 static void ide_controller_write(struct ide_state *ide, offs_t offset, int size, UINT32 data);
194
195
196
197 /*************************************
198 *
199 * Interrupts
200 *
201 *************************************/
202
signal_interrupt(struct ide_state * ide)203 static INLINE void signal_interrupt(struct ide_state *ide)
204 {
205 LOG(("IDE interrupt assert\n"));
206
207 /* signal an interrupt */
208 if (ide->intf->interrupt)
209 (*ide->intf->interrupt)(ASSERT_LINE);
210 ide->interrupt_pending = 1;
211 ide->bus_master_status |= IDE_BUSMASTER_STATUS_IRQ;
212 }
213
214
clear_interrupt(struct ide_state * ide)215 static INLINE void clear_interrupt(struct ide_state *ide)
216 {
217 LOG(("IDE interrupt clear\n"));
218
219 /* clear an interrupt */
220 if (ide->intf->interrupt)
221 (*ide->intf->interrupt)(CLEAR_LINE);
222 ide->interrupt_pending = 0;
223 }
224
225
226
227 /*************************************
228 *
229 * Delayed interrupt handling
230 *
231 *************************************/
232
delayed_interrupt(int which)233 static void delayed_interrupt(int which)
234 {
235 struct ide_state *ide = &idestate[which];
236 ide->status &= ~IDE_STATUS_BUSY;
237 signal_interrupt(ide);
238 }
239
240
delayed_interrupt_buffer_ready(int which)241 static void delayed_interrupt_buffer_ready(int which)
242 {
243 struct ide_state *ide = &idestate[which];
244 ide->status &= ~IDE_STATUS_BUSY;
245 ide->status |= IDE_STATUS_BUFFER_READY;
246 signal_interrupt(ide);
247 }
248
249
signal_delayed_interrupt(struct ide_state * ide,double time,int buffer_ready)250 static INLINE void signal_delayed_interrupt(struct ide_state *ide, double time, int buffer_ready)
251 {
252 /* clear buffer ready and set the busy flag */
253 ide->status &= ~IDE_STATUS_BUFFER_READY;
254 ide->status |= IDE_STATUS_BUSY;
255
256 /* set a timer */
257 if (buffer_ready)
258 timer_set(time, ide - idestate, delayed_interrupt_buffer_ready);
259 else
260 timer_set(time, ide - idestate, delayed_interrupt);
261 }
262
263
264
265 /*************************************
266 *
267 * Initialization & reset
268 *
269 *************************************/
270
ide_controller_init_custom(int which,struct ide_interface * intf,struct chd_file * diskhandle)271 int ide_controller_init_custom(int which, struct ide_interface *intf, struct chd_file *diskhandle)
272 {
273 struct ide_state *ide = &idestate[which];
274 const struct hard_disk_info *hdinfo;
275
276 /* NULL interface is immediate failure */
277 if (!intf)
278 return 1;
279
280 /* reset the IDE state */
281 memset(ide, 0, sizeof(*ide));
282 ide->intf = intf;
283
284 /* set MAME harddisk handle */
285 ide->disk = hard_disk_open(diskhandle);
286
287 /* get and copy the geometry */
288 if (ide->disk)
289 {
290 hdinfo = hard_disk_get_info(ide->disk);
291 ide->num_cylinders = hdinfo->cylinders;
292 ide->num_sectors = hdinfo->sectors;
293 ide->num_heads = hdinfo->heads;
294 if (hdinfo->sectorbytes != IDE_DISK_SECTOR_SIZE)
295 /* wrong sector len */
296 return 1;
297 #if PRINTF_IDE_COMMANDS
298 printf("CHS: %d %d %d\n", ide->num_cylinders, ide->num_heads, ide->num_sectors);
299 #endif
300 }
301
302 /* build the features page */
303 ide_build_features(ide);
304
305 /* create a timer for timing status */
306 ide->last_status_timer = timer_alloc(NULL);
307 ide->reset_timer = timer_alloc(reset_callback);
308
309 /* register ide status */
310 state_save_register_UINT8 ("ide", which, "adapter_control", &ide->adapter_control, 1);
311 state_save_register_UINT8 ("ide", which, "status", &ide->status, 1);
312 state_save_register_UINT8 ("ide", which, "error", &ide->error, 1);
313 state_save_register_UINT8 ("ide", which, "command", &ide->command, 1);
314 state_save_register_UINT8 ("ide", which, "interrupt_pending", &ide->interrupt_pending, 1);
315 state_save_register_UINT8 ("ide", which, "precomp_offset", &ide->precomp_offset, 1);
316
317 state_save_register_UINT8 ("ide", which, "buffer", ide->buffer, IDE_DISK_SECTOR_SIZE);
318 state_save_register_UINT8 ("ide", which, "features", ide->features, IDE_DISK_SECTOR_SIZE);
319 state_save_register_UINT16("ide", which, "buffer_offset", &ide->buffer_offset, 1);
320 state_save_register_UINT16("ide", which, "sector_count", &ide->sector_count, 1);
321
322 state_save_register_UINT16("ide", which, "block_count", &ide->block_count, 1);
323 state_save_register_UINT16("ide", which, "sectors_until_int", &ide->sectors_until_int, 1);
324
325 state_save_register_UINT8 ("ide", which, "dma_active", &ide->dma_active, 1);
326 state_save_register_UINT8 ("ide", which, "dma_cpu", &ide->dma_cpu, 1);
327 state_save_register_UINT8 ("ide", which, "dma_address_xor", &ide->dma_address_xor, 1);
328 state_save_register_UINT8 ("ide", which, "dma_last_buffer", &ide->dma_last_buffer, 1);
329 state_save_register_UINT32("ide", which, "dma_address", &ide->dma_address, 1);
330 state_save_register_UINT32("ide", which, "dma_descriptor", &ide->dma_descriptor, 1);
331 state_save_register_UINT32("ide", which, "dma_bytes_left", &ide->dma_bytes_left, 1);
332
333 state_save_register_UINT8 ("ide", which, "bus_master_command", &ide->bus_master_command, 1);
334 state_save_register_UINT8 ("ide", which, "bus_master_status", &ide->bus_master_status, 1);
335 state_save_register_UINT32("ide", which, "bus_master_descriptor", &ide->bus_master_descriptor, 1);
336
337 state_save_register_UINT16("ide", which, "cur_cylinder", &ide->cur_cylinder, 1);
338 state_save_register_UINT8 ("ide", which, "cur_sector", &ide->cur_sector, 1);
339 state_save_register_UINT8 ("ide", which, "cur_head", &ide->cur_head, 1);
340 state_save_register_UINT8 ("ide", which, "cur_head_reg", &ide->cur_head_reg, 1);
341
342 state_save_register_UINT32("ide", which, "cur_lba", &ide->cur_lba, 1);
343
344 state_save_register_UINT16("ide", which, "num_cylinders", &ide->num_cylinders, 1);
345 state_save_register_UINT8 ("ide", which, "num_sectors", &ide->num_sectors, 1);
346 state_save_register_UINT8 ("ide", which, "num_heads", &ide->num_heads, 1);
347
348 state_save_register_UINT8 ("ide", which, "config_unknown", &ide->config_unknown, 1);
349 state_save_register_UINT8 ("ide", which, "config_register", ide->config_register, IDE_CONFIG_REGISTERS);
350 state_save_register_UINT8 ("ide", which, "config_register_num", &ide->config_register_num, 1);
351
352 state_save_register_int ("ide", which, "master_password_enable", &ide->master_password_enable);
353 state_save_register_int ("ide", which, "user_password_enable", &ide->user_password_enable);
354
355 return 0;
356 }
357
ide_controller_init(int which,struct ide_interface * intf)358 int ide_controller_init(int which, struct ide_interface *intf)
359 {
360 /* we only support one hard disk right now; get a handle to it */
361 return ide_controller_init_custom(which, intf, get_disk_handle(0));
362 }
363
364
ide_controller_reset(int which)365 void ide_controller_reset(int which)
366 {
367 struct ide_state *ide = &idestate[which];
368
369 LOG(("IDE controller reset performed\n"));
370
371 /* reset the drive state */
372 ide->status = IDE_STATUS_DRIVE_READY | IDE_STATUS_SEEK_COMPLETE;
373 ide->error = IDE_ERROR_DEFAULT;
374 ide->buffer_offset = 0;
375 ide->master_password_enable = (ide->master_password != NULL);
376 ide->user_password_enable = (ide->user_password != NULL);
377 clear_interrupt(ide);
378 }
379
380
ide_get_features(int which)381 UINT8 *ide_get_features(int which)
382 {
383 struct ide_state *ide = &idestate[which];
384 return ide->features;
385 }
386
387
ide_set_master_password(int which,UINT8 * password)388 void ide_set_master_password(int which, UINT8 *password)
389 {
390 struct ide_state *ide = &idestate[which];
391
392 ide->master_password = password;
393 ide->master_password_enable = (ide->master_password != NULL);
394 }
395
396
ide_set_user_password(int which,UINT8 * password)397 void ide_set_user_password(int which, UINT8 *password)
398 {
399 struct ide_state *ide = &idestate[which];
400
401 ide->user_password = password;
402 ide->user_password_enable = (ide->user_password != NULL);
403 }
404
405
reset_callback(int param)406 static void reset_callback(int param)
407 {
408 ide_controller_reset(param);
409 }
410
411
412
413 /*************************************
414 *
415 * Convert offset/mem_mask to offset
416 * and size
417 *
418 *************************************/
419
convert_to_offset_and_size32(offs_t * offset,data32_t mem_mask)420 static INLINE int convert_to_offset_and_size32(offs_t *offset, data32_t mem_mask)
421 {
422 int size = 4;
423
424 /* determine which real offset */
425 if (mem_mask & 0x000000ff)
426 {
427 (*offset)++, size = 3;
428 if (mem_mask & 0x0000ff00)
429 {
430 (*offset)++, size = 2;
431 if (mem_mask & 0x00ff0000)
432 (*offset)++, size = 1;
433 }
434 }
435
436 /* determine the real size */
437 if (!(mem_mask & 0xff000000))
438 return size;
439 size--;
440 if (!(mem_mask & 0x00ff0000))
441 return size;
442 size--;
443 if (!(mem_mask & 0x0000ff00))
444 return size;
445 size--;
446 return size;
447 }
448
convert_to_offset_and_size16(offs_t * offset,data32_t mem_mask)449 static INLINE int convert_to_offset_and_size16(offs_t *offset, data32_t mem_mask)
450 {
451 int size = 2;
452
453 /* determine which real offset */
454 if (mem_mask & 0x000000ff)
455 (*offset)++, size = 1;
456
457 if (!(mem_mask & 0x0000ff00))
458 return size;
459 size--;
460 return size;
461 }
462
463
464
465 /*************************************
466 *
467 * Compute the LBA address
468 *
469 *************************************/
470
lba_address(struct ide_state * ide)471 static INLINE UINT32 lba_address(struct ide_state *ide)
472 {
473 /* LBA direct? */
474 if (ide->cur_head_reg & 0x40)
475 return ide->cur_sector + ide->cur_cylinder * 256 + ide->cur_head * 16777216;
476
477 /* standard CHS */
478 else
479 return (ide->cur_cylinder * ide->num_heads + ide->cur_head) * ide->num_sectors + ide->cur_sector - 1;
480 }
481
482
483
484 /*************************************
485 *
486 * Advance to the next sector
487 *
488 *************************************/
489
next_sector(struct ide_state * ide)490 static INLINE void next_sector(struct ide_state *ide)
491 {
492 /* LBA direct? */
493 if (ide->cur_head_reg & 0x40)
494 {
495 ide->cur_sector++;
496 if (ide->cur_sector == 0)
497 {
498 ide->cur_cylinder++;
499 if (ide->cur_cylinder == 0)
500 ide->cur_head++;
501 }
502 }
503
504 /* standard CHS */
505 else
506 {
507 /* sectors are 1-based */
508 ide->cur_sector++;
509 if (ide->cur_sector > ide->num_sectors)
510 {
511 /* heads are 0 based */
512 ide->cur_sector = 1;
513 ide->cur_head++;
514 if (ide->cur_head >= ide->num_heads)
515 {
516 ide->cur_head = 0;
517 ide->cur_cylinder++;
518 }
519 }
520 }
521
522 ide->cur_lba = lba_address(ide);
523 }
524
525
526
527 /*************************************
528 *
529 * Build a features page
530 *
531 *************************************/
532
swap_strncpy(UINT8 * dst,const char * src,int field_size_in_words)533 static void swap_strncpy(UINT8 *dst, const char *src, int field_size_in_words)
534 {
535 int i;
536
537 for (i = 0; i < field_size_in_words * 2 && src[i]; i++)
538 dst[i ^ 1] = src[i];
539 for ( ; i < field_size_in_words; i++)
540 dst[i ^ 1] = ' ';
541 }
542
543
ide_build_features(struct ide_state * ide)544 static void ide_build_features(struct ide_state *ide)
545 {
546 int total_sectors = ide->num_cylinders * ide->num_heads * ide->num_sectors;
547 int sectors_per_track = ide->num_heads * ide->num_sectors;
548
549 memset(ide->buffer, 0, IDE_DISK_SECTOR_SIZE);
550
551 /* basic geometry */
552 ide->features[ 0*2+0] = 0x5a; /* 0: configuration bits */
553 ide->features[ 0*2+1] = 0x04;
554 ide->features[ 1*2+0] = ide->num_cylinders & 0xff; /* 1: logical cylinders */
555 ide->features[ 1*2+1] = ide->num_cylinders >> 8;
556 ide->features[ 2*2+0] = 0; /* 2: reserved */
557 ide->features[ 2*2+1] = 0;
558 ide->features[ 3*2+0] = ide->num_heads & 0xff; /* 3: logical heads */
559 ide->features[ 3*2+1] = ide->num_heads >> 8;
560 ide->features[ 4*2+0] = 0; /* 4: vendor specific (obsolete) */
561 ide->features[ 4*2+1] = 0;
562 ide->features[ 5*2+0] = 0; /* 5: vendor specific (obsolete) */
563 ide->features[ 5*2+1] = 0;
564 ide->features[ 6*2+0] = ide->num_sectors & 0xff; /* 6: logical sectors per logical track */
565 ide->features[ 6*2+1] = ide->num_sectors >> 8;
566 ide->features[ 7*2+0] = 0; /* 7: vendor-specific */
567 ide->features[ 7*2+1] = 0;
568 ide->features[ 8*2+0] = 0; /* 8: vendor-specific */
569 ide->features[ 8*2+1] = 0;
570 ide->features[ 9*2+0] = 0; /* 9: vendor-specific */
571 ide->features[ 9*2+1] = 0;
572 swap_strncpy(&ide->features[10*2+0], /* 10-19: serial number */
573 "00000000000000000000", 10);
574 ide->features[20*2+0] = 0; /* 20: vendor-specific */
575 ide->features[20*2+1] = 0;
576 ide->features[21*2+0] = 0; /* 21: vendor-specific */
577 ide->features[21*2+1] = 0;
578 ide->features[22*2+0] = 4; /* 22: # of vendor-specific bytes on read/write long commands */
579 ide->features[22*2+1] = 0;
580 swap_strncpy(&ide->features[23*2+0], /* 23-26: firmware revision */
581 "1.0", 4);
582 swap_strncpy(&ide->features[27*2+0], /* 27-46: model number */
583 "MAME Compressed Hard Disk", 20);
584 ide->features[47*2+0] = 0x01; /* 47: read/write multiple support */
585 ide->features[47*2+1] = 0x80;
586 ide->features[48*2+0] = 0; /* 48: reserved */
587 ide->features[48*2+1] = 0;
588 ide->features[49*2+0] = 0x03; /* 49: capabilities */
589 ide->features[49*2+1] = 0x0f;
590 ide->features[50*2+0] = 0; /* 50: reserved */
591 ide->features[50*2+1] = 0;
592 ide->features[51*2+0] = 2; /* 51: PIO data transfer cycle timing mode */
593 ide->features[51*2+1] = 0;
594 ide->features[52*2+0] = 2; /* 52: single word DMA transfer cycle timing mode */
595 ide->features[52*2+1] = 0;
596 ide->features[53*2+0] = 3; /* 53: field validity */
597 ide->features[53*2+1] = 0;
598 ide->features[54*2+0] = ide->num_cylinders & 0xff; /* 54: number of current logical cylinders */
599 ide->features[54*2+1] = ide->num_cylinders >> 8;
600 ide->features[55*2+0] = ide->num_heads & 0xff; /* 55: number of current logical heads */
601 ide->features[55*2+1] = ide->num_heads >> 8;
602 ide->features[56*2+0] = ide->num_sectors & 0xff; /* 56: number of current logical sectors per track */
603 ide->features[56*2+1] = ide->num_sectors >> 8;
604 ide->features[57*2+0] = sectors_per_track & 0xff; /* 57-58: number of current logical sectors per track */
605 ide->features[57*2+1] = sectors_per_track >> 8;
606 ide->features[58*2+0] = sectors_per_track >> 16;
607 ide->features[58*2+1] = sectors_per_track >> 24;
608 ide->features[59*2+0] = 0; /* 59: multiple sector timing */
609 ide->features[59*2+1] = 0;
610 ide->features[60*2+0] = total_sectors & 0xff; /* 60-61: total user addressable sectors */
611 ide->features[60*2+1] = total_sectors >> 8;
612 ide->features[61*2+0] = total_sectors >> 16;
613 ide->features[61*2+1] = total_sectors >> 24;
614 ide->features[62*2+0] = 0x07; /* 62: single word dma transfer */
615 ide->features[62*2+1] = 0x00;
616 ide->features[63*2+0] = 0x07; /* 63: multiword DMA transfer */
617 ide->features[63*2+1] = 0x04;
618 ide->features[64*2+0] = 0x03; /* 64: flow control PIO transfer modes supported */
619 ide->features[64*2+1] = 0x00;
620 ide->features[65*2+0] = 0x78; /* 65: minimum multiword DMA transfer cycle time per word */
621 ide->features[65*2+1] = 0x00;
622 ide->features[66*2+0] = 0x78; /* 66: mfr's recommended multiword DMA transfer cycle time */
623 ide->features[66*2+1] = 0x00;
624 ide->features[67*2+0] = 0x4d; /* 67: minimum PIO transfer cycle time without flow control */
625 ide->features[67*2+1] = 0x01;
626 ide->features[68*2+0] = 0x78; /* 68: minimum PIO transfer cycle time with IORDY */
627 ide->features[68*2+1] = 0x00;
628 ide->features[69*2+0] = 0x00; /* 69-70: reserved */
629 ide->features[69*2+1] = 0x00;
630 ide->features[71*2+0] = 0x00; /* 71: reserved for IDENTIFY PACKET command */
631 ide->features[71*2+1] = 0x00;
632 ide->features[72*2+0] = 0x00; /* 72: reserved for IDENTIFY PACKET command */
633 ide->features[72*2+1] = 0x00;
634 ide->features[73*2+0] = 0x00; /* 73: reserved for IDENTIFY PACKET command */
635 ide->features[73*2+1] = 0x00;
636 ide->features[74*2+0] = 0x00; /* 74: reserved for IDENTIFY PACKET command */
637 ide->features[74*2+1] = 0x00;
638 ide->features[75*2+0] = 0x00; /* 75: queue depth */
639 ide->features[75*2+1] = 0x00;
640 ide->features[76*2+0] = 0x00; /* 76-79: reserved */
641 ide->features[76*2+1] = 0x00;
642 ide->features[80*2+0] = 0x00; /* 80: major version number */
643 ide->features[80*2+1] = 0x00;
644 ide->features[81*2+0] = 0x00; /* 81: minor version number */
645 ide->features[81*2+1] = 0x00;
646 ide->features[82*2+0] = 0x00; /* 82: command set supported */
647 ide->features[82*2+1] = 0x00;
648 ide->features[83*2+0] = 0x00; /* 83: command sets supported */
649 ide->features[83*2+1] = 0x00;
650 ide->features[84*2+0] = 0x00; /* 84: command set/feature supported extension */
651 ide->features[84*2+1] = 0x00;
652 ide->features[85*2+0] = 0x00; /* 85: command set/feature enabled */
653 ide->features[85*2+1] = 0x00;
654 ide->features[86*2+0] = 0x00; /* 86: command set/feature enabled */
655 ide->features[86*2+1] = 0x00;
656 ide->features[87*2+0] = 0x00; /* 87: command set/feature default */
657 ide->features[87*2+1] = 0x00;
658 ide->features[88*2+0] = 0x00; /* 88: additional DMA modes */
659 ide->features[88*2+1] = 0x00;
660 ide->features[89*2+0] = 0x00; /* 89: time required for security erase unit completion */
661 ide->features[89*2+1] = 0x00;
662 ide->features[90*2+0] = 0x00; /* 90: time required for enhanced security erase unit completion */
663 ide->features[90*2+1] = 0x00;
664 ide->features[91*2+0] = 0x00; /* 91: current advanced power management value */
665 ide->features[91*2+1] = 0x00;
666 ide->features[92*2+0] = 0x00; /* 92: master password revision code */
667 ide->features[92*2+1] = 0x00;
668 ide->features[93*2+0] = 0x00; /* 93: hardware reset result */
669 ide->features[93*2+1] = 0x00;
670 ide->features[94*2+0] = 0x00; /* 94: acoustic management values */
671 ide->features[94*2+1] = 0x00;
672 ide->features[95*2+0] = 0x00; /* 95-99: reserved */
673 ide->features[95*2+1] = 0x00;
674 ide->features[100*2+0] = total_sectors & 0xff; /* 100-103: maximum 48-bit LBA */
675 ide->features[100*2+1] = total_sectors >> 8;
676 ide->features[101*2+0] = total_sectors >> 16;
677 ide->features[101*2+1] = total_sectors >> 24;
678 ide->features[102*2+0] = 0x00;
679 ide->features[102*2+1] = 0x00;
680 ide->features[103*2+0] = 0x00;
681 ide->features[103*2+1] = 0x00;
682 ide->features[104*2+0] = 0x00; /* 104-126: reserved */
683 ide->features[104*2+1] = 0x00;
684 ide->features[127*2+0] = 0x00; /* 127: removable media status notification */
685 ide->features[127*2+1] = 0x00;
686 ide->features[128*2+0] = 0x00; /* 128: security status */
687 ide->features[128*2+1] = 0x00;
688 ide->features[129*2+0] = 0x00; /* 129-159: vendor specific */
689 ide->features[129*2+1] = 0x00;
690 ide->features[160*2+0] = 0x00; /* 160: CFA power mode 1 */
691 ide->features[160*2+1] = 0x00;
692 ide->features[161*2+0] = 0x00; /* 161-175: reserved for CompactFlash */
693 ide->features[161*2+1] = 0x00;
694 ide->features[176*2+0] = 0x00; /* 176-205: current media serial number */
695 ide->features[176*2+1] = 0x00;
696 ide->features[206*2+0] = 0x00; /* 206-254: reserved */
697 ide->features[206*2+1] = 0x00;
698 ide->features[255*2+0] = 0x00; /* 255: integrity word */
699 ide->features[255*2+1] = 0x00;
700 }
701
702
703
704 /*************************************
705 *
706 * security error handling
707 *
708 *************************************/
709
security_error_done(int which)710 static void security_error_done(int which)
711 {
712 struct ide_state *ide = &idestate[which];
713
714 /* clear error state */
715 ide->status &= ~IDE_STATUS_ERROR;
716 ide->status |= IDE_STATUS_DRIVE_READY;
717 }
718
security_error(struct ide_state * ide)719 static void security_error(struct ide_state *ide)
720 {
721 /* set error state */
722 ide->status |= IDE_STATUS_ERROR;
723 ide->status &= ~IDE_STATUS_DRIVE_READY;
724
725 /* just set a timer and mark ourselves error */
726 timer_set(TIME_SECURITY_ERROR, ide - idestate, security_error_done);
727 }
728
729
730
731 /*************************************
732 *
733 * Sector reading
734 *
735 *************************************/
736
continue_read(struct ide_state * ide)737 static void continue_read(struct ide_state *ide)
738 {
739 /* reset the totals */
740 ide->buffer_offset = 0;
741
742 /* clear the buffer ready flag */
743 ide->status &= ~IDE_STATUS_BUFFER_READY;
744
745 if (ide->master_password_enable || ide->user_password_enable)
746 {
747 security_error(ide);
748
749 ide->sector_count = 0;
750 ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
751 ide->dma_active = 0;
752
753 return;
754 }
755
756 /* if there is more data to read, keep going */
757 if (ide->sector_count > 0)
758 ide->sector_count--;
759 if (ide->sector_count > 0)
760 read_next_sector(ide);
761 else
762 {
763 ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
764 ide->dma_active = 0;
765 }
766 }
767
768
write_buffer_to_dma(struct ide_state * ide)769 static void write_buffer_to_dma(struct ide_state *ide)
770 {
771 int bytesleft = IDE_DISK_SECTOR_SIZE;
772 UINT8 *data = ide->buffer;
773
774 // LOG(("Writing sector to %08X\n", ide->dma_address));
775
776 /* loop until we've consumed all bytes */
777 while (bytesleft--)
778 {
779 /* if we're out of space, grab the next descriptor */
780 if (ide->dma_bytes_left == 0)
781 {
782 /* if we're out of buffer space, that's bad */
783 if (ide->dma_last_buffer)
784 {
785 LOG(("DMA Out of buffer space!\n"));
786 return;
787 }
788
789 /* fetch the address */
790 ide->dma_address = cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor);
791 ide->dma_address |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 8;
792 ide->dma_address |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 16;
793 ide->dma_address |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 24;
794 ide->dma_address &= 0xfffffffe;
795
796 /* fetch the length */
797 ide->dma_bytes_left = cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor);
798 ide->dma_bytes_left |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 8;
799 ide->dma_bytes_left |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 16;
800 ide->dma_bytes_left |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 24;
801 ide->dma_last_buffer = (ide->dma_bytes_left >> 31) & 1;
802 ide->dma_bytes_left &= 0xfffe;
803 if (ide->dma_bytes_left == 0)
804 ide->dma_bytes_left = 0x10000;
805
806 // LOG(("New DMA descriptor: address = %08X bytes = %04X last = %d\n", ide->dma_address, ide->dma_bytes_left, ide->dma_last_buffer));
807 }
808
809 /* write the next byte */
810 cpunum_write_byte(ide->dma_cpu, ide->dma_address++, *data++);
811 ide->dma_bytes_left--;
812 }
813 }
814
815
read_sector_done(int which)816 static void read_sector_done(int which)
817 {
818 struct ide_state *ide = &idestate[which];
819 int lba = lba_address(ide), count = 0;
820
821 /* now do the read */
822 if (ide->disk)
823 count = hard_disk_read(ide->disk, lba, 1, ide->buffer);
824
825 /* by default, mark the buffer ready and the seek complete */
826 ide->status |= IDE_STATUS_BUFFER_READY;
827 ide->status |= IDE_STATUS_SEEK_COMPLETE;
828
829 /* and clear the busy adn error flags */
830 ide->status &= ~IDE_STATUS_ERROR;
831 ide->status &= ~IDE_STATUS_BUSY;
832
833 /* if we succeeded, advance to the next sector and set the nice bits */
834 if (count == 1)
835 {
836 /* advance the pointers, unless this is the last sector */
837 /* Gauntlet: Dark Legacy checks to make sure we stop on the last sector */
838 if (ide->sector_count != 1)
839 next_sector(ide);
840
841 /* clear the error value */
842 ide->error = IDE_ERROR_NONE;
843
844 /* signal an interrupt */
845 if (--ide->sectors_until_int == 0 || ide->sector_count == 1)
846 {
847 ide->sectors_until_int = ((ide->command == IDE_COMMAND_READ_MULTIPLE_BLOCK) ? ide->block_count : 1);
848 signal_interrupt(ide);
849 }
850
851 /* keep going for DMA */
852 if (ide->dma_active)
853 {
854 write_buffer_to_dma(ide);
855 continue_read(ide);
856 }
857 }
858
859 /* if we got an error, we need to report it */
860 else
861 {
862 /* set the error flag and the error */
863 ide->status |= IDE_STATUS_ERROR;
864 ide->error = IDE_ERROR_BAD_SECTOR;
865 ide->bus_master_status |= IDE_BUSMASTER_STATUS_ERROR;
866 ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
867
868 /* signal an interrupt */
869 signal_interrupt(ide);
870 }
871 }
872
873
read_first_sector(struct ide_state * ide)874 static void read_first_sector(struct ide_state *ide)
875 {
876 /* mark ourselves busy */
877 ide->status |= IDE_STATUS_BUSY;
878
879 /* just set a timer */
880 if (ide->command == IDE_COMMAND_READ_MULTIPLE_BLOCK)
881 {
882 double seek_time;
883
884 if (ide->cur_lba == lba_address(ide))
885 seek_time = TIME_NO_SEEK_MULTISECTOR;
886 else
887 seek_time = TIME_SEEK_MULTISECTOR;
888
889 timer_set(seek_time, ide - idestate, read_sector_done);
890 }
891 else
892 timer_set(TIME_PER_SECTOR, ide - idestate, read_sector_done);
893 }
894
895
read_next_sector(struct ide_state * ide)896 static void read_next_sector(struct ide_state *ide)
897 {
898 /* mark ourselves busy */
899 ide->status |= IDE_STATUS_BUSY;
900
901 if (ide->command == IDE_COMMAND_READ_MULTIPLE_BLOCK)
902 {
903 if (ide->sectors_until_int != 1)
904 /* make ready now */
905 read_sector_done(ide - idestate);
906 else
907 /* just set a timer */
908 timer_set(TIME_IN_USEC(1), ide - idestate, read_sector_done);
909 }
910 else
911 /* just set a timer */
912 timer_set(TIME_PER_SECTOR, ide - idestate, read_sector_done);
913 }
914
915
916
917 /*************************************
918 *
919 * Sector writing
920 *
921 *************************************/
922
923 static void write_sector_done(int which);
924
continue_write(struct ide_state * ide)925 static void continue_write(struct ide_state *ide)
926 {
927 /* reset the totals */
928 ide->buffer_offset = 0;
929
930 /* clear the buffer ready flag */
931 ide->status &= ~IDE_STATUS_BUFFER_READY;
932 ide->status |= IDE_STATUS_BUSY;
933
934 if (ide->command == IDE_COMMAND_WRITE_MULTIPLE_BLOCK)
935 {
936 if (ide->sectors_until_int != 1)
937 {
938 /* ready to write now */
939 write_sector_done(ide - idestate);
940 }
941 else
942 {
943 /* set a timer to do the write */
944 timer_set(TIME_PER_SECTOR, ide - idestate, write_sector_done);
945 }
946 }
947 else
948 {
949 /* set a timer to do the write */
950 timer_set(TIME_PER_SECTOR, ide - idestate, write_sector_done);
951 }
952 }
953
954
read_buffer_from_dma(struct ide_state * ide)955 static void read_buffer_from_dma(struct ide_state *ide)
956 {
957 int bytesleft = IDE_DISK_SECTOR_SIZE;
958 UINT8 *data = ide->buffer;
959
960 // LOG(("Reading sector from %08X\n", ide->dma_address));
961
962 /* loop until we've consumed all bytes */
963 while (bytesleft--)
964 {
965 /* if we're out of space, grab the next descriptor */
966 if (ide->dma_bytes_left == 0)
967 {
968 /* if we're out of buffer space, that's bad */
969 if (ide->dma_last_buffer)
970 {
971 LOG(("DMA Out of buffer space!\n"));
972 return;
973 }
974
975 /* fetch the address */
976 ide->dma_address = cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor);
977 ide->dma_address |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 8;
978 ide->dma_address |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 16;
979 ide->dma_address |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 24;
980 ide->dma_address &= 0xfffffffe;
981
982 /* fetch the length */
983 ide->dma_bytes_left = cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor);
984 ide->dma_bytes_left |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 8;
985 ide->dma_bytes_left |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 16;
986 ide->dma_bytes_left |= cpunum_read_byte(ide->dma_cpu, ide->dma_descriptor++ ^ ide->dma_address_xor) << 24;
987 ide->dma_last_buffer = (ide->dma_bytes_left >> 31) & 1;
988 ide->dma_bytes_left &= 0xfffe;
989 if (ide->dma_bytes_left == 0)
990 ide->dma_bytes_left = 0x10000;
991
992 // LOG(("New DMA descriptor: address = %08X bytes = %04X last = %d\n", ide->dma_address, ide->dma_bytes_left, ide->dma_last_buffer));
993 }
994
995 /* read the next byte */
996 *data++ = cpunum_read_byte(ide->dma_cpu, ide->dma_address++);
997 ide->dma_bytes_left--;
998 }
999 }
1000
1001
write_sector_done(int which)1002 static void write_sector_done(int which)
1003 {
1004 struct ide_state *ide = &idestate[which];
1005 int lba = lba_address(ide), count = 0;
1006
1007 /* now do the write */
1008 if (ide->disk)
1009 count = hard_disk_write(ide->disk, lba, 1, ide->buffer);
1010
1011 /* by default, mark the buffer ready and the seek complete */
1012 ide->status |= IDE_STATUS_BUFFER_READY;
1013 ide->status |= IDE_STATUS_SEEK_COMPLETE;
1014
1015 /* and clear the busy adn error flags */
1016 ide->status &= ~IDE_STATUS_ERROR;
1017 ide->status &= ~IDE_STATUS_BUSY;
1018
1019 /* if we succeeded, advance to the next sector and set the nice bits */
1020 if (count == 1)
1021 {
1022 /* advance the pointers, unless this is the last sector */
1023 /* Gauntlet: Dark Legacy checks to make sure we stop on the last sector */
1024 if (ide->sector_count != 1)
1025 next_sector(ide);
1026
1027 /* clear the error value */
1028 ide->error = IDE_ERROR_NONE;
1029
1030 /* signal an interrupt */
1031 if (--ide->sectors_until_int == 0 || ide->sector_count == 1)
1032 {
1033 ide->sectors_until_int = ((ide->command == IDE_COMMAND_WRITE_MULTIPLE_BLOCK) ? ide->block_count : 1);
1034 signal_interrupt(ide);
1035 }
1036
1037 /* signal an interrupt if there's more data needed */
1038 if (ide->sector_count > 0)
1039 ide->sector_count--;
1040 if (ide->sector_count == 0)
1041 ide->status &= ~IDE_STATUS_BUFFER_READY;
1042
1043 /* keep going for DMA */
1044 if (ide->dma_active && ide->sector_count != 0)
1045 {
1046 read_buffer_from_dma(ide);
1047 continue_write(ide);
1048 }
1049 else
1050 ide->dma_active = 0;
1051 }
1052
1053 /* if we got an error, we need to report it */
1054 else
1055 {
1056 /* set the error flag and the error */
1057 ide->status |= IDE_STATUS_ERROR;
1058 ide->error = IDE_ERROR_BAD_SECTOR;
1059 ide->bus_master_status |= IDE_BUSMASTER_STATUS_ERROR;
1060 ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ACTIVE;
1061
1062 /* signal an interrupt */
1063 signal_interrupt(ide);
1064 }
1065 }
1066
1067
1068
1069 /*************************************
1070 *
1071 * Handle IDE commands
1072 *
1073 *************************************/
1074
handle_command(struct ide_state * ide,UINT8 command)1075 void handle_command(struct ide_state *ide, UINT8 command)
1076 {
1077 /* implicitly clear interrupts here */
1078 clear_interrupt(ide);
1079
1080 ide->command = command;
1081 switch (command)
1082 {
1083 case IDE_COMMAND_READ_MULTIPLE:
1084 case IDE_COMMAND_READ_MULTIPLE_ONCE:
1085 LOGPRINT(("IDE Read multiple: C=%d H=%d S=%d LBA=%d count=%d\n",
1086 ide->cur_cylinder, ide->cur_head, ide->cur_sector, lba_address(ide), ide->sector_count));
1087
1088 /* reset the buffer */
1089 ide->buffer_offset = 0;
1090 ide->sectors_until_int = 1;
1091 ide->dma_active = 0;
1092
1093 /* start the read going */
1094 read_first_sector(ide);
1095 break;
1096
1097 case IDE_COMMAND_READ_MULTIPLE_BLOCK:
1098 LOGPRINT(("IDE Read multiple block: C=%d H=%d S=%d LBA=%d count=%d\n",
1099 ide->cur_cylinder, ide->cur_head, ide->cur_sector, lba_address(ide), ide->sector_count));
1100
1101 /* reset the buffer */
1102 ide->buffer_offset = 0;
1103 ide->sectors_until_int = 1;
1104 ide->dma_active = 0;
1105
1106 /* start the read going */
1107 read_first_sector(ide);
1108 break;
1109
1110 case IDE_COMMAND_READ_DMA:
1111 LOGPRINT(("IDE Read multiple DMA: C=%d H=%d S=%d LBA=%d count=%d\n",
1112 ide->cur_cylinder, ide->cur_head, ide->cur_sector, lba_address(ide), ide->sector_count));
1113
1114 /* reset the buffer */
1115 ide->buffer_offset = 0;
1116 ide->sectors_until_int = ide->sector_count;
1117 ide->dma_active = 1;
1118
1119 /* start the read going */
1120 if (ide->bus_master_command & 1)
1121 read_first_sector(ide);
1122 break;
1123
1124 case IDE_COMMAND_WRITE_MULTIPLE:
1125 LOGPRINT(("IDE Write multiple: C=%d H=%d S=%d LBA=%d count=%d\n",
1126 ide->cur_cylinder, ide->cur_head, ide->cur_sector, lba_address(ide), ide->sector_count));
1127
1128 /* reset the buffer */
1129 ide->buffer_offset = 0;
1130 ide->sectors_until_int = 1;
1131 ide->dma_active = 0;
1132
1133 /* mark the buffer ready */
1134 ide->status |= IDE_STATUS_BUFFER_READY;
1135 break;
1136
1137 case IDE_COMMAND_WRITE_MULTIPLE_BLOCK:
1138 LOGPRINT(("IDE Write multiple block: C=%d H=%d S=%d LBA=%d count=%d\n",
1139 ide->cur_cylinder, ide->cur_head, ide->cur_sector, lba_address(ide), ide->sector_count));
1140
1141 /* reset the buffer */
1142 ide->buffer_offset = 0;
1143 ide->sectors_until_int = 1;
1144 ide->dma_active = 0;
1145
1146 /* mark the buffer ready */
1147 ide->status |= IDE_STATUS_BUFFER_READY;
1148 break;
1149
1150 case IDE_COMMAND_WRITE_DMA:
1151 LOGPRINT(("IDE Write multiple DMA: C=%d H=%d S=%d LBA=%d count=%d\n",
1152 ide->cur_cylinder, ide->cur_head, ide->cur_sector, lba_address(ide), ide->sector_count));
1153
1154 /* reset the buffer */
1155 ide->buffer_offset = 0;
1156 ide->sectors_until_int = ide->sector_count;
1157 ide->dma_active = 1;
1158
1159 /* start the read going */
1160 if (ide->bus_master_command & 1)
1161 {
1162 read_buffer_from_dma(ide);
1163 continue_write(ide);
1164 }
1165 break;
1166
1167 case IDE_COMMAND_SECURITY_UNLOCK:
1168 LOGPRINT(("IDE Security Unlock\n"));
1169
1170 /* reset the buffer */
1171 ide->buffer_offset = 0;
1172 ide->sectors_until_int = 0;
1173 ide->dma_active = 0;
1174
1175 /* mark the buffer ready */
1176 ide->status |= IDE_STATUS_BUFFER_READY;
1177 signal_interrupt(ide);
1178 break;
1179
1180 case IDE_COMMAND_GET_INFO:
1181 LOGPRINT(("IDE Read features\n"));
1182
1183 /* reset the buffer */
1184 ide->buffer_offset = 0;
1185 ide->sector_count = 1;
1186
1187 /* build the features page */
1188 memcpy(ide->buffer, ide->features, sizeof(ide->buffer));
1189
1190 /* indicate everything is ready */
1191 ide->status |= IDE_STATUS_BUFFER_READY;
1192 ide->status |= IDE_STATUS_SEEK_COMPLETE;
1193
1194 /* and clear the busy adn error flags */
1195 ide->status &= ~IDE_STATUS_ERROR;
1196 ide->status &= ~IDE_STATUS_BUSY;
1197
1198 /* clear the error too */
1199 ide->error = IDE_ERROR_NONE;
1200
1201 /* signal an interrupt */
1202 signal_delayed_interrupt(ide, MINIMUM_COMMAND_TIME, 1);
1203 break;
1204
1205 case IDE_COMMAND_SET_CONFIG:
1206 LOGPRINT(("IDE Set configuration (%d heads, %d sectors)\n", ide->cur_head + 1, ide->sector_count));
1207
1208 ide->num_sectors = ide->sector_count;
1209 ide->num_heads = ide->cur_head + 1;
1210
1211 /* signal an interrupt */
1212 signal_interrupt(ide);
1213 break;
1214
1215 case IDE_COMMAND_UNKNOWN_F9:
1216 /* only used by Killer Instinct AFAICT */
1217 LOGPRINT(("IDE unknown command (F9)\n"));
1218
1219 /* signal an interrupt */
1220 signal_interrupt(ide);
1221 break;
1222
1223 case IDE_COMMAND_SET_FEATURES:
1224 LOGPRINT(("IDE Set features (%02X %02X %02X %02X %02X)\n", ide->precomp_offset, ide->sector_count & 0xff, ide->cur_sector, ide->cur_cylinder & 0xff, ide->cur_cylinder >> 8));
1225
1226 /* signal an interrupt */
1227 signal_delayed_interrupt(ide, MINIMUM_COMMAND_TIME, 0);
1228 break;
1229
1230 case IDE_COMMAND_SET_BLOCK_COUNT:
1231 LOGPRINT(("IDE Set block count (%02X)\n", ide->sector_count));
1232
1233 ide->block_count = ide->sector_count;
1234
1235 /* signal an interrupt */
1236 signal_interrupt(ide);
1237 break;
1238
1239 default:
1240 LOGPRINT(("IDE unknown command (%02X)\n", command));
1241 #ifdef MAME_DEBUG
1242 {
1243 extern int debug_key_pressed;
1244 debug_key_pressed = 1;
1245 }
1246 #endif
1247 break;
1248 }
1249 }
1250
1251
1252
1253 /*************************************
1254 *
1255 * IDE controller read
1256 *
1257 *************************************/
1258
ide_controller_read(struct ide_state * ide,offs_t offset,int size)1259 static UINT32 ide_controller_read(struct ide_state *ide, offs_t offset, int size)
1260 {
1261 UINT32 result = 0;
1262
1263 /* logit */
1264 if (offset != IDE_ADDR_DATA && offset != IDE_ADDR_STATUS_COMMAND && offset != IDE_ADDR_STATUS_CONTROL)
1265 LOG(("%08X:IDE read at %03X, size=%d\n", activecpu_get_previouspc(), offset, size));
1266
1267 switch (offset)
1268 {
1269 /* unknown config register */
1270 case IDE_ADDR_CONFIG_UNK:
1271 return ide->config_unknown;
1272
1273 /* active config register */
1274 case IDE_ADDR_CONFIG_REGISTER:
1275 return ide->config_register_num;
1276
1277 /* data from active config register */
1278 case IDE_ADDR_CONFIG_DATA:
1279 if (ide->config_register_num < IDE_CONFIG_REGISTERS)
1280 return ide->config_register[ide->config_register_num];
1281 return 0;
1282
1283 /* read data if there's data to be read */
1284 case IDE_ADDR_DATA:
1285 if (ide->status & IDE_STATUS_BUFFER_READY)
1286 {
1287 /* fetch the correct amount of data */
1288 result = ide->buffer[ide->buffer_offset++];
1289 if (size > 1)
1290 result |= ide->buffer[ide->buffer_offset++] << 8;
1291 if (size > 2)
1292 {
1293 result |= ide->buffer[ide->buffer_offset++] << 16;
1294 result |= ide->buffer[ide->buffer_offset++] << 24;
1295 }
1296
1297 /* if we're at the end of the buffer, handle it */
1298 if (ide->buffer_offset >= IDE_DISK_SECTOR_SIZE)
1299 continue_read(ide);
1300 }
1301 break;
1302
1303 /* return the current error */
1304 case IDE_ADDR_ERROR:
1305 return ide->error;
1306
1307 /* return the current sector count */
1308 case IDE_ADDR_SECTOR_COUNT:
1309 return ide->sector_count;
1310
1311 /* return the current sector */
1312 case IDE_ADDR_SECTOR_NUMBER:
1313 return ide->cur_sector;
1314
1315 /* return the current cylinder LSB */
1316 case IDE_ADDR_CYLINDER_LSB:
1317 return ide->cur_cylinder & 0xff;
1318
1319 /* return the current cylinder MSB */
1320 case IDE_ADDR_CYLINDER_MSB:
1321 return ide->cur_cylinder >> 8;
1322
1323 /* return the current head */
1324 case IDE_ADDR_HEAD_NUMBER:
1325 return ide->cur_head_reg;
1326
1327 /* return the current status and clear any pending interrupts */
1328 case IDE_ADDR_STATUS_COMMAND:
1329 /* return the current status but don't clear interrupts */
1330 case IDE_ADDR_STATUS_CONTROL:
1331 result = ide->status;
1332 if (timer_timeelapsed(ide->last_status_timer) > TIME_PER_ROTATION)
1333 {
1334 result |= IDE_STATUS_HIT_INDEX;
1335 timer_adjust(ide->last_status_timer, TIME_NEVER, 0, 0);
1336 }
1337
1338 /* clear interrutps only when reading the real status */
1339 if (offset == IDE_ADDR_STATUS_COMMAND)
1340 {
1341 if (ide->interrupt_pending)
1342 clear_interrupt(ide);
1343 }
1344
1345 /* take a bit of time to speed up people who poll hard */
1346 activecpu_adjust_icount(-100);
1347 break;
1348
1349 /* log anything else */
1350 default:
1351 logerror("%08X:unknown IDE read at %03X, size=%d\n", activecpu_get_previouspc(), offset, size);
1352 break;
1353 }
1354
1355 /* return the result */
1356 return result;
1357 }
1358
1359
1360
1361 /*************************************
1362 *
1363 * IDE controller write
1364 *
1365 *************************************/
1366
ide_controller_write(struct ide_state * ide,offs_t offset,int size,UINT32 data)1367 static void ide_controller_write(struct ide_state *ide, offs_t offset, int size, UINT32 data)
1368 {
1369 /* logit */
1370 if (offset != IDE_ADDR_DATA)
1371 LOG(("%08X:IDE write to %03X = %08X, size=%d\n", activecpu_get_previouspc(), offset, data, size));
1372
1373 switch (offset)
1374 {
1375 /* unknown config register */
1376 case IDE_ADDR_CONFIG_UNK:
1377 ide->config_unknown = data;
1378 break;
1379
1380 /* active config register */
1381 case IDE_ADDR_CONFIG_REGISTER:
1382 ide->config_register_num = data;
1383 break;
1384
1385 /* data from active config register */
1386 case IDE_ADDR_CONFIG_DATA:
1387 if (ide->config_register_num < IDE_CONFIG_REGISTERS)
1388 ide->config_register[ide->config_register_num] = data;
1389 break;
1390
1391 /* write data */
1392 case IDE_ADDR_DATA:
1393 if (ide->status & IDE_STATUS_BUFFER_READY)
1394 {
1395 /* store the correct amount of data */
1396 ide->buffer[ide->buffer_offset++] = data;
1397 if (size > 1)
1398 ide->buffer[ide->buffer_offset++] = data >> 8;
1399 if (size > 2)
1400 {
1401 ide->buffer[ide->buffer_offset++] = data >> 16;
1402 ide->buffer[ide->buffer_offset++] = data >> 24;
1403 }
1404
1405 /* if we're at the end of the buffer, handle it */
1406 if (ide->buffer_offset >= IDE_DISK_SECTOR_SIZE)
1407 {
1408 if (ide->command != IDE_COMMAND_SECURITY_UNLOCK)
1409 continue_write(ide);
1410 else
1411 {
1412 if (ide->user_password_enable && memcmp(ide->buffer, ide->user_password, 2 + 32) == 0)
1413 {
1414 LOGPRINT(("IDE Unlocked user password\n"));
1415 ide->user_password_enable = 0;
1416 }
1417 if (ide->master_password_enable && memcmp(ide->buffer, ide->master_password, 2 + 32) == 0)
1418 {
1419 LOGPRINT(("IDE Unlocked master password\n"));
1420 ide->master_password_enable = 0;
1421 }
1422 #if PRINTF_IDE_PASSWORD
1423 {
1424 int i;
1425
1426 for (i = 0; i < 34; i += 2)
1427 {
1428 if (i % 8 == 2)
1429 printf("\n");
1430
1431 printf("0x%02x, 0x%02x, ", ide->buffer[i], ide->buffer[i + 1]);
1432 //printf("0x%02x%02x, ", ide->buffer[i], ide->buffer[i + 1]);
1433 }
1434 printf("\n");
1435 }
1436 #endif
1437
1438 /* clear the busy adn error flags */
1439 ide->status &= ~IDE_STATUS_ERROR;
1440 ide->status &= ~IDE_STATUS_BUSY;
1441 ide->status &= ~IDE_STATUS_BUFFER_READY;
1442
1443 if (ide->master_password_enable || ide->user_password_enable)
1444 security_error(ide);
1445 else
1446 ide->status |= IDE_STATUS_DRIVE_READY;
1447 }
1448 }
1449 }
1450 break;
1451
1452 /* precompensation offset?? */
1453 case IDE_ADDR_ERROR:
1454 ide->precomp_offset = data;
1455 break;
1456
1457 /* sector count */
1458 case IDE_ADDR_SECTOR_COUNT:
1459 ide->sector_count = data ? data : 256;
1460 break;
1461
1462 /* current sector */
1463 case IDE_ADDR_SECTOR_NUMBER:
1464 ide->cur_sector = data;
1465 break;
1466
1467 /* current cylinder LSB */
1468 case IDE_ADDR_CYLINDER_LSB:
1469 ide->cur_cylinder = (ide->cur_cylinder & 0xff00) | (data & 0xff);
1470 break;
1471
1472 /* current cylinder MSB */
1473 case IDE_ADDR_CYLINDER_MSB:
1474 ide->cur_cylinder = (ide->cur_cylinder & 0x00ff) | ((data & 0xff) << 8);
1475 break;
1476
1477 /* current head */
1478 case IDE_ADDR_HEAD_NUMBER:
1479 ide->cur_head = data & 0x0f;
1480 ide->cur_head_reg = data;
1481 // drive index = data & 0x10
1482 // LBA mode = data & 0x40
1483 break;
1484
1485 /* command */
1486 case IDE_ADDR_STATUS_COMMAND:
1487 handle_command(ide, data);
1488 break;
1489
1490 /* adapter control */
1491 case IDE_ADDR_STATUS_CONTROL:
1492 ide->adapter_control = data;
1493
1494 /* handle controller reset */
1495 //if (data == 0x04)
1496 if (data & 0x04)
1497 {
1498 ide->status |= IDE_STATUS_BUSY;
1499 ide->status &= ~IDE_STATUS_DRIVE_READY;
1500 timer_adjust(ide->reset_timer, TIME_IN_MSEC(5), ide - idestate, 0);
1501 }
1502 break;
1503 }
1504 }
1505
1506
1507
1508 /*************************************
1509 *
1510 * Bus master read
1511 *
1512 *************************************/
1513
ide_bus_master_read(struct ide_state * ide,offs_t offset,int size)1514 static UINT32 ide_bus_master_read(struct ide_state *ide, offs_t offset, int size)
1515 {
1516 LOG(("%08X:ide_bus_master_read(%d, %d)\n", activecpu_get_previouspc(), offset, size));
1517
1518 /* command register */
1519 if (offset == 0)
1520 return ide->bus_master_command | (ide->bus_master_status << 16);
1521
1522 /* status register */
1523 if (offset == 2)
1524 return ide->bus_master_status;
1525
1526 /* descriptor table register */
1527 if (offset == 4)
1528 return ide->bus_master_descriptor;
1529
1530 return 0xffffffff;
1531 }
1532
1533
1534
1535 /*************************************
1536 *
1537 * Bus master write
1538 *
1539 *************************************/
1540
ide_bus_master_write(struct ide_state * ide,offs_t offset,int size,UINT32 data)1541 static void ide_bus_master_write(struct ide_state *ide, offs_t offset, int size, UINT32 data)
1542 {
1543 LOG(("%08X:ide_bus_master_write(%d, %d, %08X)\n", activecpu_get_previouspc(), offset, size, data));
1544
1545 /* command register */
1546 if (offset == 0)
1547 {
1548 UINT8 old = ide->bus_master_command;
1549 UINT8 val = data & 0xff;
1550
1551 /* save the read/write bit and the start/stop bit */
1552 ide->bus_master_command = (old & 0xf6) | (val & 0x09);
1553 ide->bus_master_status = (ide->bus_master_status & ~IDE_BUSMASTER_STATUS_ACTIVE) | (val & 0x01);
1554
1555 /* handle starting a transfer */
1556 if (!(old & 1) && (val & 1))
1557 {
1558 /* reset all the DMA data */
1559 ide->dma_bytes_left = 0;
1560 ide->dma_last_buffer = 0;
1561 ide->dma_descriptor = ide->bus_master_descriptor;
1562 ide->dma_cpu = cpu_getactivecpu();
1563 ide->dma_address_xor = (activecpu_endianess() == CPU_IS_LE) ? 0 : 3;
1564
1565 /* if we're going live, start the pending read/write */
1566 if (ide->dma_active)
1567 {
1568 if (ide->bus_master_command & 8)
1569 read_next_sector(ide);
1570 else
1571 {
1572 read_buffer_from_dma(ide);
1573 continue_write(ide);
1574 }
1575 }
1576 }
1577 }
1578
1579 /* status register */
1580 if (offset <= 2 && offset + size > 2)
1581 {
1582 UINT8 old = ide->bus_master_status;
1583 UINT8 val = data >> (8 * (2 - offset));
1584
1585 /* save the DMA capable bits */
1586 ide->bus_master_status = (old & 0x9f) | (val & 0x60);
1587
1588 /* clear interrupt and error bits */
1589 if (val & IDE_BUSMASTER_STATUS_IRQ)
1590 ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
1591 if (val & IDE_BUSMASTER_STATUS_ERROR)
1592 ide->bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
1593 }
1594
1595 /* descriptor table register */
1596 if (offset == 4)
1597 ide->bus_master_descriptor = data & 0xfffffffc;
1598 }
1599
1600
1601
1602 /*************************************
1603 *
1604 * 32-bit IDE handlers
1605 *
1606 *************************************/
1607
READ32_HANDLER(ide_controller32_0_r)1608 READ32_HANDLER( ide_controller32_0_r )
1609 {
1610 int size;
1611
1612 offset *= 4;
1613 size = convert_to_offset_and_size32(&offset, mem_mask);
1614
1615 return ide_controller_read(&idestate[0], offset, size) << ((offset & 3) * 8);
1616 }
1617
1618
WRITE32_HANDLER(ide_controller32_0_w)1619 WRITE32_HANDLER( ide_controller32_0_w )
1620 {
1621 int size;
1622
1623 offset *= 4;
1624 size = convert_to_offset_and_size32(&offset, mem_mask);
1625
1626 ide_controller_write(&idestate[0], offset, size, data >> ((offset & 3) * 8));
1627 }
1628
1629
READ32_HANDLER(ide_bus_master32_0_r)1630 READ32_HANDLER( ide_bus_master32_0_r )
1631 {
1632 int size;
1633
1634 offset *= 4;
1635 size = convert_to_offset_and_size32(&offset, mem_mask);
1636
1637 return ide_bus_master_read(&idestate[0], offset, size) << ((offset & 3) * 8);
1638 }
1639
1640
WRITE32_HANDLER(ide_bus_master32_0_w)1641 WRITE32_HANDLER( ide_bus_master32_0_w )
1642 {
1643 int size;
1644
1645 offset *= 4;
1646 size = convert_to_offset_and_size32(&offset, mem_mask);
1647
1648 ide_bus_master_write(&idestate[0], offset, size, data >> ((offset & 3) * 8));
1649 }
1650
1651
1652
1653 /*************************************
1654 *
1655 * 16-bit IDE handlers
1656 *
1657 *************************************/
1658
READ16_HANDLER(ide_controller16_0_r)1659 READ16_HANDLER( ide_controller16_0_r )
1660 {
1661 int size;
1662
1663 offset *= 2;
1664 size = convert_to_offset_and_size16(&offset, mem_mask);
1665
1666 return ide_controller_read(&idestate[0], offset, size) << ((offset & 1) * 8);
1667 }
1668
1669
WRITE16_HANDLER(ide_controller16_0_w)1670 WRITE16_HANDLER( ide_controller16_0_w )
1671 {
1672 int size;
1673
1674 offset *= 2;
1675 size = convert_to_offset_and_size16(&offset, mem_mask);
1676
1677 ide_controller_write(&idestate[0], offset, size, data >> ((offset & 1) * 8));
1678 }
1679