1 /***************************************************************************
2
3 Midway/Williams Audio Boards
4 ----------------------------
5
6 6809 MEMORY MAP
7
8 Function Address R/W Data
9 ---------------------------------------------------------------
10 Program RAM 0000-07FF R/W D0-D7
11
12 Music (YM-2151) 2000-2001 R/W D0-D7
13
14 6821 PIA 4000-4003 R/W D0-D7
15
16 HC55516 clock low, digit latch 6000 W D0
17 HC55516 clock high 6800 W xx
18
19 Bank select 7800 W D0-D2
20
21 Banked Program ROM 8000-FFFF R D0-D7
22
23 ****************************************************************************/
24
25 #include "driver.h"
26 #include "machine/6821pia.h"
27 #include "cpu/m6809/m6809.h"
28 #include "williams.h"
29
30
31
32 /***************************************************************************
33 STATIC GLOBALS
34 ****************************************************************************/
35
36 UINT8 williams_sound_int_state;
37
38 static INT8 sound_cpunum;
39 static INT8 soundalt_cpunum;
40 static UINT8 williams_pianum;
41
42 static UINT8 adpcm_bank_count;
43
44
45
46 /***************************************************************************
47 PROTOTYPES
48 ****************************************************************************/
49
50 static void init_audio_state(void);
51
52 static void cvsd_ym2151_irq(int state);
53 static void adpcm_ym2151_irq(int state);
54 static void cvsd_irqa(int state);
55 static void cvsd_irqb(int state);
56
57 static READ_HANDLER( cvsd_pia_r );
58
59 static WRITE_HANDLER( cvsd_pia_w );
60 static WRITE_HANDLER( cvsd_bank_select_w );
61
62 static READ_HANDLER( adpcm_command_r );
63 static WRITE_HANDLER( adpcm_bank_select_w );
64 static WRITE_HANDLER( adpcm_6295_bank_select_w );
65
66 static READ_HANDLER( narc_command_r );
67 static READ_HANDLER( narc_command2_r );
68 static WRITE_HANDLER( narc_command2_w );
69 static WRITE_HANDLER( narc_master_bank_select_w );
70 static WRITE_HANDLER( narc_slave_bank_select_w );
71
72
73
74 /***************************************************************************
75 PROCESSOR STRUCTURES
76 ****************************************************************************/
77
78 /* CVSD readmem/writemem structures */
MEMORY_READ_START(williams_cvsd_readmem)79 MEMORY_READ_START( williams_cvsd_readmem )
80 { 0x0000, 0x07ff, MRA_RAM },
81 { 0x2000, 0x2001, YM2151_status_port_0_r },
82 { 0x4000, 0x4003, cvsd_pia_r },
83 { 0x8000, 0xffff, MRA_BANK6 },
84 MEMORY_END
85
86
87 MEMORY_WRITE_START( williams_cvsd_writemem )
88 { 0x0000, 0x07ff, MWA_RAM },
89 { 0x2000, 0x2000, YM2151_register_port_0_w },
90 { 0x2001, 0x2001, YM2151_data_port_0_w },
91 { 0x4000, 0x4003, cvsd_pia_w },
92 { 0x6000, 0x6000, hc55516_0_digit_clock_clear_w },
93 { 0x6800, 0x6800, hc55516_0_clock_set_w },
94 { 0x7800, 0x7800, cvsd_bank_select_w },
95 { 0x8000, 0xffff, MWA_ROM },
96 MEMORY_END
97
98
99
100 /* ADPCM readmem/writemem structures */
101 MEMORY_READ_START( williams_adpcm_readmem )
102 { 0x0000, 0x1fff, MRA_RAM },
103 { 0x2401, 0x2401, YM2151_status_port_0_r },
104 { 0x2c00, 0x2c00, OKIM6295_status_0_r },
105 { 0x3000, 0x3000, adpcm_command_r },
106 { 0x4000, 0xbfff, MRA_BANK6 },
107 { 0xc000, 0xffff, MRA_ROM },
108 MEMORY_END
109
110
111 MEMORY_WRITE_START( williams_adpcm_writemem )
112 { 0x0000, 0x1fff, MWA_RAM },
113 { 0x2000, 0x2000, adpcm_bank_select_w },
114 { 0x2400, 0x2400, YM2151_register_port_0_w },
115 { 0x2401, 0x2401, YM2151_data_port_0_w },
116 { 0x2800, 0x2800, DAC_0_data_w },
117 { 0x2c00, 0x2c00, OKIM6295_data_0_w },
118 { 0x3400, 0x3400, adpcm_6295_bank_select_w },
119 { 0x3c00, 0x3c00, MWA_NOP },/*mk_sound_talkback_w }, -- talkback port? */
120 { 0x4000, 0xffff, MWA_ROM },
121 MEMORY_END
122
123
124
125 /* NARC master readmem/writemem structures */
126 MEMORY_READ_START( williams_narc_master_readmem )
127 { 0x0000, 0x1fff, MRA_RAM },
128 { 0x2001, 0x2001, YM2151_status_port_0_r },
129 { 0x3000, 0x3000, MRA_NOP },
130 { 0x3400, 0x3400, narc_command_r },
131 { 0x4000, 0xbfff, MRA_BANK6 },
132 { 0xc000, 0xffff, MRA_ROM },
133 MEMORY_END
134
135
136 MEMORY_WRITE_START( williams_narc_master_writemem )
137 { 0x0000, 0x1fff, MWA_RAM },
138 { 0x2000, 0x2000, YM2151_register_port_0_w },
139 { 0x2001, 0x2001, YM2151_data_port_0_w },
140 { 0x2800, 0x2800, MWA_NOP },/*mk_sound_talkback_w }, -- talkback port? */
141 { 0x2c00, 0x2c00, narc_command2_w },
142 { 0x3000, 0x3000, DAC_0_data_w },
143 { 0x3800, 0x3800, narc_master_bank_select_w },
144 { 0x4000, 0xffff, MWA_ROM },
145 MEMORY_END
146
147
148
149 /* NARC slave readmem/writemem structures */
150 MEMORY_READ_START( williams_narc_slave_readmem )
151 { 0x0000, 0x1fff, MRA_RAM },
152 { 0x3000, 0x3000, MRA_NOP },
153 { 0x3400, 0x3400, narc_command2_r },
154 { 0x4000, 0xbfff, MRA_BANK5 },
155 { 0xc000, 0xffff, MRA_ROM },
156 MEMORY_END
157
158
159 MEMORY_WRITE_START( williams_narc_slave_writemem )
160 { 0x0000, 0x1fff, MWA_RAM },
161 { 0x2000, 0x2000, hc55516_0_clock_set_w },
162 { 0x2400, 0x2400, hc55516_0_digit_clock_clear_w },
163 { 0x3000, 0x3000, DAC_1_data_w },
164 { 0x3800, 0x3800, narc_slave_bank_select_w },
165 { 0x3c00, 0x3c00, MWA_NOP },
166 { 0x4000, 0xffff, MWA_ROM },
167 MEMORY_END
168
169
170
171 /* PIA structure */
172 static struct pia6821_interface cvsd_pia_intf =
173 {
174 /*inputs : A/B,CA/B1,CA/B2 */ 0, 0, 0, 0, 0, 0,
175 /*outputs: A/B,CA/B2 */ DAC_0_data_w, 0, 0, 0,
176 /*irqs : A/B */ cvsd_irqa, cvsd_irqb
177 };
178
179
180
181 /***************************************************************************
182 AUDIO STRUCTURES
183 ****************************************************************************/
184
185 /* YM2151 structure (CVSD variant) */
186 static struct YM2151interface cvsd_ym2151_interface =
187 {
188 1, /* 1 chip */
189 3579580,
190 { YM3012_VOL(10,MIXER_PAN_CENTER,10,MIXER_PAN_CENTER) },
191 { cvsd_ym2151_irq }
192 };
193
194
195 /* YM2151 structure (ADPCM variant) */
196 static struct YM2151interface adpcm_ym2151_interface =
197 {
198 1, /* 1 chip */
199 3579580,
200 { YM3012_VOL(10,MIXER_PAN_CENTER,10,MIXER_PAN_CENTER) },
201 { adpcm_ym2151_irq }
202 };
203
204
205 /* DAC structure (single DAC variant) */
206 static struct DACinterface single_dac_interface =
207 {
208 1,
209 { 50 }
210 };
211
212
213 /* DAC structure (double DAC variant) */
214 static struct DACinterface double_dac_interface =
215 {
216 2,
217 { 50, 50 }
218 };
219
220
221 /* CVSD structure */
222 static struct hc55516_interface cvsd_interface =
223 {
224 1, /* 1 chip */
225 { 80 }
226 };
227
228
229 /* OKIM6295 structure(s) */
230 static struct OKIM6295interface adpcm_6295_interface =
231 {
232 1, /* 1 chip */
233 { 8000 }, /* 8000 Hz frequency */
234 { REGION_SOUND1 }, /* memory */
235 { 50 }
236 };
237
238
239
240 /***************************************************************************
241 MACHINE DRIVERS
242 ****************************************************************************/
243
244 MACHINE_DRIVER_START( williams_cvsd_sound )
245 MDRV_CPU_ADD_TAG("cvsd", M6809, 8000000/4)
MDRV_CPU_FLAGS(CPU_AUDIO_CPU)246 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
247 MDRV_CPU_MEMORY(williams_cvsd_readmem,williams_cvsd_writemem)
248
249 MDRV_SOUND_ATTRIBUTES(SOUND_SUPPORTS_STEREO)
250 MDRV_SOUND_ADD(YM2151, cvsd_ym2151_interface)
251 MDRV_SOUND_ADD(DAC, single_dac_interface)
252 MDRV_SOUND_ADD(HC55516,cvsd_interface)
253 MACHINE_DRIVER_END
254
255
256 MACHINE_DRIVER_START( williams_adpcm_sound )
257 MDRV_CPU_ADD_TAG("adpcm", M6809, 8000000/4)
258 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
259 MDRV_CPU_MEMORY(williams_adpcm_readmem,williams_adpcm_writemem)
260
261 MDRV_SOUND_ATTRIBUTES(SOUND_SUPPORTS_STEREO)
262 MDRV_SOUND_ADD(YM2151, adpcm_ym2151_interface)
263 MDRV_SOUND_ADD(DAC, single_dac_interface)
264 MDRV_SOUND_ADD(OKIM6295,adpcm_6295_interface)
265 MACHINE_DRIVER_END
266
267
268 MACHINE_DRIVER_START( williams_narc_sound )
269 MDRV_CPU_ADD_TAG("narc1", M6809, 8000000/4)
270 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
271 MDRV_CPU_MEMORY(williams_narc_master_readmem,williams_narc_master_writemem)
272
273 MDRV_CPU_ADD_TAG("narc2", M6809, 8000000/4)
274 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
275 MDRV_CPU_MEMORY(williams_narc_slave_readmem,williams_narc_slave_writemem)
276
277 MDRV_SOUND_ATTRIBUTES(SOUND_SUPPORTS_STEREO)
278 MDRV_SOUND_ADD(YM2151, adpcm_ym2151_interface)
279 MDRV_SOUND_ADD(DAC, double_dac_interface)
280 MDRV_SOUND_ADD(HC55516,cvsd_interface)
281 MACHINE_DRIVER_END
282
283
284
285 /***************************************************************************
286 static INLINES
287 ****************************************************************************/
288
289 static INLINE UINT8 *get_cvsd_bank_base(int data)
290 {
291 UINT8 *RAM = memory_region(REGION_CPU1 + sound_cpunum);
292 int bank = data & 3;
293 int quarter = (data >> 2) & 3;
294 if (bank == 3) bank = 0;
295 return &RAM[0x10000 + (bank * 0x20000) + (quarter * 0x8000)];
296 }
297
298
get_adpcm_bank_base(int data)299 static INLINE UINT8 *get_adpcm_bank_base(int data)
300 {
301 UINT8 *RAM = memory_region(REGION_CPU1 + sound_cpunum);
302 int bank = data & 7;
303 return &RAM[0x10000 + (bank * 0x8000)];
304 }
305
306
get_narc_master_bank_base(int data)307 static INLINE UINT8 *get_narc_master_bank_base(int data)
308 {
309 UINT8 *RAM = memory_region(REGION_CPU1 + sound_cpunum);
310 int bank = data & 3;
311 if (!(data & 4)) bank = 0;
312 return &RAM[0x10000 + (bank * 0x8000)];
313 }
314
315
get_narc_slave_bank_base(int data)316 static INLINE UINT8 *get_narc_slave_bank_base(int data)
317 {
318 UINT8 *RAM = memory_region(REGION_CPU1 + soundalt_cpunum);
319 int bank = data & 7;
320 return &RAM[0x10000 + (bank * 0x8000)];
321 }
322
323
324
325 /***************************************************************************
326 INITIALIZATION
327 ****************************************************************************/
328
williams_cvsd_init(int cpunum,int pianum)329 void williams_cvsd_init(int cpunum, int pianum)
330 {
331 /* configure the CPU */
332 sound_cpunum = mame_find_cpu_index("cvsd");
333 soundalt_cpunum = -1;
334
335 /* configure the PIA */
336 williams_pianum = pianum;
337 pia_config(pianum, PIA_STANDARD_ORDERING, &cvsd_pia_intf);
338
339 /* initialize the global variables */
340 init_audio_state();
341
342 /* reset the chip */
343 williams_cvsd_reset_w(1);
344 williams_cvsd_reset_w(0);
345
346 /* reset the IRQ state */
347 pia_set_input_ca1(williams_pianum, 1);
348 }
349
350
williams_adpcm_init(int cpunum)351 void williams_adpcm_init(int cpunum)
352 {
353 UINT8 *RAM;
354 int i;
355
356 /* configure the CPU */
357 sound_cpunum = mame_find_cpu_index("adpcm");
358 soundalt_cpunum = -1;
359
360 /* install the fixed ROM */
361 RAM = memory_region(REGION_CPU1 + sound_cpunum);
362 memcpy(&RAM[0xc000], &RAM[0x4c000], 0x4000);
363
364 /* initialize the global variables */
365 init_audio_state();
366
367 /* reset the chip */
368 williams_adpcm_reset_w(1);
369 williams_adpcm_reset_w(0);
370
371 /* find the number of banks in the ADPCM space */
372 for (i = 0; i < MAX_SOUND; i++)
373 if (Machine->drv->sound[i].sound_type == SOUND_OKIM6295)
374 {
375 struct OKIM6295interface *intf = (struct OKIM6295interface *)Machine->drv->sound[i].sound_interface;
376 adpcm_bank_count = memory_region_length(intf->region[0]) / 0x40000;
377 }
378 }
379
380
williams_narc_init(int cpunum)381 void williams_narc_init(int cpunum)
382 {
383 UINT8 *RAM;
384
385 /* configure the CPU */
386 sound_cpunum = mame_find_cpu_index("narc1");
387 soundalt_cpunum = mame_find_cpu_index("narc2");
388
389 /* install the fixed ROM */
390 RAM = memory_region(REGION_CPU1 + sound_cpunum);
391 memcpy(&RAM[0xc000], &RAM[0x2c000], 0x4000);
392 RAM = memory_region(REGION_CPU1 + soundalt_cpunum);
393 memcpy(&RAM[0xc000], &RAM[0x4c000], 0x4000);
394
395 /* initialize the global variables */
396 init_audio_state();
397
398 /* reset the chip */
399 williams_narc_reset_w(1);
400 williams_narc_reset_w(0);
401 }
402
403
init_audio_state(void)404 static void init_audio_state(void)
405 {
406 /* reset the YM2151 state */
407 YM2151_sh_reset();
408
409 /* clear all the interrupts */
410 williams_sound_int_state = 0;
411 if (sound_cpunum != -1)
412 {
413 cpu_set_irq_line(sound_cpunum, M6809_FIRQ_LINE, CLEAR_LINE);
414 cpu_set_irq_line(sound_cpunum, M6809_IRQ_LINE, CLEAR_LINE);
415 cpu_set_nmi_line(sound_cpunum, CLEAR_LINE);
416 }
417 if (soundalt_cpunum != -1)
418 {
419 cpu_set_irq_line(soundalt_cpunum, M6809_FIRQ_LINE, CLEAR_LINE);
420 cpu_set_irq_line(soundalt_cpunum, M6809_IRQ_LINE, CLEAR_LINE);
421 cpu_set_nmi_line(soundalt_cpunum, CLEAR_LINE);
422 }
423 }
424
425
426 #if 0
427 static void locate_audio_hotspot(UINT8 *base, UINT16 start)
428 {
429 int i;
430
431 /* search for the loop that kills performance so we can optimize it */
432 for (i = start; i < 0x10000; i++)
433 {
434 if (base[i + 0] == 0x1a && base[i + 1] == 0x50 && /* 1A 50 ORCC #$0050 */
435 base[i + 2] == 0x93 && /* 93 xx SUBD $xx */
436 base[i + 4] == 0xe3 && base[i + 5] == 0x4c && /* E3 4C ADDD $000C,U */
437 base[i + 6] == 0x9e && base[i + 7] == base[i + 3] && /* 9E xx LDX $xx */
438 base[i + 8] == 0xaf && base[i + 9] == 0x4c && /* AF 4C STX $000C,U */
439 base[i +10] == 0x1c && base[i +11] == 0xaf) /* 1C AF ANDCC #$00AF */
440 {
441 // counter.hotspot_start = i;
442 // counter.hotspot_stop = i + 12;
443 logerror("Found hotspot @ %04X", i);
444 return;
445 }
446 }
447 logerror("Found no hotspot!");
448 }
449 #endif
450
451
452
453 /***************************************************************************
454 CVSD IRQ GENERATION CALLBACKS
455 ****************************************************************************/
456
cvsd_ym2151_irq(int state)457 static void cvsd_ym2151_irq(int state)
458 {
459 pia_set_input_ca1(williams_pianum, !state);
460 }
461
462
cvsd_irqa(int state)463 static void cvsd_irqa(int state)
464 {
465 cpu_set_irq_line(sound_cpunum, M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
466 }
467
468
cvsd_irqb(int state)469 static void cvsd_irqb(int state)
470 {
471 cpu_set_nmi_line(sound_cpunum, state ? ASSERT_LINE : CLEAR_LINE);
472 }
473
474
475
476 /***************************************************************************
477 ADPCM IRQ GENERATION CALLBACKS
478 ****************************************************************************/
479
adpcm_ym2151_irq(int state)480 static void adpcm_ym2151_irq(int state)
481 {
482 cpu_set_irq_line(sound_cpunum, M6809_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
483 }
484
485
486
487 /***************************************************************************
488 CVSD BANK SELECT
489 ****************************************************************************/
490
WRITE_HANDLER(cvsd_bank_select_w)491 static WRITE_HANDLER( cvsd_bank_select_w )
492 {
493 cpu_setbank(6, get_cvsd_bank_base(data));
494 }
495
496
497
498 /***************************************************************************
499 ADPCM BANK SELECT
500 ****************************************************************************/
501
WRITE_HANDLER(adpcm_bank_select_w)502 static WRITE_HANDLER( adpcm_bank_select_w )
503 {
504 cpu_setbank(6, get_adpcm_bank_base(data));
505 }
506
507
WRITE_HANDLER(adpcm_6295_bank_select_w)508 static WRITE_HANDLER( adpcm_6295_bank_select_w )
509 {
510 if (adpcm_bank_count <= 3)
511 {
512 if (!(data & 0x04))
513 OKIM6295_set_bank_base(0, 0x00000);
514 else if (data & 0x01)
515 OKIM6295_set_bank_base(0, 0x40000);
516 else
517 OKIM6295_set_bank_base(0, 0x80000);
518 }
519 else
520 {
521 data &= 7;
522 if (data != 0)
523 OKIM6295_set_bank_base(0, (data - 1) * 0x40000);
524 }
525 }
526
527
528
529 /***************************************************************************
530 NARC BANK SELECT
531 ****************************************************************************/
532
WRITE_HANDLER(narc_master_bank_select_w)533 static WRITE_HANDLER( narc_master_bank_select_w )
534 {
535 cpu_setbank(6, get_narc_master_bank_base(data));
536 }
537
538
WRITE_HANDLER(narc_slave_bank_select_w)539 static WRITE_HANDLER( narc_slave_bank_select_w )
540 {
541 cpu_setbank(5, get_narc_slave_bank_base(data));
542 }
543
544
545
546 /***************************************************************************
547 PIA INTERFACES
548 ****************************************************************************/
549
READ_HANDLER(cvsd_pia_r)550 static READ_HANDLER( cvsd_pia_r )
551 {
552 return pia_read(williams_pianum, offset);
553 }
554
555
WRITE_HANDLER(cvsd_pia_w)556 static WRITE_HANDLER( cvsd_pia_w )
557 {
558 pia_write(williams_pianum, offset, data);
559 }
560
561
562
563 /***************************************************************************
564 CVSD COMMUNICATIONS
565 ****************************************************************************/
566
williams_cvsd_delayed_data_w(int param)567 static void williams_cvsd_delayed_data_w(int param)
568 {
569 pia_set_input_b(williams_pianum, param & 0xff);
570 pia_set_input_cb1(williams_pianum, param & 0x100);
571 pia_set_input_cb2(williams_pianum, param & 0x200);
572 }
573
574
williams_cvsd_data_w(int data)575 void williams_cvsd_data_w(int data)
576 {
577 timer_set(TIME_NOW, data, williams_cvsd_delayed_data_w);
578 }
579
580
williams_cvsd_reset_w(int state)581 void williams_cvsd_reset_w(int state)
582 {
583 /* going high halts the CPU */
584 if (state)
585 {
586 cvsd_bank_select_w(0, 0);
587 init_audio_state();
588 cpu_set_reset_line(sound_cpunum, ASSERT_LINE);
589 }
590 /* going low resets and reactivates the CPU */
591 else
592 cpu_set_reset_line(sound_cpunum, CLEAR_LINE);
593 }
594
595
596
597 /***************************************************************************
598 ADPCM COMMUNICATIONS
599 ****************************************************************************/
600
READ_HANDLER(adpcm_command_r)601 static READ_HANDLER( adpcm_command_r )
602 {
603 cpu_set_irq_line(sound_cpunum, M6809_IRQ_LINE, CLEAR_LINE);
604 williams_sound_int_state = 0;
605 return soundlatch_r(0);
606 }
607
608
williams_adpcm_data_w(int data)609 void williams_adpcm_data_w(int data)
610 {
611 soundlatch_w(0, data & 0xff);
612 if (!(data & 0x200))
613 {
614 cpu_set_irq_line(sound_cpunum, M6809_IRQ_LINE, ASSERT_LINE);
615 williams_sound_int_state = 1;
616 }
617 }
618
619
williams_adpcm_reset_w(int state)620 void williams_adpcm_reset_w(int state)
621 {
622 /* going high halts the CPU */
623 if (state)
624 {
625 adpcm_bank_select_w(0, 0);
626 init_audio_state();
627 cpu_set_reset_line(sound_cpunum, ASSERT_LINE);
628 }
629 /* going low resets and reactivates the CPU */
630 else
631 cpu_set_reset_line(sound_cpunum, CLEAR_LINE);
632 }
633
634
635
636 /***************************************************************************
637 NARC COMMUNICATIONS
638 ****************************************************************************/
639
READ_HANDLER(narc_command_r)640 static READ_HANDLER( narc_command_r )
641 {
642 cpu_set_nmi_line(sound_cpunum, CLEAR_LINE);
643 cpu_set_irq_line(sound_cpunum, M6809_IRQ_LINE, CLEAR_LINE);
644 williams_sound_int_state = 0;
645 return soundlatch_r(0);
646 }
647
648
williams_narc_data_w(int data)649 void williams_narc_data_w(int data)
650 {
651 soundlatch_w(0, data & 0xff);
652 if (!(data & 0x100))
653 cpu_set_nmi_line(sound_cpunum, ASSERT_LINE);
654 if (!(data & 0x200))
655 {
656 cpu_set_irq_line(sound_cpunum, M6809_IRQ_LINE, ASSERT_LINE);
657 williams_sound_int_state = 1;
658 }
659 }
660
661
williams_narc_reset_w(int state)662 void williams_narc_reset_w(int state)
663 {
664 /* going high halts the CPU */
665 if (state)
666 {
667 narc_master_bank_select_w(0, 0);
668 narc_slave_bank_select_w(0, 0);
669 init_audio_state();
670 cpu_set_reset_line(sound_cpunum, ASSERT_LINE);
671 cpu_set_reset_line(soundalt_cpunum, ASSERT_LINE);
672 }
673 /* going low resets and reactivates the CPU */
674 else
675 {
676 cpu_set_reset_line(sound_cpunum, CLEAR_LINE);
677 cpu_set_reset_line(soundalt_cpunum, CLEAR_LINE);
678 }
679 }
680
681
READ_HANDLER(narc_command2_r)682 static READ_HANDLER( narc_command2_r )
683 {
684 cpu_set_irq_line(soundalt_cpunum, M6809_FIRQ_LINE, CLEAR_LINE);
685 return soundlatch2_r(0);
686 }
687
688
WRITE_HANDLER(narc_command2_w)689 static WRITE_HANDLER( narc_command2_w )
690 {
691 soundlatch2_w(0, data & 0xff);
692 cpu_set_irq_line(soundalt_cpunum, M6809_FIRQ_LINE, ASSERT_LINE);
693 }
694