1 /*
2 Interface routine for 68kem <-> Mame
3 */
4
5 #include "driver.h"
6 #include "mamedbg.h"
7 #include "m68000.h"
8 #include "state.h"
9
10 struct m68k_memory_interface a68k_memory_intf;
11
12 /* If we are only using assembler cores, we need to define these
13 * otherwise they are declared by the C core. */
14
15 #ifdef A68K0
16 #ifdef A68K2
17 int m68k_ICount;
18 struct m68k_memory_interface m68k_memory_intf;
19 #endif
20 #endif
21
22 enum
23 {
24 M68K_CPU_TYPE_INVALID,
25 M68K_CPU_TYPE_68000,
26 M68K_CPU_TYPE_68010,
27 M68K_CPU_TYPE_68EC020,
28 M68K_CPU_TYPE_68020,
29 M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */
30 M68K_CPU_TYPE_68040 /* Supported by disassembler ONLY */
31 };
32
33 #define A68K_SET_PC_CALLBACK(A) (*a68k_memory_intf.changepc)(A)
34
35 int illegal_op = 0 ;
36 int illegal_pc = 0 ;
37
38 #ifdef MAME_DEBUG
m68k_illegal_opcode(void)39 void m68k_illegal_opcode(void)
40 {
41 log_cb(RETRO_LOG_DEBUG, LOGPRE "Illegal Opcode %4x at %8x\n",illegal_op,illegal_pc);
42 }
43 #endif
44
45 unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type);
46
47 #ifdef _WIN32
48 #define CONVENTION __cdecl
49 #else
50 #define CONVENTION
51 #endif
52
53 /* Use the x86 assembly core */
54 typedef struct
55 {
56 UINT32 d[8]; /* 0x0004 8 Data registers */
57 UINT32 a[8]; /* 0x0024 8 Address registers */
58
59 UINT32 isp; /* 0x0048 */
60
61 UINT32 sr_high; /* 0x004C System registers */
62 UINT32 ccr; /* 0x0050 CCR in Intel Format */
63 UINT32 x_carry; /* 0x0054 Extended Carry */
64
65 UINT32 pc; /* 0x0058 Program Counter */
66
67 UINT32 IRQ_level; /* 0x005C IRQ level you want the MC68K process (0=None) */
68
69 /* Backward compatible with C emulator - Only set in Debug compile */
70
71 UINT16 sr;
72 UINT16 filler;
73
74 int (*irq_callback)(int irqline);
75
76 UINT32 previous_pc; /* last PC used */
77
78 int (*reset_callback)(void);
79
80 UINT32 sfc; /* Source Function Code. (68010) */
81 UINT32 dfc; /* Destination Function Code. (68010) */
82 UINT32 usp; /* User Stack (All) */
83 UINT32 vbr; /* Vector Base Register. (68010) */
84
85 UINT32 BankID; /* Memory bank in use */
86 UINT32 CPUtype; /* CPU Type 0=68000,1=68010,2=68020 */
87 UINT32 FullPC;
88
89 struct m68k_memory_interface Memory_Interface;
90
91 } a68k_cpu_context;
92
93
94 static UINT8 M68K_layout[] = {
95 M68K_PC, M68K_ISP, -1,
96 M68K_SR, M68K_USP, -1,
97 M68K_D0, M68K_A0, -1,
98 M68K_D1, M68K_A1, -1,
99 M68K_D2, M68K_A2, -1,
100 M68K_D3, M68K_A3, -1,
101 M68K_D4, M68K_A4, -1,
102 M68K_D5, M68K_A5, -1,
103 M68K_D6, M68K_A6, -1,
104 M68K_D7, M68K_A7, 0
105 };
106
107 static UINT8 m68k_win_layout[] = {
108 48, 0,32,13, /* register window (top right) */
109 0, 0,47,13, /* disassembler window (top left) */
110 0,14,47, 8, /* memory #1 window (left, middle) */
111 48,14,32, 8, /* memory #2 window (right, middle) */
112 0,23,80, 1 /* command line window (bottom rows) */
113 };
114
115 #ifdef A68K0
116 extern a68k_cpu_context M68000_regs;
117
118 extern void CONVENTION M68000_RUN(void);
119 extern void CONVENTION M68000_RESET(void);
120
121 #endif
122
123 #ifdef A68K2
124 extern a68k_cpu_context M68020_regs;
125
126 extern void CONVENTION M68020_RUN(void);
127 extern void CONVENTION M68020_RESET(void);
128 #endif
129
130 /***************************************************************************/
131 /* Save State stuff */
132 /***************************************************************************/
133
134 static int IntelFlag[32] = {
135 0x0000,0x0001,0x0800,0x0801,0x0040,0x0041,0x0840,0x0841,
136 0x0080,0x0081,0x0880,0x0881,0x00C0,0x00C1,0x08C0,0x08C1,
137 0x0100,0x0101,0x0900,0x0901,0x0140,0x0141,0x0940,0x0941,
138 0x0180,0x0181,0x0980,0x0981,0x01C0,0x01C1,0x09C0,0x09C1
139 };
140
141
142 /* The assembler engine only keeps flags in intel format, so ... */
143
144 static UINT32 zero = 0;
145 static int stopped = 0;
146
a68k_prepare_substate(void)147 static void a68k_prepare_substate(void)
148 {
149 stopped = ((M68000_regs.IRQ_level & 0x80) != 0);
150
151 M68000_regs.sr = ((M68000_regs.ccr >> 4) & 0x1C)
152 | (M68000_regs.ccr & 0x01)
153 | ((M68000_regs.ccr >> 10) & 0x02)
154 | (M68000_regs.sr_high << 8);
155 }
156
a68k_post_load(void)157 static void a68k_post_load(void)
158 {
159 int intel = M68000_regs.sr & 0x1f;
160
161 M68000_regs.sr_high = M68000_regs.sr >> 8;
162 M68000_regs.x_carry = (IntelFlag[intel] >> 8) & 0x01;
163 M68000_regs.ccr = IntelFlag[intel] & 0x0EFF;
164 }
165
a68k_state_register(const char * type)166 void a68k_state_register(const char *type)
167 {
168 int cpu = cpu_getactivecpu();
169
170 state_save_register_UINT32(type, cpu, "D" , &M68000_regs.d[0], 8);
171 state_save_register_UINT32(type, cpu, "A" , &M68000_regs.a[0], 8);
172 state_save_register_UINT32(type, cpu, "PPC" , &M68000_regs.previous_pc, 1);
173 state_save_register_UINT32(type, cpu, "PC" , &M68000_regs.pc, 1);
174 state_save_register_UINT32(type, cpu, "USP" , &M68000_regs.usp, 1);
175 state_save_register_UINT32(type, cpu, "ISP" , &M68000_regs.isp, 1);
176 state_save_register_UINT32(type, cpu, "MSP" , &zero, 1);
177 state_save_register_UINT32(type, cpu, "VBR" , &M68000_regs.vbr, 1);
178 state_save_register_UINT32(type, cpu, "SFC" , &M68000_regs.sfc, 1);
179 state_save_register_UINT32(type, cpu, "DFC" , &M68000_regs.dfc, 1);
180 state_save_register_UINT32(type, cpu, "CACR" , &zero, 1);
181 state_save_register_UINT32(type, cpu, "CAAR" , &zero, 1);
182 state_save_register_UINT16(type, cpu, "SR" , &M68000_regs.sr, 1);
183 state_save_register_UINT32(type, cpu, "INT_LEVEL" , &M68000_regs.IRQ_level, 1);
184 state_save_register_UINT32(type, cpu, "INT_CYCLES", (UINT32 *)&m68k_ICount, 1);
185 state_save_register_int (type, cpu, "STOPPED" , &stopped);
186 state_save_register_int (type, cpu, "HALTED" , (int *)&zero);
187 state_save_register_UINT32(type, cpu, "PREF_ADDR" , &zero, 1);
188 state_save_register_UINT32(type, cpu, "PREF_DATA" , &zero, 1);
189 state_save_register_func_presave(a68k_prepare_substate);
190 state_save_register_func_postload(a68k_post_load);
191 }
192
193 /****************************************************************************
194 * 24-bit address, 16-bit data memory interface
195 ****************************************************************************/
196
197 #ifdef A68K0
198
readlong_a24_d16(offs_t address)199 static data32_t readlong_a24_d16(offs_t address)
200 {
201 data32_t result = cpu_readmem24bew_word(address) << 16;
202 return result | cpu_readmem24bew_word(address + 2);
203 }
204
writelong_a24_d16(offs_t address,data32_t data)205 static void writelong_a24_d16(offs_t address, data32_t data)
206 {
207 cpu_writemem24bew_word(address, data >> 16);
208 cpu_writemem24bew_word(address + 2, data);
209 }
210
changepc_a24_d16(offs_t pc)211 static void changepc_a24_d16(offs_t pc)
212 {
213 change_pc24bew(pc);
214 }
215
216 /* interface for 24-bit address bus, 16-bit data bus (68000, 68010) */
217 static const struct m68k_memory_interface interface_a24_d16 =
218 {
219 0,
220 cpu_readmem24bew,
221 cpu_readmem24bew_word,
222 readlong_a24_d16,
223 cpu_writemem24bew,
224 cpu_writemem24bew_word,
225 writelong_a24_d16,
226 changepc_a24_d16,
227 cpu_readmem24bew, /* Encrypted Versions */
228 cpu_readmem24bew_word,
229 readlong_a24_d16,
230 cpu_readmem24bew_word,
231 readlong_a24_d16
232 };
233
234 #endif /* A68k0 */
235
236 /****************************************************************************
237 * 24-bit address, 32-bit data memory interface
238 ****************************************************************************/
239
240 #ifdef A68K2
241
242 /* potentially misaligned 16-bit reads with a 32-bit data bus (and 24-bit address bus) */
readword_a24_d32(offs_t address)243 static data16_t readword_a24_d32(offs_t address)
244 {
245 data16_t result;
246
247 if (!(address & 1))
248 return cpu_readmem24bedw_word(address);
249 result = cpu_readmem24bedw(address) << 8;
250 return result | cpu_readmem24bedw(address + 1);
251 }
252
253 /* potentially misaligned 16-bit writes with a 32-bit data bus (and 24-bit address bus) */
writeword_a24_d32(offs_t address,data16_t data)254 static void writeword_a24_d32(offs_t address, data16_t data)
255 {
256 if (!(address & 1))
257 {
258 cpu_writemem24bedw_word(address, data);
259 return;
260 }
261 cpu_writemem24bedw(address, data >> 8);
262 cpu_writemem24bedw(address + 1, data);
263 }
264
265 /* potentially misaligned 32-bit reads with a 32-bit data bus (and 24-bit address bus) */
readlong_a24_d32(offs_t address)266 static data32_t readlong_a24_d32(offs_t address)
267 {
268 data32_t result;
269
270 if (!(address & 3))
271 return cpu_readmem24bedw_dword(address);
272 else if (!(address & 1))
273 {
274 result = cpu_readmem24bedw_word(address) << 16;
275 return result | cpu_readmem24bedw_word(address + 2);
276 }
277 result = cpu_readmem24bedw(address) << 24;
278 result |= cpu_readmem24bedw_word(address + 1) << 8;
279 return result | cpu_readmem24bedw(address + 3);
280 }
281
282 /* potentially misaligned 32-bit writes with a 32-bit data bus (and 24-bit address bus) */
writelong_a24_d32(offs_t address,data32_t data)283 static void writelong_a24_d32(offs_t address, data32_t data)
284 {
285 if (!(address & 3))
286 {
287 cpu_writemem24bedw_dword(address, data);
288 return;
289 }
290 else if (!(address & 1))
291 {
292 cpu_writemem24bedw_word(address, data >> 16);
293 cpu_writemem24bedw_word(address + 2, data);
294 return;
295 }
296 cpu_writemem24bedw(address, data >> 24);
297 cpu_writemem24bedw_word(address + 1, data >> 8);
298 cpu_writemem24bedw(address + 3, data);
299 }
300
changepc_a24_d32(offs_t pc)301 static void changepc_a24_d32(offs_t pc)
302 {
303 change_pc24bedw(pc);
304 }
305
306 /* interface for 24-bit address bus, 32-bit data bus (68EC020) */
307 static const struct m68k_memory_interface interface_a24_d32 =
308 {
309 WORD_XOR_BE(0),
310 cpu_readmem24bedw,
311 readword_a24_d32,
312 readlong_a24_d32,
313 cpu_writemem24bedw,
314 writeword_a24_d32,
315 writelong_a24_d32,
316 changepc_a24_d32,
317 cpu_readmem24bedw,
318 readword_a24_d32,
319 readlong_a24_d32,
320 readword_a24_d32,
321 readlong_a24_d32
322 };
323
324
325 /****************************************************************************
326 * 32-bit address, 32-bit data memory interface
327 ****************************************************************************/
328
329 /* potentially misaligned 16-bit reads with a 32-bit data bus (and 32-bit address bus) */
readword_a32_d32(offs_t address)330 static data16_t readword_a32_d32(offs_t address)
331 {
332 data16_t result;
333
334 if (!(address & 1))
335 return cpu_readmem32bedw_word(address);
336 result = cpu_readmem32bedw(address) << 8;
337 return result | cpu_readmem32bedw(address + 1);
338 }
339
340 /* potentially misaligned 16-bit writes with a 32-bit data bus (and 32-bit address bus) */
writeword_a32_d32(offs_t address,data16_t data)341 static void writeword_a32_d32(offs_t address, data16_t data)
342 {
343 if (!(address & 1))
344 {
345 cpu_writemem32bedw_word(address, data);
346 return;
347 }
348 cpu_writemem32bedw(address, data >> 8);
349 cpu_writemem32bedw(address + 1, data);
350 }
351
352 /* potentially misaligned 32-bit reads with a 32-bit data bus (and 32-bit address bus) */
readlong_a32_d32(offs_t address)353 static data32_t readlong_a32_d32(offs_t address)
354 {
355 data32_t result;
356
357 if (!(address & 3))
358 return cpu_readmem32bedw_dword(address);
359 else if (!(address & 1))
360 {
361 result = cpu_readmem32bedw_word(address) << 16;
362 return result | cpu_readmem32bedw_word(address + 2);
363 }
364 result = cpu_readmem32bedw(address) << 24;
365 result |= cpu_readmem32bedw_word(address + 1) << 8;
366 return result | cpu_readmem32bedw(address + 3);
367 }
368
369 /* potentially misaligned 32-bit writes with a 32-bit data bus (and 32-bit address bus) */
writelong_a32_d32(offs_t address,data32_t data)370 static void writelong_a32_d32(offs_t address, data32_t data)
371 {
372 if (!(address & 3))
373 {
374 cpu_writemem32bedw_dword(address, data);
375 return;
376 }
377 else if (!(address & 1))
378 {
379 cpu_writemem32bedw_word(address, data >> 16);
380 cpu_writemem32bedw_word(address + 2, data);
381 return;
382 }
383 cpu_writemem32bedw(address, data >> 24);
384 cpu_writemem32bedw_word(address + 1, data >> 8);
385 cpu_writemem32bedw(address + 3, data);
386 }
387
changepc_a32_d32(offs_t pc)388 static void changepc_a32_d32(offs_t pc)
389 {
390 change_pc32bedw(pc);
391 }
392
393 /* interface for 24-bit address bus, 32-bit data bus (68020) */
394 static const struct m68k_memory_interface interface_a32_d32 =
395 {
396 WORD_XOR_BE(0),
397 cpu_readmem32bedw,
398 readword_a32_d32,
399 readlong_a32_d32,
400 cpu_writemem32bedw,
401 writeword_a32_d32,
402 writelong_a32_d32,
403 changepc_a32_d32,
404 cpu_readmem32bedw,
405 readword_a32_d32,
406 readlong_a32_d32,
407 readword_a32_d32,
408 readlong_a32_d32
409 };
410
411 #endif /* A68K2 */
412
413 /********************************************/
414 /* Interface routines to link Mame -> 68KEM */
415 /********************************************/
416
417 #define READOP(a) (cpu_readop16((a) ^ a68k_memory_intf.opcode_xor))
418
419 #ifdef A68K0
420
m68000_init(void)421 void m68000_init(void)
422 {
423 a68k_state_register("m68000");
424 M68000_regs.reset_callback = 0;
425 }
426
m68k16_reset_common(void)427 static void m68k16_reset_common(void)
428 {
429 int (*rc)(void);
430
431 rc = M68000_regs.reset_callback;
432 memset(&M68000_regs,0,sizeof(M68000_regs));
433 M68000_regs.reset_callback = rc;
434
435 M68000_regs.a[7] = M68000_regs.isp = (( READOP(0) << 16 ) | READOP(2));
436 M68000_regs.pc = (( READOP(4) << 16 ) | READOP(6)) & 0xffffff;
437 M68000_regs.sr_high = 0x27;
438
439 #ifdef MAME_DEBUG
440 M68000_regs.sr = 0x2700;
441 #endif
442
443 M68000_RESET();
444 }
445
m68000_reset(void * param)446 void m68000_reset(void *param)
447 {
448 struct m68k_encryption_interface *interface = param;
449
450 /* Default Memory Routines */
451 if (a68k_memory_intf.read8 != cpu_readmem24bew)
452 a68k_memory_intf = interface_a24_d16;
453
454 /* Import encryption routines if present */
455 if (param)
456 {
457 a68k_memory_intf.read8pc = interface->read8pc;
458 a68k_memory_intf.read16pc = interface->read16pc;
459 a68k_memory_intf.read32pc = interface->read32pc;
460 a68k_memory_intf.read16d = interface->read16d;
461 a68k_memory_intf.read32d = interface->read32d;
462 }
463
464 m68k16_reset_common();
465 M68000_regs.Memory_Interface = a68k_memory_intf;
466 }
467
m68000_exit(void)468 void m68000_exit(void)
469 {
470 /* nothing to do ? */
471 }
472
473
474 #ifdef TRACE68K /* Trace */
475 static int skiptrace=0;
476 #endif
477
m68000_execute(int cycles)478 int m68000_execute(int cycles)
479 {
480 if (M68000_regs.IRQ_level == 0x80) return cycles; /* STOP with no IRQs */
481
482 m68k_ICount = cycles;
483
484 #ifdef MAME_DEBUG
485 do
486 {
487 if (mame_debug)
488 {
489 #ifdef TRACE68K
490
491 int StartCycle = m68k_ICount;
492
493 skiptrace++;
494
495 if (skiptrace > 0)
496 {
497 int mycount, areg, dreg;
498 areg = dreg = 0;
499
500 for (mycount=7;mycount>=0;mycount--)
501 {
502 areg = areg + M68000_regs.a[mycount];
503 dreg = dreg + M68000_regs.d[mycount];
504 }
505
506 log_cb(RETRO_LOG_DEBUG, LOGPRE "=> %8x %8x ",areg,dreg);
507 log_cb(RETRO_LOG_DEBUG, LOGPRE "%6x %4x %d\n",M68000_regs.pc,M68000_regs.sr & 0x271F,m68k_ICount);
508 }
509 #endif
510
511 /*m68k_memory_intf = a68k_memory_intf;*/
512
513 MAME_Debug();
514 M68000_RUN();
515
516 #ifdef TRACE68K
517 if ((M68000_regs.IRQ_level & 0x80) || (cpu_getstatus(cpu_getactivecpu()) == 0))
518 m68k_ICount = 0;
519 else
520 m68k_ICount = StartCycle - 12;
521 #endif
522 }
523 else
524 M68000_RUN();
525 } while (m68k_ICount > 0);
526
527 #else
528
529 M68000_RUN();
530
531 #endif /* MAME_DEBUG */
532
533 return (cycles - m68k_ICount);
534 }
535
536
m68000_get_context(void * dst)537 unsigned m68000_get_context(void *dst)
538 {
539 if( dst )
540 *(a68k_cpu_context*)dst = M68000_regs;
541 return sizeof(a68k_cpu_context);
542 }
543
m68000_set_context(void * src)544 void m68000_set_context(void *src)
545 {
546 if( src )
547 {
548 M68000_regs = *(a68k_cpu_context*)src;
549 a68k_memory_intf = M68000_regs.Memory_Interface;
550 }
551 }
552
m68000_get_reg(int regnum)553 unsigned m68000_get_reg(int regnum)
554 {
555 switch( regnum )
556 {
557 case REG_PC:
558 case M68K_PC: return M68000_regs.pc;
559 case REG_SP:
560 case M68K_ISP: return M68000_regs.isp;
561 case M68K_USP: return M68000_regs.usp;
562 case M68K_SR: return M68000_regs.sr;
563 case M68K_VBR: return M68000_regs.vbr;
564 case M68K_SFC: return M68000_regs.sfc;
565 case M68K_DFC: return M68000_regs.dfc;
566 case M68K_D0: return M68000_regs.d[0];
567 case M68K_D1: return M68000_regs.d[1];
568 case M68K_D2: return M68000_regs.d[2];
569 case M68K_D3: return M68000_regs.d[3];
570 case M68K_D4: return M68000_regs.d[4];
571 case M68K_D5: return M68000_regs.d[5];
572 case M68K_D6: return M68000_regs.d[6];
573 case M68K_D7: return M68000_regs.d[7];
574 case M68K_A0: return M68000_regs.a[0];
575 case M68K_A1: return M68000_regs.a[1];
576 case M68K_A2: return M68000_regs.a[2];
577 case M68K_A3: return M68000_regs.a[3];
578 case M68K_A4: return M68000_regs.a[4];
579 case M68K_A5: return M68000_regs.a[5];
580 case M68K_A6: return M68000_regs.a[6];
581 case M68K_A7: return M68000_regs.a[7];
582 case REG_PREVIOUSPC: return M68000_regs.previous_pc;
583 /* TODO: Verify that this is the right thing to do for the purpose? */
584 default:
585 if( regnum <= REG_SP_CONTENTS )
586 {
587 unsigned offset = M68000_regs.isp + 4 * (REG_SP_CONTENTS - regnum);
588 if( offset < 0xfffffd )
589 return (*a68k_memory_intf.read32)( offset );
590 }
591 }
592 return 0;
593 }
594
m68000_set_reg(int regnum,unsigned val)595 void m68000_set_reg(int regnum, unsigned val)
596 {
597 switch( regnum )
598 {
599 case REG_PC:
600 case M68K_PC: M68000_regs.pc = val; break;
601 case REG_SP:
602 case M68K_ISP: M68000_regs.isp = val; break;
603 case M68K_USP: M68000_regs.usp = val; break;
604 case M68K_SR: M68000_regs.sr = val; break;
605 case M68K_VBR: M68000_regs.vbr = val; break;
606 case M68K_SFC: M68000_regs.sfc = val; break;
607 case M68K_DFC: M68000_regs.dfc = val; break;
608 case M68K_D0: M68000_regs.d[0] = val; break;
609 case M68K_D1: M68000_regs.d[1] = val; break;
610 case M68K_D2: M68000_regs.d[2] = val; break;
611 case M68K_D3: M68000_regs.d[3] = val; break;
612 case M68K_D4: M68000_regs.d[4] = val; break;
613 case M68K_D5: M68000_regs.d[5] = val; break;
614 case M68K_D6: M68000_regs.d[6] = val; break;
615 case M68K_D7: M68000_regs.d[7] = val; break;
616 case M68K_A0: M68000_regs.a[0] = val; break;
617 case M68K_A1: M68000_regs.a[1] = val; break;
618 case M68K_A2: M68000_regs.a[2] = val; break;
619 case M68K_A3: M68000_regs.a[3] = val; break;
620 case M68K_A4: M68000_regs.a[4] = val; break;
621 case M68K_A5: M68000_regs.a[5] = val; break;
622 case M68K_A6: M68000_regs.a[6] = val; break;
623 case M68K_A7: M68000_regs.a[7] = val; break;
624 /* TODO: Verify that this is the right thing to do for the purpose? */
625 default:
626 if( regnum <= REG_SP_CONTENTS )
627 {
628 unsigned offset = M68000_regs.isp + 4 * (REG_SP_CONTENTS - regnum);
629 if( offset < 0xfffffd )
630 (*a68k_memory_intf.write32)( offset, val );
631 }
632 }
633 }
634
m68k_assert_irq(int int_line)635 void m68k_assert_irq(int int_line)
636 {
637 /* Save icount */
638 int StartCount = m68k_ICount;
639
640 M68000_regs.IRQ_level = int_line;
641
642 /* Now check for Interrupt */
643
644 m68k_ICount = -1;
645 M68000_RUN();
646
647 /* Restore Count */
648 m68k_ICount = StartCount;
649 }
650
m68k_clear_irq(int int_line)651 void m68k_clear_irq(int int_line)
652 {
653 M68000_regs.IRQ_level = 0;
654 }
655
m68000_set_irq_line(int irqline,int state)656 void m68000_set_irq_line(int irqline, int state)
657 {
658 if (irqline == IRQ_LINE_NMI)
659 irqline = 7;
660 switch(state)
661 {
662 case CLEAR_LINE:
663 m68k_clear_irq(irqline);
664 return;
665 case ASSERT_LINE:
666 m68k_assert_irq(irqline);
667 return;
668 default:
669 m68k_assert_irq(irqline);
670 return;
671 }
672 }
673
m68000_set_irq_callback(int (* callback)(int irqline))674 void m68000_set_irq_callback(int (*callback)(int irqline))
675 {
676 M68000_regs.irq_callback = callback;
677 }
678
m68000_set_reset_callback(int (* callback)(void))679 void m68000_set_reset_callback(int (*callback)(void))
680 {
681 M68000_regs.reset_callback = callback;
682 }
683
684 /****************************************************************************
685 * Return a formatted string for a register
686 ****************************************************************************/
m68000_info(void * context,int regnum)687 const char *m68000_info(void *context, int regnum)
688 {
689 #ifdef MAME_DEBUG
690 extern int m68k_disassemble(char* str_buff, int pc, int cputype);
691 #endif
692
693 static char buffer[32][47+1];
694 static int which;
695 a68k_cpu_context *r = context;
696
697 which = (which+1) % 32;
698 buffer[which][0] = '\0';
699 if( !context )
700 r = &M68000_regs;
701
702 switch( regnum )
703 {
704 case CPU_INFO_REG+M68K_PC: sprintf(buffer[which], "PC:%06X", r->pc); break;
705 case CPU_INFO_REG+M68K_ISP: sprintf(buffer[which], "ISP:%08X", r->isp); break;
706 case CPU_INFO_REG+M68K_USP: sprintf(buffer[which], "USP:%08X", r->usp); break;
707 case CPU_INFO_REG+M68K_SR: sprintf(buffer[which], "SR:%08X", r->sr); break;
708 case CPU_INFO_REG+M68K_VBR: sprintf(buffer[which], "VBR:%08X", r->vbr); break;
709 case CPU_INFO_REG+M68K_SFC: sprintf(buffer[which], "SFC:%08X", r->sfc); break;
710 case CPU_INFO_REG+M68K_DFC: sprintf(buffer[which], "DFC:%08X", r->dfc); break;
711 case CPU_INFO_REG+M68K_D0: sprintf(buffer[which], "D0:%08X", r->d[0]); break;
712 case CPU_INFO_REG+M68K_D1: sprintf(buffer[which], "D1:%08X", r->d[1]); break;
713 case CPU_INFO_REG+M68K_D2: sprintf(buffer[which], "D2:%08X", r->d[2]); break;
714 case CPU_INFO_REG+M68K_D3: sprintf(buffer[which], "D3:%08X", r->d[3]); break;
715 case CPU_INFO_REG+M68K_D4: sprintf(buffer[which], "D4:%08X", r->d[4]); break;
716 case CPU_INFO_REG+M68K_D5: sprintf(buffer[which], "D5:%08X", r->d[5]); break;
717 case CPU_INFO_REG+M68K_D6: sprintf(buffer[which], "D6:%08X", r->d[6]); break;
718 case CPU_INFO_REG+M68K_D7: sprintf(buffer[which], "D7:%08X", r->d[7]); break;
719 case CPU_INFO_REG+M68K_A0: sprintf(buffer[which], "A0:%08X", r->a[0]); break;
720 case CPU_INFO_REG+M68K_A1: sprintf(buffer[which], "A1:%08X", r->a[1]); break;
721 case CPU_INFO_REG+M68K_A2: sprintf(buffer[which], "A2:%08X", r->a[2]); break;
722 case CPU_INFO_REG+M68K_A3: sprintf(buffer[which], "A3:%08X", r->a[3]); break;
723 case CPU_INFO_REG+M68K_A4: sprintf(buffer[which], "A4:%08X", r->a[4]); break;
724 case CPU_INFO_REG+M68K_A5: sprintf(buffer[which], "A5:%08X", r->a[5]); break;
725 case CPU_INFO_REG+M68K_A6: sprintf(buffer[which], "A6:%08X", r->a[6]); break;
726 case CPU_INFO_REG+M68K_A7: sprintf(buffer[which], "A7:%08X", r->a[7]); break;
727 case CPU_INFO_FLAGS:
728 sprintf(buffer[which], "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
729 r->sr & 0x8000 ? 'T':'.',
730 r->sr & 0x4000 ? '?':'.',
731 r->sr & 0x2000 ? 'S':'.',
732 r->sr & 0x1000 ? '?':'.',
733 r->sr & 0x0800 ? '?':'.',
734 r->sr & 0x0400 ? 'I':'.',
735 r->sr & 0x0200 ? 'I':'.',
736 r->sr & 0x0100 ? 'I':'.',
737 r->sr & 0x0080 ? '?':'.',
738 r->sr & 0x0040 ? '?':'.',
739 r->sr & 0x0020 ? '?':'.',
740 r->sr & 0x0010 ? 'X':'.',
741 r->sr & 0x0008 ? 'N':'.',
742 r->sr & 0x0004 ? 'Z':'.',
743 r->sr & 0x0002 ? 'V':'.',
744 r->sr & 0x0001 ? 'C':'.');
745 break;
746 case CPU_INFO_NAME: return "68000";
747 case CPU_INFO_FAMILY: return "Motorola 68K";
748 case CPU_INFO_VERSION: return "0.16";
749 case CPU_INFO_FILE: return __FILE__;
750 case CPU_INFO_CREDITS: return "Copyright 1998,99 Mike Coates, Darren Olafson. All rights reserved";
751 case CPU_INFO_REG_LAYOUT: return (const char*)M68K_layout;
752 case CPU_INFO_WIN_LAYOUT: return (const char*)m68k_win_layout;
753 }
754 return buffer[which];
755 }
756
m68000_dasm(char * buffer,unsigned pc)757 unsigned m68000_dasm(char *buffer, unsigned pc)
758 {
759 A68K_SET_PC_CALLBACK(pc);
760
761 #ifdef MAME_DEBUG
762 m68k_memory_intf = a68k_memory_intf;
763 return m68k_disassemble(buffer, pc, M68K_CPU_TYPE_68000);
764 #else
765 sprintf(buffer, "$%04X", cpu_readop16(pc) );
766 return 2;
767 #endif
768 }
769
770 /****************************************************************************
771 * M68010 section
772 ****************************************************************************/
773
774 #if (HAS_M68010)
775
m68010_reset(void * param)776 void m68010_reset(void *param)
777 {
778 if (a68k_memory_intf.read8 != cpu_readmem24bew)
779 a68k_memory_intf = interface_a24_d16;
780
781 m68k16_reset_common();
782
783 M68000_regs.CPUtype=1;
784 M68000_regs.Memory_Interface = a68k_memory_intf;
785 }
786
m68010_init(void)787 void m68010_init(void) { m68000_init(); }
m68010_exit(void)788 void m68010_exit(void) { m68000_exit(); }
m68010_execute(int cycles)789 int m68010_execute(int cycles) { return m68000_execute(cycles); }
m68010_get_context(void * dst)790 unsigned m68010_get_context(void *dst) { return m68000_get_context(dst); }
791
m68010_set_context(void * src)792 void m68010_set_context(void *src)
793 {
794 if( src )
795 {
796 M68000_regs = *(a68k_cpu_context*)src;
797 a68k_memory_intf = M68000_regs.Memory_Interface;
798 }
799 }
800
m68010_get_reg(int regnum)801 unsigned m68010_get_reg(int regnum) { return m68000_get_reg(regnum); }
m68010_set_reg(int regnum,unsigned val)802 void m68010_set_reg(int regnum, unsigned val) { m68000_set_reg(regnum,val); }
m68010_set_irq_line(int irqline,int state)803 void m68010_set_irq_line(int irqline, int state) { m68000_set_irq_line(irqline,state); }
m68010_set_irq_callback(int (* callback)(int irqline))804 void m68010_set_irq_callback(int (*callback)(int irqline)) { m68000_set_irq_callback(callback); }
805
m68010_info(void * context,int regnum)806 const char *m68010_info(void *context, int regnum)
807 {
808 switch( regnum )
809 {
810 case CPU_INFO_NAME: return "68010";
811 }
812 return m68000_info(context,regnum);
813 }
814
m68010_dasm(char * buffer,unsigned pc)815 unsigned m68010_dasm(char *buffer, unsigned pc)
816 {
817 A68K_SET_PC_CALLBACK(pc);
818
819 #ifdef MAME_DEBUG
820 m68k_memory_intf = a68k_memory_intf;
821 return m68k_disassemble(buffer, pc, M68K_CPU_TYPE_68010);
822 #else
823 sprintf(buffer, "$%04X", cpu_readop16(pc) );
824 return 2;
825 #endif
826 }
827 #endif
828
829
830 #endif /* A68K0 */
831
832
833 /****************************************************************************
834 * M68020 section
835 ****************************************************************************/
836
837 #ifdef A68K2
838
m68020_init(void)839 void m68020_init(void)
840 {
841 a68k_state_register("m68020");
842 M68020_regs.reset_callback = 0;
843 }
844
m68k32_reset_common(void)845 static void m68k32_reset_common(void)
846 {
847 int (*rc)(void);
848
849 rc = M68020_regs.reset_callback;
850 memset(&M68020_regs,0,sizeof(M68020_regs));
851 M68020_regs.reset_callback = rc;
852
853 M68020_regs.a[7] = M68020_regs.isp = (( READOP(0) << 16 ) | READOP(2));
854 M68020_regs.pc = (( READOP(4) << 16 ) | READOP(6)) & 0xffffff;
855 M68020_regs.sr_high = 0x27;
856
857 #ifdef MAME_DEBUG
858 M68020_regs.sr = 0x2700;
859 #endif
860
861 M68020_RESET();
862 }
863
864 #if (HAS_M68020)
865
m68020_reset(void * param)866 void m68020_reset(void *param)
867 {
868 if (a68k_memory_intf.read8 != cpu_readmem32bedw)
869 a68k_memory_intf = interface_a32_d32;
870
871 m68k32_reset_common();
872
873 M68020_regs.CPUtype=2;
874 M68020_regs.Memory_Interface = a68k_memory_intf;
875 }
876
m68020_exit(void)877 void m68020_exit(void)
878 {
879 /* nothing to do ? */
880 }
881
m68020_execute(int cycles)882 int m68020_execute(int cycles)
883 {
884 if (M68020_regs.IRQ_level == 0x80) return cycles; /* STOP with no IRQs */
885
886 m68k_ICount = cycles;
887
888 #ifdef MAME_DEBUG
889 do
890 {
891 if (mame_debug)
892 {
893 #ifdef TRACE68K
894
895 int StartCycle = m68k_ICount;
896
897 skiptrace++;
898
899 if (skiptrace > 0)
900 {
901 int mycount, areg, dreg;
902 areg = dreg = 0;
903 for (mycount=7;mycount>=0;mycount--)
904 {
905 areg = areg + M68020_regs.a[mycount];
906 dreg = dreg + M68020_regs.d[mycount];
907 }
908
909 log_cb(RETRO_LOG_DEBUG, LOGPRE "=> %8x %8x ",areg,dreg);
910 log_cb(RETRO_LOG_DEBUG, LOGPRE "%6x %4x %d\n",M68020_regs.pc,M68020_regs.sr & 0x271F,m68k_ICount);
911 }
912 #endif
913
914 #if 0
915 m68k_memory_intf = a68k_memory_intf;
916 #endif
917 MAME_Debug();
918 M68020_RUN();
919
920 #ifdef TRACE68K
921 if ((M68020_regs.IRQ_level & 0x80) || (cpu_getstatus(cpu_getactivecpu()) == 0))
922 m68k_ICount = 0;
923 else
924 m68k_ICount = StartCycle - 12;
925 #endif
926 }
927 else
928 M68020_RUN();
929
930 } while (m68k_ICount > 0);
931
932 #else
933
934 M68020_RUN();
935
936 #endif /* MAME_DEBUG */
937
938 return (cycles - m68k_ICount);
939 }
940
m68020_get_context(void * dst)941 unsigned m68020_get_context(void *dst)
942 {
943 if( dst )
944 *(a68k_cpu_context*)dst = M68020_regs;
945 return sizeof(a68k_cpu_context);
946 }
947
m68020_set_context(void * src)948 void m68020_set_context(void *src)
949 {
950 if( src )
951 {
952 M68020_regs = *(a68k_cpu_context*)src;
953 a68k_memory_intf = M68020_regs.Memory_Interface;
954 }
955 }
956
m68020_get_reg(int regnum)957 unsigned m68020_get_reg(int regnum)
958 {
959 switch( regnum )
960 {
961 case REG_PC:
962 case M68K_PC: return M68020_regs.pc;
963 case REG_SP:
964 case M68K_ISP: return M68020_regs.isp;
965 case M68K_USP: return M68020_regs.usp;
966 case M68K_SR: return M68020_regs.sr;
967 case M68K_VBR: return M68020_regs.vbr;
968 case M68K_SFC: return M68020_regs.sfc;
969 case M68K_DFC: return M68020_regs.dfc;
970 case M68K_D0: return M68020_regs.d[0];
971 case M68K_D1: return M68020_regs.d[1];
972 case M68K_D2: return M68020_regs.d[2];
973 case M68K_D3: return M68020_regs.d[3];
974 case M68K_D4: return M68020_regs.d[4];
975 case M68K_D5: return M68020_regs.d[5];
976 case M68K_D6: return M68020_regs.d[6];
977 case M68K_D7: return M68020_regs.d[7];
978 case M68K_A0: return M68020_regs.a[0];
979 case M68K_A1: return M68020_regs.a[1];
980 case M68K_A2: return M68020_regs.a[2];
981 case M68K_A3: return M68020_regs.a[3];
982 case M68K_A4: return M68020_regs.a[4];
983 case M68K_A5: return M68020_regs.a[5];
984 case M68K_A6: return M68020_regs.a[6];
985 case M68K_A7: return M68020_regs.a[7];
986 case REG_PREVIOUSPC: return M68020_regs.previous_pc;
987 /* TODO: Verify that this is the right thing to do for the purpose? */
988 default:
989 if( regnum <= REG_SP_CONTENTS )
990 {
991 unsigned offset = M68020_regs.isp + 4 * (REG_SP_CONTENTS - regnum);
992 if( offset < 0xfffffd )
993 return (*a68k_memory_intf.read32)( offset );
994 }
995 }
996 return 0;
997 }
998
m68020_set_reg(int regnum,unsigned val)999 void m68020_set_reg(int regnum, unsigned val)
1000 {
1001 switch( regnum )
1002 {
1003 case REG_PC:
1004 case M68K_PC: M68020_regs.pc = val; break;
1005 case REG_SP:
1006 case M68K_ISP: M68020_regs.isp = val; break;
1007 case M68K_USP: M68020_regs.usp = val; break;
1008 case M68K_SR: M68020_regs.sr = val; break;
1009 case M68K_VBR: M68020_regs.vbr = val; break;
1010 case M68K_SFC: M68020_regs.sfc = val; break;
1011 case M68K_DFC: M68020_regs.dfc = val; break;
1012 case M68K_D0: M68020_regs.d[0] = val; break;
1013 case M68K_D1: M68020_regs.d[1] = val; break;
1014 case M68K_D2: M68020_regs.d[2] = val; break;
1015 case M68K_D3: M68020_regs.d[3] = val; break;
1016 case M68K_D4: M68020_regs.d[4] = val; break;
1017 case M68K_D5: M68020_regs.d[5] = val; break;
1018 case M68K_D6: M68020_regs.d[6] = val; break;
1019 case M68K_D7: M68020_regs.d[7] = val; break;
1020 case M68K_A0: M68020_regs.a[0] = val; break;
1021 case M68K_A1: M68020_regs.a[1] = val; break;
1022 case M68K_A2: M68020_regs.a[2] = val; break;
1023 case M68K_A3: M68020_regs.a[3] = val; break;
1024 case M68K_A4: M68020_regs.a[4] = val; break;
1025 case M68K_A5: M68020_regs.a[5] = val; break;
1026 case M68K_A6: M68020_regs.a[6] = val; break;
1027 case M68K_A7: M68020_regs.a[7] = val; break;
1028 /* TODO: Verify that this is the right thing to do for the purpose? */
1029 default:
1030 if( regnum <= REG_SP_CONTENTS )
1031 {
1032 unsigned offset = M68020_regs.isp + 4 * (REG_SP_CONTENTS - regnum);
1033 if( offset < 0xfffffd )
1034 (*a68k_memory_intf.write32)( offset, val );
1035 }
1036 }
1037 }
1038
m68020_assert_irq(int int_line)1039 void m68020_assert_irq(int int_line)
1040 {
1041 /* Save icount */
1042 int StartCount = m68k_ICount;
1043
1044 M68020_regs.IRQ_level = int_line;
1045
1046 /* Now check for Interrupt */
1047
1048 m68k_ICount = -1;
1049 M68020_RUN();
1050
1051 /* Restore Count */
1052 m68k_ICount = StartCount;
1053 }
1054
m68020_clear_irq(int int_line)1055 void m68020_clear_irq(int int_line)
1056 {
1057 M68020_regs.IRQ_level = 0;
1058 }
1059
m68020_set_irq_line(int irqline,int state)1060 void m68020_set_irq_line(int irqline, int state)
1061 {
1062 if (irqline == IRQ_LINE_NMI)
1063 irqline = 7;
1064 switch(state)
1065 {
1066 case CLEAR_LINE:
1067 m68020_clear_irq(irqline);
1068 return;
1069 case ASSERT_LINE:
1070 m68020_assert_irq(irqline);
1071 return;
1072 default:
1073 m68020_assert_irq(irqline);
1074 return;
1075 }
1076 }
1077
m68020_set_irq_callback(int (* callback)(int irqline))1078 void m68020_set_irq_callback(int (*callback)(int irqline))
1079 {
1080 M68020_regs.irq_callback = callback;
1081 }
1082
m68020_set_reset_callback(int (* callback)(void))1083 void m68020_set_reset_callback(int (*callback)(void))
1084 {
1085 M68020_regs.reset_callback = callback;
1086 }
1087
m68020_info(void * context,int regnum)1088 const char *m68020_info(void *context, int regnum)
1089 {
1090 #ifdef MAME_DEBUG
1091 extern int m68k_disassemble(char* str_buff, int pc, int cputype);
1092 #endif
1093
1094 static char buffer[32][47+1];
1095 static int which;
1096 a68k_cpu_context *r = context;
1097
1098 which = (which + 1) % 32;
1099 buffer[which][0] = '\0';
1100 if( !context )
1101 r = &M68020_regs;
1102
1103 switch( regnum )
1104 {
1105 case CPU_INFO_REG+M68K_PC: sprintf(buffer[which], "PC:%06X", r->pc); break;
1106 case CPU_INFO_REG+M68K_ISP: sprintf(buffer[which], "ISP:%08X", r->isp); break;
1107 case CPU_INFO_REG+M68K_USP: sprintf(buffer[which], "USP:%08X", r->usp); break;
1108 case CPU_INFO_REG+M68K_SR: sprintf(buffer[which], "SR:%08X", r->sr); break;
1109 case CPU_INFO_REG+M68K_VBR: sprintf(buffer[which], "VBR:%08X", r->vbr); break;
1110 case CPU_INFO_REG+M68K_SFC: sprintf(buffer[which], "SFC:%08X", r->sfc); break;
1111 case CPU_INFO_REG+M68K_DFC: sprintf(buffer[which], "DFC:%08X", r->dfc); break;
1112 case CPU_INFO_REG+M68K_D0: sprintf(buffer[which], "D0:%08X", r->d[0]); break;
1113 case CPU_INFO_REG+M68K_D1: sprintf(buffer[which], "D1:%08X", r->d[1]); break;
1114 case CPU_INFO_REG+M68K_D2: sprintf(buffer[which], "D2:%08X", r->d[2]); break;
1115 case CPU_INFO_REG+M68K_D3: sprintf(buffer[which], "D3:%08X", r->d[3]); break;
1116 case CPU_INFO_REG+M68K_D4: sprintf(buffer[which], "D4:%08X", r->d[4]); break;
1117 case CPU_INFO_REG+M68K_D5: sprintf(buffer[which], "D5:%08X", r->d[5]); break;
1118 case CPU_INFO_REG+M68K_D6: sprintf(buffer[which], "D6:%08X", r->d[6]); break;
1119 case CPU_INFO_REG+M68K_D7: sprintf(buffer[which], "D7:%08X", r->d[7]); break;
1120 case CPU_INFO_REG+M68K_A0: sprintf(buffer[which], "A0:%08X", r->a[0]); break;
1121 case CPU_INFO_REG+M68K_A1: sprintf(buffer[which], "A1:%08X", r->a[1]); break;
1122 case CPU_INFO_REG+M68K_A2: sprintf(buffer[which], "A2:%08X", r->a[2]); break;
1123 case CPU_INFO_REG+M68K_A3: sprintf(buffer[which], "A3:%08X", r->a[3]); break;
1124 case CPU_INFO_REG+M68K_A4: sprintf(buffer[which], "A4:%08X", r->a[4]); break;
1125 case CPU_INFO_REG+M68K_A5: sprintf(buffer[which], "A5:%08X", r->a[5]); break;
1126 case CPU_INFO_REG+M68K_A6: sprintf(buffer[which], "A6:%08X", r->a[6]); break;
1127 case CPU_INFO_REG+M68K_A7: sprintf(buffer[which], "A7:%08X", r->a[7]); break;
1128 case CPU_INFO_FLAGS:
1129 sprintf(buffer[which], "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
1130 r->sr & 0x8000 ? 'T':'.',
1131 r->sr & 0x4000 ? '?':'.',
1132 r->sr & 0x2000 ? 'S':'.',
1133 r->sr & 0x1000 ? '?':'.',
1134 r->sr & 0x0800 ? '?':'.',
1135 r->sr & 0x0400 ? 'I':'.',
1136 r->sr & 0x0200 ? 'I':'.',
1137 r->sr & 0x0100 ? 'I':'.',
1138 r->sr & 0x0080 ? '?':'.',
1139 r->sr & 0x0040 ? '?':'.',
1140 r->sr & 0x0020 ? '?':'.',
1141 r->sr & 0x0010 ? 'X':'.',
1142 r->sr & 0x0008 ? 'N':'.',
1143 r->sr & 0x0004 ? 'Z':'.',
1144 r->sr & 0x0002 ? 'V':'.',
1145 r->sr & 0x0001 ? 'C':'.');
1146 break;
1147 case CPU_INFO_NAME: return "68020";
1148 case CPU_INFO_FAMILY: return "Motorola 68K";
1149 case CPU_INFO_VERSION: return "0.16";
1150 case CPU_INFO_FILE: return __FILE__;
1151 case CPU_INFO_CREDITS: return "Copyright 1998,99 Mike Coates, Darren Olafson. All rights reserved";
1152 case CPU_INFO_REG_LAYOUT: return (const char*)M68K_layout;
1153 case CPU_INFO_WIN_LAYOUT: return (const char*)m68k_win_layout;
1154 }
1155 return buffer[which];
1156 }
1157
m68020_dasm(char * buffer,unsigned pc)1158 unsigned m68020_dasm(char *buffer, unsigned pc)
1159 {
1160 A68K_SET_PC_CALLBACK(pc);
1161
1162 #ifdef MAME_DEBUG
1163 m68k_memory_intf = a68k_memory_intf;
1164 return m68k_disassemble(buffer, pc, M68K_CPU_TYPE_68020);
1165 #else
1166 sprintf(buffer, "$%04X", cpu_readop16(pc) );
1167 return 2;
1168 #endif
1169 }
1170 #endif
1171
1172 #if (HAS_M68EC020)
1173
m68ec020_reset(void * param)1174 void m68ec020_reset(void *param)
1175 {
1176 if (a68k_memory_intf.read8 != cpu_readmem24bedw)
1177 a68k_memory_intf = interface_a24_d32;
1178
1179 m68k32_reset_common();
1180
1181 M68020_regs.CPUtype=2;
1182 M68020_regs.Memory_Interface = a68k_memory_intf;
1183 }
1184
m68ec020_init(void)1185 void m68ec020_init(void) { m68020_init(); }
m68ec020_exit(void)1186 void m68ec020_exit(void) { m68020_exit(); }
m68ec020_execute(int cycles)1187 int m68ec020_execute(int cycles) { return m68020_execute(cycles); }
m68ec020_get_context(void * dst)1188 unsigned m68ec020_get_context(void *dst) { return m68020_get_context(dst); }
1189
m68ec020_set_context(void * src)1190 void m68ec020_set_context(void *src)
1191 {
1192 if( src )
1193 {
1194 M68020_regs = *(a68k_cpu_context*)src;
1195 a68k_memory_intf = M68020_regs.Memory_Interface;
1196 }
1197 }
1198
m68ec020_get_reg(int regnum)1199 unsigned m68ec020_get_reg(int regnum) { return m68020_get_reg(regnum); }
m68ec020_set_reg(int regnum,unsigned val)1200 void m68ec020_set_reg(int regnum, unsigned val) { m68020_set_reg(regnum,val); }
m68ec020_set_irq_line(int irqline,int state)1201 void m68ec020_set_irq_line(int irqline, int state) { m68020_set_irq_line(irqline,state); }
m68ec020_set_irq_callback(int (* callback)(int irqline))1202 void m68ec020_set_irq_callback(int (*callback)(int irqline)) { m68020_set_irq_callback(callback); }
1203
m68ec020_info(void * context,int regnum)1204 const char *m68ec020_info(void *context, int regnum)
1205 {
1206 switch( regnum )
1207 {
1208 case CPU_INFO_NAME: return "68EC020";
1209 }
1210 return m68020_info(context,regnum);
1211 }
1212
m68ec020_dasm(char * buffer,unsigned pc)1213 unsigned m68ec020_dasm(char *buffer, unsigned pc)
1214 {
1215 A68K_SET_PC_CALLBACK(pc);
1216
1217 #ifdef MAME_DEBUG
1218 m68k_memory_intf = a68k_memory_intf;
1219 return m68k_disassemble(buffer, pc, M68K_CPU_TYPE_68EC020);
1220 #else
1221 sprintf(buffer, "$%04X", cpu_readop16(pc) );
1222 return 2;
1223 #endif
1224 }
1225
1226 #endif
1227
1228 #endif /* A68K2 */
1229