1 /*****************************************************************************
2 *
3 * z180.c
4 * Portable Z180 emulator V0.2
5 *
6 * Copyright (C) 2000 Juergen Buchmueller, all rights reserved.
7 *
8 * - This source code is released as freeware for non-commercial purposes.
9 * - You are free to use and redistribute this code in modified or
10 * unmodified form, provided you list me in the credits.
11 * - If you modify this source code, you must add a notice to each modified
12 * source file that it has been changed. If you're a nice person, you
13 * will clearly mark each change too. :)
14 * - If you wish to use this for commercial purposes, please contact me at
15 * pullmoll@t-online.de
16 * - The author of this copywritten work reserves the right to change the
17 * terms of its usage and license at any time, including retroactively
18 * - This entire notice must remain in the source code.
19 *
20 *****************************************************************************/
21
22 #include "driver.h"
23 #include "cpuintrf.h"
24 #include "state.h"
25 #include "mamedbg.h"
26 #include "z180.h"
27 #include "log.h"
28
29 /* execute main opcodes inside a big switch statement */
30 /* execute main opcodes inside a big switch statement */
31 #ifndef BIG_SWITCH
32 #define BIG_SWITCH 1
33 #endif
34
35 /* use big flag arrays (4*64K) for ADD/ADC/SUB/SBC/CP results */
36 #define BIG_FLAGS_ARRAY 1
37
38 /* Set to 1 for a more exact (but somewhat slower) Z180 emulation */
39 #define Z180_EXACT 1
40
41 /* on JP and JR opcodes check for tight loops */
42 #define BUSY_LOOP_HACKS 1
43
44 /* check for delay loops counting down BC */
45 #define TIME_LOOP_HACKS 1
46
47 static UINT8 z180_reg_layout[] = {
48 Z180_PC, Z180_SP, Z180_AF, Z180_BC, Z180_DE, Z180_HL, -1,
49 Z180_IX, Z180_IY, Z180_AF2, Z180_BC2, Z180_DE2, Z180_HL2, -1,
50 Z180_R, Z180_I, Z180_IL, Z180_IM, Z180_IFF1, Z180_IFF2, -1,
51 Z180_INT0_STATE,Z180_INT1_STATE,Z180_INT2_STATE,Z180_DC0, Z180_DC1,Z180_DC2,Z180_DC3, -1,
52 Z180_CCR,Z180_ITC,Z180_CBR, Z180_BBR, Z180_CBAR, Z180_OMCR, 0
53 };
54
55 static UINT8 z180_win_layout[] = {
56 27, 0,53, 6, /* register window (top rows) */
57 0, 0,26,22, /* disassembler window (left colums) */
58 27, 7,53, 6, /* memory #1 window (right, upper middle) */
59 27,14,53, 8, /* memory #2 window (right, lower middle) */
60 0,23,80, 1, /* command line window (bottom rows) */
61 };
62
63 /****************************************************************************/
64 /* The Z180 registers. HALT is set to 1 when the CPU is halted, the refresh */
65 /* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128) */
66 /****************************************************************************/
67 typedef struct {
68 /* 00 */ PAIR PREPC,PC,SP,AF,BC,DE,HL,IX,IY;
69 /* 24 */ PAIR AF2,BC2,DE2,HL2;
70 /* 34 */ UINT8 R,R2,IFF1,IFF2,HALT,IM,I;
71 /* 3B */ UINT8 tmdr_latch; /* flag latched TMDR0H, TMDR1H values */
72 /* 3C */ UINT32 iol; /* I/O line status bits */
73 /* 40 */ UINT8 io[64]; /* 64 internal 8 bit registers */
74 /* 80 */ offs_t mmu[16]; /* MMU address translation */
75 /* c0 */ UINT8 tmdr[2]; /* latched TMDR0H and TMDR1H values */
76 /* c2 */ UINT8 irq_max; /* number of daisy chain devices */
77 /* c3 */ INT8 request_irq; /* daisy chain next request device */
78 /* c4 */ INT8 service_irq; /* daisy chain next reti handling device */
79 /* c5 */ UINT8 nmi_state; /* nmi line state */
80 /* c6 */ UINT8 irq_state[10]; /* irq line states (INT0,INT1,INT2) */
81 /* d0 */ UINT8 int_state[Z80_MAXDAISY];
82 /* d4 */ Z80_DaisyChain irq[Z80_MAXDAISY];
83 /* e4 */ int (*irq_callback)(int irqline);
84 /* e8 */ int extra_cycles; /* extra cycles for interrupts */
85 } Z180_Regs;
86
87 #define CF 0x01
88 #define NF 0x02
89 #define PF 0x04
90 #define VF PF
91 #define XF 0x08
92 #define HF 0x10
93 #define YF 0x20
94 #define ZF 0x40
95 #define SF 0x80
96
97 /* I/O line status flags */
98 #define Z180_CKA0 0x00000001 /* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
99 #define Z180_CKA1 0x00000002 /* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
100 #define Z180_CKS 0x00000004 /* I/O serial clock (active high) */
101 #define Z180_CTS0 0x00000100 /* I clear to send 0 (active low) */
102 #define Z180_CTS1 0x00000200 /* I clear to send 1 (active low) or RXS (mux) */
103 #define Z180_DCD0 0x00000400 /* I data carrier detect (active low) */
104 #define Z180_DREQ0 0x00000800 /* I data request DMA ch 0 (active low) or CKA0 (mux) */
105 #define Z180_DREQ1 0x00001000 /* I data request DMA ch 1 (active low) */
106 #define Z180_RXA0 0x00002000 /* I asynchronous receive data 0 (active high) */
107 #define Z180_RXA1 0x00004000 /* I asynchronous receive data 1 (active high) */
108 #define Z180_RXS 0x00008000 /* I clocked serial receive data (active high) or CTS1 (mux) */
109 #define Z180_RTS0 0x00010000 /* O request to send (active low) */
110 #define Z180_TEND0 0x00020000 /* O transfer end 0 (active low) or CKA1 (mux) */
111 #define Z180_TEND1 0x00040000 /* O transfer end 1 (active low) */
112 #define Z180_A18_TOUT 0x00080000 /* O transfer out (PRT channel, active low) or A18 (mux) */
113 #define Z180_TXA0 0x00100000 /* O asynchronous transmit data 0 (active high) */
114 #define Z180_TXA1 0x00200000 /* O asynchronous transmit data 1 (active high) */
115 #define Z180_TXS 0x00400000 /* O clocked serial transmit data (active high) */
116
117 #define _PPC Z180.PREPC.d /* previous program counter */
118
119 #define _PCD Z180.PC.d
120 #define _PC Z180.PC.w.l
121
122 #define _SPD Z180.SP.d
123 #define _SP Z180.SP.w.l
124
125 #define _AFD Z180.AF.d
126 #define _AF Z180.AF.w.l
127 #define _A Z180.AF.b.h
128 #define _F Z180.AF.b.l
129
130 #define _BCD Z180.BC.d
131 #define _BC Z180.BC.w.l
132 #define _B Z180.BC.b.h
133 #define _C Z180.BC.b.l
134
135 #define _DED Z180.DE.d
136 #define _DE Z180.DE.w.l
137 #define _D Z180.DE.b.h
138 #define _E Z180.DE.b.l
139
140 #define _HLD Z180.HL.d
141 #define _HL Z180.HL.w.l
142 #define _H Z180.HL.b.h
143 #define _L Z180.HL.b.l
144
145 #define _IXD Z180.IX.d
146 #define _IX Z180.IX.w.l
147 #define _HX Z180.IX.b.h
148 #define _LX Z180.IX.b.l
149
150 #define _IYD Z180.IY.d
151 #define _IY Z180.IY.w.l
152 #define _HY Z180.IY.b.h
153 #define _LY Z180.IY.b.l
154
155 #define _I Z180.I
156 #define _R Z180.R
157 #define _R2 Z180.R2
158 #define _IM Z180.IM
159 #define _IFF1 Z180.IFF1
160 #define _IFF2 Z180.IFF2
161 #define _HALT Z180.HALT
162
163 #define IO(n) Z180.io[(n)-Z180_CNTLA0]
164 #define IO_CNTLA0 IO(Z180_CNTLA0)
165 #define IO_CNTLA1 IO(Z180_CNTLA1)
166 #define IO_CNTLB0 IO(Z180_CNTLB0)
167 #define IO_CNTLB1 IO(Z180_CNTLB1)
168 #define IO_STAT0 IO(Z180_STAT0)
169 #define IO_STAT1 IO(Z180_STAT1)
170 #define IO_TDR0 IO(Z180_TDR0)
171 #define IO_TDR1 IO(Z180_TDR1)
172 #define IO_RDR0 IO(Z180_RDR0)
173 #define IO_RDR1 IO(Z180_RDR1)
174 #define IO_CNTR IO(Z180_CNTR)
175 #define IO_TRDR IO(Z180_TRDR)
176 #define IO_TMDR0L IO(Z180_TMDR0L)
177 #define IO_TMDR0H IO(Z180_TMDR0H)
178 #define IO_RLDR0L IO(Z180_RLDR0L)
179 #define IO_RLDR0H IO(Z180_RLDR0H)
180 #define IO_TCR IO(Z180_TCR)
181 #define IO_IO11 IO(Z180_IO11)
182 #define IO_ASEXT0 IO(Z180_ASEXT0)
183 #define IO_ASEXT1 IO(Z180_ASEXT1)
184 #define IO_TMDR1L IO(Z180_TMDR1L)
185 #define IO_TMDR1H IO(Z180_TMDR1H)
186 #define IO_RLDR1L IO(Z180_RLDR1L)
187 #define IO_RLDR1H IO(Z180_RLDR1H)
188 #define IO_FRC IO(Z180_FRC)
189 #define IO_IO19 IO(Z180_IO19)
190 #define IO_ASTC0L IO(Z180_ASTC0L)
191 #define IO_ASTC0H IO(Z180_ASTC0H)
192 #define IO_ASTC1L IO(Z180_ASTC1L)
193 #define IO_ASTC1H IO(Z180_ASTC1H)
194 #define IO_CMR IO(Z180_CMR)
195 #define IO_CCR IO(Z180_CCR)
196 #define IO_SAR0L IO(Z180_SAR0L)
197 #define IO_SAR0H IO(Z180_SAR0H)
198 #define IO_SAR0B IO(Z180_SAR0B)
199 #define IO_DAR0L IO(Z180_DAR0L)
200 #define IO_DAR0H IO(Z180_DAR0H)
201 #define IO_DAR0B IO(Z180_DAR0B)
202 #define IO_BCR0L IO(Z180_BCR0L)
203 #define IO_BCR0H IO(Z180_BCR0H)
204 #define IO_MAR1L IO(Z180_MAR1L)
205 #define IO_MAR1H IO(Z180_MAR1H)
206 #define IO_MAR1B IO(Z180_MAR1B)
207 #define IO_IAR1L IO(Z180_IAR1L)
208 #define IO_IAR1H IO(Z180_IAR1H)
209 #define IO_IAR1B IO(Z180_IAR1B)
210 #define IO_BCR1L IO(Z180_BCR1L)
211 #define IO_BCR1H IO(Z180_BCR1H)
212 #define IO_DSTAT IO(Z180_DSTAT)
213 #define IO_DMODE IO(Z180_DMODE)
214 #define IO_DCNTL IO(Z180_DCNTL)
215 #define IO_IL IO(Z180_IL)
216 #define IO_ITC IO(Z180_ITC)
217 #define IO_IO35 IO(Z180_IO35)
218 #define IO_RCR IO(Z180_RCR)
219 #define IO_IO37 IO(Z180_IO37)
220 #define IO_CBR IO(Z180_CBR)
221 #define IO_BBR IO(Z180_BBR)
222 #define IO_CBAR IO(Z180_CBAR)
223 #define IO_IO3B IO(Z180_IO3B)
224 #define IO_IO3C IO(Z180_IO3C)
225 #define IO_IO3D IO(Z180_IO3D)
226 #define IO_OMCR IO(Z180_OMCR)
227 #define IO_IOCR IO(Z180_IOCR)
228
229 /* 00 ASCI control register A ch 0 */
230 #define Z180_CNTLA0_MPE 0x80
231 #define Z180_CNTLA0_RE 0x40
232 #define Z180_CNTLA0_TE 0x20
233 #define Z180_CNTLA0_RTS0 0x10
234 #define Z180_CNTLA0_MPBR_EFR 0x08
235 #define Z180_CNTLA0_MODE_DATA 0x04
236 #define Z180_CNTLA0_MODE_PARITY 0x02
237 #define Z180_CNTLA0_MODE_STOPB 0x01
238
239 #define Z180_CNTLA0_RESET 0x10
240 #define Z180_CNTLA0_RMASK 0xff
241 #define Z180_CNTLA0_WMASK 0xff
242
243 /* 01 ASCI control register A ch 1 */
244 #define Z180_CNTLA1_MPE 0x80
245 #define Z180_CNTLA1_RE 0x40
246 #define Z180_CNTLA1_TE 0x20
247 #define Z180_CNTLA1_CKA1D 0x10
248 #define Z180_CNTLA1_MPBR_EFR 0x08
249 #define Z180_CNTLA1_MODE 0x07
250
251 #define Z180_CNTLA1_RESET 0x10
252 #define Z180_CNTLA1_RMASK 0xff
253 #define Z180_CNTLA1_WMASK 0xff
254
255 /* 02 ASCI control register B ch 0 */
256 #define Z180_CNTLB0_MPBT 0x80
257 #define Z180_CNTLB0_MP 0x40
258 #define Z180_CNTLB0_CTS_PS 0x20
259 #define Z180_CNTLB0_PEO 0x10
260 #define Z180_CNTLB0_DR 0x08
261 #define Z180_CNTLB0_SS 0x07
262
263 #define Z180_CNTLB0_RESET 0x07
264 #define Z180_CNTLB0_RMASK 0xff
265 #define Z180_CNTLB0_WMASK 0xff
266
267 /* 03 ASCI control register B ch 1 */
268 #define Z180_CNTLB1_MPBT 0x80
269 #define Z180_CNTLB1_MP 0x40
270 #define Z180_CNTLB1_CTS_PS 0x20
271 #define Z180_CNTLB1_PEO 0x10
272 #define Z180_CNTLB1_DR 0x08
273 #define Z180_CNTLB1_SS 0x07
274
275 #define Z180_CNTLB1_RESET 0x07
276 #define Z180_CNTLB1_RMASK 0xff
277 #define Z180_CNTLB1_WMASK 0xff
278
279 /* 04 ASCI status register 0 */
280 #define Z180_STAT0_RDRF 0x80
281 #define Z180_STAT0_OVRN 0x40
282 #define Z180_STAT0_PE 0x20
283 #define Z180_STAT0_FE 0x10
284 #define Z180_STAT0_RIE 0x08
285 #define Z180_STAT0_DCD0 0x04
286 #define Z180_STAT0_TDRE 0x02
287 #define Z180_STAT0_TIE 0x01
288
289 #define Z180_STAT0_RESET 0x00
290 #define Z180_STAT0_RMASK 0xff
291 #define Z180_STAT0_WMASK 0x09
292
293 /* 05 ASCI status register 1 */
294 #define Z180_STAT1_RDRF 0x80
295 #define Z180_STAT1_OVRN 0x40
296 #define Z180_STAT1_PE 0x20
297 #define Z180_STAT1_FE 0x10
298 #define Z180_STAT1_RIE 0x08
299 #define Z180_STAT1_CTS1E 0x04
300 #define Z180_STAT1_TDRE 0x02
301 #define Z180_STAT1_TIE 0x01
302
303 #define Z180_STAT1_RESET 0x00
304 #define Z180_STAT1_RMASK 0xff
305 #define Z180_STAT1_WMASK 0x0d
306
307 /* 06 ASCI transmit data register 0 */
308 #define Z180_TDR0_TDR 0xff
309
310 #define Z180_TDR0_RESET 0x00
311 #define Z180_TDR0_RMASK 0xff
312 #define Z180_TDR0_WMASK 0xff
313
314 /* 07 ASCI transmit data register 1 */
315 #define Z180_TDR1_TDR 0xff
316
317 #define Z180_TDR1_RESET 0x00
318 #define Z180_TDR1_RMASK 0xff
319 #define Z180_TDR1_WMASK 0xff
320
321 /* 08 ASCI receive register 0 */
322 #define Z180_RDR0_RDR 0xff
323
324 #define Z180_RDR0_RESET 0x00
325 #define Z180_RDR0_RMASK 0xff
326 #define Z180_RDR0_WMASK 0xff
327
328 /* 09 ASCI receive register 1 */
329 #define Z180_RDR1_RDR 0xff
330
331 #define Z180_RDR1_RESET 0x00
332 #define Z180_RDR1_RMASK 0xff
333 #define Z180_RDR1_WMASK 0xff
334
335 /* 0a CSI/O control/status register */
336 #define Z180_CNTR_EF 0x80
337 #define Z180_CNTR_EIE 0x40
338 #define Z180_CNTR_RE 0x20
339 #define Z180_CNTR_TE 0x10
340 #define Z180_CNTR_SS 0x07
341
342 #define Z180_CNTR_RESET 0x07
343 #define Z180_CNTR_RMASK 0xff
344 #define Z180_CNTR_WMASK 0x7f
345
346 /* 0b CSI/O transmit/receive register */
347 #define Z180_TRDR_RESET 0x00
348 #define Z180_TRDR_RMASK 0xff
349 #define Z180_TRDR_WMASK 0xff
350
351 /* 0c TIMER data register ch 0 L */
352 #define Z180_TMDR0L_RESET 0x00
353 #define Z180_TMDR0L_RMASK 0xff
354 #define Z180_TMDR0L_WMASK 0xff
355
356 /* 0d TIMER data register ch 0 H */
357 #define Z180_TMDR0H_RESET 0x00
358 #define Z180_TMDR0H_RMASK 0xff
359 #define Z180_TMDR0H_WMASK 0xff
360
361 /* 0e TIMER reload register ch 0 L */
362 #define Z180_RLDR0L_RESET 0xff
363 #define Z180_RLDR0L_RMASK 0xff
364 #define Z180_RLDR0L_WMASK 0xff
365
366 /* 0f TIMER reload register ch 0 H */
367 #define Z180_RLDR0H_RESET 0xff
368 #define Z180_RLDR0H_RMASK 0xff
369 #define Z180_RLDR0H_WMASK 0xff
370
371 /* 10 TIMER control register */
372 #define Z180_TCR_TIF1 0x80
373 #define Z180_TCR_TIF0 0x40
374 #define Z180_TCR_TIE1 0x20
375 #define Z180_TCR_TIE0 0x10
376 #define Z180_TCR_TOC1 0x08
377 #define Z180_TCR_TOC0 0x04
378 #define Z180_TCR_TDE1 0x02
379 #define Z180_TCR_TDE0 0x01
380
381 #define Z180_TCR_RESET 0x00
382 #define Z180_TCR_RMASK 0xff
383 #define Z180_TCR_WMASK 0xff
384
385 /* 11 reserved */
386 #define Z180_IO11_RESET 0x00
387 #define Z180_IO11_RMASK 0xff
388 #define Z180_IO11_WMASK 0xff
389
390 /* 12 (Z8S180/Z8L180) ASCI extension control register 0 */
391 #define Z180_ASEXT0_RDRF 0x80
392 #define Z180_ASEXT0_DCD0 0x40
393 #define Z180_ASEXT0_CTS0 0x20
394 #define Z180_ASEXT0_X1_BIT_CLK0 0x10
395 #define Z180_ASEXT0_BRG0_MODE 0x08
396 #define Z180_ASEXT0_BRK_EN 0x04
397 #define Z180_ASEXT0_BRK_DET 0x02
398 #define Z180_ASEXT0_BRK_SEND 0x01
399
400 #define Z180_ASEXT0_RESET 0x00
401 #define Z180_ASEXT0_RMASK 0xff
402 #define Z180_ASEXT0_WMASK 0xfd
403
404 /* 13 (Z8S180/Z8L180) ASCI extension control register 0 */
405 #define Z180_ASEXT1_RDRF 0x80
406 #define Z180_ASEXT1_X1_BIT_CLK1 0x10
407 #define Z180_ASEXT1_BRG1_MODE 0x08
408 #define Z180_ASEXT1_BRK_EN 0x04
409 #define Z180_ASEXT1_BRK_DET 0x02
410 #define Z180_ASEXT1_BRK_SEND 0x01
411
412 #define Z180_ASEXT1_RESET 0x00
413 #define Z180_ASEXT1_RMASK 0xff
414 #define Z180_ASEXT1_WMASK 0xfd
415
416
417 /* 14 TIMER data register ch 1 L */
418 #define Z180_TMDR1L_RESET 0x00
419 #define Z180_TMDR1L_RMASK 0xff
420 #define Z180_TMDR1L_WMASK 0xff
421
422 /* 15 TIMER data register ch 1 H */
423 #define Z180_TMDR1H_RESET 0x00
424 #define Z180_TMDR1H_RMASK 0xff
425 #define Z180_TMDR1H_WMASK 0xff
426
427 /* 16 TIMER reload register ch 1 L */
428 #define Z180_RLDR1L_RESET 0x00
429 #define Z180_RLDR1L_RMASK 0xff
430 #define Z180_RLDR1L_WMASK 0xff
431
432 /* 17 TIMER reload register ch 1 H */
433 #define Z180_RLDR1H_RESET 0x00
434 #define Z180_RLDR1H_RMASK 0xff
435 #define Z180_RLDR1H_WMASK 0xff
436
437 /* 18 free running counter */
438 #define Z180_FRC_RESET 0x00
439 #define Z180_FRC_RMASK 0xff
440 #define Z180_FRC_WMASK 0xff
441
442 /* 19 reserved */
443 #define Z180_IO19_RESET 0x00
444 #define Z180_IO19_RMASK 0xff
445 #define Z180_IO19_WMASK 0xff
446
447 /* 1a ASCI time constant ch 0 L */
448 #define Z180_ASTC0L_RESET 0x00
449 #define Z180_ASTC0L_RMASK 0xff
450 #define Z180_ASTC0L_WMASK 0xff
451
452 /* 1b ASCI time constant ch 0 H */
453 #define Z180_ASTC0H_RESET 0x00
454 #define Z180_ASTC0H_RMASK 0xff
455 #define Z180_ASTC0H_WMASK 0xff
456
457 /* 1c ASCI time constant ch 1 L */
458 #define Z180_ASTC1L_RESET 0x00
459 #define Z180_ASTC1L_RMASK 0xff
460 #define Z180_ASTC1L_WMASK 0xff
461
462 /* 1d ASCI time constant ch 1 H */
463 #define Z180_ASTC1H_RESET 0x00
464 #define Z180_ASTC1H_RMASK 0xff
465 #define Z180_ASTC1H_WMASK 0xff
466
467 /* 1e clock multiplier */
468 #define Z180_CMR_X2 0x80
469
470 #define Z180_CMR_RESET 0x7f
471 #define Z180_CMR_RMASK 0x80
472 #define Z180_CMR_WMASK 0x80
473
474 /* 1f chip control register */
475 #define Z180_CCR_CLOCK_DIVIDE 0x80
476 #define Z180_CCR_STDBY_IDLE1 0x40
477 #define Z180_CCR_BREXT 0x20
478 #define Z180_CCR_LNPHI 0x10
479 #define Z180_CCR_STDBY_IDLE0 0x08
480 #define Z180_CCR_LNIO 0x04
481 #define Z180_CCR_LNCPU_CTL 0x02
482 #define Z180_CCR_LNAD_DATA 0x01
483
484 #define Z180_CCR_RESET 0x00
485 #define Z180_CCR_RMASK 0xff
486 #define Z180_CCR_WMASK 0xff
487
488 /* 20 DMA source address register ch 0 L */
489 #define Z180_SAR0L_SAR 0xff
490
491 #define Z180_SAR0L_RESET 0x00
492 #define Z180_SAR0L_RMASK 0xff
493 #define Z180_SAR0L_WMASK 0xff
494
495 /* 21 DMA source address register ch 0 H */
496 #define Z180_SAR0H_SAR 0xff
497
498 #define Z180_SAR0H_RESET 0x00
499 #define Z180_SAR0H_RMASK 0xff
500 #define Z180_SAR0H_WMASK 0xff
501
502 /* 22 DMA source address register ch 0 B */
503 #define Z180_SAR0B_SAR 0x0f
504
505 #define Z180_SAR0B_RESET 0x00
506 #define Z180_SAR0B_RMASK 0x0f
507 #define Z180_SAR0B_WMASK 0x0f
508
509 /* 23 DMA destination address register ch 0 L */
510 #define Z180_DAR0L_DAR 0xff
511
512 #define Z180_DAR0L_RESET 0x00
513 #define Z180_DAR0L_RMASK 0xff
514 #define Z180_DAR0L_WMASK 0xff
515
516 /* 24 DMA destination address register ch 0 H */
517 #define Z180_DAR0H_DAR 0xff
518
519 #define Z180_DAR0H_RESET 0x00
520 #define Z180_DAR0H_RMASK 0xff
521 #define Z180_DAR0H_WMASK 0xff
522
523 /* 25 DMA destination address register ch 0 B */
524 #define Z180_DAR0B_DAR 0x00
525
526 #define Z180_DAR0B_RESET 0x00
527 #define Z180_DAR0B_RMASK 0x0f
528 #define Z180_DAR0B_WMASK 0x0f
529
530 /* 26 DMA byte count register ch 0 L */
531 #define Z180_BCR0L_BCR 0xff
532
533 #define Z180_BCR0L_RESET 0x00
534 #define Z180_BCR0L_RMASK 0xff
535 #define Z180_BCR0L_WMASK 0xff
536
537 /* 27 DMA byte count register ch 0 H */
538 #define Z180_BCR0H_BCR 0xff
539
540 #define Z180_BCR0H_RESET 0x00
541 #define Z180_BCR0H_RMASK 0xff
542 #define Z180_BCR0H_WMASK 0xff
543
544 /* 28 DMA memory address register ch 1 L */
545 #define Z180_MAR1L_MAR 0xff
546
547 #define Z180_MAR1L_RESET 0x00
548 #define Z180_MAR1L_RMASK 0xff
549 #define Z180_MAR1L_WMASK 0xff
550
551 /* 29 DMA memory address register ch 1 H */
552 #define Z180_MAR1H_MAR 0xff
553
554 #define Z180_MAR1H_RESET 0x00
555 #define Z180_MAR1H_RMASK 0xff
556 #define Z180_MAR1H_WMASK 0xff
557
558 /* 2a DMA memory address register ch 1 B */
559 #define Z180_MAR1B_MAR 0x0f
560
561 #define Z180_MAR1B_RESET 0x00
562 #define Z180_MAR1B_RMASK 0x0f
563 #define Z180_MAR1B_WMASK 0x0f
564
565 /* 2b DMA I/O address register ch 1 L */
566 #define Z180_IAR1L_IAR 0xff
567
568 #define Z180_IAR1L_RESET 0x00
569 #define Z180_IAR1L_RMASK 0xff
570 #define Z180_IAR1L_WMASK 0xff
571
572 /* 2c DMA I/O address register ch 1 H */
573 #define Z180_IAR1H_IAR 0xff
574
575 #define Z180_IAR1H_RESET 0x00
576 #define Z180_IAR1H_RMASK 0xff
577 #define Z180_IAR1H_WMASK 0xff
578
579 /* 2d (Z8S180/Z8L180) DMA I/O address register ch 1 B */
580 #define Z180_IAR1B_IAR 0x0f
581
582 #define Z180_IAR1B_RESET 0x00
583 #define Z180_IAR1B_RMASK 0x0f
584 #define Z180_IAR1B_WMASK 0x0f
585
586 /* 2e DMA byte count register ch 1 L */
587 #define Z180_BCR1L_BCR 0xff
588
589 #define Z180_BCR1L_RESET 0x00
590 #define Z180_BCR1L_RMASK 0xff
591 #define Z180_BCR1L_WMASK 0xff
592
593 /* 2f DMA byte count register ch 1 H */
594 #define Z180_BCR1H_BCR 0xff
595
596 #define Z180_BCR1H_RESET 0x00
597 #define Z180_BCR1H_RMASK 0xff
598 #define Z180_BCR1H_WMASK 0xff
599
600 /* 30 DMA status register */
601 #define Z180_DSTAT_DE1 0x80 /* DMA enable ch 1 */
602 #define Z180_DSTAT_DE0 0x40 /* DMA enable ch 0 */
603 #define Z180_DSTAT_DWE1 0x20 /* DMA write enable ch 0 (active low) */
604 #define Z180_DSTAT_DWE0 0x10 /* DMA write enable ch 1 (active low) */
605 #define Z180_DSTAT_DIE1 0x08 /* DMA IRQ enable ch 1 */
606 #define Z180_DSTAT_DIE0 0x04 /* DMA IRQ enable ch 0 */
607 #define Z180_DSTAT_DME 0x01 /* DMA enable (read only) */
608
609 #define Z180_DSTAT_RESET 0x30
610 #define Z180_DSTAT_RMASK 0xfd
611 #define Z180_DSTAT_WMASK 0xcc
612
613 /* 31 DMA mode register */
614 #define Z180_DMODE_DM 0x30
615 #define Z180_DMODE_SM 0x0c
616 #define Z180_DMODE_MMOD 0x04
617
618 #define Z180_DMODE_RESET 0x00
619 #define Z180_DMODE_RMASK 0x3e
620 #define Z180_DMODE_WMASK 0x3e
621
622 /* 32 DMA/WAIT control register */
623 #define Z180_DCNTL_MWI1 0x80
624 #define Z180_DCNTL_MWI0 0x40
625 #define Z180_DCNTL_IWI1 0x20
626 #define Z180_DCNTL_IWI0 0x10
627 #define Z180_DCNTL_DMS1 0x08
628 #define Z180_DCNTL_DMS0 0x04
629 #define Z180_DCNTL_DIM1 0x02
630 #define Z180_DCNTL_DIM0 0x01
631
632 #define Z180_DCNTL_RESET 0x00
633 #define Z180_DCNTL_RMASK 0xff
634 #define Z180_DCNTL_WMASK 0xff
635
636 /* 33 INT vector low register */
637 #define Z180_IL_IL 0xe0
638
639 #define Z180_IL_RESET 0x00
640 #define Z180_IL_RMASK 0xe0
641 #define Z180_IL_WMASK 0xe0
642
643 /* 34 INT/TRAP control register */
644 #define Z180_ITC_TRAP 0x80
645 #define Z180_ITC_UFO 0x40
646 #define Z180_ITC_ITE2 0x04
647 #define Z180_ITC_ITE1 0x02
648 #define Z180_ITC_ITE0 0x01
649
650 #define Z180_ITC_RESET 0x01
651 #define Z180_ITC_RMASK 0xc7
652 #define Z180_ITC_WMASK 0x87
653
654 /* 35 reserved */
655 #define Z180_IO35_RESET 0x00
656 #define Z180_IO35_RMASK 0xff
657 #define Z180_IO35_WMASK 0xff
658
659 /* 36 refresh control register */
660 #define Z180_RCR_REFE 0x80
661 #define Z180_RCR_REFW 0x80
662 #define Z180_RCR_CYC 0x03
663
664 #define Z180_RCR_RESET 0xc0
665 #define Z180_RCR_RMASK 0xc3
666 #define Z180_RCR_WMASK 0xc3
667
668 /* 37 reserved */
669 #define Z180_IO37_RESET 0x00
670 #define Z180_IO37_RMASK 0xff
671 #define Z180_IO37_WMASK 0xff
672
673 /* 38 MMU common base register */
674 #define Z180_CBR_CB 0xff
675
676 #define Z180_CBR_RESET 0x00
677 #define Z180_CBR_RMASK 0xff
678 #define Z180_CBR_WMASK 0xff
679
680 /* 39 MMU bank base register */
681 #define Z180_BBR_BB 0xff
682
683 #define Z180_BBR_RESET 0x00
684 #define Z180_BBR_RMASK 0xff
685 #define Z180_BBR_WMASK 0xff
686
687 /* 3a MMU common/bank area register */
688 #define Z180_CBAR_CA 0xf0
689 #define Z180_CBAR_BA 0x0f
690
691 #define Z180_CBAR_RESET 0xf0
692 #define Z180_CBAR_RMASK 0xff
693 #define Z180_CBAR_WMASK 0xff
694
695 /* 3b reserved */
696 #define Z180_IO3B_RESET 0x00
697 #define Z180_IO3B_RMASK 0xff
698 #define Z180_IO3B_WMASK 0xff
699
700 /* 3c reserved */
701 #define Z180_IO3C_RESET 0x00
702 #define Z180_IO3C_RMASK 0xff
703 #define Z180_IO3C_WMASK 0xff
704
705 /* 3d reserved */
706 #define Z180_IO3D_RESET 0x00
707 #define Z180_IO3D_RMASK 0xff
708 #define Z180_IO3D_WMASK 0xff
709
710 /* 3e operation mode control register */
711 #define Z180_OMCR_RESET 0x00
712 #define Z180_OMCR_RMASK 0xff
713 #define Z180_OMCR_WMASK 0xff
714
715 /* 3f I/O control register */
716 #define Z180_IOCR_RESET 0x00
717 #define Z180_IOCR_RMASK 0xff
718 #define Z180_IOCR_WMASK 0xff
719
720 int z180_icount;
721 static Z180_Regs Z180;
722 static UINT32 EA;
723 static int after_EI = 0;
724
725 static UINT8 SZ[256]; /* zero and sign flags */
726 static UINT8 SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
727 static UINT8 SZP[256]; /* zero, sign and parity flags */
728 static UINT8 SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
729 static UINT8 SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
730
731 #if BIG_FLAGS_ARRAY
732 static UINT8 *SZHVC_add = 0;
733 static UINT8 *SZHVC_sub = 0;
734 #endif
735
736 /****************************************************************************
737 * Burn an odd amount of cycles, that is instructions taking something
738 * different from 4 T-states per opcode (and R increment)
739 ****************************************************************************/
BURNODD(int cycles,int opcodes,int cyclesum)740 static INLINE void BURNODD(int cycles, int opcodes, int cyclesum)
741 {
742 if( cycles > 0 )
743 {
744 _R += (cycles / cyclesum) * opcodes;
745 z180_icount -= (cycles / cyclesum) * cyclesum;
746 }
747 }
748
749 static data8_t z180_readcontrol(offs_t port);
750 static void z180_writecontrol(offs_t port, data8_t data);
751 static void z180_dma0(void);
752 static void z180_dma1(void);
753
754 #include "z180daa.h"
755 #include "z180ops.h"
756 #include "z180tbl.h"
757
758 #include "z180cb.c"
759 #include "z180xy.c"
760 #include "z180dd.c"
761 #include "z180fd.c"
762 #include "z180ed.c"
763 #include "z180op.c"
764
z180_readcontrol(offs_t port)765 static data8_t z180_readcontrol(offs_t port)
766 {
767 /* normal external readport */
768 data8_t data = cpu_readport16(port);
769
770 /* but ignore the data and read the internal register */
771 switch ((port & 0x3f) + Z180_CNTLA0)
772 {
773 case Z180_CNTLA0:
774 data = IO_CNTLA0 & Z180_CNTLA0_RMASK;
775 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTLA0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
776 break;
777
778 case Z180_CNTLA1:
779 data = IO_CNTLA1 & Z180_CNTLA1_RMASK;
780 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTLA1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
781 break;
782
783 case Z180_CNTLB0:
784 data = IO_CNTLB0 & Z180_CNTLB0_RMASK;
785 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTLB0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
786 break;
787
788 case Z180_CNTLB1:
789 data = IO_CNTLB1 & Z180_CNTLB1_RMASK;
790 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTLB1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
791 break;
792
793 case Z180_STAT0:
794 data = IO_STAT0 & Z180_STAT0_RMASK;
795 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d STAT0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
796 break;
797
798 case Z180_STAT1:
799 data = IO_STAT1 & Z180_STAT1_RMASK;
800 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d STAT1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
801 break;
802
803 case Z180_TDR0:
804 data = IO_TDR0 & Z180_TDR0_RMASK;
805 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TDR0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
806 break;
807
808 case Z180_TDR1:
809 data = IO_TDR1 & Z180_TDR1_RMASK;
810 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TDR1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
811 break;
812
813 case Z180_RDR0:
814 data = IO_RDR0 & Z180_RDR0_RMASK;
815 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RDR0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
816 break;
817
818 case Z180_RDR1:
819 data = IO_RDR1 & Z180_RDR1_RMASK;
820 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RDR1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
821 break;
822
823 case Z180_CNTR:
824 data = IO_CNTR & Z180_CNTR_RMASK;
825 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
826 break;
827
828 case Z180_TRDR:
829 data = IO_TRDR & Z180_TRDR_RMASK;
830 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TRDR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
831 break;
832
833 case Z180_TMDR0L:
834 data = IO_TMDR0L & Z180_TMDR0L_RMASK;
835 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TMDR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
836 /* if timer is counting, latch the MSB and set the latch flag */
837 if ((IO_TCR & Z180_TCR_TDE0) == 0)
838 {
839 Z180.tmdr_latch |= 1;
840 Z180.tmdr[0] = IO_TMDR0H;
841 }
842 break;
843
844 case Z180_TMDR0H:
845 /* read latched value? */
846 if (Z180.tmdr_latch & 1)
847 {
848 Z180.tmdr_latch &= ~1;
849 data = Z180.tmdr[0] & Z180_TMDR1H_RMASK;
850 }
851 else
852 {
853 data = IO_TMDR0H & Z180_TMDR0H_RMASK;
854 }
855 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TMDR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
856 break;
857
858 case Z180_RLDR0L:
859 data = IO_RLDR0L & Z180_RLDR0L_RMASK;
860 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RLDR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
861 break;
862
863 case Z180_RLDR0H:
864 data = IO_RLDR0H & Z180_RLDR0H_RMASK;
865 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RLDR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
866 break;
867
868 case Z180_TCR:
869 data = IO_TCR & Z180_TCR_RMASK;
870 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
871 break;
872
873 case Z180_IO11:
874 data = IO_IO11 & Z180_IO11_RMASK;
875 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO11 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
876 break;
877
878 case Z180_ASEXT0:
879 data = IO_ASEXT0 & Z180_ASEXT0_RMASK;
880 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASEXT0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
881 break;
882
883 case Z180_ASEXT1:
884 data = IO_ASEXT1 & Z180_ASEXT1_RMASK;
885 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASEXT1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
886 break;
887
888 case Z180_TMDR1L:
889 data = IO_TMDR1L & Z180_TMDR1L_RMASK;
890 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TMDR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
891 /* if timer is counting, latch the MSB and set the latch flag */
892 if ((IO_TCR & Z180_TCR_TDE1) == 0)
893 {
894 Z180.tmdr_latch |= 2;
895 Z180.tmdr[1] = IO_TMDR1H;
896 }
897 break;
898
899 case Z180_TMDR1H:
900 /* read latched value? */
901 if (Z180.tmdr_latch & 2)
902 {
903 Z180.tmdr_latch &= ~2;
904 data = Z180.tmdr[0] & Z180_TMDR1H_RMASK;
905 }
906 else
907 {
908 data = IO_TMDR1H & Z180_TMDR1H_RMASK;
909 }
910 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TMDR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
911 break;
912
913 case Z180_RLDR1L:
914 data = IO_RLDR1L & Z180_RLDR1L_RMASK;
915 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RLDR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
916 break;
917
918 case Z180_RLDR1H:
919 data = IO_RLDR1H & Z180_RLDR1H_RMASK;
920 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RLDR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
921 break;
922
923 case Z180_FRC:
924 data = IO_FRC & Z180_FRC_RMASK;
925 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d FRC rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
926 break;
927
928 case Z180_IO19:
929 data = IO_IO19 & Z180_IO19_RMASK;
930 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO19 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
931 break;
932
933 case Z180_ASTC0L:
934 data = IO_ASTC0L & Z180_ASTC0L_RMASK;
935 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASTC0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
936 break;
937
938 case Z180_ASTC0H:
939 data = IO_ASTC0H & Z180_ASTC0H_RMASK;
940 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASTC0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
941 break;
942
943 case Z180_ASTC1L:
944 data = IO_ASTC1L & Z180_ASTC1L_RMASK;
945 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASTC1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
946 break;
947
948 case Z180_ASTC1H:
949 data = IO_ASTC1H & Z180_ASTC1H_RMASK;
950 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASTC1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
951 break;
952
953 case Z180_CMR:
954 data = IO_CMR & Z180_CMR_RMASK;
955 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CMR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
956 break;
957
958 case Z180_CCR:
959 data = IO_CCR & Z180_CCR_RMASK;
960 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
961 break;
962
963 case Z180_SAR0L:
964 data = IO_SAR0L & Z180_SAR0L_RMASK;
965 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d SAR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
966 break;
967
968 case Z180_SAR0H:
969 data = IO_SAR0H & Z180_SAR0H_RMASK;
970 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d SAR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
971 break;
972
973 case Z180_SAR0B:
974 data = IO_SAR0B & Z180_SAR0B_RMASK;
975 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d SAR0B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
976 break;
977
978 case Z180_DAR0L:
979 data = IO_DAR0L & Z180_DAR0L_RMASK;
980 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DAR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
981 break;
982
983 case Z180_DAR0H:
984 data = IO_DAR0H & Z180_DAR0H_RMASK;
985 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DAR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
986 break;
987
988 case Z180_DAR0B:
989 data = IO_DAR0B & Z180_DAR0B_RMASK;
990 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DAR0B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
991 break;
992
993 case Z180_BCR0L:
994 data = IO_BCR0L & Z180_BCR0L_RMASK;
995 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BCR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
996 break;
997
998 case Z180_BCR0H:
999 data = IO_BCR0H & Z180_BCR0H_RMASK;
1000 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BCR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1001 break;
1002
1003 case Z180_MAR1L:
1004 data = IO_MAR1L & Z180_MAR1L_RMASK;
1005 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d MAR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1006 break;
1007
1008 case Z180_MAR1H:
1009 data = IO_MAR1H & Z180_MAR1H_RMASK;
1010 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d MAR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1011 break;
1012
1013 case Z180_MAR1B:
1014 data = IO_MAR1B & Z180_MAR1B_RMASK;
1015 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d MAR1B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1016 break;
1017
1018 case Z180_IAR1L:
1019 data = IO_IAR1L & Z180_IAR1L_RMASK;
1020 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IAR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1021 break;
1022
1023 case Z180_IAR1H:
1024 data = IO_IAR1H & Z180_IAR1H_RMASK;
1025 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IAR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1026 break;
1027
1028 case Z180_IAR1B:
1029 data = IO_IAR1B & Z180_IAR1B_RMASK;
1030 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IAR1B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1031 break;
1032
1033 case Z180_BCR1L:
1034 data = IO_BCR1L & Z180_BCR1L_RMASK;
1035 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BCR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1036 break;
1037
1038 case Z180_BCR1H:
1039 data = IO_BCR1H & Z180_BCR1H_RMASK;
1040 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BCR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1041 break;
1042
1043 case Z180_DSTAT:
1044 data = IO_DSTAT & Z180_DSTAT_RMASK;
1045 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DSTAT rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1046 break;
1047
1048 case Z180_DMODE:
1049 data = IO_DMODE & Z180_DMODE_RMASK;
1050 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DMODE rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1051 break;
1052
1053 case Z180_DCNTL:
1054 data = IO_DCNTL & Z180_DCNTL_RMASK;
1055 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DCNTL rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1056 break;
1057
1058 case Z180_IL:
1059 data = IO_IL & Z180_IL_RMASK;
1060 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IL rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1061 break;
1062
1063 case Z180_ITC:
1064 data = IO_ITC & Z180_ITC_RMASK;
1065 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ITC rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1066 break;
1067
1068 case Z180_IO35:
1069 data = IO_IO35 & Z180_IO35_RMASK;
1070 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO35 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1071 break;
1072
1073 case Z180_RCR:
1074 data = IO_RCR & Z180_RCR_RMASK;
1075 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1076 break;
1077
1078 case Z180_IO37:
1079 data = IO_IO37 & Z180_IO37_RMASK;
1080 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO37 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1081 break;
1082
1083 case Z180_CBR:
1084 data = IO_CBR & Z180_CBR_RMASK;
1085 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CBR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1086 break;
1087
1088 case Z180_BBR:
1089 data = IO_BBR & Z180_BBR_RMASK;
1090 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BBR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1091 break;
1092
1093 case Z180_CBAR:
1094 data = IO_CBAR & Z180_CBAR_RMASK;
1095 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CBAR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1096 break;
1097
1098 case Z180_IO3B:
1099 data = IO_IO3B & Z180_IO3B_RMASK;
1100 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO3B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1101 break;
1102
1103 case Z180_IO3C:
1104 data = IO_IO3C & Z180_IO3C_RMASK;
1105 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO3C rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1106 break;
1107
1108 case Z180_IO3D:
1109 data = IO_IO3D & Z180_IO3D_RMASK;
1110 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO3D rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1111 break;
1112
1113 case Z180_OMCR:
1114 data = IO_OMCR & Z180_OMCR_RMASK;
1115 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d OMCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1116 break;
1117
1118 case Z180_IOCR:
1119 data = IO_IOCR & Z180_IOCR_RMASK;
1120 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IOCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]);
1121 break;
1122 }
1123 return data;
1124 }
1125
z180_writecontrol(offs_t port,data8_t data)1126 static void z180_writecontrol(offs_t port, data8_t data)
1127 {
1128 /* normal external write port */
1129 cpu_writeport16(port, data);
1130 /* store the data in the internal register */
1131 switch ((port & 0x3f) + Z180_CNTLA0)
1132 {
1133 case Z180_CNTLA0:
1134 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTLA0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLA0_WMASK);
1135 IO_CNTLA0 = (IO_CNTLA0 & ~Z180_CNTLA0_WMASK) | (data & Z180_CNTLA0_WMASK);
1136 break;
1137
1138 case Z180_CNTLA1:
1139 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTLA1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLA1_WMASK);
1140 IO_CNTLA1 = (IO_CNTLA1 & ~Z180_CNTLA1_WMASK) | (data & Z180_CNTLA1_WMASK);
1141 break;
1142
1143 case Z180_CNTLB0:
1144 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTLB0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLB0_WMASK);
1145 IO_CNTLB0 = (IO_CNTLB0 & ~Z180_CNTLB0_WMASK) | (data & Z180_CNTLB0_WMASK);
1146 break;
1147
1148 case Z180_CNTLB1:
1149 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTLB1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLB1_WMASK);
1150 IO_CNTLB1 = (IO_CNTLB1 & ~Z180_CNTLB1_WMASK) | (data & Z180_CNTLB1_WMASK);
1151 break;
1152
1153 case Z180_STAT0:
1154 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d STAT0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_STAT0_WMASK);
1155 IO_STAT0 = (IO_STAT0 & ~Z180_STAT0_WMASK) | (data & Z180_STAT0_WMASK);
1156 break;
1157
1158 case Z180_STAT1:
1159 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d STAT1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_STAT1_WMASK);
1160 IO_STAT1 = (IO_STAT1 & ~Z180_STAT1_WMASK) | (data & Z180_STAT1_WMASK);
1161 break;
1162
1163 case Z180_TDR0:
1164 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TDR0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TDR0_WMASK);
1165 IO_TDR0 = (IO_TDR0 & ~Z180_TDR0_WMASK) | (data & Z180_TDR0_WMASK);
1166 break;
1167
1168 case Z180_TDR1:
1169 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TDR1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TDR1_WMASK);
1170 IO_TDR1 = (IO_TDR1 & ~Z180_TDR1_WMASK) | (data & Z180_TDR1_WMASK);
1171 break;
1172
1173 case Z180_RDR0:
1174 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RDR0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RDR0_WMASK);
1175 IO_RDR0 = (IO_RDR0 & ~Z180_RDR0_WMASK) | (data & Z180_RDR0_WMASK);
1176 break;
1177
1178 case Z180_RDR1:
1179 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RDR1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RDR1_WMASK);
1180 IO_RDR1 = (IO_RDR1 & ~Z180_RDR1_WMASK) | (data & Z180_RDR1_WMASK);
1181 break;
1182
1183 case Z180_CNTR:
1184 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CNTR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTR_WMASK);
1185 IO_CNTR = (IO_CNTR & ~Z180_CNTR_WMASK) | (data & Z180_CNTR_WMASK);
1186 break;
1187
1188 case Z180_TRDR:
1189 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TRDR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TRDR_WMASK);
1190 IO_TRDR = (IO_TRDR & ~Z180_TRDR_WMASK) | (data & Z180_TRDR_WMASK);
1191 break;
1192
1193 case Z180_TMDR0L:
1194 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TMDR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR0L_WMASK);
1195 IO_TMDR0L = (IO_TMDR0L & ~Z180_TMDR0L_WMASK) | (data & Z180_TMDR0L_WMASK);
1196 break;
1197
1198 case Z180_TMDR0H:
1199 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TMDR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR0H_WMASK);
1200 IO_TMDR0H = (IO_TMDR0H & ~Z180_TMDR0H_WMASK) | (data & Z180_TMDR0H_WMASK);
1201 break;
1202
1203 case Z180_RLDR0L:
1204 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RLDR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR0L_WMASK);
1205 IO_RLDR0L = (IO_RLDR0L & ~Z180_RLDR0L_WMASK) | (data & Z180_RLDR0L_WMASK);
1206 break;
1207
1208 case Z180_RLDR0H:
1209 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RLDR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR0H_WMASK);
1210 IO_RLDR0H = (IO_RLDR0H & ~Z180_RLDR0H_WMASK) | (data & Z180_RLDR0H_WMASK);
1211 break;
1212
1213 case Z180_TCR:
1214 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TCR_WMASK);
1215 IO_TCR = (IO_TCR & ~Z180_TCR_WMASK) | (data & Z180_TCR_WMASK);
1216 break;
1217
1218 case Z180_IO11:
1219 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO11 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO11_WMASK);
1220 IO_IO11 = (IO_IO11 & ~Z180_IO11_WMASK) | (data & Z180_IO11_WMASK);
1221 break;
1222
1223 case Z180_ASEXT0:
1224 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASEXT0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASEXT0_WMASK);
1225 IO_ASEXT0 = (IO_ASEXT0 & ~Z180_ASEXT0_WMASK) | (data & Z180_ASEXT0_WMASK);
1226 break;
1227
1228 case Z180_ASEXT1:
1229 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASEXT1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASEXT1_WMASK);
1230 IO_ASEXT1 = (IO_ASEXT1 & ~Z180_ASEXT1_WMASK) | (data & Z180_ASEXT1_WMASK);
1231 break;
1232
1233 case Z180_TMDR1L:
1234 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TMDR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR1L_WMASK);
1235 IO_TMDR1L = (IO_TMDR1L & ~Z180_TMDR1L_WMASK) | (data & Z180_TMDR1L_WMASK);
1236 break;
1237
1238 case Z180_TMDR1H:
1239 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TMDR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR1H_WMASK);
1240 IO_TMDR1H = (IO_TMDR1H & ~Z180_TMDR1H_WMASK) | (data & Z180_TMDR1H_WMASK);
1241 break;
1242
1243 case Z180_RLDR1L:
1244 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RLDR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR1L_WMASK);
1245 IO_RLDR1L = (IO_RLDR1L & ~Z180_RLDR1L_WMASK) | (data & Z180_RLDR1L_WMASK);
1246 break;
1247
1248 case Z180_RLDR1H:
1249 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RLDR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR1H_WMASK);
1250 IO_RLDR1H = (IO_RLDR1H & ~Z180_RLDR1H_WMASK) | (data & Z180_RLDR1H_WMASK);
1251 break;
1252
1253 case Z180_FRC:
1254 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d FRC wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_FRC_WMASK);
1255 IO_FRC = (IO_FRC & ~Z180_FRC_WMASK) | (data & Z180_FRC_WMASK);
1256 break;
1257
1258 case Z180_IO19:
1259 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO19 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO19_WMASK);
1260 IO_IO19 = (IO_IO19 & ~Z180_IO19_WMASK) | (data & Z180_IO19_WMASK);
1261 break;
1262
1263 case Z180_ASTC0L:
1264 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASTC0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC0L_WMASK);
1265 IO_ASTC0L = (IO_ASTC0L & ~Z180_ASTC0L_WMASK) | (data & Z180_ASTC0L_WMASK);
1266 break;
1267
1268 case Z180_ASTC0H:
1269 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASTC0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC0H_WMASK);
1270 IO_ASTC0H = (IO_ASTC0H & ~Z180_ASTC0H_WMASK) | (data & Z180_ASTC0H_WMASK);
1271 break;
1272
1273 case Z180_ASTC1L:
1274 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASTC1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC1L_WMASK);
1275 IO_ASTC1L = (IO_ASTC1L & ~Z180_ASTC1L_WMASK) | (data & Z180_ASTC1L_WMASK);
1276 break;
1277
1278 case Z180_ASTC1H:
1279 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ASTC1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC1H_WMASK);
1280 IO_ASTC1H = (IO_ASTC1H & ~Z180_ASTC1H_WMASK) | (data & Z180_ASTC1H_WMASK);
1281 break;
1282
1283 case Z180_CMR:
1284 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CMR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CMR_WMASK);
1285 IO_CMR = (IO_CMR & ~Z180_CMR_WMASK) | (data & Z180_CMR_WMASK);
1286 break;
1287
1288 case Z180_CCR:
1289 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CCR_WMASK);
1290 IO_CCR = (IO_CCR & ~Z180_CCR_WMASK) | (data & Z180_CCR_WMASK);
1291 break;
1292
1293 case Z180_SAR0L:
1294 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d SAR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_SAR0L_WMASK);
1295 IO_SAR0L = (IO_SAR0L & ~Z180_SAR0L_WMASK) | (data & Z180_SAR0L_WMASK);
1296 break;
1297
1298 case Z180_SAR0H:
1299 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d SAR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_SAR0H_WMASK);
1300 IO_SAR0H = (IO_SAR0H & ~Z180_SAR0H_WMASK) | (data & Z180_SAR0H_WMASK);
1301 break;
1302
1303 case Z180_SAR0B:
1304 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d SAR0B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_SAR0B_WMASK);
1305 IO_SAR0B = (IO_SAR0B & ~Z180_SAR0B_WMASK) | (data & Z180_SAR0B_WMASK);
1306 break;
1307
1308 case Z180_DAR0L:
1309 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DAR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DAR0L_WMASK);
1310 IO_DAR0L = (IO_DAR0L & ~Z180_DAR0L_WMASK) | (data & Z180_DAR0L_WMASK);
1311 break;
1312
1313 case Z180_DAR0H:
1314 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DAR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DAR0H_WMASK);
1315 IO_DAR0H = (IO_DAR0H & ~Z180_DAR0H_WMASK) | (data & Z180_DAR0H_WMASK);
1316 break;
1317
1318 case Z180_DAR0B:
1319 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DAR0B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DAR0B_WMASK);
1320 IO_DAR0B = (IO_DAR0B & ~Z180_DAR0B_WMASK) | (data & Z180_DAR0B_WMASK);
1321 break;
1322
1323 case Z180_BCR0L:
1324 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BCR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR0L_WMASK);
1325 IO_BCR0L = (IO_BCR0L & ~Z180_BCR0L_WMASK) | (data & Z180_BCR0L_WMASK);
1326 break;
1327
1328 case Z180_BCR0H:
1329 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BCR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR0H_WMASK);
1330 IO_BCR0H = (IO_BCR0H & ~Z180_BCR0H_WMASK) | (data & Z180_BCR0H_WMASK);
1331 break;
1332
1333 case Z180_MAR1L:
1334 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d MAR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_MAR1L_WMASK);
1335 IO_MAR1L = (IO_MAR1L & ~Z180_MAR1L_WMASK) | (data & Z180_MAR1L_WMASK);
1336 break;
1337
1338 case Z180_MAR1H:
1339 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d MAR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_MAR1H_WMASK);
1340 IO_MAR1H = (IO_MAR1H & ~Z180_MAR1H_WMASK) | (data & Z180_MAR1H_WMASK);
1341 break;
1342
1343 case Z180_MAR1B:
1344 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d MAR1B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_MAR1B_WMASK);
1345 IO_MAR1B = (IO_MAR1B & ~Z180_MAR1B_WMASK) | (data & Z180_MAR1B_WMASK);
1346 break;
1347
1348 case Z180_IAR1L:
1349 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IAR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IAR1L_WMASK);
1350 IO_IAR1L = (IO_IAR1L & ~Z180_IAR1L_WMASK) | (data & Z180_IAR1L_WMASK);
1351 break;
1352
1353 case Z180_IAR1H:
1354 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IAR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IAR1H_WMASK);
1355 IO_IAR1H = (IO_IAR1H & ~Z180_IAR1H_WMASK) | (data & Z180_IAR1H_WMASK);
1356 break;
1357
1358 case Z180_IAR1B:
1359 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IAR1B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IAR1B_WMASK);
1360 IO_IAR1B = (IO_IAR1B & ~Z180_IAR1B_WMASK) | (data & Z180_IAR1B_WMASK);
1361 break;
1362
1363 case Z180_BCR1L:
1364 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BCR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR1L_WMASK);
1365 IO_BCR1L = (IO_BCR1L & ~Z180_BCR1L_WMASK) | (data & Z180_BCR1L_WMASK);
1366 break;
1367
1368 case Z180_BCR1H:
1369 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BCR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR1H_WMASK);
1370 IO_BCR1H = (IO_BCR1H & ~Z180_BCR1H_WMASK) | (data & Z180_BCR1H_WMASK);
1371 break;
1372
1373 case Z180_DSTAT:
1374 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DSTAT wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DSTAT_WMASK);
1375 IO_DSTAT = (IO_DSTAT & ~Z180_DSTAT_WMASK) | (data & Z180_DSTAT_WMASK);
1376 if ((data & (Z180_DSTAT_DE1 | Z180_DSTAT_DWE1)) == Z180_DSTAT_DE1)
1377 IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
1378 if ((data & (Z180_DSTAT_DE0 | Z180_DSTAT_DWE0)) == Z180_DSTAT_DE0)
1379 IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
1380 break;
1381
1382 case Z180_DMODE:
1383 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DMODE wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DMODE_WMASK);
1384 IO_DMODE = (IO_DMODE & ~Z180_DMODE_WMASK) | (data & Z180_DMODE_WMASK);
1385 break;
1386
1387 case Z180_DCNTL:
1388 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DCNTL wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DCNTL_WMASK);
1389 IO_DCNTL = (IO_DCNTL & ~Z180_DCNTL_WMASK) | (data & Z180_DCNTL_WMASK);
1390 break;
1391
1392 case Z180_IL:
1393 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IL wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IL_WMASK);
1394 IO_IL = (IO_IL & ~Z180_IL_WMASK) | (data & Z180_IL_WMASK);
1395 break;
1396
1397 case Z180_ITC:
1398 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d ITC wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ITC_WMASK);
1399 IO_ITC = (IO_ITC & ~Z180_ITC_WMASK) | (data & Z180_ITC_WMASK);
1400 break;
1401
1402 case Z180_IO35:
1403 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO35 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO35_WMASK);
1404 IO_IO35 = (IO_IO35 & ~Z180_IO35_WMASK) | (data & Z180_IO35_WMASK);
1405 break;
1406
1407 case Z180_RCR:
1408 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RCR_WMASK);
1409 IO_RCR = (IO_RCR & ~Z180_RCR_WMASK) | (data & Z180_RCR_WMASK);
1410 break;
1411
1412 case Z180_IO37:
1413 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO37 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO37_WMASK);
1414 IO_IO37 = (IO_IO37 & ~Z180_IO37_WMASK) | (data & Z180_IO37_WMASK);
1415 break;
1416
1417 case Z180_CBR:
1418 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CBR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CBR_WMASK);
1419 IO_CBR = (IO_CBR & ~Z180_CBR_WMASK) | (data & Z180_CBR_WMASK);
1420 z180_mmu();
1421 break;
1422
1423 case Z180_BBR:
1424 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d BBR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BBR_WMASK);
1425 IO_BBR = (IO_BBR & ~Z180_BBR_WMASK) | (data & Z180_BBR_WMASK);
1426 z180_mmu();
1427 break;
1428
1429 case Z180_CBAR:
1430 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CBAR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CBAR_WMASK);
1431 IO_CBAR = (IO_CBAR & ~Z180_CBAR_WMASK) | (data & Z180_CBAR_WMASK);
1432 z180_mmu();
1433 break;
1434
1435 case Z180_IO3B:
1436 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO3B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO3B_WMASK);
1437 IO_IO3B = (IO_IO3B & ~Z180_IO3B_WMASK) | (data & Z180_IO3B_WMASK);
1438 break;
1439
1440 case Z180_IO3C:
1441 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO3C wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO3C_WMASK);
1442 IO_IO3C = (IO_IO3C & ~Z180_IO3C_WMASK) | (data & Z180_IO3C_WMASK);
1443 break;
1444
1445 case Z180_IO3D:
1446 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IO3D wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO3D_WMASK);
1447 IO_IO3D = (IO_IO3D & ~Z180_IO3D_WMASK) | (data & Z180_IO3D_WMASK);
1448 break;
1449
1450 case Z180_OMCR:
1451 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d OMCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_OMCR_WMASK);
1452 IO_OMCR = (IO_OMCR & ~Z180_OMCR_WMASK) | (data & Z180_OMCR_WMASK);
1453 break;
1454
1455 case Z180_IOCR:
1456 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d IOCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IOCR_WMASK);
1457 IO_IOCR = (IO_IOCR & ~Z180_IOCR_WMASK) | (data & Z180_IOCR_WMASK);
1458 break;
1459 }
1460 }
1461
z180_dma0(void)1462 static void z180_dma0(void)
1463 {
1464 offs_t sar0 = 65536 * IO_SAR0B + 256 * IO_SAR0H + IO_SAR0L;
1465 offs_t dar0 = 65536 * IO_DAR0B + 256 * IO_DAR0H + IO_DAR0L;
1466 int bcr0 = 256 * IO_BCR0H + IO_BCR0L;
1467 int count = (IO_DMODE & Z180_DMODE_MMOD) ? bcr0 : 1;
1468
1469 if (bcr0 == 0)
1470 {
1471 IO_DSTAT &= ~Z180_DSTAT_DE0;
1472 return;
1473 }
1474
1475 while (count-- > 0)
1476 {
1477 /* last transfer happening now? */
1478 if (bcr0 == 1)
1479 {
1480 Z180.iol |= Z180_TEND0;
1481 }
1482 switch( IO_DMODE & (Z180_DMODE_SM | Z180_DMODE_DM) )
1483 {
1484 case 0x00: /* memory SAR0+1 to memory DAR0+1 */
1485 cpu_writemem20(dar0++, cpu_readmem20(sar0++));
1486 break;
1487 case 0x04: /* memory SAR0-1 to memory DAR0+1 */
1488 cpu_writemem20(dar0++, cpu_readmem20(sar0--));
1489 break;
1490 case 0x08: /* memory SAR0 fixed to memory DAR0+1 */
1491 cpu_writemem20(dar0++, cpu_readmem20(sar0));
1492 break;
1493 case 0x0c: /* I/O SAR0 fixed to memory DAR0+1 */
1494 if (Z180.iol & Z180_DREQ0)
1495 {
1496 cpu_writemem20(dar0++, IN(sar0));
1497 /* edge sensitive DREQ0 ? */
1498 if (IO_DCNTL & Z180_DCNTL_DIM0)
1499 {
1500 Z180.iol &= ~Z180_DREQ0;
1501 count = 0;
1502 }
1503 }
1504 break;
1505 case 0x10: /* memory SAR0+1 to memory DAR0-1 */
1506 cpu_writemem20(dar0--, cpu_readmem20(sar0++));
1507 break;
1508 case 0x14: /* memory SAR0-1 to memory DAR0-1 */
1509 cpu_writemem20(dar0--, cpu_readmem20(sar0--));
1510 break;
1511 case 0x18: /* memory SAR0 fixed to memory DAR0-1 */
1512 cpu_writemem20(dar0--, cpu_readmem20(sar0));
1513 break;
1514 case 0x1c: /* I/O SAR0 fixed to memory DAR0-1 */
1515 if (Z180.iol & Z180_DREQ0)
1516 {
1517 cpu_writemem20(dar0--, IN(sar0));
1518 /* edge sensitive DREQ0 ? */
1519 if (IO_DCNTL & Z180_DCNTL_DIM0)
1520 {
1521 Z180.iol &= ~Z180_DREQ0;
1522 count = 0;
1523 }
1524 }
1525 break;
1526 case 0x20: /* memory SAR0+1 to memory DAR0 fixed */
1527 cpu_writemem20(dar0, cpu_readmem20(sar0++));
1528 break;
1529 case 0x24: /* memory SAR0-1 to memory DAR0 fixed */
1530 cpu_writemem20(dar0, cpu_readmem20(sar0--));
1531 break;
1532 case 0x28: /* reserved */
1533 break;
1534 case 0x2c: /* reserved */
1535 break;
1536 case 0x30: /* memory SAR0+1 to I/O DAR0 fixed */
1537 if (Z180.iol & Z180_DREQ0)
1538 {
1539 OUT(dar0, cpu_readmem20(sar0++));
1540 /* edge sensitive DREQ0 ? */
1541 if (IO_DCNTL & Z180_DCNTL_DIM0)
1542 {
1543 Z180.iol &= ~Z180_DREQ0;
1544 count = 0;
1545 }
1546 }
1547 break;
1548 case 0x34: /* memory SAR0-1 to I/O DAR0 fixed */
1549 if (Z180.iol & Z180_DREQ0)
1550 {
1551 OUT(dar0, cpu_readmem20(sar0--));
1552 /* edge sensitive DREQ0 ? */
1553 if (IO_DCNTL & Z180_DCNTL_DIM0)
1554 {
1555 Z180.iol &= ~Z180_DREQ0;
1556 count = 0;
1557 }
1558 }
1559 break;
1560 case 0x38: /* reserved */
1561 break;
1562 case 0x3c: /* reserved */
1563 break;
1564 }
1565 bcr0--;
1566 count--;
1567 if ((z180_icount -= 6) < 0)
1568 break;
1569 }
1570
1571 IO_SAR0L = sar0;
1572 IO_SAR0H = sar0 >> 8;
1573 IO_SAR0B = sar0 >> 16;
1574 IO_DAR0L = dar0;
1575 IO_DAR0H = dar0 >> 8;
1576 IO_DAR0B = dar0 >> 16;
1577 IO_BCR0L = bcr0;
1578 IO_BCR0H = bcr0 >> 8;
1579
1580 /* DMA terminal count? */
1581 if (bcr0 == 0)
1582 {
1583 Z180.iol &= ~Z180_TEND0;
1584 IO_DSTAT &= ~Z180_DSTAT_DE0;
1585 /* terminal count interrupt enabled? */
1586 if (IO_DSTAT & Z180_DSTAT_DIE0 && _IFF1)
1587 take_interrupt(Z180_INT_DMA0);
1588 }
1589 }
1590
z180_dma1(void)1591 static void z180_dma1(void)
1592 {
1593 offs_t mar1 = 65536 * IO_MAR1B + 256 * IO_MAR1H + IO_MAR1L;
1594 offs_t iar1 = 256 * IO_IAR1H + IO_IAR1L;
1595 int bcr1 = 256 * IO_BCR1H + IO_BCR1L;
1596
1597 if ((Z180.iol & Z180_DREQ1) == 0)
1598 return;
1599
1600 /* counter is zero? */
1601 if (bcr1 == 0)
1602 {
1603 IO_DSTAT &= ~Z180_DSTAT_DE1;
1604 return;
1605 }
1606
1607 /* last transfer happening now? */
1608 if (bcr1 == 1)
1609 {
1610 Z180.iol |= Z180_TEND1;
1611 }
1612
1613 switch (IO_DCNTL & (Z180_DCNTL_DIM1 | Z180_DCNTL_DIM0))
1614 {
1615 case 0x00: /* memory MAR1+1 to I/O IAR1 fixed */
1616 cpu_writeport16(iar1, cpu_readmem20(mar1++));
1617 break;
1618 case 0x01: /* memory MAR1-1 to I/O IAR1 fixed */
1619 cpu_writeport16(iar1, cpu_readmem20(mar1--));
1620 break;
1621 case 0x02: /* I/O IAR1 fixed to memory MAR1+1 */
1622 cpu_writemem20(mar1++, cpu_readport16(iar1));
1623 break;
1624 case 0x03: /* I/O IAR1 fixed to memory MAR1-1 */
1625 cpu_writemem20(mar1--, cpu_readport16(iar1));
1626 break;
1627 }
1628
1629 /* edge sensitive DREQ1 ? */
1630 if (IO_DCNTL & Z180_DCNTL_DIM1)
1631 Z180.iol &= ~Z180_DREQ1;
1632
1633 IO_MAR1L = mar1;
1634 IO_MAR1H = mar1 >> 8;
1635 IO_MAR1B = mar1 >> 16;
1636 IO_BCR1L = bcr1;
1637 IO_BCR1H = bcr1 >> 8;
1638
1639 /* DMA terminal count? */
1640 if (bcr1 == 0)
1641 {
1642 Z180.iol &= ~Z180_TEND1;
1643 IO_DSTAT &= ~Z180_DSTAT_DE1;
1644 if (IO_DSTAT & Z180_DSTAT_DIE1 && _IFF1)
1645 take_interrupt(Z180_INT_DMA1);
1646 }
1647
1648 /* six cycles per transfer (minimum) */
1649 z180_icount -= 6;
1650 }
1651
z180_write_iolines(UINT32 data)1652 static void z180_write_iolines(UINT32 data)
1653 {
1654 UINT32 changes = Z180.iol ^ data;
1655
1656 /* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
1657 if (changes & Z180_CKA0)
1658 {
1659 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CKA0 %d\n", cpu_getactivecpu(), data & Z180_CKA0 ? 1 : 0);
1660 Z180.iol = (Z180.iol & ~Z180_CKA0) | (data & Z180_CKA0);
1661 }
1662
1663 /* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
1664 if (changes & Z180_CKA1)
1665 {
1666 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CKA1 %d\n", cpu_getactivecpu(), data & Z180_CKA1 ? 1 : 0);
1667 Z180.iol = (Z180.iol & ~Z180_CKA1) | (data & Z180_CKA1);
1668 }
1669
1670 /* I/O serial clock (active high) */
1671 if (changes & Z180_CKS)
1672 {
1673 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CKS %d\n", cpu_getactivecpu(), data & Z180_CKS ? 1 : 0);
1674 Z180.iol = (Z180.iol & ~Z180_CKS) | (data & Z180_CKS);
1675 }
1676
1677 /* I clear to send 0 (active low) */
1678 if (changes & Z180_CTS0)
1679 {
1680 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CTS0 %d\n", cpu_getactivecpu(), data & Z180_CTS0 ? 1 : 0);
1681 Z180.iol = (Z180.iol & ~Z180_CTS0) | (data & Z180_CTS0);
1682 }
1683
1684 /* I clear to send 1 (active low) or RXS (mux) */
1685 if (changes & Z180_CTS1)
1686 {
1687 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d CTS1 %d\n", cpu_getactivecpu(), data & Z180_CTS1 ? 1 : 0);
1688 Z180.iol = (Z180.iol & ~Z180_CTS1) | (data & Z180_CTS1);
1689 }
1690
1691 /* I data carrier detect (active low) */
1692 if (changes & Z180_DCD0)
1693 {
1694 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DCD0 %d\n", cpu_getactivecpu(), data & Z180_DCD0 ? 1 : 0);
1695 Z180.iol = (Z180.iol & ~Z180_DCD0) | (data & Z180_DCD0);
1696 }
1697
1698 /* I data request DMA ch 0 (active low) or CKA0 (mux) */
1699 if (changes & Z180_DREQ0)
1700 {
1701 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DREQ0 %d\n", cpu_getactivecpu(), data & Z180_DREQ0 ? 1 : 0);
1702 Z180.iol = (Z180.iol & ~Z180_DREQ0) | (data & Z180_DREQ0);
1703 }
1704
1705 /* I data request DMA ch 1 (active low) */
1706 if (changes & Z180_DREQ1)
1707 {
1708 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d DREQ1 %d\n", cpu_getactivecpu(), data & Z180_DREQ1 ? 1 : 0);
1709 Z180.iol = (Z180.iol & ~Z180_DREQ1) | (data & Z180_DREQ1);
1710 }
1711
1712 /* I asynchronous receive data 0 (active high) */
1713 if (changes & Z180_RXA0)
1714 {
1715 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RXA0 %d\n", cpu_getactivecpu(), data & Z180_RXA0 ? 1 : 0);
1716 Z180.iol = (Z180.iol & ~Z180_RXA0) | (data & Z180_RXA0);
1717 }
1718
1719 /* I asynchronous receive data 1 (active high) */
1720 if (changes & Z180_RXA1)
1721 {
1722 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RXA1 %d\n", cpu_getactivecpu(), data & Z180_RXA1 ? 1 : 0);
1723 Z180.iol = (Z180.iol & ~Z180_RXA1) | (data & Z180_RXA1);
1724 }
1725
1726 /* I clocked serial receive data (active high) or CTS1 (mux) */
1727 if (changes & Z180_RXS)
1728 {
1729 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RXS %d\n", cpu_getactivecpu(), data & Z180_RXS ? 1 : 0);
1730 Z180.iol = (Z180.iol & ~Z180_RXS) | (data & Z180_RXS);
1731 }
1732
1733 /* O request to send (active low) */
1734 if (changes & Z180_RTS0)
1735 {
1736 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d RTS0 won't change output\n", cpu_getactivecpu());
1737 }
1738
1739 /* O transfer end 0 (active low) or CKA1 (mux) */
1740 if (changes & Z180_TEND0)
1741 {
1742 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TEND0 won't change output\n", cpu_getactivecpu());
1743 }
1744
1745 /* O transfer end 1 (active low) */
1746 if (changes & Z180_TEND1)
1747 {
1748 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TEND1 won't change output\n", cpu_getactivecpu());
1749 }
1750
1751 /* O transfer out (PRT channel, active low) or A18 (mux) */
1752 if (changes & Z180_A18_TOUT)
1753 {
1754 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TOUT won't change output\n", cpu_getactivecpu());
1755 }
1756
1757 /* O asynchronous transmit data 0 (active high) */
1758 if (changes & Z180_TXA0)
1759 {
1760 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TXA0 won't change output\n", cpu_getactivecpu());
1761 }
1762
1763 /* O asynchronous transmit data 1 (active high) */
1764 if (changes & Z180_TXA1)
1765 {
1766 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TXA1 won't change output\n", cpu_getactivecpu());
1767 }
1768
1769 /* O clocked serial transmit data (active high) */
1770 if (changes & Z180_TXS)
1771 {
1772 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d TXS won't change output\n", cpu_getactivecpu());
1773 }
1774 }
1775
1776
z180_init(void)1777 void z180_init(void)
1778 {
1779 int cpu = cpu_getactivecpu();
1780
1781 state_save_register_UINT16("z180", cpu, "AF", &Z180.AF.w.l, 1);
1782 state_save_register_UINT16("z180", cpu, "BC", &Z180.BC.w.l, 1);
1783 state_save_register_UINT16("z180", cpu, "DE", &Z180.DE.w.l, 1);
1784 state_save_register_UINT16("z180", cpu, "HL", &Z180.HL.w.l, 1);
1785 state_save_register_UINT16("z180", cpu, "IX", &Z180.IX.w.l, 1);
1786 state_save_register_UINT16("z180", cpu, "IY", &Z180.IY.w.l, 1);
1787 state_save_register_UINT16("z180", cpu, "PC", &Z180.PC.w.l, 1);
1788 state_save_register_UINT16("z180", cpu, "SP", &Z180.SP.w.l, 1);
1789 state_save_register_UINT16("z180", cpu, "AF2", &Z180.AF2.w.l, 1);
1790 state_save_register_UINT16("z180", cpu, "BC2", &Z180.BC2.w.l, 1);
1791 state_save_register_UINT16("z180", cpu, "DE2", &Z180.DE2.w.l, 1);
1792 state_save_register_UINT16("z180", cpu, "HL2", &Z180.HL2.w.l, 1);
1793 state_save_register_UINT8("z180", cpu, "R", &Z180.R, 1);
1794 state_save_register_UINT8("z180", cpu, "R2", &Z180.R2, 1);
1795 state_save_register_UINT8("z180", cpu, "IFF1", &Z180.IFF1, 1);
1796 state_save_register_UINT8("z180", cpu, "IFF2", &Z180.IFF2, 1);
1797 state_save_register_UINT8("z180", cpu, "HALT", &Z180.HALT, 1);
1798 state_save_register_UINT8("z180", cpu, "IM", &Z180.IM, 1);
1799 state_save_register_UINT8("z180", cpu, "I", &Z180.I, 1);
1800 state_save_register_UINT8("z180", cpu, "irq_max", &Z180.irq_max, 1);
1801 state_save_register_INT8("z180", cpu, "request_irq", &Z180.request_irq, 1);
1802 state_save_register_INT8("z180", cpu, "service_irq", &Z180.service_irq, 1);
1803 state_save_register_UINT8("z180", cpu, "int_state", Z180.int_state, 4);
1804 state_save_register_UINT8("z180", cpu, "nmi_state", &Z180.nmi_state, 1);
1805 state_save_register_UINT8("z180", cpu, "int0_state", &Z180.irq_state[0], 1);
1806 state_save_register_UINT8("z180", cpu, "int1_state", &Z180.irq_state[1], 1);
1807 state_save_register_UINT8("z180", cpu, "int2_state", &Z180.irq_state[2], 1);
1808 /* daisy chain needs to be saved by z80ctc.c somehow */
1809 }
1810
1811 /****************************************************************************
1812 * Reset registers to their initial values
1813 ****************************************************************************/
z180_reset(void * param)1814 void z180_reset(void *param)
1815 {
1816 Z80_DaisyChain *daisy_chain = (Z80_DaisyChain *)param;
1817 int i, p;
1818 #if BIG_FLAGS_ARRAY
1819 if( !SZHVC_add || !SZHVC_sub )
1820 {
1821 int oldval, newval, val;
1822 UINT8 *padd, *padc, *psub, *psbc;
1823 /* allocate big flag arrays once */
1824 SZHVC_add = (UINT8 *)malloc(2*256*256);
1825 SZHVC_sub = (UINT8 *)malloc(2*256*256);
1826 if( !SZHVC_add || !SZHVC_sub )
1827 {
1828 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180: failed to allocate 2 * 128K flags arrays!!!\n");
1829 /*raise(SIGABRT);*/
1830 }
1831 padd = &SZHVC_add[ 0*256];
1832 padc = &SZHVC_add[256*256];
1833 psub = &SZHVC_sub[ 0*256];
1834 psbc = &SZHVC_sub[256*256];
1835 for (oldval = 0; oldval < 256; oldval++)
1836 {
1837 for (newval = 0; newval < 256; newval++)
1838 {
1839 /* add or adc w/o carry set */
1840 val = newval - oldval;
1841 *padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
1842 #if Z180_EXACT
1843 *padd |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1844 #endif
1845 if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF;
1846 if( newval < oldval ) *padd |= CF;
1847 if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF;
1848 padd++;
1849
1850 /* adc with carry set */
1851 val = newval - oldval - 1;
1852 *padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
1853 #if Z180_EXACT
1854 *padc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1855 #endif
1856 if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF;
1857 if( newval <= oldval ) *padc |= CF;
1858 if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF;
1859 padc++;
1860
1861 /* cp, sub or sbc w/o carry set */
1862 val = oldval - newval;
1863 *psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
1864 #if Z180_EXACT
1865 *psub |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1866 #endif
1867 if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF;
1868 if( newval > oldval ) *psub |= CF;
1869 if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF;
1870 psub++;
1871
1872 /* sbc with carry set */
1873 val = oldval - newval - 1;
1874 *psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
1875 #if Z180_EXACT
1876 *psbc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1877 #endif
1878 if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF;
1879 if( newval >= oldval ) *psbc |= CF;
1880 if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF;
1881 psbc++;
1882 }
1883 }
1884 }
1885 #endif
1886 for (i = 0; i < 256; i++)
1887 {
1888 p = 0;
1889 if( i&0x01 ) ++p;
1890 if( i&0x02 ) ++p;
1891 if( i&0x04 ) ++p;
1892 if( i&0x08 ) ++p;
1893 if( i&0x10 ) ++p;
1894 if( i&0x20 ) ++p;
1895 if( i&0x40 ) ++p;
1896 if( i&0x80 ) ++p;
1897 SZ[i] = i ? i & SF : ZF;
1898 #if Z180_EXACT
1899 SZ[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */
1900 #endif
1901 SZ_BIT[i] = i ? i & SF : ZF | PF;
1902 #if Z180_EXACT
1903 SZ_BIT[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */
1904 #endif
1905 SZP[i] = SZ[i] | ((p & 1) ? 0 : PF);
1906 SZHV_inc[i] = SZ[i];
1907 if( i == 0x80 ) SZHV_inc[i] |= VF;
1908 if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF;
1909 SZHV_dec[i] = SZ[i] | NF;
1910 if( i == 0x7f ) SZHV_dec[i] |= VF;
1911 if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF;
1912 }
1913
1914 memset(&Z180, 0, sizeof(Z180));
1915 _IX = _IY = 0xffff; /* IX and IY are FFFF after a reset! */
1916 _F = ZF; /* Zero flag is set */
1917 Z180.request_irq = -1;
1918 Z180.service_irq = -1;
1919 Z180.nmi_state = CLEAR_LINE;
1920 Z180.irq_state[0] = CLEAR_LINE;
1921 Z180.irq_state[1] = CLEAR_LINE;
1922 Z180.irq_state[2] = CLEAR_LINE;
1923
1924 /* reset io registers */
1925 IO_CNTLA0 = Z180_CNTLA0_RESET;
1926 IO_CNTLA1 = Z180_CNTLA1_RESET;
1927 IO_CNTLB0 = Z180_CNTLB0_RESET;
1928 IO_CNTLB1 = Z180_CNTLB1_RESET;
1929 IO_STAT0 = Z180_STAT0_RESET;
1930 IO_STAT1 = Z180_STAT1_RESET;
1931 IO_TDR0 = Z180_TDR0_RESET;
1932 IO_TDR1 = Z180_TDR1_RESET;
1933 IO_RDR0 = Z180_RDR0_RESET;
1934 IO_RDR1 = Z180_RDR1_RESET;
1935 IO_CNTR = Z180_CNTR_RESET;
1936 IO_TRDR = Z180_TRDR_RESET;
1937 IO_TMDR0L = Z180_TMDR0L_RESET;
1938 IO_TMDR0H = Z180_TMDR0H_RESET;
1939 IO_RLDR0L = Z180_RLDR0L_RESET;
1940 IO_RLDR0H = Z180_RLDR0H_RESET;
1941 IO_TCR = Z180_TCR_RESET;
1942 IO_IO11 = Z180_IO11_RESET;
1943 IO_ASEXT0 = Z180_ASEXT0_RESET;
1944 IO_ASEXT1 = Z180_ASEXT1_RESET;
1945 IO_TMDR1L = Z180_TMDR1L_RESET;
1946 IO_TMDR1H = Z180_TMDR1H_RESET;
1947 IO_RLDR1L = Z180_RLDR1L_RESET;
1948 IO_RLDR1H = Z180_RLDR1H_RESET;
1949 IO_FRC = Z180_FRC_RESET;
1950 IO_IO19 = Z180_IO19_RESET;
1951 IO_ASTC0L = Z180_ASTC0L_RESET;
1952 IO_ASTC0H = Z180_ASTC0H_RESET;
1953 IO_ASTC1L = Z180_ASTC1L_RESET;
1954 IO_ASTC1H = Z180_ASTC1H_RESET;
1955 IO_CMR = Z180_CMR_RESET;
1956 IO_CCR = Z180_CCR_RESET;
1957 IO_SAR0L = Z180_SAR0L_RESET;
1958 IO_SAR0H = Z180_SAR0H_RESET;
1959 IO_SAR0B = Z180_SAR0B_RESET;
1960 IO_DAR0L = Z180_DAR0L_RESET;
1961 IO_DAR0H = Z180_DAR0H_RESET;
1962 IO_DAR0B = Z180_DAR0B_RESET;
1963 IO_BCR0L = Z180_BCR0L_RESET;
1964 IO_BCR0H = Z180_BCR0H_RESET;
1965 IO_MAR1L = Z180_MAR1L_RESET;
1966 IO_MAR1H = Z180_MAR1H_RESET;
1967 IO_MAR1B = Z180_MAR1B_RESET;
1968 IO_IAR1L = Z180_IAR1L_RESET;
1969 IO_IAR1H = Z180_IAR1H_RESET;
1970 IO_IAR1B = Z180_IAR1B_RESET;
1971 IO_BCR1L = Z180_BCR1L_RESET;
1972 IO_BCR1H = Z180_BCR1H_RESET;
1973 IO_DSTAT = Z180_DSTAT_RESET;
1974 IO_DMODE = Z180_DMODE_RESET;
1975 IO_DCNTL = Z180_DCNTL_RESET;
1976 IO_IL = Z180_IL_RESET;
1977 IO_ITC = Z180_ITC_RESET;
1978 IO_IO35 = Z180_IO35_RESET;
1979 IO_RCR = Z180_RCR_RESET;
1980 IO_IO37 = Z180_IO37_RESET;
1981 IO_CBR = Z180_CBR_RESET;
1982 IO_BBR = Z180_BBR_RESET;
1983 IO_CBAR = Z180_CBAR_RESET;
1984 IO_IO3B = Z180_IO3B_RESET;
1985 IO_IO3C = Z180_IO3C_RESET;
1986 IO_IO3D = Z180_IO3D_RESET;
1987 IO_OMCR = Z180_OMCR_RESET;
1988 IO_IOCR = Z180_IOCR_RESET;
1989
1990 if( daisy_chain )
1991 {
1992 while( daisy_chain->irq_param != -1 && Z180.irq_max < Z80_MAXDAISY )
1993 {
1994 /* set callbackhandler after reti */
1995 Z180.irq[Z180.irq_max] = *daisy_chain;
1996 /* device reset */
1997 if( Z180.irq[Z180.irq_max].reset )
1998 Z180.irq[Z180.irq_max].reset(Z180.irq[Z180.irq_max].irq_param);
1999 Z180.irq_max++;
2000 daisy_chain++;
2001 }
2002 }
2003 z180_mmu();
2004 z180_change_pc(_PCD);
2005 }
2006
z180_exit(void)2007 void z180_exit(void)
2008 {
2009 #if BIG_FLAGS_ARRAY
2010 if (SZHVC_add) free(SZHVC_add);
2011 SZHVC_add = NULL;
2012 if (SZHVC_sub) free(SZHVC_sub);
2013 SZHVC_sub = NULL;
2014 #endif
2015 }
2016
2017 /****************************************************************************
2018 * Execute 'cycles' T-states. Return number of T-states really executed
2019 ****************************************************************************/
z180_execute(int cycles)2020 int z180_execute(int cycles)
2021 {
2022 z180_icount = cycles - Z180.extra_cycles;
2023 Z180.extra_cycles = 0;
2024
2025 again:
2026 /* check if any DMA transfer is running */
2027 if ((IO_DSTAT & Z180_DSTAT_DME) == Z180_DSTAT_DME)
2028 {
2029 /* check if DMA channel 0 is running and also is in burst mode */
2030 if ((IO_DSTAT & Z180_DSTAT_DE0) == Z180_DSTAT_DE0 &&
2031 (IO_DMODE & Z180_DMODE_MMOD) == Z180_DMODE_MMOD)
2032 {
2033 CALL_MAME_DEBUG;
2034 z180_dma0();
2035 }
2036 else
2037 {
2038 do
2039 {
2040 _PPC = _PCD;
2041 CALL_MAME_DEBUG;
2042 _R++;
2043 EXEC_INLINE(op,ROP());
2044 z180_dma0();
2045 z180_dma1();
2046 /* If DMA is done break out to the faster loop */
2047 if ((IO_DSTAT & Z180_DSTAT_DME) != Z180_DSTAT_DME)
2048 break;
2049 } while( z180_icount > 0 );
2050 }
2051 }
2052
2053 if (z180_icount > 0)
2054 {
2055 do
2056 {
2057 _PPC = _PCD;
2058 CALL_MAME_DEBUG;
2059 _R++;
2060 EXEC_INLINE(op,ROP());
2061 /* If DMA is started go to check the mode */
2062 if ((IO_DSTAT & Z180_DSTAT_DME) == Z180_DSTAT_DME)
2063 goto again;
2064 } while( z180_icount > 0 );
2065 }
2066
2067 z180_icount -= Z180.extra_cycles;
2068 Z180.extra_cycles = 0;
2069
2070 return cycles - z180_icount;
2071 }
2072
2073 /****************************************************************************
2074 * Burn 'cycles' T-states. Adjust R register for the lost time
2075 ****************************************************************************/
z180_burn(int cycles)2076 void z180_burn(int cycles)
2077 {
2078 if( cycles > 0 )
2079 {
2080 /* NOP takes 3 cycles per instruction */
2081 int n = (cycles + 2) / 3;
2082 _R += n;
2083 z180_icount -= 3 * n;
2084 }
2085 }
2086
2087 /****************************************************************************
2088 * Get all registers in given buffer
2089 ****************************************************************************/
z180_get_context(void * dst)2090 unsigned z180_get_context (void *dst)
2091 {
2092 if( dst )
2093 *(Z180_Regs*)dst = Z180;
2094 return sizeof(Z180_Regs);
2095 }
2096
2097 /****************************************************************************
2098 * Set all registers to given values
2099 ****************************************************************************/
z180_set_context(void * src)2100 void z180_set_context (void *src)
2101 {
2102 if( src )
2103 Z180 = *(Z180_Regs*)src;
2104 z180_change_pc(_PCD);
2105 }
2106
2107 /****************************************************************************
2108 * Get a pointer to a cycle count table
2109 ****************************************************************************/
z180_get_cycle_table(int which)2110 const void *z180_get_cycle_table (int which)
2111 {
2112 if (which >= 0 && which <= Z180_TABLE_xycb)
2113 return cc[which];
2114 return NULL;
2115 }
2116
2117 /****************************************************************************
2118 * Set a new cycle count table
2119 ****************************************************************************/
z180_set_cycle_table(int which,void * new_table)2120 void z180_set_cycle_table (int which, void *new_table)
2121 {
2122 if (which >= 0 && which <= Z180_TABLE_ex)
2123 cc[which] = new_table;
2124 }
2125
2126 /****************************************************************************
2127 * Return a specific register
2128 ****************************************************************************/
z180_get_reg(int regnum)2129 unsigned z180_get_reg (int regnum)
2130 {
2131 switch( regnum )
2132 {
2133 case REG_PC: return _PCD;
2134 case Z180_PC: return Z180.PC.w.l;
2135 case REG_SP: return _SPD;
2136 case Z180_SP: return Z180.SP.w.l;
2137 case Z180_AF: return Z180.AF.w.l;
2138 case Z180_BC: return Z180.BC.w.l;
2139 case Z180_DE: return Z180.DE.w.l;
2140 case Z180_HL: return Z180.HL.w.l;
2141 case Z180_IX: return Z180.IX.w.l;
2142 case Z180_IY: return Z180.IY.w.l;
2143 case Z180_R: return (Z180.R & 0x7f) | (Z180.R2 & 0x80);
2144 case Z180_I: return Z180.I;
2145 case Z180_AF2: return Z180.AF2.w.l;
2146 case Z180_BC2: return Z180.BC2.w.l;
2147 case Z180_DE2: return Z180.DE2.w.l;
2148 case Z180_HL2: return Z180.HL2.w.l;
2149 case Z180_IM: return Z180.IM;
2150 case Z180_IFF1: return Z180.IFF1;
2151 case Z180_IFF2: return Z180.IFF2;
2152 case Z180_HALT: return Z180.HALT;
2153 case Z180_NMI_STATE: return Z180.nmi_state;
2154 case Z180_INT0_STATE: return Z180.irq_state[0];
2155 case Z180_INT1_STATE: return Z180.irq_state[1];
2156 case Z180_INT2_STATE: return Z180.irq_state[2];
2157 case Z180_DC0: return Z180.int_state[0];
2158 case Z180_DC1: return Z180.int_state[1];
2159 case Z180_DC2: return Z180.int_state[2];
2160 case Z180_DC3: return Z180.int_state[3];
2161 case Z180_CNTLA0: return Z180.io[0x00];
2162 case Z180_CNTLA1: return Z180.io[0x01];
2163 case Z180_CNTLB0: return Z180.io[0x02];
2164 case Z180_CNTLB1: return Z180.io[0x03];
2165 case Z180_STAT0: return Z180.io[0x04];
2166 case Z180_STAT1: return Z180.io[0x05];
2167 case Z180_TDR0: return Z180.io[0x06];
2168 case Z180_TDR1: return Z180.io[0x07];
2169 case Z180_RDR0: return Z180.io[0x08];
2170 case Z180_RDR1: return Z180.io[0x09];
2171 case Z180_CNTR: return Z180.io[0x0a];
2172 case Z180_TRDR: return Z180.io[0x0b];
2173 case Z180_TMDR0L: return Z180.io[0x0c];
2174 case Z180_TMDR0H: return Z180.io[0x0d];
2175 case Z180_RLDR0L: return Z180.io[0x0e];
2176 case Z180_RLDR0H: return Z180.io[0x0f];
2177 case Z180_TCR: return Z180.io[0x10];
2178 case Z180_IO11: return Z180.io[0x11];
2179 case Z180_ASEXT0: return Z180.io[0x12];
2180 case Z180_ASEXT1: return Z180.io[0x13];
2181 case Z180_TMDR1L: return Z180.io[0x14];
2182 case Z180_TMDR1H: return Z180.io[0x15];
2183 case Z180_RLDR1L: return Z180.io[0x16];
2184 case Z180_RLDR1H: return Z180.io[0x17];
2185 case Z180_FRC: return Z180.io[0x18];
2186 case Z180_IO19: return Z180.io[0x19];
2187 case Z180_ASTC0L: return Z180.io[0x1a];
2188 case Z180_ASTC0H: return Z180.io[0x1b];
2189 case Z180_ASTC1L: return Z180.io[0x1c];
2190 case Z180_ASTC1H: return Z180.io[0x1d];
2191 case Z180_CMR: return Z180.io[0x1e];
2192 case Z180_CCR: return Z180.io[0x1f];
2193 case Z180_SAR0L: return Z180.io[0x20];
2194 case Z180_SAR0H: return Z180.io[0x21];
2195 case Z180_SAR0B: return Z180.io[0x22];
2196 case Z180_DAR0L: return Z180.io[0x23];
2197 case Z180_DAR0H: return Z180.io[0x24];
2198 case Z180_DAR0B: return Z180.io[0x25];
2199 case Z180_BCR0L: return Z180.io[0x26];
2200 case Z180_BCR0H: return Z180.io[0x27];
2201 case Z180_MAR1L: return Z180.io[0x28];
2202 case Z180_MAR1H: return Z180.io[0x29];
2203 case Z180_MAR1B: return Z180.io[0x2a];
2204 case Z180_IAR1L: return Z180.io[0x2b];
2205 case Z180_IAR1H: return Z180.io[0x2c];
2206 case Z180_IAR1B: return Z180.io[0x2d];
2207 case Z180_BCR1L: return Z180.io[0x2e];
2208 case Z180_BCR1H: return Z180.io[0x2f];
2209 case Z180_DSTAT: return Z180.io[0x30];
2210 case Z180_DMODE: return Z180.io[0x31];
2211 case Z180_DCNTL: return Z180.io[0x32];
2212 case Z180_IL: return Z180.io[0x33];
2213 case Z180_ITC: return Z180.io[0x34];
2214 case Z180_IO35: return Z180.io[0x35];
2215 case Z180_RCR: return Z180.io[0x36];
2216 case Z180_IO37: return Z180.io[0x37];
2217 case Z180_CBR: return Z180.io[0x38];
2218 case Z180_BBR: return Z180.io[0x39];
2219 case Z180_CBAR: return Z180.io[0x3a];
2220 case Z180_IO3B: return Z180.io[0x3b];
2221 case Z180_IO3C: return Z180.io[0x3c];
2222 case Z180_IO3D: return Z180.io[0x3d];
2223 case Z180_OMCR: return Z180.io[0x3e];
2224 case Z180_IOCR: return Z180.io[0x3f];
2225 case Z180_IOLINES: return Z180.iol; break;
2226 case REG_PREVIOUSPC: return Z180.PREPC.w.l;
2227 default:
2228 if( regnum <= REG_SP_CONTENTS )
2229 {
2230 unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum);
2231 if( offset < 0xffff )
2232 return RM( offset ) | ( RM( offset + 1) << 8 );
2233 }
2234 }
2235 return 0;
2236 }
2237
2238 /****************************************************************************
2239 * Set a specific register
2240 ****************************************************************************/
z180_set_reg(int regnum,unsigned val)2241 void z180_set_reg (int regnum, unsigned val)
2242 {
2243 switch( regnum )
2244 {
2245 case REG_PC: _PC = val; z180_change_pc(_PCD); break;
2246 case Z180_PC: Z180.PC.w.l = val; break;
2247 case REG_SP: _SP = val; break;
2248 case Z180_SP: Z180.SP.w.l = val; break;
2249 case Z180_AF: Z180.AF.w.l = val; break;
2250 case Z180_BC: Z180.BC.w.l = val; break;
2251 case Z180_DE: Z180.DE.w.l = val; break;
2252 case Z180_HL: Z180.HL.w.l = val; break;
2253 case Z180_IX: Z180.IX.w.l = val; break;
2254 case Z180_IY: Z180.IY.w.l = val; break;
2255 case Z180_R: Z180.R = val; Z180.R2 = val & 0x80; break;
2256 case Z180_I: Z180.I = val; break;
2257 case Z180_AF2: Z180.AF2.w.l = val; break;
2258 case Z180_BC2: Z180.BC2.w.l = val; break;
2259 case Z180_DE2: Z180.DE2.w.l = val; break;
2260 case Z180_HL2: Z180.HL2.w.l = val; break;
2261 case Z180_IM: Z180.IM = val; break;
2262 case Z180_IFF1: Z180.IFF1 = val; break;
2263 case Z180_IFF2: Z180.IFF2 = val; break;
2264 case Z180_HALT: Z180.HALT = val; break;
2265 case Z180_NMI_STATE: z180_set_irq_line(IRQ_LINE_NMI,val); break;
2266 case Z180_INT0_STATE: z180_set_irq_line(0,val); break;
2267 case Z180_INT1_STATE: z180_set_irq_line(1,val); break;
2268 case Z180_INT2_STATE: z180_set_irq_line(2,val); break;
2269 case Z180_DC0: Z180.int_state[0] = val; break;
2270 case Z180_DC1: Z180.int_state[1] = val; break;
2271 case Z180_DC2: Z180.int_state[2] = val; break;
2272 case Z180_DC3: Z180.int_state[3] = val; break;
2273 case Z180_CNTLA0: Z180.io[0x00] = val; break;
2274 case Z180_CNTLA1: Z180.io[0x01] = val; break;
2275 case Z180_CNTLB0: Z180.io[0x02] = val; break;
2276 case Z180_CNTLB1: Z180.io[0x03] = val; break;
2277 case Z180_STAT0: Z180.io[0x04] = val; break;
2278 case Z180_STAT1: Z180.io[0x05] = val; break;
2279 case Z180_TDR0: Z180.io[0x06] = val; break;
2280 case Z180_TDR1: Z180.io[0x07] = val; break;
2281 case Z180_RDR0: Z180.io[0x08] = val; break;
2282 case Z180_RDR1: Z180.io[0x09] = val; break;
2283 case Z180_CNTR: Z180.io[0x0a] = val; break;
2284 case Z180_TRDR: Z180.io[0x0b] = val; break;
2285 case Z180_TMDR0L: Z180.io[0x0c] = val; break;
2286 case Z180_TMDR0H: Z180.io[0x0d] = val; break;
2287 case Z180_RLDR0L: Z180.io[0x0e] = val; break;
2288 case Z180_RLDR0H: Z180.io[0x0f] = val; break;
2289 case Z180_TCR: Z180.io[0x10] = val; break;
2290 case Z180_IO11: Z180.io[0x11] = val; break;
2291 case Z180_ASEXT0: Z180.io[0x12] = val; break;
2292 case Z180_ASEXT1: Z180.io[0x13] = val; break;
2293 case Z180_TMDR1L: Z180.io[0x14] = val; break;
2294 case Z180_TMDR1H: Z180.io[0x15] = val; break;
2295 case Z180_RLDR1L: Z180.io[0x16] = val; break;
2296 case Z180_RLDR1H: Z180.io[0x17] = val; break;
2297 case Z180_FRC: Z180.io[0x18] = val; break;
2298 case Z180_IO19: Z180.io[0x19] = val; break;
2299 case Z180_ASTC0L: Z180.io[0x1a] = val; break;
2300 case Z180_ASTC0H: Z180.io[0x1b] = val; break;
2301 case Z180_ASTC1L: Z180.io[0x1c] = val; break;
2302 case Z180_ASTC1H: Z180.io[0x1d] = val; break;
2303 case Z180_CMR: Z180.io[0x1e] = val; break;
2304 case Z180_CCR: Z180.io[0x1f] = val; break;
2305 case Z180_SAR0L: Z180.io[0x20] = val; break;
2306 case Z180_SAR0H: Z180.io[0x21] = val; break;
2307 case Z180_SAR0B: Z180.io[0x22] = val; break;
2308 case Z180_DAR0L: Z180.io[0x23] = val; break;
2309 case Z180_DAR0H: Z180.io[0x24] = val; break;
2310 case Z180_DAR0B: Z180.io[0x25] = val; break;
2311 case Z180_BCR0L: Z180.io[0x26] = val; break;
2312 case Z180_BCR0H: Z180.io[0x27] = val; break;
2313 case Z180_MAR1L: Z180.io[0x28] = val; break;
2314 case Z180_MAR1H: Z180.io[0x29] = val; break;
2315 case Z180_MAR1B: Z180.io[0x2a] = val; break;
2316 case Z180_IAR1L: Z180.io[0x2b] = val; break;
2317 case Z180_IAR1H: Z180.io[0x2c] = val; break;
2318 case Z180_IAR1B: Z180.io[0x2d] = val; break;
2319 case Z180_BCR1L: Z180.io[0x2e] = val; break;
2320 case Z180_BCR1H: Z180.io[0x2f] = val; break;
2321 case Z180_DSTAT: Z180.io[0x30] = val; break;
2322 case Z180_DMODE: Z180.io[0x31] = val; break;
2323 case Z180_DCNTL: Z180.io[0x32] = val; break;
2324 case Z180_IL: Z180.io[0x33] = val; break;
2325 case Z180_ITC: Z180.io[0x34] = val; break;
2326 case Z180_IO35: Z180.io[0x35] = val; break;
2327 case Z180_RCR: Z180.io[0x36] = val; break;
2328 case Z180_IO37: Z180.io[0x37] = val; break;
2329 case Z180_CBR: Z180.io[0x38] = val; z180_mmu(); break;
2330 case Z180_BBR: Z180.io[0x39] = val; z180_mmu(); break;
2331 case Z180_CBAR: Z180.io[0x3a] = val; z180_mmu(); break;
2332 case Z180_IO3B: Z180.io[0x3b] = val; break;
2333 case Z180_IO3C: Z180.io[0x3c] = val; break;
2334 case Z180_IO3D: Z180.io[0x3d] = val; break;
2335 case Z180_OMCR: Z180.io[0x3e] = val; break;
2336 case Z180_IOCR: Z180.io[0x3f] = val; break;
2337 case Z180_IOLINES: z180_write_iolines(val); break;
2338 default:
2339 if( regnum <= REG_SP_CONTENTS )
2340 {
2341 unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum);
2342 if( offset < 0xffff )
2343 {
2344 WM( offset, val & 0xff );
2345 WM( offset+1, (val >> 8) & 0xff );
2346 }
2347 }
2348 }
2349 }
2350
READ_HANDLER(z180_internal_r)2351 READ_HANDLER( z180_internal_r )
2352 {
2353 return Z180.io[offset & 0x3f];
2354 }
2355
WRITE_HANDLER(z180_internal_w)2356 WRITE_HANDLER( z180_internal_w )
2357 {
2358 z180_set_reg( Z180_CNTLA0 + (offset & 0x3f), data );
2359 }
2360
2361 /****************************************************************************
2362 * Set IRQ line state
2363 ****************************************************************************/
z180_set_irq_line(int irqline,int state)2364 void z180_set_irq_line(int irqline, int state)
2365 {
2366 if (irqline == IRQ_LINE_NMI)
2367 {
2368 if( Z180.nmi_state == state ) return;
2369
2370 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d set_irq_line (NMI) %d\n", cpu_getactivecpu(), state);
2371 Z180.nmi_state = state;
2372 if( state == CLEAR_LINE ) return;
2373
2374 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d take NMI\n", cpu_getactivecpu());
2375 _PPC = -1; /* there isn't a valid previous program counter */
2376 LEAVE_HALT; /* Check if processor was halted */
2377
2378 /* disable DMA transfers!! */
2379 IO_DSTAT &= ~Z180_DSTAT_DME;
2380
2381 _IFF1 = 0;
2382 PUSH( PC );
2383 _PCD = 0x0066;
2384 Z180.extra_cycles += 11;
2385 }
2386 else
2387 {
2388 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d set_irq_line %d\n",cpu_getactivecpu() , state);
2389 Z180.irq_state[irqline] = state;
2390 if( state == CLEAR_LINE ) return;
2391
2392 if( irqline == 0 && Z180.irq_max )
2393 {
2394 int daisychain, device, int_state;
2395 daisychain = (*Z180.irq_callback)(irqline);
2396 device = daisychain >> 8;
2397 int_state = daisychain & 0xff;
2398 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d daisy chain $%04x -> device %d, state $%02x",cpu_getactivecpu(), daisychain, device, int_state);
2399
2400 if( Z180.int_state[device] != int_state )
2401 {
2402 log_cb(RETRO_LOG_DEBUG, LOGPRE " change\n");
2403 /* set new interrupt status */
2404 Z180.int_state[device] = int_state;
2405 /* check interrupt status */
2406 Z180.request_irq = Z180.service_irq = -1;
2407
2408 /* search higher IRQ or IEO */
2409 for( device = 0 ; device < Z180.irq_max ; device ++ )
2410 {
2411 /* IEO = disable ? */
2412 if( Z180.int_state[device] & Z80_INT_IEO )
2413 {
2414 Z180.request_irq = -1; /* if IEO is disable , masking lower IRQ */
2415 Z180.service_irq = device; /* set highest interrupt service device */
2416 }
2417 /* IRQ = request ? */
2418 if( Z180.int_state[device] & Z80_INT_REQ )
2419 Z180.request_irq = device;
2420 }
2421 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d daisy chain service_irq $%02x, request_irq $%02x\n", cpu_getactivecpu(), Z180.service_irq, Z180.request_irq);
2422 if( Z180.request_irq < 0 ) return;
2423 }
2424 else
2425 {
2426 log_cb(RETRO_LOG_DEBUG, LOGPRE " no change\n");
2427 return;
2428 }
2429 }
2430 take_interrupt(irqline);
2431 }
2432 }
2433
2434 /****************************************************************************
2435 * Set IRQ vector callback
2436 ****************************************************************************/
z180_set_irq_callback(int (* callback)(int))2437 void z180_set_irq_callback(int (*callback)(int))
2438 {
2439 log_cb(RETRO_LOG_DEBUG, LOGPRE "Z180 #%d set_irq_callback $%08x\n",cpu_getactivecpu() , (int)callback);
2440 Z180.irq_callback = callback;
2441 }
2442
2443 /****************************************************************************
2444 * Return a formatted string for a register
2445 ****************************************************************************/
z180_info(void * context,int regnum)2446 const char *z180_info(void *context, int regnum)
2447 {
2448 static char buffer[32][47+1];
2449 static int which = 0;
2450 Z180_Regs *r = context;
2451
2452 which = (which+1) % 32;
2453 buffer[which][0] = '\0';
2454 if( !context )
2455 r = &Z180;
2456
2457 switch( regnum )
2458 {
2459 case CPU_INFO_REG+Z180_PC: sprintf(buffer[which], "PC:%04X", r->PC.w.l); break;
2460 case CPU_INFO_REG+Z180_SP: sprintf(buffer[which], "SP:%04X", r->SP.w.l); break;
2461 case CPU_INFO_REG+Z180_AF: sprintf(buffer[which], "AF:%04X", r->AF.w.l); break;
2462 case CPU_INFO_REG+Z180_BC: sprintf(buffer[which], "BC:%04X", r->BC.w.l); break;
2463 case CPU_INFO_REG+Z180_DE: sprintf(buffer[which], "DE:%04X", r->DE.w.l); break;
2464 case CPU_INFO_REG+Z180_HL: sprintf(buffer[which], "HL:%04X", r->HL.w.l); break;
2465 case CPU_INFO_REG+Z180_IX: sprintf(buffer[which], "IX:%04X", r->IX.w.l); break;
2466 case CPU_INFO_REG+Z180_IY: sprintf(buffer[which], "IY:%04X", r->IY.w.l); break;
2467 case CPU_INFO_REG+Z180_R: sprintf(buffer[which], "R :%02X", (r->R & 0x7f) | (r->R2 & 0x80)); break;
2468 case CPU_INFO_REG+Z180_I: sprintf(buffer[which], "I :%02X", r->I); break;
2469 case CPU_INFO_REG+Z180_IL: sprintf(buffer[which], "IL :%02X", r->io[Z180_IL-Z180_CNTLA0]); break;
2470 case CPU_INFO_REG+Z180_AF2: sprintf(buffer[which], "AF'%04X", r->AF2.w.l); break;
2471 case CPU_INFO_REG+Z180_BC2: sprintf(buffer[which], "BC'%04X", r->BC2.w.l); break;
2472 case CPU_INFO_REG+Z180_DE2: sprintf(buffer[which], "DE'%04X", r->DE2.w.l); break;
2473 case CPU_INFO_REG+Z180_HL2: sprintf(buffer[which], "HL'%04X", r->HL2.w.l); break;
2474 case CPU_INFO_REG+Z180_IM: sprintf(buffer[which], "IM :%X", r->IM); break;
2475 case CPU_INFO_REG+Z180_IFF1: sprintf(buffer[which], "IFF1:%X", r->IFF1); break;
2476 case CPU_INFO_REG+Z180_IFF2: sprintf(buffer[which], "IFF2:%X", r->IFF2); break;
2477 case CPU_INFO_REG+Z180_HALT: sprintf(buffer[which], "HALT:%X", r->HALT); break;
2478 case CPU_INFO_REG+Z180_INT0_STATE: sprintf(buffer[which], "INT0:%X", r->irq_state[0]); break;
2479 case CPU_INFO_REG+Z180_INT1_STATE: sprintf(buffer[which], "INT1:%X", r->irq_state[1]); break;
2480 case CPU_INFO_REG+Z180_INT2_STATE: sprintf(buffer[which], "INT2:%X", r->irq_state[2]); break;
2481 case CPU_INFO_REG+Z180_DC0: if(Z180.irq_max >= 1) sprintf(buffer[which], "DC0:%X", r->int_state[0]); break;
2482 case CPU_INFO_REG+Z180_DC1: if(Z180.irq_max >= 2) sprintf(buffer[which], "DC1:%X", r->int_state[1]); break;
2483 case CPU_INFO_REG+Z180_DC2: if(Z180.irq_max >= 3) sprintf(buffer[which], "DC2:%X", r->int_state[2]); break;
2484 case CPU_INFO_REG+Z180_DC3: if(Z180.irq_max >= 4) sprintf(buffer[which], "DC3:%X", r->int_state[3]); break;
2485 case CPU_INFO_REG+Z180_CCR: sprintf(buffer[which], "CCR :%02X", r->io[Z180_CCR-Z180_CNTLA0]); break;
2486 case CPU_INFO_REG+Z180_ITC: sprintf(buffer[which], "ITC :%02X", r->io[Z180_ITC-Z180_CNTLA0]); break;
2487 case CPU_INFO_REG+Z180_CBR: sprintf(buffer[which], "CBR :%02X", r->io[Z180_CBR-Z180_CNTLA0]); break;
2488 case CPU_INFO_REG+Z180_BBR: sprintf(buffer[which], "BBR :%02X", r->io[Z180_BBR-Z180_CNTLA0]); break;
2489 case CPU_INFO_REG+Z180_CBAR: sprintf(buffer[which], "CBAR:%02X", r->io[Z180_CBAR-Z180_CNTLA0]); break;
2490 case CPU_INFO_REG+Z180_OMCR: sprintf(buffer[which], "OMCR:%02X", r->io[Z180_OMCR-Z180_CNTLA0]); break;
2491 case CPU_INFO_REG+Z180_IOCR: sprintf(buffer[which], "IOCR:%02X", r->io[Z180_IOCR-Z180_CNTLA0]); break;
2492 case CPU_INFO_FLAGS:
2493 sprintf(buffer[which], "%c%c%c%c%c%c%c%c",
2494 r->AF.b.l & 0x80 ? 'S':'.',
2495 r->AF.b.l & 0x40 ? 'Z':'.',
2496 r->AF.b.l & 0x20 ? '5':'.',
2497 r->AF.b.l & 0x10 ? 'H':'.',
2498 r->AF.b.l & 0x08 ? '3':'.',
2499 r->AF.b.l & 0x04 ? 'P':'.',
2500 r->AF.b.l & 0x02 ? 'N':'.',
2501 r->AF.b.l & 0x01 ? 'C':'.');
2502 break;
2503 case CPU_INFO_NAME: return "Z180";
2504 case CPU_INFO_FAMILY: return "Zilog Z8x180";
2505 case CPU_INFO_VERSION: return "0.2";
2506 case CPU_INFO_FILE: return __FILE__;
2507 case CPU_INFO_CREDITS: return "Copyright (C) 2000 Juergen Buchmueller, all rights reserved.";
2508 case CPU_INFO_REG_LAYOUT: return (const char *)z180_reg_layout;
2509 case CPU_INFO_WIN_LAYOUT: return (const char *)z180_win_layout;
2510 }
2511 return buffer[which];
2512 }
2513
z180_dasm(char * buffer,unsigned pc)2514 unsigned z180_dasm( char *buffer, unsigned pc )
2515 {
2516 #ifdef MAME_DEBUG
2517 return DasmZ180( buffer, pc );
2518 #else
2519 sprintf( buffer, "$%02X", cpu_readop(pc) );
2520 return 1;
2521 #endif
2522 }
2523