1 /***************************************************************************
2
3 Atari CoJag hardware
4
5 driver by Aaron Giles
6
7 Games supported:
8 * Area 51
9 * Maximum Force (2 Sets)
10 * Area 51/Maximum Force Duo (2 Sets)
11 * Vicious Circle
12
13 In the future:
14 * Fishin' Frenzy
15 * Freeze
16
17 To do:
18 * map out unused RAM per-game via MRA_NOP/MWA_NOP
19
20 ****************************************************************************
21
22 Memory map (TBA)
23
24 ========================================================================
25 MAIN CPU
26 ========================================================================
27
28 ------------------------------------------------------------
29 000000-3FFFFF R/W xxxxxxxx xxxxxxxx DRAM 0
30 400000-7FFFFF R/W xxxxxxxx xxxxxxxx DRAM 1
31 F00000-F000FF R/W xxxxxxxx xxxxxxxx Tom Internal Registers
32 F00400-F005FF R/W xxxxxxxx xxxxxxxx CLUT - color lookup table A
33 F00600-F007FF R/W xxxxxxxx xxxxxxxx CLUT - color lookup table B
34 F00800-F00D9F R/W xxxxxxxx xxxxxxxx LBUF - line buffer A
35 F01000-F0159F R/W xxxxxxxx xxxxxxxx LBUF - line buffer B
36 F01800-F01D9F R/W xxxxxxxx xxxxxxxx LBUF - line buffer currently selected
37 F02000-F021FF R/W xxxxxxxx xxxxxxxx GPU control registers
38 F02200-F022FF R/W xxxxxxxx xxxxxxxx Blitter registers
39 F03000-F03FFF R/W xxxxxxxx xxxxxxxx Local GPU RAM
40 F08800-F08D9F R/W xxxxxxxx xxxxxxxx LBUF - 32-bit access to line buffer A
41 F09000-F0959F R/W xxxxxxxx xxxxxxxx LBUF - 32-bit access to line buffer B
42 F09800-F09D9F R/W xxxxxxxx xxxxxxxx LBUF - 32-bit access to line buffer currently selected
43 F0B000-F0BFFF R/W xxxxxxxx xxxxxxxx 32-bit access to local GPU RAM
44 F10000-F13FFF R/W xxxxxxxx xxxxxxxx Jerry
45 F14000-F17FFF R/W xxxxxxxx xxxxxxxx Joysticks and GPIO0-5
46 F18000-F1AFFF R/W xxxxxxxx xxxxxxxx Jerry DSP
47 F1B000-F1CFFF R/W xxxxxxxx xxxxxxxx Local DSP RAM
48 F1D000-F1DFFF R xxxxxxxx xxxxxxxx Wavetable ROM
49 ------------------------------------------------------------
50
51 ***************************************************************************/
52
53
54 #include "driver.h"
55 #include "cpu/mips/r3000.h"
56 #include "cpu/jaguar/jaguar.h"
57 #include "machine/idectrl.h"
58 #include "jaguar.h"
59
60
61
62 /*************************************
63 *
64 * Global variables
65 *
66 *************************************/
67
68 data32_t *jaguar_shared_ram;
69 data32_t *jaguar_gpu_ram;
70 data32_t *jaguar_gpu_clut;
71 data32_t *jaguar_dsp_ram;
72 data32_t *jaguar_wave_rom;
73 UINT8 cojag_is_r3000;
74
75
76
77 /*************************************
78 *
79 * Local variables
80 *
81 *************************************/
82
83 static data32_t misc_control_data;
84 static UINT8 eeprom_enable;
85
86 static data32_t *rom_base;
87 static size_t rom_size;
88
89 static struct ide_interface ide_intf =
90 {
91 jaguar_external_int
92 };
93
94
95
96 /*************************************
97 *
98 * Machine init
99 *
100 *************************************/
101
MACHINE_INIT(cojag)102 static MACHINE_INIT( cojag )
103 {
104 /* 68020 only: copy the interrupt vectors into RAM */
105 if (!cojag_is_r3000)
106 memcpy(jaguar_shared_ram, rom_base, 0x10);
107
108 /* set up main CPU RAM/ROM banks */
109 cpu_setbank(3, jaguar_gpu_ram);
110
111 /* set up DSP RAM/ROM banks */
112 cpu_setbank(10, jaguar_shared_ram);
113 cpu_setbank(11, jaguar_gpu_clut);
114 cpu_setbank(12, jaguar_gpu_ram);
115 cpu_setbank(13, jaguar_dsp_ram);
116
117 /* clear any spinuntil stuff */
118 jaguar_gpu_resume();
119 jaguar_dsp_resume();
120
121 /* halt the CPUs */
122 jaguargpu_ctrl_w(1, G_CTRL, 0, 0);
123 jaguardsp_ctrl_w(2, D_CTRL, 0, 0);
124
125 /* init the sound system */
126 cojag_sound_reset();
127
128 /* reset the IDE controller */
129 ide_controller_reset(0);
130 }
131
132
133
134 /*************************************
135 *
136 * Misc. control bits
137 *
138 *************************************/
139
READ32_HANDLER(misc_control_r)140 static READ32_HANDLER( misc_control_r )
141 {
142 /* D7 = board reset (low)
143 D6 = audio must & reset (high)
144 D5 = volume control data (invert on write)
145 D4 = volume control clock
146 D0 = shared memory select (0=XBUS) */
147
148 return misc_control_data ^ 0x20;
149 }
150
151
WRITE32_HANDLER(misc_control_w)152 static WRITE32_HANDLER( misc_control_w )
153 {
154 log_cb(RETRO_LOG_DEBUG, LOGPRE "%08X:misc_control_w(%02X)\n", activecpu_get_previouspc(), data);
155
156 /* D7 = board reset (low)
157 D6 = audio must & reset (high)
158 D5 = volume control data (invert on write)
159 D4 = volume control clock
160 D0 = shared memory select (0=XBUS) */
161
162 /* handle resetting the DSPs */
163 if (!(data & 0x80))
164 {
165 /* clear any spinuntil stuff */
166 jaguar_gpu_resume();
167 jaguar_dsp_resume();
168
169 /* halt the CPUs */
170 jaguargpu_ctrl_w(1, G_CTRL, 0, 0);
171 jaguardsp_ctrl_w(2, D_CTRL, 0, 0);
172 }
173
174 COMBINE_DATA(&misc_control_data);
175 }
176
177
178
179 /*************************************
180 *
181 * 32-bit access to the GPU
182 *
183 *************************************/
184
READ32_HANDLER(gpuctrl_r)185 static READ32_HANDLER( gpuctrl_r )
186 {
187 return jaguargpu_ctrl_r(1, offset);
188 }
189
190
WRITE32_HANDLER(gpuctrl_w)191 static WRITE32_HANDLER( gpuctrl_w )
192 {
193 jaguargpu_ctrl_w(1, offset, data, mem_mask);
194 }
195
196
197
198 /*************************************
199 *
200 * 32-bit access to the DSP
201 *
202 *************************************/
203
READ32_HANDLER(dspctrl_r)204 static READ32_HANDLER( dspctrl_r )
205 {
206 return jaguardsp_ctrl_r(2, offset);
207 }
208
209
WRITE32_HANDLER(dspctrl_w)210 static WRITE32_HANDLER( dspctrl_w )
211 {
212 jaguardsp_ctrl_w(2, offset, data, mem_mask);
213 }
214
215
216
217 /*************************************
218 *
219 * Input ports
220 *
221 *************************************/
222
READ32_HANDLER(jamma_r)223 static READ32_HANDLER( jamma_r )
224 {
225 return readinputport(0) | (readinputport(1) << 16);
226 }
227
228
READ32_HANDLER(status_r)229 static READ32_HANDLER( status_r )
230 {
231 /* D23-20 = /SER-4-1*/
232 /* D19-16 = COINR4-1*/
233 /* D7 = /VSYNCNEQ*/
234 /* D6 = /S-TEST*/
235 /* D5 = /VOLUMEUP*/
236 /* D4 = /VOLUMEDOWN*/
237 /* D3-D0 = ACTC4-1*/
238 return readinputport(2) | (readinputport(2) << 16);
239 }
240
241
242
243 /*************************************
244 *
245 * Output ports
246 *
247 *************************************/
248
WRITE32_HANDLER(latch_w)249 static WRITE32_HANDLER( latch_w )
250 {
251 log_cb(RETRO_LOG_DEBUG, LOGPRE "%08X:latch_w(%X)\n", activecpu_get_previouspc(), data);
252 }
253
254
255
256 /*************************************
257 *
258 * EEPROM access
259 *
260 *************************************/
261
READ32_HANDLER(eeprom_data_r)262 static READ32_HANDLER( eeprom_data_r )
263 {
264 if (cojag_is_r3000)
265 return ((UINT32 *)generic_nvram)[offset] | 0xffffff00;
266 else
267 return ((UINT32 *)generic_nvram)[offset] | 0x00ffffff;
268 }
269
270
WRITE32_HANDLER(eeprom_enable_w)271 static WRITE32_HANDLER( eeprom_enable_w )
272 {
273 eeprom_enable = 1;
274 }
275
276
WRITE32_HANDLER(eeprom_data_w)277 static WRITE32_HANDLER( eeprom_data_w )
278 {
279 /* if (eeprom_enable)*/
280 {
281 if (cojag_is_r3000)
282 ((UINT32 *)generic_nvram)[offset] = data & 0x000000ff;
283 else
284 ((UINT32 *)generic_nvram)[offset] = data & 0xff000000;
285 }
286 /* else*/
287 /* log_cb(RETRO_LOG_DEBUG, LOGPRE "%08X:error writing to disabled EEPROM\n", activecpu_get_previouspc());*/
288 eeprom_enable = 0;
289 }
290
291
292
293 /*************************************
294 *
295 * GPU synchronization & speedup
296 *
297 *************************************/
298
299 /*
300 Explanation:
301
302 The GPU generally sits in a tight loop waiting for the main CPU to store
303 a jump address into a specific memory location. This speedup is designed
304 to catch that loop, which looks like this:
305
306 load (r28),r21
307 jump (r21)
308 nop
309
310 When nothing is pending, the GPU keeps the address of the load instruction
311 at (r28) so that it loops back on itself. When the main CPU wants to execute
312 a command, it stores an alternate address to (r28).
313
314 Even if we don't optimize this case, we do need to detect when a command
315 is written to the GPU in order to improve synchronization until the GPU
316 has finished. To do this, we start a temporary high frequency timer and
317 run it until we get back to the spin loop.
318 */
319
320 static data32_t *gpu_jump_address;
321 static UINT8 gpu_command_pending;
322 static data32_t gpu_spin_pc;
323
gpu_sync_timer(int param)324 static void gpu_sync_timer(int param)
325 {
326 /* if a command is still pending, and we haven't maxed out our timer, set a new one */
327 if (gpu_command_pending && param < 1000)
328 timer_set(TIME_IN_USEC(50), ++param, gpu_sync_timer);
329 }
330
331
WRITE32_HANDLER(gpu_jump_w)332 static WRITE32_HANDLER( gpu_jump_w )
333 {
334 /* update the data in memory */
335 COMBINE_DATA(gpu_jump_address);
336 log_cb(RETRO_LOG_DEBUG, LOGPRE "%08X:GPU jump address = %08X\n", activecpu_get_previouspc(), *gpu_jump_address);
337
338 /* if the GPU is suspended, release it now */
339 jaguar_gpu_resume();
340
341 /* start the sync timer going, and note that there is a command pending */
342 timer_set(TIME_NOW, 0, gpu_sync_timer);
343 gpu_command_pending = 1;
344 }
345
346
READ32_HANDLER(gpu_jump_r)347 static READ32_HANDLER( gpu_jump_r )
348 {
349 /* if the current GPU command is just pointing back to the spin loop, and */
350 /* we're reading it from the spin loop, we can optimize */
351 if (*gpu_jump_address == gpu_spin_pc && activecpu_get_previouspc() == gpu_spin_pc)
352 {
353 #if ENABLE_SPEEDUP_HACKS
354 /* spin if we're allowed */
355 jaguar_gpu_suspend();
356 #endif
357
358 /* no command is pending */
359 gpu_command_pending = 0;
360 }
361
362 /* return the current value */
363 return *gpu_jump_address;
364 }
365
366
367
368 /*************************************
369 *
370 * Main CPU speedup (R3000 games)
371 *
372 *************************************/
373
374 /*
375 Explanation:
376
377 Instead of sitting in a tight loop, the CPU will run the random number
378 generator over and over while waiting for an interrupt. In order to catch
379 that, we snoop the memory location it is polling, and see if it is read
380 at least 5 times in a row, each time less than 200 cycles apart. If so,
381 we assume it is spinning. Also, by waiting for 5 iterations, we let it
382 crank through some random numbers, just not several thousand every frame.
383 */
384
385 #if ENABLE_SPEEDUP_HACKS
386
387 static data32_t *main_speedup;
388 static int main_speedup_hits;
389 static UINT32 main_speedup_last_cycles;
390 static UINT32 main_speedup_max_cycles;
391
READ32_HANDLER(cojagr3k_main_speedup_r)392 static READ32_HANDLER( cojagr3k_main_speedup_r )
393 {
394 UINT32 curcycles = activecpu_gettotalcycles();
395
396 /* if it's been less than main_speedup_max_cycles cycles since the last time */
397 if (curcycles - main_speedup_last_cycles < main_speedup_max_cycles)
398 {
399 /* increment the count; if we hit 5, we can spin until an interrupt comes */
400 if (main_speedup_hits++ > 5)
401 {
402 cpu_spinuntil_int();
403 main_speedup_hits = 0;
404 }
405 }
406
407 /* if it's been more than main_speedup_max_cycles cycles, reset our count */
408 else
409 main_speedup_hits = 0;
410
411 /* remember the last cycle count */
412 main_speedup_last_cycles = curcycles;
413
414 /* return the real value */
415 return *main_speedup;
416 }
417
418 #endif
419
420
421
422 /*************************************
423 *
424 * Main CPU speedup (Area 51)
425 *
426 *************************************/
427
428 /*
429 Explanation:
430
431 Very similar to the R3000 code, except we need to verify that the value in
432 *main_speedup is actually 0.
433 */
434
435 #if ENABLE_SPEEDUP_HACKS
436
WRITE32_HANDLER(area51_main_speedup_w)437 static WRITE32_HANDLER( area51_main_speedup_w )
438 {
439 UINT32 curcycles = activecpu_gettotalcycles();
440
441 /* store the data */
442 COMBINE_DATA(main_speedup);
443
444 /* if it's been less than 400 cycles since the last time */
445 if (*main_speedup == 0 && curcycles - main_speedup_last_cycles < 400)
446 {
447 /* increment the count; if we hit 5, we can spin until an interrupt comes */
448 if (main_speedup_hits++ > 5)
449 {
450 cpu_spinuntil_int();
451 main_speedup_hits = 0;
452 }
453 }
454
455 /* if it's been more than 400 cycles, reset our count */
456 else
457 main_speedup_hits = 0;
458
459 /* remember the last cycle count */
460 main_speedup_last_cycles = curcycles;
461 }
462
463
464 /*
465 Explanation:
466
467 The Area 51/Maximum Force duo writes to a non-aligned address, so our check
468 against 0 must handle that explicitly.
469 */
470
WRITE32_HANDLER(area51mx_main_speedup_w)471 static WRITE32_HANDLER( area51mx_main_speedup_w )
472 {
473 UINT32 curcycles = activecpu_gettotalcycles();
474
475 /* store the data */
476 COMBINE_DATA(&main_speedup[offset]);
477
478 /* if it's been less than 450 cycles since the last time */
479 if (((main_speedup[0] << 16) | (main_speedup[1] >> 16)) == 0 && curcycles - main_speedup_last_cycles < 450)
480 {
481 /* increment the count; if we hit 5, we can spin until an interrupt comes */
482 if (main_speedup_hits++ > 10)
483 {
484 cpu_spinuntil_int();
485 main_speedup_hits = 0;
486 }
487 }
488
489 /* if it's been more than 450 cycles, reset our count */
490 else
491 main_speedup_hits = 0;
492
493 /* remember the last cycle count */
494 main_speedup_last_cycles = curcycles;
495 }
496
497 #endif
498
499
500
501 /*************************************
502 *
503 * Main CPU memory handlers
504 *
505 *************************************/
506
MEMORY_READ32_START(r3000_readmem)507 static MEMORY_READ32_START( r3000_readmem )
508 { 0x00000000, 0x0000ffff, MRA32_NOP }, /* just to shut up the logging*/
509
510 { 0x04000000, 0x047fffff, MRA32_RAM },
511 { 0x04e00000, 0x04e003ff, ide_controller32_0_r },
512 { 0x04f00000, 0x04f003ff, jaguar_tom_regs32_r },
513 { 0x04f00400, 0x04f007ff, MRA32_RAM },
514 { 0x04f02100, 0x04f021ff, gpuctrl_r },
515 { 0x04f02200, 0x04f022ff, jaguar_blitter_r },
516 { 0x04f03000, 0x04f03fff, MRA32_RAM },
517 { 0x04f10000, 0x04f103ff, jaguar_jerry_regs32_r },
518 { 0x04f16000, 0x04f1600b, cojag_gun_input_r }, /* GPI02*/
519 { 0x04f17000, 0x04f17003, status_r }, /* GPI03*/
520 { 0x04f17c00, 0x04f17c03, jamma_r }, /* GPI05*/
521 { 0x04f1a100, 0x04f1a13f, dspctrl_r },
522 { 0x04f1a140, 0x04f1a17f, jaguar_serial_r },
523 { 0x04f1b000, 0x04f1cfff, MRA32_RAM },
524
525 { 0x06000000, 0x06000003, misc_control_r },
526 { 0x10000000, 0x1007ffff, MRA32_RAM },
527 { 0x12000000, 0x120fffff, MRA32_RAM }, /* tested in self-test only?*/
528 { 0x18000000, 0x18001fff, eeprom_data_r },
529 { 0x1fc00000, 0x1fdfffff, MRA32_ROM },
530 MEMORY_END
531
532
533 static MEMORY_WRITE32_START( r3000_writemem )
534 { 0x04000000, 0x047fffff, MWA32_RAM, &jaguar_shared_ram },
535 { 0x04e00000, 0x04e003ff, ide_controller32_0_w },
536 { 0x04f00000, 0x04f003ff, jaguar_tom_regs32_w },
537 { 0x04f00400, 0x04f007ff, MWA32_RAM, &jaguar_gpu_clut },
538 { 0x04f02100, 0x04f021ff, gpuctrl_w },
539 { 0x04f02200, 0x04f022ff, jaguar_blitter_w },
540 { 0x04f03000, 0x04f03fff, MWA32_RAM, &jaguar_gpu_ram },
541 { 0x04f0b000, 0x04f0bfff, MWA32_BANK3 },
542 { 0x04f10000, 0x04f103ff, jaguar_jerry_regs32_w },
543 { 0x04f17800, 0x04f17803, latch_w }, /* GPI04*/
544 { 0x04f1a100, 0x04f1a13f, dspctrl_w },
545 { 0x04f1a140, 0x04f1a17f, jaguar_serial_w },
546 { 0x04f1b000, 0x04f1cfff, MWA32_RAM, &jaguar_dsp_ram },
547
548 { 0x06000000, 0x06000003, misc_control_w },
549 { 0x10000000, 0x1007ffff, MWA32_RAM },
550 { 0x12000000, 0x120fffff, MWA32_RAM }, /* tested in self-test only?*/
551 { 0x14000004, 0x14000007, watchdog_reset32_w },
552 { 0x16000000, 0x16000003, eeprom_enable_w },
553 { 0x18000000, 0x18001fff, eeprom_data_w, (data32_t **)&generic_nvram, &generic_nvram_size },
554 { 0x1fc00000, 0x1fdfffff, MWA32_ROM, &rom_base, &rom_size },
555 MEMORY_END
556
557
558 static MEMORY_READ32_START( m68020_readmem )
559 { 0x000000, 0x7fffff, MRA32_RAM },
560 { 0x800000, 0x9fffff, MRA32_ROM },
561 { 0xa00000, 0xa1ffff, MRA32_RAM },
562 { 0xa20000, 0xa21fff, eeprom_data_r },
563 { 0xb70000, 0xb70003, misc_control_r },
564 { 0xc00000, 0xdfffff, MRA32_BANK2 },
565 { 0xe00000, 0xe003ff, ide_controller32_0_r },
566 { 0xf00000, 0xf003ff, jaguar_tom_regs32_r },
567 { 0xf00400, 0xf007ff, MRA32_RAM },
568 { 0xf02100, 0xf021ff, gpuctrl_r },
569 { 0xf02200, 0xf022ff, jaguar_blitter_r },
570 { 0xf03000, 0xf03fff, MRA32_RAM },
571 { 0xf10000, 0xf103ff, jaguar_jerry_regs32_r },
572 { 0xf16000, 0xf1600b, cojag_gun_input_r }, /* GPI02*/
573 { 0xf17000, 0xf17003, status_r }, /* GPI03*/
574 { 0xf17c00, 0xf17c03, jamma_r }, /* GPI05*/
575 { 0xf1a100, 0xf1a13f, dspctrl_r },
576 { 0xf1a140, 0xf1a17f, jaguar_serial_r },
577 { 0xf1b000, 0xf1cfff, MRA32_RAM },
578 MEMORY_END
579
580
581 static MEMORY_WRITE32_START( m68020_writemem )
582 { 0x000000, 0x7fffff, MWA32_RAM, &jaguar_shared_ram },
583 { 0x800000, 0x9fffff, MWA32_ROM, &rom_base, &rom_size },
584 { 0xa00000, 0xa1ffff, MWA32_RAM },
585 { 0xa20000, 0xa21fff, eeprom_data_w, (data32_t **)&generic_nvram, &generic_nvram_size },
586 { 0xa30000, 0xa30003, watchdog_reset32_w },
587 { 0xa40000, 0xa40003, eeprom_enable_w },
588 { 0xb70000, 0xb70003, misc_control_w },
589 { 0xe00000, 0xe003ff, ide_controller32_0_w },
590 { 0xf00000, 0xf003ff, jaguar_tom_regs32_w },
591 { 0xf00400, 0xf007ff, MWA32_RAM, &jaguar_gpu_clut },
592 { 0xf02100, 0xf021ff, gpuctrl_w },
593 { 0xf02200, 0xf022ff, jaguar_blitter_w },
594 { 0xf03000, 0xf03fff, MWA32_RAM, &jaguar_gpu_ram },
595 { 0xf0b000, 0xf0bfff, MWA32_BANK3 },
596 { 0xf10000, 0xf103ff, jaguar_jerry_regs32_w },
597 /* { 0xf17800, 0xf17803, latch_w }, */ /* GPI04*/
598 { 0xf1a100, 0xf1a13f, dspctrl_w },
599 { 0xf1a140, 0xf1a17f, jaguar_serial_w },
600 { 0xf1b000, 0xf1cfff, MWA32_RAM, &jaguar_dsp_ram },
601 MEMORY_END
602
603
604
605 /*************************************
606 *
607 * GPU memory handlers
608 *
609 *************************************/
610
611 static MEMORY_READ32_START( gpu_readmem )
612 { 0x000000, 0x7fffff, MRA32_BANK10 },
613 { 0xe00000, 0xe003ff, ide_controller32_0_r },
614 { 0xf00000, 0xf003ff, jaguar_tom_regs32_r },
615 { 0xf00400, 0xf007ff, MRA32_BANK11 },
616 { 0xf02100, 0xf021ff, gpuctrl_r },
617 { 0xf02200, 0xf022ff, jaguar_blitter_r },
618 { 0xf03000, 0xf03fff, MRA32_BANK12 },
619 { 0xf10000, 0xf103ff, jaguar_jerry_regs32_r },
620 MEMORY_END
621
622
623 static MEMORY_WRITE32_START( gpu_writemem )
624 { 0x000000, 0x7fffff, MWA32_BANK10 },
625 { 0xe00000, 0xe003ff, ide_controller32_0_w },
626 { 0xf00000, 0xf003ff, jaguar_tom_regs32_w },
627 { 0xf00400, 0xf007ff, MWA32_BANK11 },
628 { 0xf02100, 0xf021ff, gpuctrl_w },
629 { 0xf02200, 0xf022ff, jaguar_blitter_w },
630 { 0xf03000, 0xf03fff, MWA32_BANK12 },
631 { 0xf10000, 0xf103ff, jaguar_jerry_regs32_w },
632 MEMORY_END
633
634
635
636 /*************************************
637 *
638 * DSP memory handlers
639 *
640 *************************************/
641
642 static MEMORY_READ32_START( dsp_readmem )
643 { 0x000000, 0x7fffff, MRA32_BANK10 },
644 { 0xf10000, 0xf103ff, jaguar_jerry_regs32_r },
645 { 0xf1a100, 0xf1a13f, dspctrl_r },
646 { 0xf1a140, 0xf1a17f, jaguar_serial_r },
647 { 0xf1b000, 0xf1cfff, MRA32_BANK13 },
648 { 0xf1d000, 0xf1dfff, MRA32_ROM },
649 MEMORY_END
650
651
652 static MEMORY_WRITE32_START( dsp_writemem )
653 { 0x000000, 0x7fffff, MWA32_BANK10 },
654 { 0xf10000, 0xf103ff, jaguar_jerry_regs32_w },
655 { 0xf1a100, 0xf1a13f, dspctrl_w },
656 { 0xf1a140, 0xf1a17f, jaguar_serial_w },
657 { 0xf1b000, 0xf1cfff, MWA32_BANK13 },
658 { 0xf1d000, 0xf1dfff, MWA32_ROM, &jaguar_wave_rom },
659 MEMORY_END
660
661
662
663 /*************************************
664 *
665 * Port definitions
666 *
667 *************************************/
668
669 INPUT_PORTS_START( area51 )
670 PORT_START
671 PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
672 PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START2 )
673 PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNUSED )
674
675 PORT_START
676 PORT_BIT( 0x00ff, IP_ACTIVE_LOW, IPT_UNUSED )
677 PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
678 PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNUSED )
679
680 PORT_START
681 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
682 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
683 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN3 )
684 PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_COIN4 )
685 PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_SPECIAL ) /* volume down*/
686 PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_SPECIAL ) /* volume up*/
687 PORT_SERVICE( 0x0040, IP_ACTIVE_LOW ) /* s-test*/
688 PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_SPECIAL ) /* vsyncneq*/
689 PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
690
691 PORT_START /* fake analog X */
692 PORT_ANALOG( 0xff, 0x80, IPT_LIGHTGUN_X, 50, 10, 0, 255 )
693
694 PORT_START /* fake analog Y */
695 PORT_ANALOG( 0xff, 0x80, IPT_LIGHTGUN_Y, 70, 10, 0, 255 )
696
697 PORT_START /* fake analog X */
698 PORT_ANALOG( 0xff, 0x80, IPT_LIGHTGUN_X | IPF_PLAYER2, 50, 10, 0, 255 )
699
700 PORT_START /* fake analog Y */
701 PORT_ANALOG( 0xff, 0x80, IPT_LIGHTGUN_Y | IPF_PLAYER2, 70, 10, 0, 255 )
702
703 PORT_START /* gun triggers */
704 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SPECIAL ) /* gun data valid*/
705 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SPECIAL ) /* gun data valid*/
706 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
707 PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
708 PORT_BIT( 0xfff0, IP_ACTIVE_LOW, IPT_UNKNOWN )
709 INPUT_PORTS_END
710
711
712 INPUT_PORTS_START( vcircle )
713 PORT_START
714 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER2 )
715 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON5 | IPF_PLAYER2 )
716 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON6 | IPF_PLAYER2 )
717 PORT_BIT( 0x00f8, IP_ACTIVE_LOW, IPT_UNUSED )
718 PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START2 )
719 PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
720 PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
721 PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 )
722 PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER2 )
723 PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER2 )
724 PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER2 )
725 PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER2 )
726
727 PORT_START
728 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER1 )
729 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON5 | IPF_PLAYER1 )
730 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON6 | IPF_PLAYER1 )
731 PORT_BIT( 0x00f8, IP_ACTIVE_LOW, IPT_UNUSED )
732 PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_START1 )
733 PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
734 PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
735 PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1 )
736 PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER1 )
737 PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER1 )
738 PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER1 )
739 PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER1 )
740
741 PORT_START
742 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
743 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
744 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_COIN3 )
745 PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_COIN4 )
746 PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_SPECIAL ) /* volume down*/
747 PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_SPECIAL ) /* volume up*/
748 PORT_SERVICE( 0x0040, IP_ACTIVE_LOW ) /* s-test*/
749 PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_SPECIAL ) /* vsyncneq*/
750 PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
751
752 PORT_START
753 PORT_BIT( 0x000f, IP_ACTIVE_HIGH, IPT_SPECIAL ) /* coin returns*/
754 PORT_BIT( 0x00f0, IP_ACTIVE_LOW, IPT_UNUSED )
755 PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
756 INPUT_PORTS_END
757
758
759
760 /*************************************
761 *
762 * Sound interfaces
763 *
764 *************************************/
765
766 static struct DACinterface dac_interface =
767 {
768 2,
769 { MIXER(100, MIXER_PAN_LEFT), MIXER(100, MIXER_PAN_RIGHT) }
770 };
771
772
773
774 /*************************************
775 *
776 * Machine driver
777 *
778 *************************************/
779
780 static struct r3000_config config =
781 {
782 0, /* 1 if we have an FPU, 0 otherwise */
783 4096, /* code cache size */
784 4096 /* data cache size */
785 };
786
787
788 static struct jaguar_config gpu_config =
789 {
790 jaguar_gpu_cpu_int
791 };
792
793
794 static struct jaguar_config dsp_config =
795 {
796 jaguar_dsp_cpu_int
797 };
798
799
800 MACHINE_DRIVER_START( cojagr3k )
801
802 /* basic machine hardware */
803 MDRV_CPU_ADD(R3000BE, 66000000/2)
MDRV_CPU_CONFIG(config)804 MDRV_CPU_CONFIG(config)
805 MDRV_CPU_MEMORY(r3000_readmem,r3000_writemem)
806
807 MDRV_CPU_ADD(JAGUARGPU, 52000000/2)
808 MDRV_CPU_CONFIG(gpu_config)
809 MDRV_CPU_MEMORY(gpu_readmem,gpu_writemem)
810
811 MDRV_CPU_ADD(JAGUARDSP, 52000000/2)
812 MDRV_CPU_CONFIG(dsp_config)
813 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
814 MDRV_CPU_MEMORY(dsp_readmem,dsp_writemem)
815
816 MDRV_FRAMES_PER_SECOND(60)
817 MDRV_VBLANK_DURATION(DEFAULT_REAL_60HZ_VBLANK_DURATION)
818
819 MDRV_MACHINE_INIT(cojag)
820 MDRV_NVRAM_HANDLER(generic_1fill)
821
822 /* video hardware */
823 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER | VIDEO_UPDATE_BEFORE_VBLANK)
824 MDRV_SCREEN_SIZE(42*8, 30*8)
825 MDRV_VISIBLE_AREA(0*8, 42*8-1, 0*8, 30*8-1)
826 MDRV_PALETTE_LENGTH(65534)
827
828 MDRV_VIDEO_START(cojag)
829 MDRV_VIDEO_UPDATE(cojag)
830
831 /* sound hardware */
832 MDRV_SOUND_ATTRIBUTES(SOUND_SUPPORTS_STEREO)
833 MDRV_SOUND_ADD(DAC, dac_interface)
834 MACHINE_DRIVER_END
835
836
837 MACHINE_DRIVER_START( r3knarrow )
838 MDRV_IMPORT_FROM(cojagr3k)
839
840 /* video hardware */
841 MDRV_VISIBLE_AREA(0*8, 40*8-1, 0*8, 30*8-1)
842 MACHINE_DRIVER_END
843
844
845 MACHINE_DRIVER_START( cojag68k )
846
847 /* basic machine hardware */
848 MDRV_CPU_ADD(M68EC020, 50000000/2)
849 MDRV_CPU_MEMORY(m68020_readmem,m68020_writemem)
850
851 MDRV_CPU_ADD(JAGUARGPU, 52000000/2)
852 MDRV_CPU_CONFIG(gpu_config)
853 MDRV_CPU_MEMORY(gpu_readmem,gpu_writemem)
854
855 MDRV_CPU_ADD(JAGUARDSP, 52000000/2)
856 MDRV_CPU_CONFIG(dsp_config)
857 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
858 MDRV_CPU_MEMORY(dsp_readmem,dsp_writemem)
859
860 MDRV_FRAMES_PER_SECOND(60)
861 MDRV_VBLANK_DURATION(DEFAULT_REAL_60HZ_VBLANK_DURATION)
862
863 MDRV_MACHINE_INIT(cojag)
864 MDRV_NVRAM_HANDLER(generic_1fill)
865
866 /* video hardware */
867 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER | VIDEO_UPDATE_BEFORE_VBLANK)
868 MDRV_SCREEN_SIZE(40*8, 30*8)
869 MDRV_VISIBLE_AREA(0*8, 40*8-1, 0*8, 30*8-1)
870 MDRV_PALETTE_LENGTH(65534)
871
872 MDRV_VIDEO_START(cojag)
873 MDRV_VIDEO_UPDATE(cojag)
874
875 /* sound hardware */
876 MDRV_SOUND_ATTRIBUTES(SOUND_SUPPORTS_STEREO)
877 MDRV_SOUND_ADD(DAC, dac_interface)
878 MACHINE_DRIVER_END
879
880
881
882 /*************************************
883 *
884 * ROM definition(s)
885 *
886 * Date Information comes from either
887 * ROM labels or from the Self-Test
888 * as "Main"
889 *
890 *************************************/
891
892 ROM_START( area51 ) /* 68020 based, Area51 v?? Date: Oct 25, 1995 */
893 ROM_REGION( 0x800000, REGION_CPU1, 0 ) /* 4MB for RAM at 0 */
894
895 ROM_REGION32_BE( 0x200000, REGION_USER1, ROMREGION_DISPOSE ) /* 2MB for 68020 code */
896 ROM_LOAD32_BYTE( "3h", 0x00000, 0x80000, CRC(116d37e6) SHA1(5d36cae792dd349faa77cd2d8018722a28ee55c1) )
897 ROM_LOAD32_BYTE( "3p", 0x00001, 0x80000, CRC(eb10f539) SHA1(dadc4be5a442dd4bd17385033056555e528ed994) )
898 ROM_LOAD32_BYTE( "3m", 0x00002, 0x80000, CRC(c6d8322b) SHA1(90cf848a4195c51b505653cc2c74a3b9e3c851b8) )
899 ROM_LOAD32_BYTE( "3k", 0x00003, 0x80000, CRC(729eb1b7) SHA1(21864b4281b1ad17b2903e3aa294e4be74161e80) )
900
901 DISK_REGION( REGION_DISKS )
902 DISK_IMAGE( "area51.chd", 0, MD5(130b330eff59403f8fc3433ff501852b) SHA1(9ea749404c9a5d44f407cdb8803293ec0d61410d) )
903 ROM_END
904
905
906 ROM_START( maxforce ) /* R3000 based, labeled as "Maximum Force 5-23-97 v1.05" */
907 ROM_REGION( 0x800000, REGION_CPU1, 0 ) /* 4MB for RAM at 0 */
908
909 ROM_REGION32_BE( 0x200000, REGION_USER1, ROMREGION_DISPOSE ) /* 2MB for IDT 79R3041 code */
910 ROM_LOAD32_BYTE( "maxf_105.hh", 0x00000, 0x80000, CRC(ec7f8167) SHA1(0cf057bfb1f30c2c9621d3ed25021e7ba7bdd46e) )
911 ROM_LOAD32_BYTE( "maxf_105.hl", 0x00001, 0x80000, CRC(3172611c) SHA1(00f14f871b737c66c20f95743740d964d0be3f24) )
912 ROM_LOAD32_BYTE( "maxf_105.lh", 0x00002, 0x80000, CRC(84d49423) SHA1(88d9a6724f1118f2bbef5dfa27accc2b65c5ba1d) )
913 ROM_LOAD32_BYTE( "maxf_105.ll", 0x00003, 0x80000, CRC(16d0768d) SHA1(665a6d7602a7f2f5b1f332b0220b1533143d56b1) )
914
915 DISK_REGION( REGION_DISKS )
916 DISK_IMAGE( "maxforce.chd", 0, MD5(b0a214c7b3f8ba9d592396332fc974c9) SHA1(59d77280afdb2d1f801ee81786aa7d3166ec2695) )
917 ROM_END
918
919
920 ROM_START( maxf_102 ) /* R3000 based, labeled as "Maximum Force 2-27-97 v1.02" */
921 ROM_REGION( 0x800000, REGION_CPU1, 0 ) /* 4MB for RAM at 0 */
922
923 ROM_REGION32_BE( 0x200000, REGION_USER1, ROMREGION_DISPOSE ) /* 2MB for IDT 79R3041 code */
924 ROM_LOAD32_BYTE( "maxf_102.hh", 0x00000, 0x80000, CRC(8ff7009d) SHA1(da22eae298a6e0e36f503fa091ac3913423dcd0f) )
925 ROM_LOAD32_BYTE( "maxf_102.hl", 0x00001, 0x80000, CRC(96c2cc1d) SHA1(b332b8c042b92c736131c478cefac1c3c2d2673b) )
926 ROM_LOAD32_BYTE( "maxf_102.lh", 0x00002, 0x80000, CRC(459ffba5) SHA1(adb40db6904e84c17f32ac6518fd2e994da7883f) )
927 ROM_LOAD32_BYTE( "maxf_102.ll", 0x00003, 0x80000, CRC(e491be7f) SHA1(cbe281c099a4aa87067752d68cf2bb0ab3900531) )
928
929 DISK_REGION( REGION_DISKS )
930 DISK_IMAGE( "maxforce.chd", 0, MD5(b0a214c7b3f8ba9d592396332fc974c9) SHA1(59d77280afdb2d1f801ee81786aa7d3166ec2695) )
931 ROM_END
932
933
934 ROM_START( area51mx ) /* 68020 based, Labeled as "68020 MAX/A51 KIT 2.0" Date: Apr 22, 1998 */
935 ROM_REGION( 0x800000, REGION_CPU1, 0 ) /* 4MB for RAM at 0 */
936
937 ROM_REGION32_BE( 0x200000, REGION_USER1, ROMREGION_DISPOSE ) /* 2MB for 68020 code */
938 ROM_LOAD32_BYTE( "area51mx.3h", 0x00000, 0x80000, CRC(47cbf30b) SHA1(23377bcc65c0fc330d5bc7e76e233bae043ac364) )
939 ROM_LOAD32_BYTE( "area51mx.3p", 0x00001, 0x80000, CRC(a3c93684) SHA1(f6b3357bb69900a176fd6bc6b819b2f57b7d0f59) )
940 ROM_LOAD32_BYTE( "area51mx.3m", 0x00002, 0x80000, CRC(d800ac17) SHA1(3d515c8608d8101ee9227116175b3c3f1fe22e0c) )
941 ROM_LOAD32_BYTE( "area51mx.3k", 0x00003, 0x80000, CRC(0e78f308) SHA1(adc4c8e441eb8fe525d0a6220eb3a2a8791a7289) )
942
943 DISK_REGION( REGION_DISKS )
944 DISK_IMAGE( "area51mx.chd", 0, MD5(fce1a0954759fa22e50747959716823d) SHA1(7e629045eb5baa8cd522273befffbf8520828938) )
945 ROM_END
946
947
948 ROM_START( a51mxr3k ) /* R3000 based, Labeled as "R3K Max/A51 Kit Ver 1.0" */
949 ROM_REGION( 0x800000, REGION_CPU1, 0 ) /* 4MB for RAM at 0 */
950
951 ROM_REGION32_BE( 0x200000, REGION_USER1, ROMREGION_DISPOSE ) /* 2MB for IDT 79R3041 code */
952 ROM_LOAD32_BYTE( "a51mxr3k.hh", 0x00000, 0x80000, CRC(a984dab2) SHA1(debb3bc11ff49e87a52e89a69533a1bab7db700e) )
953 ROM_LOAD32_BYTE( "a51mxr3k.hl", 0x00001, 0x80000, CRC(0af49d74) SHA1(c19f26056a823fd32293e9a7b3ea868640eabf49) )
954 ROM_LOAD32_BYTE( "a51mxr3k.lh", 0x00002, 0x80000, CRC(d7d94dac) SHA1(2060a74715f36a0d7f5dd0855eda48ad1f20f095) )
955 ROM_LOAD32_BYTE( "a51mxr3k.ll", 0x00003, 0x80000, CRC(ece9e5ae) SHA1(7e44402726f5afa6d1670b27aa43ad13d21c4ad9) )
956
957 DISK_REGION( REGION_DISKS )
958 DISK_IMAGE( "area51mx.chd", 0, MD5(fce1a0954759fa22e50747959716823d) SHA1(7e629045eb5baa8cd522273befffbf8520828938) )
959 ROM_END
960
961
962 ROM_START( vcircle )
963 ROM_REGION( 0x10, REGION_CPU1, 0 ) /* dummy region for R3000 */
964
965 ROM_REGION32_BE( 0x200000, REGION_USER1, ROMREGION_DISPOSE ) /* 2MB for R3000 code */
966 ROM_LOAD32_BYTE( "hh", 0x00000, 0x80000, CRC(7276f5f5) SHA1(716287e370a4f300b1743103f8031afc82de38ca) )
967 ROM_LOAD32_BYTE( "hl", 0x00001, 0x80000, CRC(146060a1) SHA1(f291989f1f0ef228757f1990fb14da5ff8f3cf8d) )
968 ROM_LOAD32_BYTE( "lh", 0x00002, 0x80000, CRC(be4b2ef6) SHA1(4332b3036e9cb12685e914d085d9a63aa856f0be) )
969 ROM_LOAD32_BYTE( "ll", 0x00003, 0x80000, CRC(ba8753eb) SHA1(0322e0e37d814a38d08ba191b1a97fb1a55fe461) )
970
971 DISK_REGION( REGION_DISKS )
972 DISK_IMAGE( "vcircle.chd", 0, MD5(fc316bd92363573d60083514223c6816) SHA1(f1d3e3d081d10ec42d07cd695d52b44812264983) )
973 ROM_END
974
975
976
977 /*************************************
978 *
979 * Driver initialization
980 *
981 *************************************/
982
983 static void common_init(UINT8 crosshair, UINT16 gpu_jump_offs, UINT16 spin_pc)
984 {
985 /* copy over the ROM */
986 memcpy(rom_base, memory_region(REGION_USER1), rom_size);
987 cojag_is_r3000 = (Machine->drv->cpu[0].cpu_type == CPU_R3000BE);
988 cojag_draw_crosshair = crosshair;
989
990 /* install synchronization hooks for GPU */
991 if (cojag_is_r3000)
992 install_mem_write32_handler(0, 0x04f0b000 + gpu_jump_offs, 0x04f0b003 + gpu_jump_offs, gpu_jump_w);
993 else
994 install_mem_write32_handler(0, 0xf0b000 + gpu_jump_offs, 0xf0b003 + gpu_jump_offs, gpu_jump_w);
995 install_mem_read32_handler(1, 0xf03000 + gpu_jump_offs, 0xf03003 + gpu_jump_offs, gpu_jump_r);
996 gpu_jump_address = &jaguar_gpu_ram[gpu_jump_offs/4];
997 gpu_spin_pc = 0xf03000 + spin_pc;
998
999 /* init the sound system and install DSP speedups */
1000 cojag_sound_init();
1001
1002 /* spin up the hard disk */
1003 ide_controller_init(0, &ide_intf);
1004 }
1005
1006
DRIVER_INIT(area51)1007 static DRIVER_INIT( area51 )
1008 {
1009 common_init(1, 0x5c4, 0x5a0);
1010
1011 #if ENABLE_SPEEDUP_HACKS
1012 /* install speedup for main CPU */
1013 main_speedup = install_mem_write32_handler(0, 0xa02030, 0xa02033, area51_main_speedup_w);
1014 #endif
1015 }
1016
1017
DRIVER_INIT(maxforce)1018 static DRIVER_INIT( maxforce )
1019 {
1020 common_init(1, 0x0c0, 0x09e);
1021
1022 /* patch the protection */
1023 rom_base[0x220/4] = 0x03e00008;
1024
1025 #if ENABLE_SPEEDUP_HACKS
1026 /* install speedup for main CPU */
1027 main_speedup_max_cycles = 120;
1028 main_speedup = install_mem_read32_handler(0, 0x1000865c, 0x1000865f, cojagr3k_main_speedup_r);
1029 #endif
1030 }
1031
1032
DRIVER_INIT(area51mx)1033 static DRIVER_INIT( area51mx )
1034 {
1035 common_init(1, 0x0c0, 0x09e);
1036
1037 /* patch the protection */
1038 rom_base[0x418/4] = 0x4e754e75;
1039
1040 #if ENABLE_SPEEDUP_HACKS
1041 /* install speedup for main CPU */
1042 main_speedup = install_mem_write32_handler(0, 0xa19550, 0xa19557, area51mx_main_speedup_w);
1043 #endif
1044 }
1045
1046
DRIVER_INIT(a51mxr3k)1047 static DRIVER_INIT( a51mxr3k )
1048 {
1049 common_init(1, 0x0c0, 0x09e);
1050
1051 /* patch the protection */
1052 rom_base[0x220/4] = 0x03e00008;
1053
1054 #if ENABLE_SPEEDUP_HACKS
1055 /* install speedup for main CPU */
1056 main_speedup_max_cycles = 120;
1057 main_speedup = install_mem_read32_handler(0, 0x10006f0c, 0x10006f0f, cojagr3k_main_speedup_r);
1058 #endif
1059 }
1060
1061
DRIVER_INIT(vcircle)1062 static DRIVER_INIT( vcircle )
1063 {
1064 common_init(0, 0x5c0, 0x5a0);
1065
1066 #if ENABLE_SPEEDUP_HACKS
1067 /* install speedup for main CPU */
1068 main_speedup_max_cycles = 50;
1069 main_speedup = install_mem_read32_handler(0, 0x12005b34, 0x12005b37, cojagr3k_main_speedup_r);
1070 #endif
1071 }
1072
1073
1074
1075 /*************************************
1076 *
1077 * Game driver(s)
1078 *
1079 *************************************/
1080
1081 GAME( 1995, area51, 0, cojag68k, area51, area51, ROT0, "Atari Games", "Area 51" )
1082 GAME( 1996, maxforce, 0, r3knarrow, area51, maxforce, ROT0, "Atari Games", "Maximum Force v1.05" )
1083 GAME( 1996, maxf_102, maxforce, r3knarrow, area51, maxforce, ROT0, "Atari Games", "Maximum Force v1.02" )
1084 GAME( 1998, area51mx, 0, cojag68k, area51, area51mx, ROT0, "Atari Games", "Area 51 - Maximum Force Duo v2.0" )
1085 GAME( 1998, a51mxr3k, area51mx, r3knarrow, area51, a51mxr3k, ROT0, "Atari Games", "Area 51 - Maximum Force Duo (R3000)" )
1086 GAME( 1996, vcircle, 0, cojagr3k, vcircle, vcircle, ROT0, "Atari Games", "Vicious Circle (prototype)" )
1087