1 /****************************************
2
3 Libble Rabble (c) 1983 Namco
4 Toypop (c) 1986 Namco
5
6 driver by Edgardo E. Contini Salvan (pag2806@iperbole.bologna.it)
7
8 6809 main CPU,
9 6809 sound and
10 68000 to create the background image.
11
12 Libble Rabble and Toypop run on the same board, but the memory map is subtly
13 different.
14
15 Notes:
16 ------
17 - Libble Rabble Easter egg:
18 - enter service mode
19 - turn off the service mode switch, and turn it on again quickly to remain
20 on the monitor test grid
21 - Enter the following sequence using the right joystick:
22 9xU 2xR 9xD 2xL
23 (c) 1983 NAMCO LTD. will appear on the screen.
24
25
26 TODO:
27 - I haven't found any Easter egg in Toy Pop. Maybe they had stopped inserting
28 them by that time.
29
30 ****************************************/
31
32 #include "driver.h"
33 #include "vidhrdw/generic.h"
34 #include "machine/namcoio.h"
35
36
37 // vidhrdw\toypop.c
38 extern data16_t *toypop_bg_image;
39 extern data8_t *toypop_videoram;
40 WRITE_HANDLER( toypop_videoram_w );
41 READ16_HANDLER( toypop_merged_background_r );
42 WRITE16_HANDLER( toypop_merged_background_w );
43 WRITE_HANDLER( toypop_palettebank_w );
44 WRITE16_HANDLER( toypop_flipscreen_w );
45 WRITE16_HANDLER( liblrabl_flipscreen_w );
46 VIDEO_START( toypop );
47 VIDEO_UPDATE( toypop );
48 PALETTE_INIT( toypop );
49
50
51
52 /***************************************************************************
53
54 Custom I/O initialization
55
56 ***************************************************************************/
57
READ_HANDLER(in0_l)58 static READ_HANDLER( in0_l ) { return readinputport(0); } // P1 joystick
READ_HANDLER(in0_h)59 static READ_HANDLER( in0_h ) { return readinputport(0) >> 4; } // P2 joystick
READ_HANDLER(in1_l)60 static READ_HANDLER( in1_l ) { return readinputport(1); } // fire and start buttons
READ_HANDLER(in1_h)61 static READ_HANDLER( in1_h ) { return readinputport(1) >> 4; } // coins
READ_HANDLER(dipA_l)62 static READ_HANDLER( dipA_l ) { return readinputport(2); } // dips A
READ_HANDLER(dipA_h)63 static READ_HANDLER( dipA_h ) { return readinputport(2) >> 4; } // dips A
READ_HANDLER(dipB_l)64 static READ_HANDLER( dipB_l ) { return readinputport(3); } // dips B
READ_HANDLER(dipB_h)65 static READ_HANDLER( dipB_h ) { return readinputport(3) >> 4; } // dips B
READ_HANDLER(in2_l)66 static READ_HANDLER( in2_l ) { return readinputport(4); } // P1 joystick left in liblrabl
READ_HANDLER(in2_h)67 static READ_HANDLER( in2_h ) { return readinputport(4) >> 4; } // P2 joystick left in liblrabl
READ_HANDLER(in3)68 static READ_HANDLER( in3 ) { return readinputport(5); } // test, cocktail, optional buttons
WRITE_HANDLER(out_coin0)69 static WRITE_HANDLER( out_coin0 )
70 {
71 coin_lockout_global_w(data & 4);
72 coin_counter_w(0,~data & 8);
73 }
WRITE_HANDLER(out_coin1)74 static WRITE_HANDLER( out_coin1 )
75 {
76 coin_counter_w(1,~data & 1);
77 }
WRITE_HANDLER(flip)78 static WRITE_HANDLER( flip )
79 {
80 flip_screen_set(data & 1);
81 }
82
83 /* chip #0: player inputs, buttons, coins */
84 static struct namcoio_interface intf0_coin =
85 {
86 { in1_h, in0_l, in0_h, in1_l }, /* port read handlers */
87 { out_coin0, out_coin1 } /* port write handlers */
88 };
89 static struct namcoio_interface intf0 =
90 {
91 { in1_h, in0_l, in0_h, in1_l }, /* port read handlers */
92 { NULL, NULL } /* port write handlers */
93 };
94
95 /* chip #1: dip switches */
96 static struct namcoio_interface intf1 =
97 {
98 { dipA_h, dipB_l, dipB_h, dipA_l }, /* port read handlers */
99 { flip, NULL } /* port write handlers */
100 };
101
102 /* chip #2: test/cocktail, optional buttons */
103 static struct namcoio_interface intf2 =
104 {
105 { NULL, in2_l, in2_h, in3 }, /* port read handlers */
106 { NULL, NULL } /* port write handlers */
107 };
108
109 static DRIVER_INIT( 58c_56_56 )
110 {
111 namcoio_init(0, NAMCOIO_58XX, &intf0_coin);
112 namcoio_init(1, NAMCOIO_56XX, &intf1);
113 namcoio_init(2, NAMCOIO_56XX, &intf2);
114 }
115
116 static DRIVER_INIT( 58_56_56 )
117 {
118 namcoio_init(0, NAMCOIO_58XX, &intf0);
119 namcoio_init(1, NAMCOIO_56XX, &intf1);
120 namcoio_init(2, NAMCOIO_56XX, &intf2);
121 }
122
123
124 /***************************************************************************/
125
126
127 static int interrupt_enable_68k;
128 static data8_t *toypop_m68000_sharedram;
129
130
READ_HANDLER(toypop_sound_sharedram_r)131 READ_HANDLER( toypop_sound_sharedram_r )
132 {
133 return namco_soundregs[offset];
134 }
135
WRITE_HANDLER(toypop_sound_sharedram_w)136 WRITE_HANDLER( toypop_sound_sharedram_w )
137 {
138 if (offset < 0x40)
139 namco_15xx_w(offset,data);
140 else
141 namco_soundregs[offset] = data;
142 }
143
READ16_HANDLER(toypop_m68000_sharedram_r)144 READ16_HANDLER( toypop_m68000_sharedram_r )
145 {
146 return toypop_m68000_sharedram[offset];
147 }
148
WRITE16_HANDLER(toypop_m68000_sharedram_w)149 WRITE16_HANDLER( toypop_m68000_sharedram_w )
150 {
151 if (ACCESSING_LSB)
152 toypop_m68000_sharedram[offset] = data & 0xff;
153 }
154
READ_HANDLER(toypop_main_interrupt_enable_r)155 READ_HANDLER( toypop_main_interrupt_enable_r )
156 {
157 cpu_interrupt_enable(0,1);
158 return 0;
159 }
160
WRITE_HANDLER(toypop_main_interrupt_enable_w)161 WRITE_HANDLER( toypop_main_interrupt_enable_w )
162 {
163 cpu_interrupt_enable(0,1);
164 cpu_set_irq_line(0, 0, CLEAR_LINE);
165 }
166
WRITE_HANDLER(toypop_main_interrupt_disable_w)167 WRITE_HANDLER( toypop_main_interrupt_disable_w )
168 {
169 cpu_interrupt_enable(0,0);
170 }
171
WRITE_HANDLER(toypop_sound_interrupt_enable_acknowledge_w)172 WRITE_HANDLER( toypop_sound_interrupt_enable_acknowledge_w )
173 {
174 cpu_interrupt_enable(1,1);
175 cpu_set_irq_line(1, 0, CLEAR_LINE);
176 }
177
WRITE_HANDLER(toypop_sound_interrupt_disable_w)178 WRITE_HANDLER( toypop_sound_interrupt_disable_w )
179 {
180 cpu_interrupt_enable(1,0);
181 }
182
INTERRUPT_GEN(toypop_main_interrupt)183 INTERRUPT_GEN( toypop_main_interrupt )
184 {
185 irq0_line_assert(); // this also checks if irq is enabled - IMPORTANT!
186 // so don't replace with cpu_set_irq_line(0, 0, ASSERT_LINE);
187
188 namcoio_set_irq_line(0,PULSE_LINE);
189 namcoio_set_irq_line(1,PULSE_LINE);
190 namcoio_set_irq_line(2,PULSE_LINE);
191 }
192
WRITE_HANDLER(toypop_sound_clear_w)193 WRITE_HANDLER( toypop_sound_clear_w )
194 {
195 cpu_set_reset_line(1, CLEAR_LINE);
196 }
197
WRITE_HANDLER(toypop_sound_assert_w)198 WRITE_HANDLER( toypop_sound_assert_w )
199 {
200 cpu_set_reset_line(1, ASSERT_LINE);
201 }
202
WRITE_HANDLER(toypop_m68000_clear_w)203 WRITE_HANDLER( toypop_m68000_clear_w )
204 {
205 cpu_set_reset_line(2, CLEAR_LINE);
206 }
207
WRITE_HANDLER(toypop_m68000_assert_w)208 WRITE_HANDLER( toypop_m68000_assert_w )
209 {
210 cpu_set_reset_line(2, ASSERT_LINE);
211 }
212
MACHINE_INIT(toypop)213 MACHINE_INIT( toypop )
214 {
215 cpu_interrupt_enable(0,0);
216 cpu_set_irq_line(0, 0, CLEAR_LINE);
217 cpu_interrupt_enable(1,0);
218 cpu_set_irq_line(1, 0, CLEAR_LINE);
219 interrupt_enable_68k = 0;
220 }
221
INTERRUPT_GEN(toypop_m68000_interrupt)222 INTERRUPT_GEN( toypop_m68000_interrupt )
223 {
224 if (interrupt_enable_68k)
225 cpu_set_irq_line(2, 6, HOLD_LINE);
226 }
227
WRITE_HANDLER(toypop_68k_irq_trigger_w)228 static WRITE_HANDLER( toypop_68k_irq_trigger_w )
229 {
230 if (interrupt_enable_68k)
231 cpu_set_irq_line(2, 6, HOLD_LINE);
232 }
233
WRITE16_HANDLER(toypop_m68000_interrupt_enable_w)234 WRITE16_HANDLER( toypop_m68000_interrupt_enable_w )
235 {
236 interrupt_enable_68k = 1;
237 }
238
WRITE16_HANDLER(toypop_m68000_interrupt_disable_w)239 WRITE16_HANDLER( toypop_m68000_interrupt_disable_w )
240 {
241 interrupt_enable_68k = 0;
242 }
243
244
245
246 /*************************************
247 *
248 * Main CPU memory handlers
249 *
250 *************************************/
251
MEMORY_READ_START(readmem_mainCPU_liblrabl)252 static MEMORY_READ_START( readmem_mainCPU_liblrabl )
253 { 0x0000, 0x2fff, MRA_RAM }, /* RAM everywhere else */
254 { 0x6000, 0x63ff, toypop_sound_sharedram_r }, /* shared RAM with sound CPU */
255 { 0x6800, 0x683f, namcoio_r }, /* custom I/O */
256 { 0x7800, 0x7800, watchdog_reset_r }, /* not sure; this is NOT irq enable (game crashes otherwise) */
257 { 0x8000, 0xffff, MRA_ROM }, /* ROM code */
258 MEMORY_END
259
260 static MEMORY_READ_START( readmem_mainCPU_toypop )
261 { 0x0000, 0x2fff, MRA_RAM }, /* RAM everywhere else */
262 { 0x6000, 0x603f, namcoio_r }, /* custom I/O */
263 { 0x6800, 0x6bff, toypop_sound_sharedram_r }, /* shared RAM with sound CPU */
264 { 0x7000, 0x7000, toypop_main_interrupt_enable_r }, /* enable interrupt?? */
265 { 0x8000, 0xffff, MRA_ROM }, /* ROM code */
266 MEMORY_END
267
268 static MEMORY_WRITE_START( writemem_mainCPU_liblrabl )
269 { 0x0000, 0x07ff, toypop_videoram_w, &toypop_videoram }, /* video RAM */
270 { 0x0800, 0x0f7f, MWA_RAM }, /* general RAM, area 1 */
271 { 0x0f80, 0x0fff, MWA_RAM, &spriteram }, /* sprite RAM, area 1 */
272 { 0x1000, 0x177f, MWA_RAM }, /* general RAM, area 2 */
273 { 0x1780, 0x17ff, MWA_RAM, &spriteram_2 }, /* sprite RAM, area 2 */
274 { 0x1800, 0x1f7f, MWA_RAM }, /* general RAM, area 3 */
275 { 0x1f80, 0x1fff, MWA_RAM, &spriteram_3 }, /* sprite RAM, area 3 */
276 { 0x2800, 0x2fff, MWA_RAM, &toypop_m68000_sharedram }, /* shared RAM with the 68000 CPU */
277 { 0x6000, 0x63ff, toypop_sound_sharedram_w }, /* shared RAM with sound CPU */
278 { 0x6800, 0x683f, namcoio_w }, /* custom I/O */
279 { 0x7000, 0x7000, toypop_main_interrupt_enable_w }, /* enable interrupt */
280 { 0x7800, 0x7800, toypop_main_interrupt_disable_w }, /* disable interrupt */
281 { 0x8000, 0x8000, toypop_m68000_clear_w }, /* reset 68000 */
282 { 0x8800, 0x8800, toypop_m68000_assert_w }, /* reset 68000 */
283 { 0x9000, 0x9000, toypop_sound_clear_w }, /* sound CPU reset */
284 { 0x9800, 0x9800, toypop_sound_assert_w }, /* sound CPU reset */
285 { 0xa000, 0xa001, toypop_palettebank_w }, /* background image palette */
286 { 0x8000, 0xffff, MWA_ROM }, /* ROM code */
287 MEMORY_END
288
289 static MEMORY_WRITE_START( writemem_mainCPU_toypop )
290 { 0x0000, 0x07ff, toypop_videoram_w, &toypop_videoram }, /* video RAM */
291 { 0x0800, 0x0f7f, MWA_RAM }, /* general RAM, area 1 */
292 { 0x0f80, 0x0fff, MWA_RAM, &spriteram }, /* sprite RAM, area 1 */
293 { 0x1000, 0x177f, MWA_RAM }, /* general RAM, area 2 */
294 { 0x1780, 0x17ff, MWA_RAM, &spriteram_2 }, /* sprite RAM, area 2 */
295 { 0x1800, 0x1f7f, MWA_RAM }, /* general RAM, area 3 */
296 { 0x1f80, 0x1fff, MWA_RAM, &spriteram_3 }, /* sprite RAM, area 3 */
297 { 0x2800, 0x2fff, MWA_RAM, &toypop_m68000_sharedram }, /* shared RAM with the 68000 CPU */
298 { 0x6000, 0x603f, namcoio_w }, /* custom I/O */
299 { 0x6800, 0x6bff, toypop_sound_sharedram_w }, /* shared RAM with sound CPU */
300 { 0x7000, 0x7000, toypop_main_interrupt_disable_w }, /* disable interrupt */
301 { 0x8000, 0x8000, toypop_m68000_clear_w }, /* reset 68000 */
302 { 0x8800, 0x8800, toypop_m68000_assert_w }, /* reset 68000 */
303 { 0x9000, 0x9000, toypop_sound_clear_w }, /* sound CPU reset */
304 { 0x9800, 0x9800, toypop_sound_assert_w }, /* sound CPU reset */
305 { 0xa000, 0xa001, toypop_palettebank_w }, /* background image palette */
306 { 0x8000, 0xffff, MWA_ROM }, /* ROM code */
307 MEMORY_END
308
309
310 /*************************************
311 *
312 * Sound CPU memory handlers
313 *
314 *************************************/
315
316 static MEMORY_READ_START( readmem_soundCPU )
317 { 0x0000, 0x03ff, toypop_sound_sharedram_r },
318 { 0xe000, 0xffff, MRA_ROM },
319 MEMORY_END
320
321 static MEMORY_WRITE_START( writemem_soundCPU )
322 { 0x0000, 0x03ff, toypop_sound_sharedram_w, &namco_soundregs }, /* shared RAM with the main CPU + sound registers */
323 { 0x2000, 0x2000, toypop_sound_interrupt_disable_w }, /* ??? toypop doesn't write here */
324 { 0x4000, 0x4000, toypop_sound_interrupt_enable_acknowledge_w },
325 { 0x6000, 0x6000, watchdog_reset_w },
326 { 0xe000, 0xffff, MWA_ROM },
327 MEMORY_END
328
329
330
331 /*************************************
332 *
333 * 68k CPU memory handlers
334 *
335 *************************************/
336
337 static MEMORY_READ16_START( readmem_68k )
338 { 0x000000, 0x007fff, MRA16_ROM }, // ROM code
339 { 0x080000, 0x0bffff, MRA16_RAM }, // RAM
340 { 0x100000, 0x100fff, toypop_m68000_sharedram_r }, // shared RAM with the main CPU
341 { 0x180000, 0x187fff, toypop_merged_background_r }, // RAM merged with the background image
342 { 0x190000, 0x1dffff, MRA16_RAM }, // RAM containing the background image
343 MEMORY_END
344
345 static MEMORY_WRITE16_START( writemem_68k )
346 { 0x000000, 0x007fff, MWA16_ROM }, /* ROM code */
347 { 0x080000, 0x0bffff, MWA16_RAM }, /* RAM */
348 { 0x100000, 0x100fff, toypop_m68000_sharedram_w }, /* shared RAM with the main CPU */
349 { 0x180000, 0x187fff, toypop_merged_background_w }, /* RAM that has to be merged with the background image */
350 { 0x18fffc, 0x18ffff, toypop_flipscreen_w }, /* flip mode */
351 { 0x190000, 0x1dffff, MWA16_RAM, &toypop_bg_image }, /* RAM containing the background image */
352 { 0x300000, 0x300001, toypop_m68000_interrupt_enable_w }, /* interrupt enable */
353 { 0x380000, 0x380001, toypop_m68000_interrupt_disable_w }, /* interrupt disable */
354 MEMORY_END
355
356
357
358 INPUT_PORTS_START( liblrabl )
359 /* The inputs are not memory mapped, they are handled by three I/O chips. */
360 PORT_START /* 58XX #0 pins 22-29 */
361 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_UP | IPF_8WAY )
362 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_RIGHT | IPF_8WAY )
363 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_DOWN | IPF_8WAY )
364 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_LEFT | IPF_8WAY )
365 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_UP | IPF_8WAY | IPF_COCKTAIL )
366 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_RIGHT | IPF_8WAY | IPF_COCKTAIL )
367 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_DOWN | IPF_8WAY | IPF_COCKTAIL )
368 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_JOYSTICKRIGHT_LEFT | IPF_8WAY | IPF_COCKTAIL )
369
370 PORT_START /* 58XX #0 pins 30-33 and 38-41 */
371 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
372 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
373 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
374 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
375 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
376 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
377 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
378 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
379
380 PORT_START /* 56XX #1 pins 22-29 */
381 PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )
382 PORT_DIPSETTING( 0x02, "1" )
383 PORT_DIPSETTING( 0x00, "2" )
384 PORT_DIPSETTING( 0x03, "3" )
385 PORT_DIPSETTING( 0x01, "5" )
386 // TODO: bonus scores are different for 5 lives
387 PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Bonus_Life ) )
388 PORT_DIPSETTING( 0x04, "40k 120k and every 120k" )
389 PORT_DIPSETTING( 0x1c, "40k 120k 200k 400k..." )
390 PORT_DIPSETTING( 0x10, "40k 120k 200k" )
391 PORT_DIPSETTING( 0x0c, "40k 140k 250k 400k..." )
392 PORT_DIPSETTING( 0x18, "40k 150k and every 150k" )
393 PORT_DIPSETTING( 0x14, "50k 150k 300k 500k..." )
394 PORT_DIPSETTING( 0x08, "50k 150k 300k" )
395 PORT_DIPSETTING( 0x00, "None" )
396 PORT_DIPNAME( 0xe0, 0xe0, DEF_STR( Coin_A ) )
397 PORT_DIPSETTING( 0x80, DEF_STR( 3C_1C ) )
398 PORT_DIPSETTING( 0xc0, DEF_STR( 2C_1C ) )
399 PORT_DIPSETTING( 0x00, DEF_STR( 3C_2C ) )
400 PORT_DIPSETTING( 0xe0, DEF_STR( 1C_1C ) )
401 PORT_DIPSETTING( 0x40, DEF_STR( 2C_3C ) )
402 PORT_DIPSETTING( 0x60, DEF_STR( 1C_2C ) )
403 PORT_DIPSETTING( 0xa0, DEF_STR( 1C_3C ) )
404 PORT_DIPSETTING( 0x20, DEF_STR( 1C_6C ) )
405
406 PORT_START /* 56XX #1 pins 30-33 and 38-41 */
407 PORT_DIPNAME( 0x01, 0x01, "Freeze" )
408 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
409 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
410 PORT_DIPNAME( 0x02, 0x02, "Rack Test" )
411 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
412 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
413 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Demo_Sounds ) )
414 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
415 PORT_DIPSETTING( 0x04, DEF_STR( On ) )
416 PORT_DIPNAME( 0x18, 0x18, DEF_STR( Coin_B ) )
417 PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
418 PORT_DIPSETTING( 0x18, DEF_STR( 1C_1C ) )
419 PORT_DIPSETTING( 0x08, DEF_STR( 1C_5C ) )
420 PORT_DIPSETTING( 0x10, DEF_STR( 1C_7C ) )
421 PORT_DIPNAME( 0x20, 0x20, "Practice" )
422 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
423 PORT_DIPSETTING( 0x20, DEF_STR( On ) )
424 PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Difficulty ) )
425 PORT_DIPSETTING( 0xc0, "A" )
426 PORT_DIPSETTING( 0x40, "B" )
427 PORT_DIPSETTING( 0x80, "C" )
428 PORT_DIPSETTING( 0x00, "D" )
429
430 PORT_START /* 56XX #2 pins 22-29 */
431 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_UP | IPF_8WAY )
432 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_RIGHT | IPF_8WAY )
433 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN | IPF_8WAY )
434 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_LEFT | IPF_8WAY )
435 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_UP | IPF_8WAY | IPF_COCKTAIL )
436 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_RIGHT | IPF_8WAY | IPF_COCKTAIL )
437 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_DOWN | IPF_8WAY | IPF_COCKTAIL )
438 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_JOYSTICKLEFT_LEFT | IPF_8WAY | IPF_COCKTAIL )
439
440 PORT_START /* 56XX #2 pins 30-33 */
441 PORT_BIT( 0x03, IP_ACTIVE_LOW, IPT_UNUSED )
442 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Cabinet ) )
443 PORT_DIPSETTING( 0x04, DEF_STR( Upright ) )
444 PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
445 PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
446 INPUT_PORTS_END
447
448 INPUT_PORTS_START( toypop )
449 /* The inputs are not memory mapped, they are handled by three I/O chips. */
450 PORT_START /* 58XX #0 pins 22-29 */
451 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_4WAY )
452 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_4WAY )
453 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_4WAY )
454 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_4WAY )
455 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_4WAY | IPF_PLAYER2 )
456 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_4WAY | IPF_PLAYER2 )
457 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_4WAY | IPF_PLAYER2 )
458 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_4WAY | IPF_PLAYER2 )
459
460 PORT_START /* 58XX #0 pins 30-33 and 38-41 */
461 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
462 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
463 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
464 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
465 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
466 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
467 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
468 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
469
470 PORT_START /* 56XX #1 pins 22-29 */
471 PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )
472 PORT_DIPSETTING( 0x02, "1" )
473 PORT_DIPSETTING( 0x01, "2" )
474 PORT_DIPSETTING( 0x03, "3" )
475 PORT_DIPSETTING( 0x00, "5" )
476 PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coin_B ) )
477 PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
478 PORT_DIPSETTING( 0x04, DEF_STR( 2C_1C ) )
479 PORT_DIPSETTING( 0x0c, DEF_STR( 1C_1C ) )
480 PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
481 PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) )
482 PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
483 PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) )
484 PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
485 PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) )
486 PORT_DIPNAME( 0x40, 0x00, DEF_STR( Flip_Screen ) )
487 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
488 PORT_DIPSETTING( 0x40, DEF_STR( On ) )
489 PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
490
491 PORT_START /* 56XX #1 pins 30-33 and 38-41 */
492 PORT_DIPNAME( 0x01, 0x01, "Freeze" )
493 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
494 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
495 PORT_DIPNAME( 0x02, 0x02, "Level Select" )
496 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
497 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
498 PORT_DIPNAME( 0x04, 0x04, "2 Players Game" )
499 PORT_DIPSETTING( 0x00, "1 Credit" )
500 PORT_DIPSETTING( 0x04, "2 Credits" )
501 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
502 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
503 PORT_DIPSETTING( 0x08, DEF_STR( On ) )
504 PORT_DIPNAME( 0x10, 0x10, "Entering" ) // ???
505 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
506 PORT_DIPSETTING( 0x10, DEF_STR( On ) )
507 PORT_DIPNAME( 0x60, 0x60, DEF_STR( Difficulty ) )
508 PORT_DIPSETTING( 0x40, "Easy" )
509 PORT_DIPSETTING( 0x60, "Normal" )
510 PORT_DIPSETTING( 0x20, "Hard" )
511 PORT_DIPSETTING( 0x00, "Very hard" )
512 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Bonus_Life ) )
513 PORT_DIPSETTING( 0x80, "Every 15000 points" )
514 PORT_DIPSETTING( 0x00, "Every 20000 points" )
515
516 PORT_START /* 56XX #2 pins 22-29 */
517 PORT_BIT(0xff, IP_ACTIVE_LOW, IPT_UNUSED )
518
519 PORT_START /* 56XX #2 pins 30-33 */
520 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
521 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
522 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) // would be Cabinet, but this game has no cocktail mode
523 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) // service mode again
524 INPUT_PORTS_END
525
526
527
528 static struct GfxLayout charlayout =
529 {
530 8,8,
531 RGN_FRAC(1,1),
532 2,
533 { 0, 4 },
534 { 8*8+0, 8*8+1, 8*8+2, 8*8+3, 0, 1, 2, 3 },
535 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
536 16*8
537 };
538
539 static struct GfxLayout spritelayout =
540 {
541 16,16,
542 RGN_FRAC(1,1),
543 2,
544 { 0, 4 },
545 { 0, 1, 2, 3, 8*8, 8*8+1, 8*8+2, 8*8+3, 16*8+0, 16*8+1, 16*8+2, 16*8+3,
546 24*8+0, 24*8+1, 24*8+2, 24*8+3 },
547 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
548 32 * 8, 33 * 8, 34 * 8, 35 * 8, 36 * 8, 37 * 8, 38 * 8, 39 * 8 },
549 64*8
550 };
551
552 static struct GfxDecodeInfo gfxdecodeinfo[] =
553 {
554 { REGION_GFX1, 0, &charlayout, 0, 128 },
555 { REGION_GFX2, 0, &spritelayout, 128*4, 64 },
556 { -1 } /* end of array */
557 };
558
559
560
561 static struct namco_interface namco_interface =
562 {
563 24000, /* sample rate */
564 8, /* number of voices */
565 100, /* playback volume */
566 REGION_SOUND1 /* memory region */
567 };
568
569
570
571 static MACHINE_DRIVER_START( liblrabl )
572
573 /* basic machine hardware */
574 MDRV_CPU_ADD_TAG("main", M6809, 1536000) /* 1.536 MHz (measured on Libble Rabble board) */
575 MDRV_CPU_MEMORY(readmem_mainCPU_liblrabl,writemem_mainCPU_liblrabl)
576 MDRV_CPU_VBLANK_INT(toypop_main_interrupt,1)
577
578 MDRV_CPU_ADD(M6809, 1536000)
579 MDRV_CPU_FLAGS(CPU_AUDIO_CPU) /* 1.536 MHz (measured on Libble Rabble board) */
580 MDRV_CPU_MEMORY(readmem_soundCPU,writemem_soundCPU)
581 MDRV_CPU_VBLANK_INT(irq0_line_assert,1)
582
583 MDRV_CPU_ADD(M68000, 6144000) /* 6.144 MHz (measured on Libble Rabble board) */
584 MDRV_CPU_MEMORY(readmem_68k,writemem_68k)
585 MDRV_CPU_VBLANK_INT(toypop_m68000_interrupt,1)
586
587 MDRV_FRAMES_PER_SECOND(60.606060)
588 MDRV_VBLANK_DURATION(DEFAULT_60HZ_VBLANK_DURATION)
589 MDRV_INTERLEAVE(100) /* 100 CPU slices per frame - an high value to ensure proper */
590 /* synchronization of the CPUs */
591 MDRV_MACHINE_INIT(toypop)
592
593 /* video hardware */
594 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
595 MDRV_SCREEN_SIZE(36*8, 28*8)
596 MDRV_VISIBLE_AREA(0*8, 36*8-1, 0*8, 28*8-1)
597 MDRV_GFXDECODE(gfxdecodeinfo)
598 MDRV_PALETTE_LENGTH(256)
599 MDRV_COLORTABLE_LENGTH(128*4+64*4)
600
601 MDRV_PALETTE_INIT(toypop)
602 MDRV_VIDEO_START(toypop)
603 MDRV_VIDEO_UPDATE(toypop)
604
605 /* sound hardware */
606 MDRV_SOUND_ADD(NAMCO_15XX, namco_interface)
607 MACHINE_DRIVER_END
608
609 static MACHINE_DRIVER_START( toypop )
610
611 /* basic machine hardware */
612 MDRV_IMPORT_FROM(liblrabl)
613 MDRV_CPU_MODIFY("main")
614 MDRV_CPU_MEMORY(readmem_mainCPU_toypop,writemem_mainCPU_toypop)
615 MACHINE_DRIVER_END
616
617
618
619 /*************************************
620 *
621 * ROM definitions
622 *
623 *************************************/
624
625 ROM_START( liblrabl )
626 ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for the first CPU */
627 ROM_LOAD( "5b.rom", 0x8000, 0x4000, CRC(da7a93c2) SHA1(fe4a02cdab66722eb7b8cf58825f899b1949a6a2) )
628 ROM_LOAD( "5c.rom", 0xc000, 0x4000, CRC(6cae25dc) SHA1(de74317a7d5de1865d096c377923a764be5e6879) )
629
630 ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* 64k for the second CPU */
631 ROM_LOAD( "2c.rom", 0xe000, 0x2000, CRC(7c09e50a) SHA1(5f004d60bbb7355e008a9cda137b28bc2192b8ef) )
632
633 ROM_REGION( 0x8000, REGION_CPU3, 0 ) /* 32k for the third CPU */
634 ROM_LOAD16_BYTE( "8c.rom", 0x0000, 0x4000, CRC(a00cd959) SHA1(cc5621103c31cfbc65941615cab391db0f74e6ce) )
635 ROM_LOAD16_BYTE("10c.rom", 0x0001, 0x4000, CRC(09ce209b) SHA1(2ed46d6592f8227bac8ab54963d9a300706ade47) )
636
637 /* temporary space for graphics (disposed after conversion) */
638 ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
639 ROM_LOAD( "5p.rom", 0x0000, 0x2000, CRC(3b4937f0) SHA1(06d9de576f1c2262c34aeb91054e68c9298af688) ) /* characters */
640
641 ROM_REGION( 0x4000, REGION_GFX2, ROMREGION_DISPOSE )
642 ROM_LOAD( "9t.rom", 0x0000, 0x4000, CRC(a88e24ca) SHA1(eada133579f19de09255084dcdc386311606a335) ) /* sprites */
643
644 ROM_REGION( 0x0600, REGION_PROMS, 0 ) /* color proms */
645 ROM_LOAD( "lr1-3.1r", 0x0000, 0x0100, CRC(f3ec0d07) SHA1(b0aad1fb6df79f202889600f486853995352f9c2) ) // palette: red component
646 ROM_LOAD( "lr1-2.1s", 0x0100, 0x0100, CRC(2ae4f702) SHA1(838fdca9e91fea4f64a59880ac47c48973bb8fbf) ) // palette: green component
647 ROM_LOAD( "lr1-1.1t", 0x0200, 0x0100, CRC(7601f208) SHA1(572d070ca387b780030ed5de38a8970b7cc14349) ) // palette: blue component
648 ROM_LOAD( "lr1-5.5l", 0x0300, 0x0100, CRC(940f5397) SHA1(825a7bd78a8a08d30bad2e4890ae6e9ad88b36b8) ) /* characters */
649 ROM_LOAD( "lr1-6.2p", 0x0400, 0x0200, CRC(a6b7f850) SHA1(7cfde16dfd5c4d5b876b4fbe4f924f1385932a93) ) /* sprites */
650
651 ROM_REGION( 0x0100, REGION_SOUND1, 0 ) /* sound prom */
652 ROM_LOAD( "lr1-4.3d", 0x0000, 0x0100, CRC(16a9166a) SHA1(847cbaf7c88616576c410177e066ae1d792ac0ba) )
653 ROM_END
654
655 ROM_START( toypop )
656 ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for the first CPU */
657 ROM_LOAD( "tp1-2.5b", 0x8000, 0x4000, CRC(87469620) SHA1(2ee257486c9c044386ac7d0cd4a90583eaeb3e97) )
658 ROM_LOAD( "tp1-1.5c", 0xc000, 0x4000, CRC(dee2fd6e) SHA1(b2c12008d6d3e7544ba3c12a52a6abf9181842c8) )
659
660 ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* 64k for the second CPU */
661 ROM_LOAD( "tp1-3.2c", 0xe000, 0x2000, CRC(5f3bf6e2) SHA1(d1b3335661b9b23cb10001416c515b77b5e783e9) )
662
663 ROM_REGION( 0x8000, REGION_CPU3, 0 ) /* 32k for the third CPU */
664 ROM_LOAD16_BYTE( "tp1-4.8c", 0x0000, 0x4000, CRC(76997db3) SHA1(5023a2f20a5f2c9baff130f6832583493c71f883) )
665 ROM_LOAD16_BYTE("tp1-5.10c", 0x0001, 0x4000, CRC(37de8786) SHA1(710365e34c05d01815844c414518f93234b6160b) )
666
667 /* temporary space for graphics (disposed after conversion) */
668 ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
669 ROM_LOAD( "tp1-7.5p", 0x0000, 0x2000, CRC(95076f9e) SHA1(1e3d32b21f6d46591ec3921aba51f672d64a9023) ) /* characters */
670
671 ROM_REGION( 0x4000, REGION_GFX2, ROMREGION_DISPOSE )
672 ROM_LOAD( "tp1-6.9t", 0x0000, 0x4000, CRC(481ffeaf) SHA1(c51735ad3a1dbb46ad414408b54554e9223b2219) ) /* sprites */
673
674 ROM_REGION( 0x0600, REGION_PROMS, 0 ) /* color proms */
675 ROM_LOAD( "tp1-3.1r", 0x0000, 0x0100, CRC(cfce2fa5) SHA1(b42aa0f34d885389d2650bf7a0531b95703b8a28) ) // palette: red component
676 ROM_LOAD( "tp1-2.1s", 0x0100, 0x0100, CRC(aeaf039d) SHA1(574560526100d38635aecd71eb73499c4f57d586) ) // palette: green component
677 ROM_LOAD( "tp1-1.1t", 0x0200, 0x0100, CRC(08e7cde3) SHA1(5261aca6834d635d17f8afaa8e35848930030ba4) ) // palette: blue component
678 ROM_LOAD( "tp1-4.5l", 0x0300, 0x0100, CRC(74138973) SHA1(2e21dbb1b19dd089da52e70fcb0ca91336e004e6) ) /* characters */
679 ROM_LOAD( "tp1-5.2p", 0x0400, 0x0200, CRC(4d77fa5a) SHA1(2438910314b23ecafb553230244f3931861ad2da) ) /* sprites */
680
681 ROM_REGION( 0x0100, REGION_SOUND1, 0 ) /* sound prom */
682 ROM_LOAD( "lr1-4.3d", 0x0000, 0x0100, CRC(16a9166a) SHA1(847cbaf7c88616576c410177e066ae1d792ac0ba) )
683 ROM_END
684
685
686
687 GAME( 1983, liblrabl, 0, liblrabl, liblrabl, 58_56_56, ROT0, "Namco", "Libble Rabble" )
688 GAME( 1986, toypop, 0, toypop, toypop, 58c_56_56, ROT0, "Namco", "Toypop" )
689