1 /*
2 **
3 ** File: ymf262.c - software implementation of YMF262
4 ** FM sound generator type OPL3
5 **
6 ** Copyright (C) 2003 Jarek Burczynski
7 **
8 ** Version 0.2
9 **
10
11 Revision History:
12
13 03-03-2003: initial release
14 - thanks to Olivier Galibert and Chris Hardy for YMF262 and YAC512 chips
15 - thanks to Stiletto for the datasheets
16
17
18
19 differences between OPL2 and OPL3 not documented in Yamaha datahasheets:
20 - sinus table is a little different: the negative part is off by one...
21
22 - in order to enable selection of four different waveforms on OPL2
23 one must set bit 5 in register 0x01(test).
24 on OPL3 this bit is ignored and 4-waveform select works *always*.
25 (Don't confuse this with OPL3's 8-waveform select.)
26
27 - Envelope Generator: all 15 x rates take zero time on OPL3
28 (on OPL2 15 0 and 15 1 rates take some time while 15 2 and 15 3 rates
29 take zero time)
30
31 - channel calculations: output of operator 1 is in perfect sync with
32 output of operator 2 on OPL3; on OPL and OPL2 output of operator 1
33 is always delayed by one sample compared to output of operator 2
34
35
36 differences between OPL2 and OPL3 shown in datasheets:
37 - YMF262 does not support CSM mode
38
39
40 */
41
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <math.h>
45
46 #include "driver.h" /* use M.A.M.E. */
47 #include "ymf262.h"
48
49 #ifndef PI
50 #define PI 3.14159265358979323846
51 #endif
52
53
54
55 /* output final shift */
56 #if (OPL3_SAMPLE_BITS==16)
57 #define FINAL_SH (0)
58 #define MAXOUT (+32767)
59 #define MINOUT (-32768)
60 #else
61 #define FINAL_SH (8)
62 #define MAXOUT (+127)
63 #define MINOUT (-128)
64 #endif
65
66
67 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
68 #define EG_SH 16 /* 16.16 fixed point (EG timing) */
69 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
70 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
71
72 #define FREQ_MASK ((1<<FREQ_SH)-1)
73
74 /* envelope output entries */
75 #define ENV_BITS 10
76 #define ENV_LEN (1<<ENV_BITS)
77 #define ENV_STEP (128.0/ENV_LEN)
78
79 #define MAX_ATT_INDEX ((1<<(ENV_BITS-1))-1) /*511*/
80 #define MIN_ATT_INDEX (0)
81
82 /* sinwave entries */
83 #define SIN_BITS 10
84 #define SIN_LEN (1<<SIN_BITS)
85 #define SIN_MASK (SIN_LEN-1)
86
87 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
88
89
90
91 /* register number to channel number , slot offset */
92 #define SLOT1 0
93 #define SLOT2 1
94
95 /* Envelope Generator phases */
96
97 #define EG_ATT 4
98 #define EG_DEC 3
99 #define EG_SUS 2
100 #define EG_REL 1
101 #define EG_OFF 0
102
103
104 /* save output as raw 16-bit sample */
105
106 /*#define SAVE_SAMPLE*/
107
108 #ifdef SAVE_SAMPLE
109 static FILE *sample[1];
110 #if 1 /*save to MONO file */
111 #define SAVE_ALL_CHANNELS \
112 { signed int pom = a; \
113 fputc((unsigned short)pom&0xff,sample[0]); \
114 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
115 }
116 #else /*save to STEREO file */
117 #define SAVE_ALL_CHANNELS \
118 { signed int pom = a; \
119 fputc((unsigned short)pom&0xff,sample[0]); \
120 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
121 pom = b; \
122 fputc((unsigned short)pom&0xff,sample[0]); \
123 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
124 }
125 #endif
126 #endif
127
128 /*#define LOG_CYM_FILE*/
129 #ifdef LOG_CYM_FILE
130 FILE * cymfile = NULL;
131 #endif
132
133
134
135
136
137 #define OPL3_TYPE_YMF262 (0) /* 36 operators, 8 waveforms */
138
139
140 typedef struct{
141 UINT32 ar; /* attack rate: AR<<2 */
142 UINT32 dr; /* decay rate: DR<<2 */
143 UINT32 rr; /* release rate:RR<<2 */
144 UINT8 KSR; /* key scale rate */
145 UINT8 ksl; /* keyscale level */
146 UINT8 ksr; /* key scale rate: kcode>>KSR */
147 UINT8 mul; /* multiple: mul_tab[ML] */
148
149 /* Phase Generator */
150 UINT32 Cnt; /* frequency counter */
151 UINT32 Incr; /* frequency counter step */
152 UINT8 FB; /* feedback shift value */
153 INT32 *connect; /* slot output pointer */
154 INT32 op1_out[2]; /* slot1 output for feedback */
155 UINT8 CON; /* connection (algorithm) type */
156
157 /* Envelope Generator */
158 UINT8 eg_type; /* percussive/non-percussive mode */
159 UINT8 state; /* phase type */
160 UINT32 TL; /* total level: TL << 2 */
161 INT32 TLL; /* adjusted now TL */
162 INT32 volume; /* envelope counter */
163 UINT32 sl; /* sustain level: sl_tab[SL] */
164
165 UINT32 eg_m_ar; /* (attack state) */
166 UINT8 eg_sh_ar; /* (attack state) */
167 UINT8 eg_sel_ar; /* (attack state) */
168 UINT32 eg_m_dr; /* (decay state) */
169 UINT8 eg_sh_dr; /* (decay state) */
170 UINT8 eg_sel_dr; /* (decay state) */
171 UINT32 eg_m_rr; /* (release state) */
172 UINT8 eg_sh_rr; /* (release state) */
173 UINT8 eg_sel_rr; /* (release state) */
174
175 UINT32 key; /* 0 = KEY OFF, >0 = KEY ON */
176
177 /* LFO */
178 UINT32 AMmask; /* LFO Amplitude Modulation enable mask */
179 UINT8 vib; /* LFO Phase Modulation enable flag (active high)*/
180
181 /* waveform select */
182 UINT8 waveform_number;
183 unsigned int wavetable;
184
185 /*unsigned char reserved[128-84];*/ /*speedup: pump up the struct size to power of 2*/
186 unsigned char reserved[128-100];/*speedup: pump up the struct size to power of 2*/
187
188 } OPL3_SLOT;
189
190 typedef struct{
191 OPL3_SLOT SLOT[2];
192
193 UINT32 block_fnum; /* block+fnum */
194 UINT32 fc; /* Freq. Increment base */
195 UINT32 ksl_base; /* KeyScaleLevel Base step */
196 UINT8 kcode; /* key code (for key scaling) */
197
198 /*
199 there are 12 2-operator channels which can be combined in pairs
200 to form six 4-operator channel, they are:
201 0 and 3,
202 1 and 4,
203 2 and 5,
204 9 and 12,
205 10 and 13,
206 11 and 14
207 */
208 UINT8 extended; /* set to 1 if this channel forms up a 4op channel with another channel(only used by first of pair of channels, ie 0,1,2 and 9,10,11) */
209
210 unsigned char reserved[512-272];/*speedup:pump up the struct size to power of 2*/
211
212 } OPL3_CH;
213
214 /* OPL3 state */
215 typedef struct {
216 OPL3_CH P_CH[18]; /* OPL3 chips have 18 channels */
217
218 UINT32 pan[18*4]; /* channels output masks (0xffffffff = enable); 4 masks per one channel */
219 UINT32 pan_ctrl_value[18]; /* output control values 1 per one channel (1 value contains 4 masks) */
220
221 UINT32 eg_cnt; /* global envelope generator counter */
222 UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/288 (288=8*36) */
223 UINT32 eg_timer_add; /* step of eg_timer */
224 UINT32 eg_timer_overflow; /* envelope generator timer overlfows every 1 sample (on real chip) */
225
226 UINT32 fn_tab[1024]; /* fnumber->increment counter */
227
228 /* LFO */
229 UINT8 lfo_am_depth;
230 UINT8 lfo_pm_depth_range;
231 UINT32 lfo_am_cnt;
232 UINT32 lfo_am_inc;
233 UINT32 lfo_pm_cnt;
234 UINT32 lfo_pm_inc;
235
236 UINT32 noise_rng; /* 23 bit noise shift register */
237 UINT32 noise_p; /* current noise 'phase' */
238 UINT32 noise_f; /* current noise period */
239
240 UINT8 OPL3_mode; /* OPL3 extension enable flag */
241
242 UINT8 rhythm; /* Rhythm mode */
243
244 int T[2]; /* timer counters */
245 UINT8 st[2]; /* timer enable */
246
247 UINT32 address; /* address register */
248 UINT8 status; /* status flag */
249 UINT8 statusmask; /* status mask */
250
251 UINT8 nts; /* NTS (note select) */
252
253 /* external event callback handlers */
254 OPL3_TIMERHANDLER TimerHandler;/* TIMER handler */
255 int TimerParam; /* TIMER parameter */
256 OPL3_IRQHANDLER IRQHandler; /* IRQ handler */
257 int IRQParam; /* IRQ parameter */
258 OPL3_UPDATEHANDLER UpdateHandler;/* stream update handler */
259 int UpdateParam; /* stream update parameter */
260
261 UINT8 type; /* chip type */
262 int clock; /* master clock (Hz) */
263 int rate; /* sampling rate (Hz) */
264 double freqbase; /* frequency base */
265 double TimerBase; /* Timer base time (==sampling time)*/
266 } OPL3;
267
268
269
270 /* mapping of register number (offset) to slot number used by the emulator */
271 static const int slot_array[32]=
272 {
273 0, 2, 4, 1, 3, 5,-1,-1,
274 6, 8,10, 7, 9,11,-1,-1,
275 12,14,16,13,15,17,-1,-1,
276 -1,-1,-1,-1,-1,-1,-1,-1
277 };
278
279 /* key scale level */
280 /* table is 3dB/octave , DV converts this into 6dB/octave */
281 /* 0.1875 is bit 0 weight of the envelope counter (volume) expressed in the 'decibel' scale */
282 #define DV (0.1875/2.0)
283 static const UINT32 ksl_tab[8*16]=
284 {
285 /* OCT 0 */
286 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
287 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
288 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
289 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
290 /* OCT 1 */
291 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
292 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
293 0.000/DV, 0.750/DV, 1.125/DV, 1.500/DV,
294 1.875/DV, 2.250/DV, 2.625/DV, 3.000/DV,
295 /* OCT 2 */
296 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
297 0.000/DV, 1.125/DV, 1.875/DV, 2.625/DV,
298 3.000/DV, 3.750/DV, 4.125/DV, 4.500/DV,
299 4.875/DV, 5.250/DV, 5.625/DV, 6.000/DV,
300 /* OCT 3 */
301 0.000/DV, 0.000/DV, 0.000/DV, 1.875/DV,
302 3.000/DV, 4.125/DV, 4.875/DV, 5.625/DV,
303 6.000/DV, 6.750/DV, 7.125/DV, 7.500/DV,
304 7.875/DV, 8.250/DV, 8.625/DV, 9.000/DV,
305 /* OCT 4 */
306 0.000/DV, 0.000/DV, 3.000/DV, 4.875/DV,
307 6.000/DV, 7.125/DV, 7.875/DV, 8.625/DV,
308 9.000/DV, 9.750/DV,10.125/DV,10.500/DV,
309 10.875/DV,11.250/DV,11.625/DV,12.000/DV,
310 /* OCT 5 */
311 0.000/DV, 3.000/DV, 6.000/DV, 7.875/DV,
312 9.000/DV,10.125/DV,10.875/DV,11.625/DV,
313 12.000/DV,12.750/DV,13.125/DV,13.500/DV,
314 13.875/DV,14.250/DV,14.625/DV,15.000/DV,
315 /* OCT 6 */
316 0.000/DV, 6.000/DV, 9.000/DV,10.875/DV,
317 12.000/DV,13.125/DV,13.875/DV,14.625/DV,
318 15.000/DV,15.750/DV,16.125/DV,16.500/DV,
319 16.875/DV,17.250/DV,17.625/DV,18.000/DV,
320 /* OCT 7 */
321 0.000/DV, 9.000/DV,12.000/DV,13.875/DV,
322 15.000/DV,16.125/DV,16.875/DV,17.625/DV,
323 18.000/DV,18.750/DV,19.125/DV,19.500/DV,
324 19.875/DV,20.250/DV,20.625/DV,21.000/DV
325 };
326 #undef DV
327
328 /* sustain level table (3dB per step) */
329 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
330 #define SC(db) (UINT32) ( db * (2.0/ENV_STEP) )
331 static const UINT32 sl_tab[16]={
332 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
333 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
334 };
335 #undef SC
336
337
338 #define RATE_STEPS (8)
339 static const unsigned char eg_inc[15*RATE_STEPS]={
340
341 /*cycle:0 1 2 3 4 5 6 7*/
342
343 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
344 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
345 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
346 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
347
348 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
349 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
350 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
351 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
352
353 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
354 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
355 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
356 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
357
358 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 for decay */
359 /*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 for attack (zero time) */
360 /*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
361 };
362
363
364 #define O(a) (a*RATE_STEPS)
365
366 /* note that there is no O(13) in this table - it's directly in the code */
367 static const unsigned char eg_rate_select[16+64+16]={ /* Envelope Generator rates (16 + 64 rates + 16 RKS) */
368 /* 16 infinite time rates */
369 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
370 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
371
372 /* rates 00-12 */
373 O( 0),O( 1),O( 2),O( 3),
374 O( 0),O( 1),O( 2),O( 3),
375 O( 0),O( 1),O( 2),O( 3),
376 O( 0),O( 1),O( 2),O( 3),
377 O( 0),O( 1),O( 2),O( 3),
378 O( 0),O( 1),O( 2),O( 3),
379 O( 0),O( 1),O( 2),O( 3),
380 O( 0),O( 1),O( 2),O( 3),
381 O( 0),O( 1),O( 2),O( 3),
382 O( 0),O( 1),O( 2),O( 3),
383 O( 0),O( 1),O( 2),O( 3),
384 O( 0),O( 1),O( 2),O( 3),
385 O( 0),O( 1),O( 2),O( 3),
386
387 /* rate 13 */
388 O( 4),O( 5),O( 6),O( 7),
389
390 /* rate 14 */
391 O( 8),O( 9),O(10),O(11),
392
393 /* rate 15 */
394 O(12),O(12),O(12),O(12),
395
396 /* 16 dummy rates (same as 15 3) */
397 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
398 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
399
400 };
401 #undef O
402
403 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
404 /*shift 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0 */
405 /*mask 4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0 */
406
407 #define O(a) (a*1)
408 static const unsigned char eg_rate_shift[16+64+16]={ /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */
409 /* 16 infinite time rates */
410 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
411 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
412
413 /* rates 00-12 */
414 O(12),O(12),O(12),O(12),
415 O(11),O(11),O(11),O(11),
416 O(10),O(10),O(10),O(10),
417 O( 9),O( 9),O( 9),O( 9),
418 O( 8),O( 8),O( 8),O( 8),
419 O( 7),O( 7),O( 7),O( 7),
420 O( 6),O( 6),O( 6),O( 6),
421 O( 5),O( 5),O( 5),O( 5),
422 O( 4),O( 4),O( 4),O( 4),
423 O( 3),O( 3),O( 3),O( 3),
424 O( 2),O( 2),O( 2),O( 2),
425 O( 1),O( 1),O( 1),O( 1),
426 O( 0),O( 0),O( 0),O( 0),
427
428 /* rate 13 */
429 O( 0),O( 0),O( 0),O( 0),
430
431 /* rate 14 */
432 O( 0),O( 0),O( 0),O( 0),
433
434 /* rate 15 */
435 O( 0),O( 0),O( 0),O( 0),
436
437 /* 16 dummy rates (same as 15 3) */
438 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
439 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
440
441 };
442 #undef O
443
444
445 /* multiple table */
446 #define ML 2
447 static const UINT8 mul_tab[16]= {
448 /* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,12,12,15,15 */
449 0.50*ML, 1.00*ML, 2.00*ML, 3.00*ML, 4.00*ML, 5.00*ML, 6.00*ML, 7.00*ML,
450 8.00*ML, 9.00*ML,10.00*ML,10.00*ML,12.00*ML,12.00*ML,15.00*ML,15.00*ML
451 };
452 #undef ML
453
454 /* TL_TAB_LEN is calculated as:
455
456 * (12+1)=13 - sinus amplitude bits (Y axis)
457 * additional 1: to compensate for calculations of negative part of waveform
458 * (if we don't add it then the greatest possible _negative_ value would be -2
459 * and we really need -1 for waveform #7)
460 * 2 - sinus sign bit (Y axis)
461 * TL_RES_LEN - sinus resolution (X axis)
462 */
463 #define TL_TAB_LEN (13*2*TL_RES_LEN)
464 static signed int tl_tab[TL_TAB_LEN];
465
466 #define ENV_QUIET (TL_TAB_LEN>>4)
467
468 /* sin waveform table in 'decibel' scale */
469 /* there are eight waveforms on OPL3 chips */
470 static unsigned int sin_tab[SIN_LEN * 8];
471
472
473 /* LFO Amplitude Modulation table (verified on real YM3812)
474 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples
475
476 Length: 210 elements.
477
478 Each of the elements has to be repeated
479 exactly 64 times (on 64 consecutive samples).
480 The whole table takes: 64 * 210 = 13440 samples.
481
482 When AM = 1 data is used directly
483 When AM = 0 data is divided by 4 before being used (loosing precision is important)
484 */
485
486 #define LFO_AM_TAB_ELEMENTS 210
487
488 static const UINT8 lfo_am_table[LFO_AM_TAB_ELEMENTS] = {
489 0,0,0,0,0,0,0,
490 1,1,1,1,
491 2,2,2,2,
492 3,3,3,3,
493 4,4,4,4,
494 5,5,5,5,
495 6,6,6,6,
496 7,7,7,7,
497 8,8,8,8,
498 9,9,9,9,
499 10,10,10,10,
500 11,11,11,11,
501 12,12,12,12,
502 13,13,13,13,
503 14,14,14,14,
504 15,15,15,15,
505 16,16,16,16,
506 17,17,17,17,
507 18,18,18,18,
508 19,19,19,19,
509 20,20,20,20,
510 21,21,21,21,
511 22,22,22,22,
512 23,23,23,23,
513 24,24,24,24,
514 25,25,25,25,
515 26,26,26,
516 25,25,25,25,
517 24,24,24,24,
518 23,23,23,23,
519 22,22,22,22,
520 21,21,21,21,
521 20,20,20,20,
522 19,19,19,19,
523 18,18,18,18,
524 17,17,17,17,
525 16,16,16,16,
526 15,15,15,15,
527 14,14,14,14,
528 13,13,13,13,
529 12,12,12,12,
530 11,11,11,11,
531 10,10,10,10,
532 9,9,9,9,
533 8,8,8,8,
534 7,7,7,7,
535 6,6,6,6,
536 5,5,5,5,
537 4,4,4,4,
538 3,3,3,3,
539 2,2,2,2,
540 1,1,1,1
541 };
542
543 /* LFO Phase Modulation table (verified on real YM3812) */
544 static const INT8 lfo_pm_table[8*8*2] = {
545
546 /* FNUM2/FNUM = 00 0xxxxxxx (0x0000) */
547 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
548 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 1*/
549
550 /* FNUM2/FNUM = 00 1xxxxxxx (0x0080) */
551 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
552 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 1*/
553
554 /* FNUM2/FNUM = 01 0xxxxxxx (0x0100) */
555 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
556 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 1*/
557
558 /* FNUM2/FNUM = 01 1xxxxxxx (0x0180) */
559 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
560 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 1*/
561
562 /* FNUM2/FNUM = 10 0xxxxxxx (0x0200) */
563 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
564 4, 2, 0,-2,-4,-2, 0, 2, /*LFO PM depth = 1*/
565
566 /* FNUM2/FNUM = 10 1xxxxxxx (0x0280) */
567 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
568 5, 2, 0,-2,-5,-2, 0, 2, /*LFO PM depth = 1*/
569
570 /* FNUM2/FNUM = 11 0xxxxxxx (0x0300) */
571 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
572 6, 3, 0,-3,-6,-3, 0, 3, /*LFO PM depth = 1*/
573
574 /* FNUM2/FNUM = 11 1xxxxxxx (0x0380) */
575 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
576 7, 3, 0,-3,-7,-3, 0, 3 /*LFO PM depth = 1*/
577 };
578
579
580 /* lock level of common table */
581 static int num_lock = 0;
582
583 /* work table */
584 static void *cur_chip = NULL; /* current chip point */
585 static OPL3_SLOT *SLOT7_1,*SLOT7_2,*SLOT8_1,*SLOT8_2;
586
587 static signed int phase_modulation; /* phase modulation input (SLOT 2) */
588 static signed int phase_modulation2; /* phase modulation input (SLOT 3 in 4 operator channels) */
589 static signed int chanout[18]; /* 18 channels */
590
591
592 static UINT32 LFO_AM;
593 static INT32 LFO_PM;
594
595 /* status set and IRQ handling */
OPL3_STATUS_SET(OPL3 * chip,int flag)596 static INLINE void OPL3_STATUS_SET(OPL3 *chip,int flag)
597 {
598 /* set status flag masking out disabled IRQs */
599 chip->status |= (flag & chip->statusmask);
600 if(!(chip->status & 0x80))
601 {
602 if(chip->status & 0x7f)
603 { /* IRQ on */
604 chip->status |= 0x80;
605 /* callback user interrupt handler (IRQ is OFF to ON) */
606 if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,1);
607 }
608 }
609 }
610
611 /* status reset and IRQ handling */
OPL3_STATUS_RESET(OPL3 * chip,int flag)612 static INLINE void OPL3_STATUS_RESET(OPL3 *chip,int flag)
613 {
614 /* reset status flag */
615 chip->status &= ~flag;
616 if(chip->status & 0x80)
617 {
618 if (!(chip->status & 0x7f))
619 {
620 chip->status &= 0x7f;
621 /* callback user interrupt handler (IRQ is ON to OFF) */
622 if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,0);
623 }
624 }
625 }
626
627 /* IRQ mask set */
OPL3_STATUSMASK_SET(OPL3 * chip,int flag)628 static INLINE void OPL3_STATUSMASK_SET(OPL3 *chip,int flag)
629 {
630 chip->statusmask = flag;
631 /* IRQ handling check */
632 OPL3_STATUS_SET(chip,0);
633 OPL3_STATUS_RESET(chip,0);
634 }
635
636
637 /* advance LFO to next sample */
advance_lfo(OPL3 * chip)638 static INLINE void advance_lfo(OPL3 *chip)
639 {
640 UINT8 tmp;
641
642 /* LFO */
643 chip->lfo_am_cnt += chip->lfo_am_inc;
644 if (chip->lfo_am_cnt >= (LFO_AM_TAB_ELEMENTS<<LFO_SH) ) /* lfo_am_table is 210 elements long */
645 chip->lfo_am_cnt -= (LFO_AM_TAB_ELEMENTS<<LFO_SH);
646
647 tmp = lfo_am_table[ chip->lfo_am_cnt >> LFO_SH ];
648
649 if (chip->lfo_am_depth)
650 LFO_AM = tmp;
651 else
652 LFO_AM = tmp>>2;
653
654 chip->lfo_pm_cnt += chip->lfo_pm_inc;
655 LFO_PM = ((chip->lfo_pm_cnt>>LFO_SH) & 7) | chip->lfo_pm_depth_range;
656 }
657
658 /* advance to next sample */
advance(OPL3 * chip)659 static INLINE void advance(OPL3 *chip)
660 {
661 OPL3_CH *CH;
662 OPL3_SLOT *op;
663 int i;
664
665 /*profiler_mark(PROFILER_USER3);*/
666 chip->eg_timer += chip->eg_timer_add;
667
668 while (chip->eg_timer >= chip->eg_timer_overflow)
669 {
670 chip->eg_timer -= chip->eg_timer_overflow;
671
672 chip->eg_cnt++;
673
674 for (i=0; i<9*2*2; i++)
675 {
676 CH = &chip->P_CH[i/2];
677 op = &CH->SLOT[i&1];
678 #if 1
679 /* Envelope Generator */
680 switch(op->state)
681 {
682 case EG_ATT: /* attack phase */
683 /* if ( !(chip->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )*/
684 if ( !(chip->eg_cnt & op->eg_m_ar) )
685 {
686 op->volume += (~op->volume *
687 (eg_inc[op->eg_sel_ar + ((chip->eg_cnt>>op->eg_sh_ar)&7)])
688 ) >>3;
689
690 if (op->volume <= MIN_ATT_INDEX)
691 {
692 op->volume = MIN_ATT_INDEX;
693 op->state = EG_DEC;
694 }
695
696 }
697 break;
698
699 case EG_DEC: /* decay phase */
700 /* if ( !(chip->eg_cnt & ((1<<op->eg_sh_dr)-1) ) )*/
701 if ( !(chip->eg_cnt & op->eg_m_dr) )
702 {
703 op->volume += eg_inc[op->eg_sel_dr + ((chip->eg_cnt>>op->eg_sh_dr)&7)];
704
705 if ( op->volume >= op->sl )
706 op->state = EG_SUS;
707
708 }
709 break;
710
711 case EG_SUS: /* sustain phase */
712
713 /* this is important behaviour:
714 one can change percusive/non-percussive modes on the fly and
715 the chip will remain in sustain phase - verified on real YM3812 */
716
717 if(op->eg_type) /* non-percussive mode */
718 {
719 /* do nothing */
720 }
721 else /* percussive mode */
722 {
723 /* during sustain phase chip adds Release Rate (in percussive mode) */
724 /* if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )*/
725 if ( !(chip->eg_cnt & op->eg_m_rr) )
726 {
727 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
728
729 if ( op->volume >= MAX_ATT_INDEX )
730 op->volume = MAX_ATT_INDEX;
731 }
732 /* else do nothing in sustain phase */
733 }
734 break;
735
736 case EG_REL: /* release phase */
737 /* if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )*/
738 if ( !(chip->eg_cnt & op->eg_m_rr) )
739 {
740 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
741
742 if ( op->volume >= MAX_ATT_INDEX )
743 {
744 op->volume = MAX_ATT_INDEX;
745 op->state = EG_OFF;
746 }
747
748 }
749 break;
750
751 default:
752 break;
753 }
754 #endif
755 }
756 }
757 /*profiler_mark(PROFILER_END);*/
758
759 /*profiler_mark(PROFILER_USER4);*/
760 for (i=0; i<9*2*2; i++)
761 {
762 CH = &chip->P_CH[i/2];
763 op = &CH->SLOT[i&1];
764
765 /* Phase Generator */
766 if(op->vib)
767 {
768 UINT8 block;
769 unsigned int block_fnum = CH->block_fnum;
770
771 unsigned int fnum_lfo = (block_fnum&0x0380) >> 7;
772
773 signed int lfo_fn_table_index_offset = lfo_pm_table[LFO_PM + 16*fnum_lfo ];
774
775 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
776 {
777 block_fnum += lfo_fn_table_index_offset;
778 block = (block_fnum&0x1c00) >> 10;
779 op->Cnt += (chip->fn_tab[block_fnum&0x03ff] >> (7-block)) * op->mul;
780 }
781 else /* LFO phase modulation = zero */
782 {
783 op->Cnt += op->Incr;
784 }
785 }
786 else /* LFO phase modulation disabled for this operator */
787 {
788 op->Cnt += op->Incr;
789 }
790 }
791 /*profiler_mark(PROFILER_END);*/
792
793 /* The Noise Generator of the YM3812 is 23-bit shift register.
794 * Period is equal to 2^23-2 samples.
795 * Register works at sampling frequency of the chip, so output
796 * can change on every sample.
797 *
798 * Output of the register and input to the bit 22 is:
799 * bit0 XOR bit14 XOR bit15 XOR bit22
800 *
801 * Simply use bit 22 as the noise output.
802 */
803
804 chip->noise_p += chip->noise_f;
805 i = chip->noise_p >> FREQ_SH; /* number of events (shifts of the shift register) */
806 chip->noise_p &= FREQ_MASK;
807 while (i)
808 {
809 /*
810 UINT32 j;
811 j = ( (chip->noise_rng) ^ (chip->noise_rng>>14) ^ (chip->noise_rng>>15) ^ (chip->noise_rng>>22) ) & 1;
812 chip->noise_rng = (j<<22) | (chip->noise_rng>>1);
813 */
814
815 /*
816 Instead of doing all the logic operations above, we
817 use a trick here (and use bit 0 as the noise output).
818 The difference is only that the noise bit changes one
819 step ahead. This doesn't matter since we don't know
820 what is real state of the noise_rng after the reset.
821 */
822
823 if (chip->noise_rng & 1) chip->noise_rng ^= 0x800302;
824 chip->noise_rng >>= 1;
825
826 i--;
827 }
828 }
829
830
op_calc(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)831 static INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
832 {
833 UINT32 p;
834
835 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + (pm<<16))) >> FREQ_SH ) & SIN_MASK) ];
836
837 if (p >= TL_TAB_LEN)
838 return 0;
839 return tl_tab[p];
840 }
841
op_calc1(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)842 static INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
843 {
844 UINT32 p;
845
846 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + pm))>>FREQ_SH) & SIN_MASK)];
847
848 if (p >= TL_TAB_LEN)
849 return 0;
850 return tl_tab[p];
851 }
852
853
854 #define volume_calc(OP) ((OP)->TLL + ((UINT32)(OP)->volume) + (LFO_AM & (OP)->AMmask))
855
856 /* calculate output of a standard 2 operator channel
857 (or 1st part of a 4-op channel) */
chan_calc(OPL3_CH * CH)858 static INLINE void chan_calc( OPL3_CH *CH )
859 {
860 OPL3_SLOT *SLOT;
861 unsigned int env;
862 signed int out;
863
864 phase_modulation = 0;
865 phase_modulation2= 0;
866
867 /* SLOT 1 */
868 SLOT = &CH->SLOT[SLOT1];
869 env = volume_calc(SLOT);
870 out = SLOT->op1_out[0] + SLOT->op1_out[1];
871 SLOT->op1_out[0] = SLOT->op1_out[1];
872 SLOT->op1_out[1] = 0;
873 if( env < ENV_QUIET )
874 {
875 if (!SLOT->FB)
876 out = 0;
877 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
878 }
879 *SLOT->connect += SLOT->op1_out[1];
880 /*logerror("out0=%5i vol0=%4i ", SLOT->op1_out[1], env );*/
881
882 /* SLOT 2 */
883 SLOT++;
884 env = volume_calc(SLOT);
885 if( env < ENV_QUIET )
886 *SLOT->connect += op_calc(SLOT->Cnt, env, phase_modulation, SLOT->wavetable);
887
888 /*logerror("out1=%5i vol1=%4i\n", op_calc(SLOT->Cnt, env, phase_modulation, SLOT->wavetable), env );*/
889
890 }
891
892 /* calculate output of a 2nd part of 4-op channel */
chan_calc_ext(OPL3_CH * CH)893 static INLINE void chan_calc_ext( OPL3_CH *CH )
894 {
895 OPL3_SLOT *SLOT;
896 unsigned int env;
897
898 phase_modulation = 0;
899
900 /* SLOT 1 */
901 SLOT = &CH->SLOT[SLOT1];
902 env = volume_calc(SLOT);
903 if( env < ENV_QUIET )
904 *SLOT->connect += op_calc(SLOT->Cnt, env, phase_modulation2, SLOT->wavetable );
905
906 /* SLOT 2 */
907 SLOT++;
908 env = volume_calc(SLOT);
909 if( env < ENV_QUIET )
910 *SLOT->connect += op_calc(SLOT->Cnt, env, phase_modulation, SLOT->wavetable);
911
912 }
913
914 /*
915 operators used in the rhythm sounds generation process:
916
917 Envelope Generator:
918
919 channel operator register number Bass High Snare Tom Top
920 / slot number TL ARDR SLRR Wave Drum Hat Drum Tom Cymbal
921 6 / 0 12 50 70 90 f0 +
922 6 / 1 15 53 73 93 f3 +
923 7 / 0 13 51 71 91 f1 +
924 7 / 1 16 54 74 94 f4 +
925 8 / 0 14 52 72 92 f2 +
926 8 / 1 17 55 75 95 f5 +
927
928 Phase Generator:
929
930 channel operator register number Bass High Snare Tom Top
931 / slot number MULTIPLE Drum Hat Drum Tom Cymbal
932 6 / 0 12 30 +
933 6 / 1 15 33 +
934 7 / 0 13 31 + + +
935 7 / 1 16 34 ----- n o t u s e d -----
936 8 / 0 14 32 +
937 8 / 1 17 35 + +
938
939 channel operator register number Bass High Snare Tom Top
940 number number BLK/FNUM2 FNUM Drum Hat Drum Tom Cymbal
941 6 12,15 B6 A6 +
942
943 7 13,16 B7 A7 + + +
944
945 8 14,17 B8 A8 + + +
946
947 */
948
949 /* calculate rhythm */
950
chan_calc_rhythm(OPL3_CH * CH,unsigned int noise)951 static INLINE void chan_calc_rhythm( OPL3_CH *CH, unsigned int noise )
952 {
953 OPL3_SLOT *SLOT;
954 signed int out;
955 unsigned int env;
956
957
958 /* Bass Drum (verified on real YM3812):
959 - depends on the channel 6 'connect' register:
960 when connect = 0 it works the same as in normal (non-rhythm) mode (op1->op2->out)
961 when connect = 1 _only_ operator 2 is present on output (op2->out), operator 1 is ignored
962 - output sample always is multiplied by 2
963 */
964
965 phase_modulation = 0;
966
967 /* SLOT 1 */
968 SLOT = &CH[6].SLOT[SLOT1];
969 env = volume_calc(SLOT);
970
971 out = SLOT->op1_out[0] + SLOT->op1_out[1];
972 SLOT->op1_out[0] = SLOT->op1_out[1];
973
974 if (!SLOT->CON)
975 phase_modulation = SLOT->op1_out[0];
976 /*else ignore output of operator 1*/
977
978 SLOT->op1_out[1] = 0;
979 if( env < ENV_QUIET )
980 {
981 if (!SLOT->FB)
982 out = 0;
983 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
984 }
985
986 /* SLOT 2 */
987 SLOT++;
988 env = volume_calc(SLOT);
989 if( env < ENV_QUIET )
990 chanout[6] += op_calc(SLOT->Cnt, env, phase_modulation, SLOT->wavetable) * 2;
991
992
993 /* Phase generation is based on: */
994 /* HH (13) channel 7->slot 1 combined with channel 8->slot 2 (same combination as TOP CYMBAL but different output phases)*/
995 /* SD (16) channel 7->slot 1*/
996 /* TOM (14) channel 8->slot 1*/
997 /* TOP (17) channel 7->slot 1 combined with channel 8->slot 2 (same combination as HIGH HAT but different output phases)*/
998
999 /* Envelope generation based on: */
1000 /* HH channel 7->slot1*/
1001 /* SD channel 7->slot2*/
1002 /* TOM channel 8->slot1*/
1003 /* TOP channel 8->slot2*/
1004
1005
1006 /* The following formulas can be well optimized.
1007 I leave them in direct form for now (in case I've missed something).
1008 */
1009
1010 /* High Hat (verified on real YM3812) */
1011 env = volume_calc(SLOT7_1);
1012 if( env < ENV_QUIET )
1013 {
1014
1015 /* high hat phase generation:
1016 phase = d0 or 234 (based on frequency only)
1017 phase = 34 or 2d0 (based on noise)
1018 */
1019
1020 /* base frequency derived from operator 1 in channel 7 */
1021 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1022 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1023 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1024
1025 unsigned char res1 = (bit2 ^ bit7) | bit3;
1026
1027 /* when res1 = 0 phase = 0x000 | 0xd0; */
1028 /* when res1 = 1 phase = 0x200 | (0xd0>>2); */
1029 UINT32 phase = res1 ? (0x200|(0xd0>>2)) : 0xd0;
1030
1031 /* enable gate based on frequency of operator 2 in channel 8 */
1032 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1033 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1034
1035 unsigned char res2 = (bit3e ^ bit5e);
1036
1037 /* when res2 = 0 pass the phase from calculation above (res1); */
1038 /* when res2 = 1 phase = 0x200 | (0xd0>>2); */
1039 if (res2)
1040 phase = (0x200|(0xd0>>2));
1041
1042
1043 /* when phase & 0x200 is set and noise=1 then phase = 0x200|0xd0 */
1044 /* when phase & 0x200 is set and noise=0 then phase = 0x200|(0xd0>>2), ie no change */
1045 if (phase&0x200)
1046 {
1047 if (noise)
1048 phase = 0x200|0xd0;
1049 }
1050 else
1051 /* when phase & 0x200 is clear and noise=1 then phase = 0xd0>>2 */
1052 /* when phase & 0x200 is clear and noise=0 then phase = 0xd0, ie no change */
1053 {
1054 if (noise)
1055 phase = 0xd0>>2;
1056 }
1057
1058 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_1->wavetable) * 2;
1059 }
1060
1061 /* Snare Drum (verified on real YM3812) */
1062 env = volume_calc(SLOT7_2);
1063 if( env < ENV_QUIET )
1064 {
1065 /* base frequency derived from operator 1 in channel 7 */
1066 unsigned char bit8 = ((SLOT7_1->Cnt>>FREQ_SH)>>8)&1;
1067
1068 /* when bit8 = 0 phase = 0x100; */
1069 /* when bit8 = 1 phase = 0x200; */
1070 UINT32 phase = bit8 ? 0x200 : 0x100;
1071
1072 /* Noise bit XOR'es phase by 0x100 */
1073 /* when noisebit = 0 pass the phase from calculation above */
1074 /* when noisebit = 1 phase ^= 0x100; */
1075 /* in other words: phase ^= (noisebit<<8); */
1076 if (noise)
1077 phase ^= 0x100;
1078
1079 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_2->wavetable) * 2;
1080 }
1081
1082 /* Tom Tom (verified on real YM3812) */
1083 env = volume_calc(SLOT8_1);
1084 if( env < ENV_QUIET )
1085 chanout[8] += op_calc(SLOT8_1->Cnt, env, 0, SLOT8_1->wavetable) * 2;
1086
1087 /* Top Cymbal (verified on real YM3812) */
1088 env = volume_calc(SLOT8_2);
1089 if( env < ENV_QUIET )
1090 {
1091 /* base frequency derived from operator 1 in channel 7 */
1092 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1093 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1094 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1095
1096 unsigned char res1 = (bit2 ^ bit7) | bit3;
1097
1098 /* when res1 = 0 phase = 0x000 | 0x100; */
1099 /* when res1 = 1 phase = 0x200 | 0x100; */
1100 UINT32 phase = res1 ? 0x300 : 0x100;
1101
1102 /* enable gate based on frequency of operator 2 in channel 8 */
1103 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1104 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1105
1106 unsigned char res2 = (bit3e ^ bit5e);
1107 /* when res2 = 0 pass the phase from calculation above (res1); */
1108 /* when res2 = 1 phase = 0x200 | 0x100; */
1109 if (res2)
1110 phase = 0x300;
1111
1112 chanout[8] += op_calc(phase<<FREQ_SH, env, 0, SLOT8_2->wavetable) * 2;
1113 }
1114
1115 }
1116
1117
1118 /* generic table initialize */
init_tables(void)1119 static int init_tables(void)
1120 {
1121 signed int i,x;
1122 signed int n;
1123 double o,m;
1124
1125
1126 for (x=0; x<TL_RES_LEN; x++)
1127 {
1128 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
1129 m = floor(m);
1130
1131 /* we never reach (1<<16) here due to the (x+1) */
1132 /* result fits within 16 bits at maximum */
1133
1134 n = (int)m; /* 16 bits here */
1135 n >>= 4; /* 12 bits here */
1136 if (n&1) /* round to nearest */
1137 n = (n>>1)+1;
1138 else
1139 n = n>>1;
1140 /* 11 bits here (rounded) */
1141 n <<= 1; /* 12 bits here (as in real chip) */
1142 tl_tab[ x*2 + 0 ] = n;
1143 tl_tab[ x*2 + 1 ] = ~tl_tab[ x*2 + 0 ]; /* this *is* different from OPL2 (verified on real YMF262) */
1144
1145 for (i=1; i<13; i++)
1146 {
1147 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
1148 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = ~tl_tab[ x*2+0 + i*2*TL_RES_LEN ]; /* this *is* different from OPL2 (verified on real YMF262) */
1149 }
1150
1151 log_cb(RETRO_LOG_DEBUG, LOGPRE "tl %04i", x*2);
1152 for (i=0; i<13; i++)
1153 log_cb(RETRO_LOG_DEBUG, LOGPRE ", [%02i] %5i", i*2, tl_tab[ x*2 +0 + i*2*TL_RES_LEN ] ); /* positive */
1154 log_cb(RETRO_LOG_DEBUG, LOGPRE "\n");
1155
1156 log_cb(RETRO_LOG_DEBUG, LOGPRE "tl %04i", x*2);
1157 for (i=0; i<13; i++)
1158 log_cb(RETRO_LOG_DEBUG, LOGPRE ", [%02i] %5i", i*2, tl_tab[ x*2 +1 + i*2*TL_RES_LEN ] ); /* negative */
1159 log_cb(RETRO_LOG_DEBUG, LOGPRE "\n");
1160 }
1161
1162 for (i=0; i<SIN_LEN; i++)
1163 {
1164 /* non-standard sinus */
1165 m = sin( ((i*2)+1) * PI / SIN_LEN ); /* checked against the real chip */
1166
1167 /* we never reach zero here due to ((i*2)+1) */
1168
1169 if (m>0.0)
1170 o = 8*log(1.0/m)/log(2); /* convert to 'decibels' */
1171 else
1172 o = 8*log(-1.0/m)/log(2); /* convert to 'decibels' */
1173
1174 o = o / (ENV_STEP/4);
1175
1176 n = (int)(2.0*o);
1177 if (n&1) /* round to nearest */
1178 n = (n>>1)+1;
1179 else
1180 n = n>>1;
1181
1182 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
1183
1184 /*logerror("YMF262.C: sin [%4i (hex=%03x)]= %4i (tl_tab value=%5i)\n", i, i, sin_tab[i], tl_tab[sin_tab[i]] );*/
1185 }
1186
1187 for (i=0; i<SIN_LEN; i++)
1188 {
1189 /* these 'pictures' represent _two_ cycles */
1190 /* waveform 1: __ __ */
1191 /* / \____/ \____*/
1192 /* output only first half of the sinus waveform (positive one) */
1193
1194 if (i & (1<<(SIN_BITS-1)) )
1195 sin_tab[1*SIN_LEN+i] = TL_TAB_LEN;
1196 else
1197 sin_tab[1*SIN_LEN+i] = sin_tab[i];
1198
1199 /* waveform 2: __ __ __ __ */
1200 /* / \/ \/ \/ \*/
1201 /* abs(sin) */
1202
1203 sin_tab[2*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>1) ];
1204
1205 /* waveform 3: _ _ _ _ */
1206 /* / |_/ |_/ |_/ |_*/
1207 /* abs(output only first quarter of the sinus waveform) */
1208
1209 if (i & (1<<(SIN_BITS-2)) )
1210 sin_tab[3*SIN_LEN+i] = TL_TAB_LEN;
1211 else
1212 sin_tab[3*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>2)];
1213
1214 /* waveform 4: */
1215 /* /\ ____/\ ____*/
1216 /* \/ \/ */
1217 /* output whole sinus waveform in half the cycle(step=2) and output 0 on the other half of cycle */
1218
1219 if (i & (1<<(SIN_BITS-1)) )
1220 sin_tab[4*SIN_LEN+i] = TL_TAB_LEN;
1221 else
1222 sin_tab[4*SIN_LEN+i] = sin_tab[i*2];
1223
1224 /* waveform 5: */
1225 /* /\/\____/\/\____*/
1226 /* */
1227 /* output abs(whole sinus) waveform in half the cycle(step=2) and output 0 on the other half of cycle */
1228
1229 if (i & (1<<(SIN_BITS-1)) )
1230 sin_tab[5*SIN_LEN+i] = TL_TAB_LEN;
1231 else
1232 sin_tab[5*SIN_LEN+i] = sin_tab[(i*2) & (SIN_MASK>>1) ];
1233
1234 /* waveform 6: ____ ____ */
1235 /* */
1236 /* ____ ____*/
1237 /* output maximum in half the cycle and output minimum on the other half of cycle */
1238
1239 if (i & (1<<(SIN_BITS-1)) )
1240 sin_tab[6*SIN_LEN+i] = 1; /* negative */
1241 else
1242 sin_tab[6*SIN_LEN+i] = 0; /* positive */
1243
1244 /* waveform 7: */
1245 /* |\____ |\____ */
1246 /* \| \|*/
1247 /* output sawtooth waveform */
1248
1249 if (i & (1<<(SIN_BITS-1)) )
1250 x = ((SIN_LEN-1)-i)*16 + 1; /* negative: from 8177 to 1 */
1251 else
1252 x = i*16; /*positive: from 0 to 8176 */
1253
1254 if (x > TL_TAB_LEN)
1255 x = TL_TAB_LEN; /* clip to the allowed range */
1256
1257 sin_tab[7*SIN_LEN+i] = x;
1258
1259 /*logerror("YMF262.C: sin1[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[1*SIN_LEN+i], tl_tab[sin_tab[1*SIN_LEN+i]] );*/
1260 /*logerror("YMF262.C: sin2[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[2*SIN_LEN+i], tl_tab[sin_tab[2*SIN_LEN+i]] );*/
1261 /*logerror("YMF262.C: sin3[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[3*SIN_LEN+i], tl_tab[sin_tab[3*SIN_LEN+i]] );*/
1262 /*logerror("YMF262.C: sin4[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[4*SIN_LEN+i], tl_tab[sin_tab[4*SIN_LEN+i]] );*/
1263 /*logerror("YMF262.C: sin5[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[5*SIN_LEN+i], tl_tab[sin_tab[5*SIN_LEN+i]] );*/
1264 /*logerror("YMF262.C: sin6[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[6*SIN_LEN+i], tl_tab[sin_tab[6*SIN_LEN+i]] );*/
1265 /*logerror("YMF262.C: sin7[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[7*SIN_LEN+i], tl_tab[sin_tab[7*SIN_LEN+i]] );*/
1266 }
1267 /*logerror("YMF262.C: ENV_QUIET= %08x (dec*8=%i)\n", ENV_QUIET, ENV_QUIET*8 );*/
1268
1269 #ifdef SAVE_SAMPLE
1270 sample[0]=fopen("sampsum.pcm","wb");
1271 #endif
1272
1273 return 1;
1274 }
1275
OPLCloseTable(void)1276 static void OPLCloseTable( void )
1277 {
1278 #ifdef SAVE_SAMPLE
1279 fclose(sample[0]);
1280 #endif
1281 }
1282
1283
1284
OPL3_initalize(OPL3 * chip)1285 static void OPL3_initalize(OPL3 *chip)
1286 {
1287 int i;
1288
1289 /* frequency base */
1290 chip->freqbase = (chip->rate) ? ((double)chip->clock / (8.0*36)) / chip->rate : 0;
1291 #if 0
1292 chip->rate = (double)chip->clock / (8.0*36);
1293 chip->freqbase = 1.0;
1294 #endif
1295
1296 log_cb(RETRO_LOG_DEBUG, LOGPRE "YMF262: freqbase=%f\n", chip->freqbase);
1297
1298 /* Timer base time */
1299 chip->TimerBase = 1.0 / ((double)chip->clock / (8.0*36) );
1300
1301 /* make fnumber -> increment counter table */
1302 for( i=0 ; i < 1024 ; i++ )
1303 {
1304 /* opn phase increment counter = 20bit */
1305 chip->fn_tab[i] = (UINT32)( (double)i * 64 * chip->freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
1306 #if 0
1307 logerror("YMF262.C: fn_tab[%4i] = %08x (dec=%8i)\n",
1308 i, chip->fn_tab[i]>>6, chip->fn_tab[i]>>6 );
1309 #endif
1310 }
1311
1312 for( i=0 ; i < 16 ; i++ )
1313 {
1314 log_cb(RETRO_LOG_DEBUG, LOGPRE "YMF262.C: sl_tab[%i] = %08x\n", i, sl_tab[i] );
1315 }
1316 for( i=0 ; i < 8 ; i++ )
1317 {
1318 int j;
1319 log_cb(RETRO_LOG_DEBUG, LOGPRE "YMF262.C: ksl_tab[oct=%2i] =",i);
1320 for (j=0; j<16; j++)
1321 {
1322 log_cb(RETRO_LOG_DEBUG, LOGPRE "%08x ", ksl_tab[i*16+j] );
1323 }
1324 log_cb(RETRO_LOG_DEBUG, LOGPRE "\n");
1325 }
1326
1327
1328 /* Amplitude modulation: 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples */
1329 /* One entry from LFO_AM_TABLE lasts for 64 samples */
1330 chip->lfo_am_inc = (1.0 / 64.0 ) * (1<<LFO_SH) * chip->freqbase;
1331
1332 /* Vibrato: 8 output levels (triangle waveform); 1 level takes 1024 samples */
1333 chip->lfo_pm_inc = (1.0 / 1024.0) * (1<<LFO_SH) * chip->freqbase;
1334
1335 /*logerror ("chip->lfo_am_inc = %8x ; chip->lfo_pm_inc = %8x\n", chip->lfo_am_inc, chip->lfo_pm_inc);*/
1336
1337 /* Noise generator: a step takes 1 sample */
1338 chip->noise_f = (1.0 / 1.0) * (1<<FREQ_SH) * chip->freqbase;
1339
1340 chip->eg_timer_add = (1<<EG_SH) * chip->freqbase;
1341 chip->eg_timer_overflow = ( 1 ) * (1<<EG_SH);
1342 /*logerror("YMF262init eg_timer_add=%8x eg_timer_overflow=%8x\n", chip->eg_timer_add, chip->eg_timer_overflow);*/
1343
1344 }
1345
FM_KEYON(OPL3_SLOT * SLOT,UINT32 key_set)1346 static INLINE void FM_KEYON(OPL3_SLOT *SLOT, UINT32 key_set)
1347 {
1348 if( !SLOT->key )
1349 {
1350 /* restart Phase Generator */
1351 SLOT->Cnt = 0;
1352 /* phase -> Attack */
1353 SLOT->state = EG_ATT;
1354 }
1355 SLOT->key |= key_set;
1356 }
1357
FM_KEYOFF(OPL3_SLOT * SLOT,UINT32 key_clr)1358 static INLINE void FM_KEYOFF(OPL3_SLOT *SLOT, UINT32 key_clr)
1359 {
1360 if( SLOT->key )
1361 {
1362 SLOT->key &= key_clr;
1363
1364 if( !SLOT->key )
1365 {
1366 /* phase -> Release */
1367 if (SLOT->state>EG_REL)
1368 SLOT->state = EG_REL;
1369 }
1370 }
1371 }
1372
1373 /* update phase increment counter of operator (also update the EG rates if necessary) */
CALC_FCSLOT(OPL3_CH * CH,OPL3_SLOT * SLOT)1374 static INLINE void CALC_FCSLOT(OPL3_CH *CH,OPL3_SLOT *SLOT)
1375 {
1376 int ksr;
1377
1378 /* (frequency) phase increment counter */
1379 SLOT->Incr = CH->fc * SLOT->mul;
1380 ksr = CH->kcode >> SLOT->KSR;
1381
1382 if( SLOT->ksr != ksr )
1383 {
1384 SLOT->ksr = ksr;
1385
1386 /* calculate envelope generator rates */
1387 if ((SLOT->ar + SLOT->ksr) < 16+60)
1388 {
1389 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1390 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1391 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1392 }
1393 else
1394 {
1395 SLOT->eg_sh_ar = 0;
1396 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1397 SLOT->eg_sel_ar = 13*RATE_STEPS;
1398 }
1399 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1400 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1;
1401 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1402 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1403 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1;
1404 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1405 }
1406 }
1407
1408 /* set multi,am,vib,EG-TYP,KSR,mul */
set_mul(OPL3 * chip,int slot,int v)1409 static INLINE void set_mul(OPL3 *chip,int slot,int v)
1410 {
1411 OPL3_CH *CH = &chip->P_CH[slot/2];
1412 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1413
1414 SLOT->mul = mul_tab[v&0x0f];
1415 SLOT->KSR = (v&0x10) ? 0 : 2;
1416 SLOT->eg_type = (v&0x20);
1417 SLOT->vib = (v&0x40);
1418 SLOT->AMmask = (v&0x80) ? ~0 : 0;
1419
1420 if (chip->OPL3_mode & 1)
1421 {
1422 int chan_no = slot/2;
1423
1424 /* in OPL3 mode */
1425 /*DO THIS:*/
1426 /*if this is one of the slots of 1st channel forming up a 4-op channel*/
1427 /*do normal operation*/
1428 /*else normal 2 operator function*/
1429 /*OR THIS:*/
1430 /*if this is one of the slots of 2nd channel forming up a 4-op channel*/
1431 /*update it using channel data of 1st channel of a pair*/
1432 /*else normal 2 operator function*/
1433 switch(chan_no)
1434 {
1435 case 0: case 1: case 2:
1436 case 9: case 10: case 11:
1437 if (CH->extended)
1438 {
1439 /* normal */
1440 CALC_FCSLOT(CH,SLOT);
1441 }
1442 else
1443 {
1444 /* normal */
1445 CALC_FCSLOT(CH,SLOT);
1446 }
1447 break;
1448 case 3: case 4: case 5:
1449 case 12: case 13: case 14:
1450 if ((CH-3)->extended)
1451 {
1452 /* update this SLOT using frequency data for 1st channel of a pair */
1453 CALC_FCSLOT(CH-3,SLOT);
1454 }
1455 else
1456 {
1457 /* normal */
1458 CALC_FCSLOT(CH,SLOT);
1459 }
1460 break;
1461 default:
1462 /* normal */
1463 CALC_FCSLOT(CH,SLOT);
1464 break;
1465 }
1466 }
1467 else
1468 {
1469 /* in OPL2 mode */
1470 CALC_FCSLOT(CH,SLOT);
1471 }
1472 }
1473
1474 /* set ksl & tl */
set_ksl_tl(OPL3 * chip,int slot,int v)1475 static INLINE void set_ksl_tl(OPL3 *chip,int slot,int v)
1476 {
1477 OPL3_CH *CH = &chip->P_CH[slot/2];
1478 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1479
1480 int ksl = v>>6; /* 0 / 1.5 / 3.0 / 6.0 dB/OCT */
1481
1482 SLOT->ksl = ksl ? 3-ksl : 31;
1483 SLOT->TL = (v&0x3f)<<(ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */
1484
1485 if (chip->OPL3_mode & 1)
1486 {
1487 int chan_no = slot/2;
1488
1489 /* in OPL3 mode */
1490 /*DO THIS:*/
1491 /*if this is one of the slots of 1st channel forming up a 4-op channel*/
1492 /*do normal operation*/
1493 /*else normal 2 operator function*/
1494 /*OR THIS:*/
1495 /*if this is one of the slots of 2nd channel forming up a 4-op channel*/
1496 /*update it using channel data of 1st channel of a pair*/
1497 /*else normal 2 operator function*/
1498 switch(chan_no)
1499 {
1500 case 0: case 1: case 2:
1501 case 9: case 10: case 11:
1502 if (CH->extended)
1503 {
1504 /* normal */
1505 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1506 }
1507 else
1508 {
1509 /* normal */
1510 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1511 }
1512 break;
1513 case 3: case 4: case 5:
1514 case 12: case 13: case 14:
1515 if ((CH-3)->extended)
1516 {
1517 /* update this SLOT using frequency data for 1st channel of a pair */
1518 SLOT->TLL = SLOT->TL + ((CH-3)->ksl_base>>SLOT->ksl);
1519 }
1520 else
1521 {
1522 /* normal */
1523 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1524 }
1525 break;
1526 default:
1527 /* normal */
1528 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1529 break;
1530 }
1531 }
1532 else
1533 {
1534 /* in OPL2 mode */
1535 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1536 }
1537
1538 }
1539
1540 /* set attack rate & decay rate */
set_ar_dr(OPL3 * chip,int slot,int v)1541 static INLINE void set_ar_dr(OPL3 *chip,int slot,int v)
1542 {
1543 OPL3_CH *CH = &chip->P_CH[slot/2];
1544 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1545
1546 SLOT->ar = (v>>4) ? 16 + ((v>>4) <<2) : 0;
1547
1548 if ((SLOT->ar + SLOT->ksr) < 16+60) /* verified on real YMF262 - all 15 x rates take "zero" time */
1549 {
1550 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1551 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1552 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1553 }
1554 else
1555 {
1556 SLOT->eg_sh_ar = 0;
1557 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1558 SLOT->eg_sel_ar = 13*RATE_STEPS;
1559 }
1560
1561 SLOT->dr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1562 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1563 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1;
1564 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1565 }
1566
1567 /* set sustain level & release rate */
set_sl_rr(OPL3 * chip,int slot,int v)1568 static INLINE void set_sl_rr(OPL3 *chip,int slot,int v)
1569 {
1570 OPL3_CH *CH = &chip->P_CH[slot/2];
1571 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1572
1573 SLOT->sl = sl_tab[ v>>4 ];
1574
1575 SLOT->rr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1576 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1577 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1;
1578 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1579 }
1580
1581
update_channels(OPL3 * chip,OPL3_CH * CH)1582 static void update_channels(OPL3 *chip, OPL3_CH *CH)
1583 {
1584 /* update channel passed as a parameter and a channel at CH+=3; */
1585 if (CH->extended)
1586 { /* we've just switched to combined 4 operator mode */
1587
1588 }
1589 else
1590 { /* we've just switched to normal 2 operator mode */
1591
1592 }
1593
1594 }
1595
1596 /* write a value v to register r on OPL chip */
OPL3WriteReg(OPL3 * chip,int r,int v)1597 static void OPL3WriteReg(OPL3 *chip, int r, int v)
1598 {
1599 OPL3_CH *CH;
1600 unsigned int ch_offset = 0;
1601 int slot;
1602 int block_fnum;
1603
1604
1605
1606 #ifdef LOG_CYM_FILE
1607 if ((cymfile) && ((r&255)!=0) && (r!=255) )
1608 {
1609 if (r>0xff)
1610 fputc( (unsigned char)0xff, cymfile );/*mark writes to second register set*/
1611
1612 fputc( (unsigned char)r&0xff, cymfile );
1613 fputc( (unsigned char)v, cymfile );
1614 }
1615 #endif
1616
1617 if(r&0x100)
1618 {
1619 switch(r)
1620 {
1621 case 0x101: /* test register */
1622 return;
1623 break;
1624 case 0x104: /* 6 channels enable */
1625 {
1626 UINT8 prev;
1627
1628 CH = &chip->P_CH[0]; /* channel 0 */
1629 prev = CH->extended;
1630 CH->extended = (v>>0) & 1;
1631 if(prev != CH->extended)
1632 update_channels(chip, CH);
1633 CH++; /* channel 1 */
1634 prev = CH->extended;
1635 CH->extended = (v>>1) & 1;
1636 if(prev != CH->extended)
1637 update_channels(chip, CH);
1638 CH++; /* channel 2 */
1639 prev = CH->extended;
1640 CH->extended = (v>>2) & 1;
1641 if(prev != CH->extended)
1642 update_channels(chip, CH);
1643
1644
1645 CH = &chip->P_CH[9]; /* channel 9 */
1646 prev = CH->extended;
1647 CH->extended = (v>>3) & 1;
1648 if(prev != CH->extended)
1649 update_channels(chip, CH);
1650 CH++; /* channel 10 */
1651 prev = CH->extended;
1652 CH->extended = (v>>4) & 1;
1653 if(prev != CH->extended)
1654 update_channels(chip, CH);
1655 CH++; /* channel 11 */
1656 prev = CH->extended;
1657 CH->extended = (v>>5) & 1;
1658 if(prev != CH->extended)
1659 update_channels(chip, CH);
1660
1661 }
1662 return;
1663 break;
1664 case 0x105: /* OPL3 extensions enable register */
1665
1666 chip->OPL3_mode = v&0x01; /* OPL3 mode when bit0=1 otherwise it is OPL2 mode */
1667
1668 /* following behaviour was tested on real YMF262,
1669 switching OPL3/OPL2 modes on the fly:
1670 - does not change the waveform previously selected (unless when ....)
1671 - does not update CH.A, CH.B, CH.C and CH.D output selectors (registers c0-c8) (unless when ....)
1672 - does not disable channels 9-17 on OPL3->OPL2 switch
1673 - does not switch 4 operator channels back to 2 operator channels
1674 */
1675
1676 return;
1677 break;
1678
1679 default:
1680 if (r < 0x120)
1681 log_cb(RETRO_LOG_DEBUG, LOGPRE "YMF262: write to unknown register (set#2): %03x value=%02x\n",r,v);
1682 break;
1683 }
1684
1685 ch_offset = 9; /* register page #2 starts from channel 9 (counting from 0) */
1686 }
1687
1688 /* adjust bus to 8 bits */
1689 r &= 0xff;
1690 v &= 0xff;
1691
1692
1693 switch(r&0xe0)
1694 {
1695 case 0x00: /* 00-1f:control */
1696 switch(r&0x1f)
1697 {
1698 case 0x01: /* test register */
1699 break;
1700 case 0x02: /* Timer 1 */
1701 chip->T[0] = (256-v)*4;
1702 break;
1703 case 0x03: /* Timer 2 */
1704 chip->T[1] = (256-v)*16;
1705 break;
1706 case 0x04: /* IRQ clear / mask and Timer enable */
1707 if(v&0x80)
1708 { /* IRQ flags clear */
1709 OPL3_STATUS_RESET(chip,0x60);
1710 }
1711 else
1712 { /* set IRQ mask ,timer enable */
1713 UINT8 st1 = v & 1;
1714 UINT8 st2 = (v>>1) & 1;
1715
1716 /* IRQRST,T1MSK,t2MSK,x,x,x,ST2,ST1 */
1717 OPL3_STATUS_RESET(chip, v & 0x60);
1718 OPL3_STATUSMASK_SET(chip, (~v) & 0x60 );
1719
1720 /* timer 2 */
1721 if(chip->st[1] != st2)
1722 {
1723 double interval = st2 ? (double)chip->T[1]*chip->TimerBase : 0.0;
1724 chip->st[1] = st2;
1725 if (chip->TimerHandler) (chip->TimerHandler)(chip->TimerParam+1,interval);
1726 }
1727 /* timer 1 */
1728 if(chip->st[0] != st1)
1729 {
1730 double interval = st1 ? (double)chip->T[0]*chip->TimerBase : 0.0;
1731 chip->st[0] = st1;
1732 if (chip->TimerHandler) (chip->TimerHandler)(chip->TimerParam+0,interval);
1733 }
1734 }
1735 break;
1736 case 0x08: /* x,NTS,x,x, x,x,x,x */
1737 chip->nts = v;
1738 break;
1739
1740 default:
1741 log_cb(RETRO_LOG_DEBUG, LOGPRE "YMF262: write to unknown register: %02x value=%02x\n",r,v);
1742 break;
1743 }
1744 break;
1745 case 0x20: /* am ON, vib ON, ksr, eg_type, mul */
1746 slot = slot_array[r&0x1f];
1747 if(slot < 0) return;
1748 set_mul(chip, slot + ch_offset*2, v);
1749 break;
1750 case 0x40:
1751 slot = slot_array[r&0x1f];
1752 if(slot < 0) return;
1753 set_ksl_tl(chip, slot + ch_offset*2, v);
1754 break;
1755 case 0x60:
1756 slot = slot_array[r&0x1f];
1757 if(slot < 0) return;
1758 set_ar_dr(chip, slot + ch_offset*2, v);
1759 break;
1760 case 0x80:
1761 slot = slot_array[r&0x1f];
1762 if(slot < 0) return;
1763 set_sl_rr(chip, slot + ch_offset*2, v);
1764 break;
1765 case 0xa0:
1766 if (r == 0xbd) /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */
1767 {
1768 if (ch_offset != 0) /* 0xbd register is present in set #1 only */
1769 return;
1770
1771 chip->lfo_am_depth = v & 0x80;
1772 chip->lfo_pm_depth_range = (v&0x40) ? 8 : 0;
1773
1774 chip->rhythm = v&0x3f;
1775
1776 if(chip->rhythm&0x20)
1777 {
1778 /* BD key on/off */
1779 if(v&0x10)
1780 {
1781 FM_KEYON (&chip->P_CH[6].SLOT[SLOT1], 2);
1782 FM_KEYON (&chip->P_CH[6].SLOT[SLOT2], 2);
1783 }
1784 else
1785 {
1786 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
1787 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
1788 }
1789 /* HH key on/off */
1790 if(v&0x01) FM_KEYON (&chip->P_CH[7].SLOT[SLOT1], 2);
1791 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
1792 /* SD key on/off */
1793 if(v&0x08) FM_KEYON (&chip->P_CH[7].SLOT[SLOT2], 2);
1794 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
1795 /* TOM key on/off */
1796 if(v&0x04) FM_KEYON (&chip->P_CH[8].SLOT[SLOT1], 2);
1797 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
1798 /* TOP-CY key on/off */
1799 if(v&0x02) FM_KEYON (&chip->P_CH[8].SLOT[SLOT2], 2);
1800 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
1801 }
1802 else
1803 {
1804 /* BD key off */
1805 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
1806 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
1807 /* HH key off */
1808 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
1809 /* SD key off */
1810 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
1811 /* TOM key off */
1812 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
1813 /* TOP-CY off */
1814 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
1815 }
1816 return;
1817 }
1818
1819 /* keyon,block,fnum */
1820 if( (r&0x0f) > 8) return;
1821 CH = &chip->P_CH[(r&0x0f) + ch_offset];
1822
1823 if(!(r&0x10))
1824 { /* a0-a8 */
1825 block_fnum = (CH->block_fnum&0x1f00) | v;
1826 }
1827 else
1828 { /* b0-b8 */
1829 block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff);
1830
1831 if (chip->OPL3_mode & 1)
1832 {
1833 int chan_no = (r&0x0f) + ch_offset;
1834
1835 /* in OPL3 mode */
1836 /*DO THIS:*/
1837 /*if this is 1st channel forming up a 4-op channel*/
1838 /*ALSO keyon/off slots of 2nd channel forming up 4-op channel*/
1839 /*else normal 2 operator function keyon/off*/
1840 /*OR THIS:*/
1841 /*if this is 2nd channel forming up 4-op channel just do nothing*/
1842 /*else normal 2 operator function keyon/off*/
1843 switch(chan_no)
1844 {
1845 case 0: case 1: case 2:
1846 case 9: case 10: case 11:
1847 if (CH->extended)
1848 {
1849 /*if this is 1st channel forming up a 4-op channel*/
1850 /*ALSO keyon/off slots of 2nd channel forming up 4-op channel*/
1851 if(v&0x20)
1852 {
1853 FM_KEYON (&CH->SLOT[SLOT1], 1);
1854 FM_KEYON (&CH->SLOT[SLOT2], 1);
1855 FM_KEYON (&(CH+3)->SLOT[SLOT1], 1);
1856 FM_KEYON (&(CH+3)->SLOT[SLOT2], 1);
1857 }
1858 else
1859 {
1860 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1861 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1862 FM_KEYOFF(&(CH+3)->SLOT[SLOT1],~1);
1863 FM_KEYOFF(&(CH+3)->SLOT[SLOT2],~1);
1864 }
1865 }
1866 else
1867 {
1868 /*else normal 2 operator function keyon/off*/
1869 if(v&0x20)
1870 {
1871 FM_KEYON (&CH->SLOT[SLOT1], 1);
1872 FM_KEYON (&CH->SLOT[SLOT2], 1);
1873 }
1874 else
1875 {
1876 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1877 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1878 }
1879 }
1880 break;
1881
1882 case 3: case 4: case 5:
1883 case 12: case 13: case 14:
1884 if ((CH-3)->extended)
1885 {
1886 /*if this is 2nd channel forming up 4-op channel just do nothing*/
1887 }
1888 else
1889 {
1890 /*else normal 2 operator function keyon/off*/
1891 if(v&0x20)
1892 {
1893 FM_KEYON (&CH->SLOT[SLOT1], 1);
1894 FM_KEYON (&CH->SLOT[SLOT2], 1);
1895 }
1896 else
1897 {
1898 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1899 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1900 }
1901 }
1902 break;
1903
1904 default:
1905 if(v&0x20)
1906 {
1907 FM_KEYON (&CH->SLOT[SLOT1], 1);
1908 FM_KEYON (&CH->SLOT[SLOT2], 1);
1909 }
1910 else
1911 {
1912 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1913 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1914 }
1915 break;
1916 }
1917 }
1918 else
1919 {
1920 if(v&0x20)
1921 {
1922 FM_KEYON (&CH->SLOT[SLOT1], 1);
1923 FM_KEYON (&CH->SLOT[SLOT2], 1);
1924 }
1925 else
1926 {
1927 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1928 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1929 }
1930 }
1931 }
1932 /* update */
1933 if(CH->block_fnum != block_fnum)
1934 {
1935 UINT8 block = block_fnum >> 10;
1936
1937 CH->block_fnum = block_fnum;
1938
1939 CH->ksl_base = ksl_tab[block_fnum>>6];
1940 CH->fc = chip->fn_tab[block_fnum&0x03ff] >> (7-block);
1941
1942 /* BLK 2,1,0 bits -> bits 3,2,1 of kcode */
1943 CH->kcode = (CH->block_fnum&0x1c00)>>9;
1944
1945 /* the info below is actually opposite to what is stated in the Manuals (verifed on real YMF262) */
1946 /* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum */
1947 /* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */
1948 if (chip->nts&0x40)
1949 CH->kcode |= (CH->block_fnum&0x100)>>8; /* notesel == 1 */
1950 else
1951 CH->kcode |= (CH->block_fnum&0x200)>>9; /* notesel == 0 */
1952
1953 if (chip->OPL3_mode & 1)
1954 {
1955 int chan_no = (r&0x0f) + ch_offset;
1956 /* in OPL3 mode */
1957 /*DO THIS:*/
1958 /*if this is 1st channel forming up a 4-op channel*/
1959 /*ALSO update slots of 2nd channel forming up 4-op channel*/
1960 /*else normal 2 operator function keyon/off*/
1961 /*OR THIS:*/
1962 /*if this is 2nd channel forming up 4-op channel just do nothing*/
1963 /*else normal 2 operator function keyon/off*/
1964 switch(chan_no)
1965 {
1966 case 0: case 1: case 2:
1967 case 9: case 10: case 11:
1968 if (CH->extended)
1969 {
1970 /*if this is 1st channel forming up a 4-op channel*/
1971 /*ALSO update slots of 2nd channel forming up 4-op channel*/
1972
1973 /* refresh Total Level in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
1974 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
1975 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
1976 (CH+3)->SLOT[SLOT1].TLL = (CH+3)->SLOT[SLOT1].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT1].ksl);
1977 (CH+3)->SLOT[SLOT2].TLL = (CH+3)->SLOT[SLOT2].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT2].ksl);
1978
1979 /* refresh frequency counter in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
1980 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
1981 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
1982 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT1]);
1983 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT2]);
1984 }
1985 else
1986 {
1987 /*else normal 2 operator function*/
1988 /* refresh Total Level in both SLOTs of this channel */
1989 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
1990 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
1991
1992 /* refresh frequency counter in both SLOTs of this channel */
1993 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
1994 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
1995 }
1996 break;
1997
1998 case 3: case 4: case 5:
1999 case 12: case 13: case 14:
2000 if ((CH-3)->extended)
2001 {
2002 /*if this is 2nd channel forming up 4-op channel just do nothing*/
2003 }
2004 else
2005 {
2006 /*else normal 2 operator function*/
2007 /* refresh Total Level in both SLOTs of this channel */
2008 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2009 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2010
2011 /* refresh frequency counter in both SLOTs of this channel */
2012 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2013 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2014 }
2015 break;
2016
2017 default:
2018 /* refresh Total Level in both SLOTs of this channel */
2019 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2020 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2021
2022 /* refresh frequency counter in both SLOTs of this channel */
2023 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2024 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2025 break;
2026 }
2027 }
2028 else
2029 {
2030 /* in OPL2 mode */
2031
2032 /* refresh Total Level in both SLOTs of this channel */
2033 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2034 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2035
2036 /* refresh frequency counter in both SLOTs of this channel */
2037 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2038 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2039 }
2040 }
2041 break;
2042
2043 case 0xc0:
2044 /* CH.D, CH.C, CH.B, CH.A, FB(3bits), C */
2045 if( (r&0xf) > 8) return;
2046
2047 CH = &chip->P_CH[(r&0xf) + ch_offset];
2048
2049 if( chip->OPL3_mode & 1 )
2050 {
2051 int base = ((r&0xf) + ch_offset) * 4;
2052
2053 /* OPL3 mode */
2054 chip->pan[ base ] = (v & 0x10) ? ~0 : 0; /* ch.A */
2055 chip->pan[ base +1 ] = (v & 0x20) ? ~0 : 0; /* ch.B */
2056 chip->pan[ base +2 ] = (v & 0x40) ? ~0 : 0; /* ch.C */
2057 chip->pan[ base +3 ] = (v & 0x80) ? ~0 : 0; /* ch.D */
2058 }
2059 else
2060 {
2061 int base = ((r&0xf) + ch_offset) * 4;
2062
2063 /* OPL2 mode - always enabled */
2064 chip->pan[ base ] = ~0; /* ch.A */
2065 chip->pan[ base +1 ] = ~0; /* ch.B */
2066 chip->pan[ base +2 ] = ~0; /* ch.C */
2067 chip->pan[ base +3 ] = ~0; /* ch.D */
2068 }
2069
2070 chip->pan_ctrl_value[ (r&0xf) + ch_offset ] = v; /* store control value for OPL3/OPL2 mode switching on the fly */
2071
2072 CH->SLOT[SLOT1].FB = (v>>1)&7 ? ((v>>1)&7) + 7 : 0;
2073 CH->SLOT[SLOT1].CON = v&1;
2074
2075 if( chip->OPL3_mode & 1 )
2076 {
2077 int chan_no = (r&0x0f) + ch_offset;
2078
2079 switch(chan_no)
2080 {
2081 case 0: case 1: case 2:
2082 case 9: case 10: case 11:
2083 if (CH->extended)
2084 {
2085 UINT8 conn = (CH->SLOT[SLOT1].CON<<1) || ((CH+3)->SLOT[SLOT1].CON<<0);
2086 switch(conn)
2087 {
2088 case 0:
2089 /* 1 -> 2 -> 3 -> 4 - out */
2090
2091 CH->SLOT[SLOT1].connect = &phase_modulation;
2092 CH->SLOT[SLOT2].connect = &phase_modulation2;
2093 (CH+3)->SLOT[SLOT1].connect = &phase_modulation;
2094 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2095 break;
2096 case 1:
2097 /* 1 -> 2 -\
2098 3 -> 4 -+- out */
2099
2100 CH->SLOT[SLOT1].connect = &phase_modulation;
2101 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2102 (CH+3)->SLOT[SLOT1].connect = &phase_modulation;
2103 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2104 break;
2105 case 2:
2106 /* 1 -----------\
2107 2 -> 3 -> 4 -+- out */
2108
2109 CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
2110 CH->SLOT[SLOT2].connect = &phase_modulation2;
2111 (CH+3)->SLOT[SLOT1].connect = &phase_modulation;
2112 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2113 break;
2114 case 3:
2115 /* 1 ------\
2116 2 -> 3 -+- out
2117 4 ------/ */
2118 CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
2119 CH->SLOT[SLOT2].connect = &phase_modulation2;
2120 (CH+3)->SLOT[SLOT1].connect = &chanout[ chan_no + 3 ];
2121 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2122 break;
2123 }
2124 }
2125 else
2126 {
2127 /* 2 operators mode */
2128 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &phase_modulation;
2129 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2130 }
2131 break;
2132
2133 case 3: case 4: case 5:
2134 case 12: case 13: case 14:
2135 if ((CH-3)->extended)
2136 {
2137 UINT8 conn = ((CH-3)->SLOT[SLOT1].CON<<1) || (CH->SLOT[SLOT1].CON<<0);
2138 switch(conn)
2139 {
2140 case 0:
2141 /* 1 -> 2 -> 3 -> 4 - out */
2142
2143 (CH-3)->SLOT[SLOT1].connect = &phase_modulation;
2144 (CH-3)->SLOT[SLOT2].connect = &phase_modulation2;
2145 CH->SLOT[SLOT1].connect = &phase_modulation;
2146 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2147 break;
2148 case 1:
2149 /* 1 -> 2 -\
2150 3 -> 4 -+- out */
2151
2152 (CH-3)->SLOT[SLOT1].connect = &phase_modulation;
2153 (CH-3)->SLOT[SLOT2].connect = &chanout[ chan_no - 3 ];
2154 CH->SLOT[SLOT1].connect = &phase_modulation;
2155 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2156 break;
2157 case 2:
2158 /* 1 -----------\
2159 2 -> 3 -> 4 -+- out */
2160
2161 (CH-3)->SLOT[SLOT1].connect = &chanout[ chan_no - 3 ];
2162 (CH-3)->SLOT[SLOT2].connect = &phase_modulation2;
2163 CH->SLOT[SLOT1].connect = &phase_modulation;
2164 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2165 break;
2166 case 3:
2167 /* 1 ------\
2168 2 -> 3 -+- out
2169 4 ------/ */
2170 (CH-3)->SLOT[SLOT1].connect = &chanout[ chan_no - 3 ];
2171 (CH-3)->SLOT[SLOT2].connect = &phase_modulation2;
2172 CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
2173 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2174 break;
2175 }
2176 }
2177 else
2178 {
2179 /* 2 operators mode */
2180 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &phase_modulation;
2181 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2182 }
2183 break;
2184
2185 default:
2186 /* 2 operators mode */
2187 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &phase_modulation;
2188 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2189 break;
2190 }
2191 }
2192 else
2193 {
2194 /* OPL2 mode - always 2 operators mode */
2195 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &phase_modulation;
2196 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2197 }
2198 break;
2199
2200 case 0xe0: /* waveform select */
2201 slot = slot_array[r&0x1f];
2202 if(slot < 0) return;
2203
2204 slot += ch_offset*2;
2205
2206 CH = &chip->P_CH[slot/2];
2207
2208
2209 /* store 3-bit value written regardless of current OPL2 or OPL3 mode... (verified on real YMF262) */
2210 v &= 7;
2211 CH->SLOT[slot&1].waveform_number = v;
2212
2213 /* ... but select only waveforms 0-3 in OPL2 mode */
2214 if( !(chip->OPL3_mode & 1) )
2215 {
2216 v &= 3; /* we're in OPL2 mode */
2217 }
2218 CH->SLOT[slot&1].wavetable = v * SIN_LEN;
2219 break;
2220 }
2221 }
2222
2223 #ifdef LOG_CYM_FILE
cymfile_callback(int n)2224 static void cymfile_callback (int n)
2225 {
2226 if (cymfile)
2227 {
2228 fputc( (unsigned char)0, cymfile );
2229 }
2230 }
2231 #endif
2232
2233 /* lock/unlock for common table */
OPL3_LockTable(void)2234 static int OPL3_LockTable(void)
2235 {
2236 num_lock++;
2237 if(num_lock>1) return 0;
2238
2239 /* first time */
2240
2241 cur_chip = NULL;
2242
2243 if( !init_tables() )
2244 {
2245 num_lock--;
2246 return -1;
2247 }
2248
2249 #ifdef LOG_CYM_FILE
2250 cymfile = fopen("ymf262_.cym","wb");
2251 if (cymfile)
2252 timer_pulse ( TIME_IN_HZ(110), 0, cymfile_callback); /*110 Hz pulse timer*/
2253 else
2254 log_cb(RETRO_LOG_DEBUG, LOGPRE "Could not create ymf262_.cym file\n");
2255 #endif
2256
2257 return 0;
2258 }
2259
OPL3_UnLockTable(void)2260 static void OPL3_UnLockTable(void)
2261 {
2262 if(num_lock) num_lock--;
2263 if(num_lock) return;
2264
2265 /* last time */
2266
2267 cur_chip = NULL;
2268 OPLCloseTable();
2269
2270 #ifdef LOG_CYM_FILE
2271 fclose (cymfile);
2272 cymfile = NULL;
2273 #endif
2274
2275 }
2276
OPL3ResetChip(OPL3 * chip)2277 static void OPL3ResetChip(OPL3 *chip)
2278 {
2279 int c,s;
2280
2281 chip->eg_timer = 0;
2282 chip->eg_cnt = 0;
2283
2284 chip->noise_rng = 1; /* noise shift register */
2285 chip->nts = 0; /* note split */
2286 OPL3_STATUS_RESET(chip,0x60);
2287
2288 /* reset with register write */
2289 OPL3WriteReg(chip,0x01,0); /* test register */
2290 OPL3WriteReg(chip,0x02,0); /* Timer1 */
2291 OPL3WriteReg(chip,0x03,0); /* Timer2 */
2292 OPL3WriteReg(chip,0x04,0); /* IRQ mask clear */
2293
2294
2295 /*FIX IT registers 101, 104 and 105*/
2296
2297
2298 /*FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)*/
2299 for(c = 0xff ; c >= 0x20 ; c-- )
2300 OPL3WriteReg(chip,c,0);
2301 /*FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)*/
2302 for(c = 0x1ff ; c >= 0x120 ; c-- )
2303 OPL3WriteReg(chip,c,0);
2304
2305
2306
2307 /* reset operator parameters */
2308 for( c = 0 ; c < 9*2 ; c++ )
2309 {
2310 OPL3_CH *CH = &chip->P_CH[c];
2311 for(s = 0 ; s < 2 ; s++ )
2312 {
2313 CH->SLOT[s].state = EG_OFF;
2314 CH->SLOT[s].volume = MAX_ATT_INDEX;
2315 }
2316 }
2317 }
2318
2319 /* Create one of virtual YMF262 */
2320 /* 'clock' is chip clock in Hz */
2321 /* 'rate' is sampling rate */
OPL3Create(int type,int clock,int rate)2322 static OPL3 *OPL3Create(int type, int clock, int rate)
2323 {
2324 OPL3 *chip;
2325
2326 if (OPL3_LockTable() ==-1) return NULL;
2327
2328 /* allocate memory block */
2329 chip = (OPL3 *)malloc(sizeof(OPL3));
2330
2331 if (chip==NULL)
2332 return NULL;
2333
2334 /* clear */
2335 memset(chip, 0, sizeof(OPL3));
2336
2337 chip->type = type;
2338 chip->clock = clock;
2339 chip->rate = rate;
2340
2341 /* init global tables */
2342 OPL3_initalize(chip);
2343
2344 /* reset chip */
2345 OPL3ResetChip(chip);
2346 return chip;
2347 }
2348
2349 /* Destroy one of virtual YMF262 */
OPL3Destroy(OPL3 * chip)2350 static void OPL3Destroy(OPL3 *chip)
2351 {
2352 OPL3_UnLockTable();
2353 free(chip);
2354 }
2355
2356
2357 /* Optional handlers */
2358
OPL3SetTimerHandler(OPL3 * chip,OPL3_TIMERHANDLER TimerHandler,int channelOffset)2359 static void OPL3SetTimerHandler(OPL3 *chip,OPL3_TIMERHANDLER TimerHandler,int channelOffset)
2360 {
2361 chip->TimerHandler = TimerHandler;
2362 chip->TimerParam = channelOffset;
2363 }
OPL3SetIRQHandler(OPL3 * chip,OPL3_IRQHANDLER IRQHandler,int param)2364 static void OPL3SetIRQHandler(OPL3 *chip,OPL3_IRQHANDLER IRQHandler,int param)
2365 {
2366 chip->IRQHandler = IRQHandler;
2367 chip->IRQParam = param;
2368 }
OPL3SetUpdateHandler(OPL3 * chip,OPL3_UPDATEHANDLER UpdateHandler,int param)2369 static void OPL3SetUpdateHandler(OPL3 *chip,OPL3_UPDATEHANDLER UpdateHandler,int param)
2370 {
2371 chip->UpdateHandler = UpdateHandler;
2372 chip->UpdateParam = param;
2373 }
2374
2375 /* YMF262 I/O interface */
OPL3Write(OPL3 * chip,int a,int v)2376 static int OPL3Write(OPL3 *chip, int a, int v)
2377 {
2378 /* data bus is 8 bits */
2379 v &= 0xff;
2380
2381 switch(a&3)
2382 {
2383 case 0: /* address port 0 (register set #1) */
2384 chip->address = v;
2385 break;
2386
2387 case 1: /* data port - ignore A1 */
2388 case 3: /* data port - ignore A1 */
2389 if(chip->UpdateHandler) chip->UpdateHandler(chip->UpdateParam,0);
2390 OPL3WriteReg(chip,chip->address,v);
2391 break;
2392
2393 case 2: /* address port 1 (register set #2) */
2394
2395 /* verified on real YMF262:
2396 in OPL3 mode:
2397 address line A1 is stored during *address* write and ignored during *data* write.
2398
2399 in OPL2 mode:
2400 register set#2 writes go to register set#1 (ignoring A1)
2401 verified on registers from set#2: 0x01, 0x04, 0x20-0xef
2402 The only exception is register 0x05.
2403 */
2404 if( chip->OPL3_mode & 1 )
2405 {
2406 /* OPL3 mode */
2407 chip->address = v | 0x100;
2408 }
2409 else
2410 {
2411 /* in OPL2 mode the only accessible in set #2 is register 0x05 */
2412 if( v==5 )
2413 chip->address = v | 0x100;
2414 else
2415 chip->address = v; /* verified range: 0x01, 0x04, 0x20-0xef(set #2 becomes set #1 in opl2 mode) */
2416 }
2417 break;
2418 }
2419
2420 return chip->status>>7;
2421 }
2422
OPL3Read(OPL3 * chip,int a)2423 static unsigned char OPL3Read(OPL3 *chip,int a)
2424 {
2425 if( a==0 )
2426 {
2427 /* status port */
2428 return chip->status;
2429 }
2430
2431 return 0x00; /* verified on real YMF262 */
2432 }
2433
2434
2435
OPL3TimerOver(OPL3 * chip,int c)2436 static int OPL3TimerOver(OPL3 *chip,int c)
2437 {
2438 if( c )
2439 { /* Timer B */
2440 OPL3_STATUS_SET(chip,0x20);
2441 }
2442 else
2443 { /* Timer A */
2444 OPL3_STATUS_SET(chip,0x40);
2445 }
2446 /* reload timer */
2447 if (chip->TimerHandler) (chip->TimerHandler)(chip->TimerParam+c,(double)chip->T[c]*chip->TimerBase);
2448 return chip->status>>7;
2449 }
2450
2451
2452
2453
2454 #if (BUILD_YMF262)
2455
2456 #define MAX_OPL3_CHIPS 2
2457
2458 static OPL3 *YMF262[MAX_OPL3_CHIPS]; /* array of pointers to the YMF262's */
2459 static int YMF262NumChips = 0; /* number of chips */
2460
YMF262Init(int num,int clock,int rate)2461 int YMF262Init(int num, int clock, int rate)
2462 {
2463 int i;
2464
2465 if (YMF262NumChips)
2466 return -1; /* duplicate init. */
2467
2468 YMF262NumChips = num;
2469
2470 for (i = 0;i < YMF262NumChips; i++)
2471 {
2472 /* emulator create */
2473 YMF262[i] = OPL3Create(OPL3_TYPE_YMF262,clock,rate);
2474 if(YMF262[i] == NULL)
2475 {
2476 /* it's really bad - we run out of memeory */
2477 YMF262NumChips = 0;
2478 return -1;
2479 }
2480 }
2481
2482 return 0;
2483 }
2484
YMF262Shutdown(void)2485 void YMF262Shutdown(void)
2486 {
2487 int i;
2488
2489 for (i = 0;i < YMF262NumChips; i++)
2490 {
2491 /* emulator shutdown */
2492 OPL3Destroy(YMF262[i]);
2493 YMF262[i] = NULL;
2494 }
2495 YMF262NumChips = 0;
2496 }
YMF262ResetChip(int which)2497 void YMF262ResetChip(int which)
2498 {
2499 OPL3ResetChip(YMF262[which]);
2500 }
2501
YMF262Write(int which,int a,int v)2502 int YMF262Write(int which, int a, int v)
2503 {
2504 return OPL3Write(YMF262[which], a, v);
2505 }
2506
YMF262Read(int which,int a)2507 unsigned char YMF262Read(int which, int a)
2508 {
2509 /* Note on status register: */
2510
2511 /* YM3526(OPL) and YM3812(OPL2) return bit2 and bit1 in HIGH state */
2512
2513 /* YMF262(OPL3) always returns bit2 and bit1 in LOW state */
2514 /* which can be used to identify the chip */
2515
2516 /* YMF278(OPL4) returns bit2 in LOW and bit1 in HIGH state ??? info from manual - not verified */
2517
2518 return OPL3Read(YMF262[which], a);
2519 }
YMF262TimerOver(int which,int c)2520 int YMF262TimerOver(int which, int c)
2521 {
2522 return OPL3TimerOver(YMF262[which], c);
2523 }
2524
YMF262SetTimerHandler(int which,OPL3_TIMERHANDLER TimerHandler,int channelOffset)2525 void YMF262SetTimerHandler(int which, OPL3_TIMERHANDLER TimerHandler, int channelOffset)
2526 {
2527 OPL3SetTimerHandler(YMF262[which], TimerHandler, channelOffset);
2528 }
YMF262SetIRQHandler(int which,OPL3_IRQHANDLER IRQHandler,int param)2529 void YMF262SetIRQHandler(int which,OPL3_IRQHANDLER IRQHandler,int param)
2530 {
2531 OPL3SetIRQHandler(YMF262[which], IRQHandler, param);
2532 }
YMF262SetUpdateHandler(int which,OPL3_UPDATEHANDLER UpdateHandler,int param)2533 void YMF262SetUpdateHandler(int which,OPL3_UPDATEHANDLER UpdateHandler,int param)
2534 {
2535 OPL3SetUpdateHandler(YMF262[which], UpdateHandler, param);
2536 }
2537
2538
2539 /*
2540 ** Generate samples for one of the YMF262's
2541 **
2542 ** 'which' is the virtual YMF262 number
2543 ** '**buffers' is table of 4 pointers to the buffers: CH.A, CH.B, CH.C and CH.D
2544 ** 'length' is the number of samples that should be generated
2545 */
YMF262UpdateOne(int which,INT16 ** buffers,int length)2546 void YMF262UpdateOne(int which, INT16 **buffers, int length)
2547 {
2548 OPL3 *chip = YMF262[which];
2549 UINT8 rhythm = chip->rhythm&0x20;
2550
2551 OPL3SAMPLE *ch_a = buffers[0];
2552 OPL3SAMPLE *ch_b = buffers[1];
2553 OPL3SAMPLE *ch_c = buffers[2];
2554 OPL3SAMPLE *ch_d = buffers[3];
2555
2556 int i;
2557
2558 if( (void *)chip != cur_chip ){
2559 cur_chip = (void *)chip;
2560 /* rhythm slots */
2561 SLOT7_1 = &chip->P_CH[7].SLOT[SLOT1];
2562 SLOT7_2 = &chip->P_CH[7].SLOT[SLOT2];
2563 SLOT8_1 = &chip->P_CH[8].SLOT[SLOT1];
2564 SLOT8_2 = &chip->P_CH[8].SLOT[SLOT2];
2565 }
2566 for( i=0; i < length ; i++ )
2567 {
2568 int a,b,c,d;
2569
2570
2571 advance_lfo(chip);
2572
2573 /* clear channel outputs */
2574 memset(chanout, 0, sizeof(signed int) * 18);
2575
2576 /*profiler_mark(PROFILER_USER1);*/
2577
2578 #if 1
2579 /* register set #1 */
2580 chan_calc(&chip->P_CH[0]); /* extended 4op ch#0 part 1 or 2op ch#0 */
2581 if (chip->P_CH[0].extended)
2582 chan_calc_ext(&chip->P_CH[3]); /* extended 4op ch#0 part 2 */
2583 else
2584 chan_calc(&chip->P_CH[3]); /* standard 2op ch#3 */
2585
2586
2587 chan_calc(&chip->P_CH[1]); /* extended 4op ch#1 part 1 or 2op ch#1 */
2588 if (chip->P_CH[1].extended)
2589 chan_calc_ext(&chip->P_CH[4]); /* extended 4op ch#1 part 2 */
2590 else
2591 chan_calc(&chip->P_CH[4]); /* standard 2op ch#4 */
2592
2593
2594 chan_calc(&chip->P_CH[2]); /* extended 4op ch#2 part 1 or 2op ch#2 */
2595 if (chip->P_CH[2].extended)
2596 chan_calc_ext(&chip->P_CH[5]); /* extended 4op ch#2 part 2 */
2597 else
2598 chan_calc(&chip->P_CH[5]); /* standard 2op ch#5 */
2599
2600
2601 if(!rhythm)
2602 {
2603 chan_calc(&chip->P_CH[6]);
2604 chan_calc(&chip->P_CH[7]);
2605 chan_calc(&chip->P_CH[8]);
2606 }
2607 else /* Rhythm part */
2608 {
2609 chan_calc_rhythm(&chip->P_CH[0], (chip->noise_rng>>0)&1 );
2610 }
2611
2612 /* register set #2 */
2613 chan_calc(&chip->P_CH[ 9]);
2614 if (chip->P_CH[9].extended)
2615 chan_calc_ext(&chip->P_CH[12]);
2616 else
2617 chan_calc(&chip->P_CH[12]);
2618
2619
2620 chan_calc(&chip->P_CH[10]);
2621 if (chip->P_CH[10].extended)
2622 chan_calc_ext(&chip->P_CH[13]);
2623 else
2624 chan_calc(&chip->P_CH[13]);
2625
2626
2627 chan_calc(&chip->P_CH[11]);
2628 if (chip->P_CH[11].extended)
2629 chan_calc_ext(&chip->P_CH[14]);
2630 else
2631 chan_calc(&chip->P_CH[14]);
2632
2633
2634 /* channels 15,16,17 are fixed 2-operator channels only */
2635 chan_calc(&chip->P_CH[15]);
2636 chan_calc(&chip->P_CH[16]);
2637 chan_calc(&chip->P_CH[17]);
2638 #endif
2639 /*profiler_mark(PROFILER_END);*/
2640
2641
2642
2643 /*profiler_mark(PROFILER_USER2);*/
2644 /* accumulator register set #1 */
2645 a = chanout[0] & chip->pan[0];
2646 b = chanout[0] & chip->pan[1];
2647 c = chanout[0] & chip->pan[2];
2648 d = chanout[0] & chip->pan[3];
2649 #if 1
2650 a += chanout[1] & chip->pan[4];
2651 b += chanout[1] & chip->pan[5];
2652 c += chanout[1] & chip->pan[6];
2653 d += chanout[1] & chip->pan[7];
2654 a += chanout[2] & chip->pan[8];
2655 b += chanout[2] & chip->pan[9];
2656 c += chanout[2] & chip->pan[10];
2657 d += chanout[2] & chip->pan[11];
2658
2659 a += chanout[3] & chip->pan[12];
2660 b += chanout[3] & chip->pan[13];
2661 c += chanout[3] & chip->pan[14];
2662 d += chanout[3] & chip->pan[15];
2663 a += chanout[4] & chip->pan[16];
2664 b += chanout[4] & chip->pan[17];
2665 c += chanout[4] & chip->pan[18];
2666 d += chanout[4] & chip->pan[19];
2667 a += chanout[5] & chip->pan[20];
2668 b += chanout[5] & chip->pan[21];
2669 c += chanout[5] & chip->pan[22];
2670 d += chanout[5] & chip->pan[23];
2671
2672 a += chanout[6] & chip->pan[24];
2673 b += chanout[6] & chip->pan[25];
2674 c += chanout[6] & chip->pan[26];
2675 d += chanout[6] & chip->pan[27];
2676 a += chanout[7] & chip->pan[28];
2677 b += chanout[7] & chip->pan[29];
2678 c += chanout[7] & chip->pan[30];
2679 d += chanout[7] & chip->pan[31];
2680 a += chanout[8] & chip->pan[32];
2681 b += chanout[8] & chip->pan[33];
2682 c += chanout[8] & chip->pan[34];
2683 d += chanout[8] & chip->pan[35];
2684
2685 /* accumulator register set #2 */
2686 a += chanout[9] & chip->pan[36];
2687 b += chanout[9] & chip->pan[37];
2688 c += chanout[9] & chip->pan[38];
2689 d += chanout[9] & chip->pan[39];
2690 a += chanout[10] & chip->pan[40];
2691 b += chanout[10] & chip->pan[41];
2692 c += chanout[10] & chip->pan[42];
2693 d += chanout[10] & chip->pan[43];
2694 a += chanout[11] & chip->pan[44];
2695 b += chanout[11] & chip->pan[45];
2696 c += chanout[11] & chip->pan[46];
2697 d += chanout[11] & chip->pan[47];
2698
2699 a += chanout[12] & chip->pan[48];
2700 b += chanout[12] & chip->pan[49];
2701 c += chanout[12] & chip->pan[50];
2702 d += chanout[12] & chip->pan[51];
2703 a += chanout[13] & chip->pan[52];
2704 b += chanout[13] & chip->pan[53];
2705 c += chanout[13] & chip->pan[54];
2706 d += chanout[13] & chip->pan[55];
2707 a += chanout[14] & chip->pan[56];
2708 b += chanout[14] & chip->pan[57];
2709 c += chanout[14] & chip->pan[58];
2710 d += chanout[14] & chip->pan[59];
2711
2712 a += chanout[15] & chip->pan[60];
2713 b += chanout[15] & chip->pan[61];
2714 c += chanout[15] & chip->pan[62];
2715 d += chanout[15] & chip->pan[63];
2716 a += chanout[16] & chip->pan[64];
2717 b += chanout[16] & chip->pan[65];
2718 c += chanout[16] & chip->pan[66];
2719 d += chanout[16] & chip->pan[67];
2720 a += chanout[17] & chip->pan[68];
2721 b += chanout[17] & chip->pan[69];
2722 c += chanout[17] & chip->pan[70];
2723 d += chanout[17] & chip->pan[71];
2724 #endif
2725 a >>= FINAL_SH;
2726 b >>= FINAL_SH;
2727 c >>= FINAL_SH;
2728 d >>= FINAL_SH;
2729
2730 MAME_CLAMP_SAMPLE(a);
2731 MAME_CLAMP_SAMPLE(b);
2732 MAME_CLAMP_SAMPLE(c);
2733 MAME_CLAMP_SAMPLE(d);
2734
2735 #ifdef SAVE_SAMPLE
2736 if (which==0)
2737 {
2738 SAVE_ALL_CHANNELS
2739 }
2740 #endif
2741
2742 /* store to sound buffer */
2743 ch_a[i] = a;
2744 ch_b[i] = b;
2745 ch_c[i] = c;
2746 ch_d[i] = d;
2747 /*profiler_mark(PROFILER_END);*/
2748
2749 advance(chip);
2750 }
2751
2752 }
2753 #endif /* BUILD_YMF262 */
2754