1; this file was created with wlalink by ville helin <vhelin@iki.fi>.
2; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ld_hl_sp_e_timing.gb".
3
4[labels]
501:47f0 check_asserts_cb
601:4842 check_asserts_cb@check_asserts
701:4864 check_asserts_cb@fail0
801:4870 check_asserts_cb@ok0
901:487a check_asserts_cb@skip0
1001:4885 check_asserts_cb@out0
1101:489c check_asserts_cb@fail1
1201:48a8 check_asserts_cb@ok1
1301:48b2 check_asserts_cb@skip1
1401:48bd check_asserts_cb@out1
1501:48dd check_asserts_cb@fail2
1601:48e9 check_asserts_cb@ok2
1701:48f3 check_asserts_cb@skip2
1801:48fe check_asserts_cb@out2
1901:4915 check_asserts_cb@fail3
2001:4921 check_asserts_cb@ok3
2101:492b check_asserts_cb@skip3
2201:4936 check_asserts_cb@out3
2301:4956 check_asserts_cb@fail4
2401:4962 check_asserts_cb@ok4
2501:496c check_asserts_cb@skip4
2601:4977 check_asserts_cb@out4
2701:498e check_asserts_cb@fail5
2801:499a check_asserts_cb@ok5
2901:49a4 check_asserts_cb@skip5
3001:49af check_asserts_cb@out5
3101:49cf check_asserts_cb@fail6
3201:49db check_asserts_cb@ok6
3301:49e5 check_asserts_cb@skip6
3401:49f0 check_asserts_cb@out6
3501:4a07 check_asserts_cb@fail7
3601:4a13 check_asserts_cb@ok7
3701:4a1d check_asserts_cb@skip7
3801:4a28 check_asserts_cb@out7
3901:4b7b clear_vram
4001:4b3a disable_lcd_safe
4101:4b40 disable_lcd_safe@wait_ly_0
4201:4b8f memcpy
4301:4b98 memset
4401:4b58 print_hex4
4501:4b85 print_hex8
4601:4ba8 print_inline_string
4701:4b64 print_load_font
4801:4b70 print_newline
4901:4a2b print_reg_dump
5001:4ba1 print_string
5101:4ab0 quit
5201:4ac5 quit@cb_return
5301:4aca quit@wait_ly_1
5401:4ad0 quit@wait_ly_2
5501:4ad6 quit@wait_ly_3
5601:4adc quit@wait_ly_4
5701:4ae6 quit@success
5801:4b0d quit@failure
5901:4b22 quit@halt
6001:4b23 quit@halt_execution_0
6101:4b26 reset_screen
6201:4b49 serial_send_byte
6301:4000 font
6400:ff80 v_regs_save
6500:ff80 v_regs_save.reg_f
6600:ff81 v_regs_save.reg_a
6700:ff82 v_regs_save.reg_c
6800:ff83 v_regs_save.reg_b
6900:ff84 v_regs_save.reg_e
7000:ff85 v_regs_save.reg_d
7100:ff86 v_regs_save.reg_l
7200:ff87 v_regs_save.reg_h
7300:ff88 v_regs_flags
7400:ff89 v_regs_assert
7500:ff89 v_regs_assert.reg_f
7600:ff8a v_regs_assert.reg_a
7700:ff8b v_regs_assert.reg_c
7800:ff8c v_regs_assert.reg_b
7900:ff8d v_regs_assert.reg_e
8000:ff8e v_regs_assert.reg_d
8100:ff8f v_regs_assert.reg_l
8200:ff90 v_regs_assert.reg_h
8300:0150 main
8400:0151 main@wait_ly_5
8500:0157 main@wait_ly_6
8600:0187 test_finish
8700:01d0 wram_test
8800:01d6 hiram_test
8900:01d8 hiram_test@wait_ly_7
9000:01de hiram_test@wait_ly_8
9100:01f3 finish_round1
9200:01f5 finish_round1@wait_ly_9
9300:01fb finish_round1@wait_ly_10
9400:0211 finish_round2
95
96[definitions]
970000023b _sizeof_check_asserts_cb
980000000a _sizeof_clear_vram
990000000f _sizeof_disable_lcd_safe
10000000009 _sizeof_memcpy
10100000009 _sizeof_memset
1020000000c _sizeof_print_hex4
1030000000a _sizeof_print_hex8
10400000006 _sizeof_print_inline_string
1050000000c _sizeof_print_load_font
1060000000b _sizeof_print_newline
10700000085 _sizeof_print_reg_dump
10800000007 _sizeof_print_string
10900000076 _sizeof_quit
11000000014 _sizeof_reset_screen
1110000000f _sizeof_serial_send_byte
112000007f0 _sizeof_font
11300000008 _sizeof_v_regs_save
11400000001 _sizeof_v_regs_save.reg_f
11500000001 _sizeof_v_regs_save.reg_a
11600000001 _sizeof_v_regs_save.reg_c
11700000001 _sizeof_v_regs_save.reg_b
11800000001 _sizeof_v_regs_save.reg_e
11900000001 _sizeof_v_regs_save.reg_d
12000000001 _sizeof_v_regs_save.reg_l
12100000001 _sizeof_v_regs_save.reg_h
12200000001 _sizeof_v_regs_flags
12300000008 _sizeof_v_regs_assert
12400000001 _sizeof_v_regs_assert.reg_f
12500000001 _sizeof_v_regs_assert.reg_a
12600000001 _sizeof_v_regs_assert.reg_c
12700000001 _sizeof_v_regs_assert.reg_b
12800000001 _sizeof_v_regs_assert.reg_e
12900000001 _sizeof_v_regs_assert.reg_d
13000000001 _sizeof_v_regs_assert.reg_l
13100000001 _sizeof_v_regs_assert.reg_h
13200000037 _sizeof_main
13300000049 _sizeof_test_finish
13400000006 _sizeof_wram_test
1350000001d _sizeof_hiram_test
1360000001e _sizeof_finish_round1
137