1
2 /*
3 * O2EM Free Odyssey2 / Videopac+ Emulator
4 *
5 * Created by Daniel Boris <dboris@comcast.net> (c) 1997,1998
6 *
7 ** Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
8 * Arlindo M. de Oliveira <dgtec@users.sourceforge.net>
9 *
10 * http://o2em.sourceforge.net
11 *
12 *
13 *
14 * 8048 microcontroller emulation
15 */
16
17
18 #include <stdint.h>
19 #include "vmachine.h"
20 #include "keyboard.h"
21 #include "voice.h"
22 #include "vdc.h"
23 #include "vpp.h"
24 #include "cpu.h"
25
26 #define push(d) {intRAM[sp++] = (d); if (sp > 23) sp = 8;}
27 #define pull() (sp--, (sp < 8)?(sp=23):0, intRAM[sp])
28 #define make_psw() {psw = (cy << 7) | ac | f0 | bs | 0x08; psw = psw | ((sp - 8) >> 1);}
29 #define illegal(o) {}
30 #define undef(i) { }
31 #define ROM(adr) (rom[(adr) & 0xfff])
32
33 uint8_t acc;
34 uint16_t pc;
35 long clk;
36
37 uint8_t itimer;
38 uint8_t reg_pnt;
39 uint8_t timer_on;
40 uint8_t count_on;
41 uint8_t psw;
42 uint8_t sp;
43
44 uint8_t p1;
45 uint8_t p2;
46 uint8_t xirq_pend;
47 uint8_t tirq_pend;
48 uint8_t t_flag;
49
50 uint16_t lastpc;
51 uint16_t A11;
52 uint16_t A11ff;
53 uint8_t bs;
54 uint8_t f0;
55 uint8_t f1;
56 uint8_t ac;
57 uint8_t cy;
58 uint8_t xirq_en;
59 uint8_t tirq_en;
60 uint8_t irq_ex;
61
62 int master_count;
63
init_cpu(void)64 void init_cpu(void){
65 pc=0;
66 sp=8;
67 bs=0;
68 p1=p2=0xFF;
69 ac=cy=f0=0;
70 A11=A11ff=0;
71 timer_on=0;
72 count_on=0;
73 reg_pnt=0;
74 tirq_en=xirq_en=irq_ex=xirq_pend=tirq_pend=0;
75 }
76
77
ext_IRQ(void)78 void ext_IRQ(void){
79 int_clk = 5; /* length of pulse on /INT */
80 if (xirq_en && !irq_ex) {
81 irq_ex=1;
82 xirq_pend=0;
83 clk+=2;
84 make_psw();
85 push(pc & 0xFF);
86 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
87 pc = 0x03;
88 A11ff=A11;
89 A11=0;
90 }
91 if (pendirq && (!xirq_en)) xirq_pend=1;
92 }
93
94
tim_IRQ(void)95 void tim_IRQ(void){
96 if (tirq_en && !irq_ex) {
97 irq_ex=2;
98 tirq_pend=0;
99 clk+=2;
100 make_psw();
101 push(pc & 0xFF);
102 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
103 pc = 0x07;
104 A11ff=A11;
105 A11=0;
106 }
107 if (pendirq && (!tirq_en)) tirq_pend=1;
108 }
109
110
make_psw_debug(void)111 void make_psw_debug(void){
112 make_psw();
113 }
114
115 extern int RLOOP;
116
cpu_exec(void)117 void cpu_exec(void)
118 {
119 uint16_t adr;
120 uint8_t dat;
121 int temp;
122
123 while(RLOOP == 1)
124 {
125 uint8_t op;
126
127 clk=0;
128
129 lastpc=pc;
130 op=ROM(pc++);
131
132 switch (op)
133 {
134 case 0x00: /* NOP */
135 clk++;
136 break;
137 case 0x01: /* ILL */
138 illegal(op);
139 clk++;
140 break;
141 case 0x02: /* OUTL BUS,A */
142 clk+=2;
143 undef(0x02);
144 break;
145 case 0x03: /* ADD A,#data */
146 clk+=2;
147 cy=ac=0;
148 dat = ROM(pc++);
149 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
150 temp=acc+dat;
151 if (temp > 0xFF) cy=1;
152 acc=(temp & 0xFF);
153 break;
154 case 0x04: /* JMP */
155 pc=ROM(pc) | A11;
156 clk+=2;
157 break;
158 case 0x05: /* EN I */
159 xirq_en=1;
160 clk++;
161 break;
162 case 0x06: /* ILL */
163 clk++;
164 illegal(op);
165 break;
166 case 0x07: /* DEC A */
167 acc--;
168 clk++;
169 break;
170 case 0x08: /* INS A,BUS*/
171 clk+=2;
172 acc=in_bus();
173 break;
174 case 0x09: /* IN A,Pp */
175 acc=p1;
176 clk+=2;
177 break;
178 case 0x0A: /* IN A,Pp */
179 acc=read_P2();
180 clk+=2;
181 break;
182 case 0x0B: /* ILL */
183 clk++;
184 illegal(op);
185 break;
186 case 0x0C: /* MOVD A,P4 */
187 clk+=2;
188 acc=read_PB(0);
189 break;
190 case 0x0D: /* MOVD A,P5 */
191 clk+=2;
192 acc=read_PB(1);
193 break;
194 case 0x0E: /* MOVD A,P6 */
195 clk+=2;
196 acc=read_PB(2);
197 break;
198 case 0x0F: /* MOVD A,P7 */
199 clk+=2;
200 acc=read_PB(3);
201 break;
202 case 0x10: /* INC @Ri */
203 intRAM[intRAM[reg_pnt] & 0x3F]++;
204 clk++;
205 break;
206 case 0x11: /* INC @Ri */
207 intRAM[intRAM[reg_pnt+1] & 0x3F]++;
208 clk++;
209 break;
210 case 0x12: /* JBb address */
211 clk+=2;
212 dat = ROM(pc);
213 if (acc & 0x01)
214 pc=(pc & 0xF00) | dat;
215 else
216 pc++;
217 break;
218 case 0x13: /* ADDC A,#data */
219 clk+=2;
220 dat=ROM(pc++);
221 ac=0;
222 if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40;
223 temp=acc+dat+cy;
224 cy=0;
225 if (temp > 0xFF) cy=1;
226 acc=(temp & 0xFF);
227 break;
228
229 case 0x14: /* CALL */
230 make_psw();
231 adr = ROM(pc) | A11;
232 pc++;
233 clk+=2;
234 push(pc & 0xFF);
235 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
236 pc = adr;
237 break;
238 case 0x15: /* DIS I */
239 xirq_en=0;
240 clk++;
241 break;
242 case 0x16: /* JTF */
243 clk+=2;
244 dat = ROM(pc);
245 if (t_flag)
246 pc=(pc & 0xF00) | dat;
247 else
248 pc++;
249 t_flag=0;
250 break;
251 case 0x17: /* INC A */
252 acc++;
253 clk++;
254 break;
255 case 0x18: /* INC Rr */
256 intRAM[reg_pnt]++;
257 clk++;
258 break;
259 case 0x19: /* INC Rr */
260 intRAM[reg_pnt+1]++;
261 clk++;
262 break;
263 case 0x1A: /* INC Rr */
264 intRAM[reg_pnt+2]++;
265 clk++;
266 break;
267 case 0x1B: /* INC Rr */
268 intRAM[reg_pnt+3]++;
269 clk++;
270 break;
271 case 0x1C: /* INC Rr */
272 intRAM[reg_pnt+4]++;
273 clk++;
274 break;
275 case 0x1D: /* INC Rr */
276 intRAM[reg_pnt+5]++;
277 clk++;
278 break;
279 case 0x1E: /* INC Rr */
280 intRAM[reg_pnt+6]++;
281 clk++;
282 break;
283 case 0x1F: /* INC Rr */
284 intRAM[reg_pnt+7]++;
285 clk++;
286 break;
287 case 0x20: /* XCH A,@Ri */
288 clk++;
289 dat=acc;
290 acc=intRAM[intRAM[reg_pnt] & 0x3F];
291 intRAM[intRAM[reg_pnt] & 0x3F] = dat;
292 break;
293 case 0x21: /* XCH A,@Ri */
294 clk++;
295 dat=acc;
296 acc=intRAM[intRAM[reg_pnt+1] & 0x3F];
297 intRAM[intRAM[reg_pnt+1] & 0x3F] = dat;
298 break;
299 case 0x22: /* ILL */
300 clk++;
301 illegal(op);
302 break;
303 case 0x23: /* MOV a,#data */
304 clk+=2;
305 acc = ROM(pc++);
306 break;
307
308 case 0x24: /* JMP */
309 pc=ROM(pc) | 0x100 | A11;
310 clk+=2;
311 break;
312 case 0x25: /* EN TCNTI */
313 tirq_en=1;
314 clk++;
315 break;
316 case 0x26: /* JNT0 */
317 clk+=2;
318 dat = ROM(pc);
319 if (!get_voice_status())
320 pc=(pc & 0xF00) | dat;
321 else
322 pc++;
323 break;
324 case 0x27: /* CLR A */
325 clk++;
326 acc=0;
327 break;
328 case 0x28: /* XCH A,Rr */
329 dat=acc;
330 acc=intRAM[reg_pnt];
331 intRAM[reg_pnt]=dat;
332 clk++;
333 break;
334 case 0x29: /* XCH A,Rr */
335 dat=acc;
336 acc=intRAM[reg_pnt+1];
337 intRAM[reg_pnt+1]=dat;
338 clk++;
339 break;
340 case 0x2A: /* XCH A,Rr */
341 dat=acc;
342 acc=intRAM[reg_pnt+2];
343 intRAM[reg_pnt+2]=dat;
344 clk++;
345 break;
346 case 0x2B: /* XCH A,Rr */
347 dat=acc;
348 acc=intRAM[reg_pnt+3];
349 intRAM[reg_pnt+3]=dat;
350 clk++;
351 break;
352 case 0x2C: /* XCH A,Rr */
353 dat=acc;
354 acc=intRAM[reg_pnt+4];
355 intRAM[reg_pnt+4]=dat;
356 clk++;
357 break;
358 case 0x2D: /* XCH A,Rr */
359 dat=acc;
360 acc=intRAM[reg_pnt+5];
361 intRAM[reg_pnt+5]=dat;
362 clk++;
363 break;
364 case 0x2E: /* XCH A,Rr */
365 dat=acc;
366 acc=intRAM[reg_pnt+6];
367 intRAM[reg_pnt+6]=dat;
368 clk++;
369 break;
370 case 0x2F: /* XCH A,Rr */
371 dat=acc;
372 acc=intRAM[reg_pnt+7];
373 intRAM[reg_pnt+7]=dat;
374 clk++;
375 break;
376 case 0x30: /* XCHD A,@Ri */
377 clk++;
378 adr=intRAM[reg_pnt] & 0x3F;
379 dat=acc & 0x0F;
380 acc=acc & 0xF0;
381 acc=acc | (intRAM[adr] & 0x0F);
382 intRAM[adr] &= 0xF0;
383 intRAM[adr] |= dat;
384 break;
385 case 0x31: /* XCHD A,@Ri */
386 clk++;
387 adr=intRAM[reg_pnt+1] & 0x3F;
388 dat=acc & 0x0F;
389 acc=acc & 0xF0;
390 acc=acc | (intRAM[adr] & 0x0F);
391 intRAM[adr] &= 0xF0;
392 intRAM[adr] |= dat;
393 break;
394 case 0x32: /* JBb address */
395 clk+=2;
396 dat=ROM(pc);
397 if (acc & 0x02)
398 pc=(pc & 0xF00) | dat;
399 else
400 pc++;
401 break;
402 case 0x33: /* ILL */
403 clk++;
404 illegal(op);
405 break;
406 case 0x34: /* CALL */
407 make_psw();
408 adr = ROM(pc) | 0x100 | A11;
409 pc++;
410 clk+=2;
411 push(pc & 0xFF);
412 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
413 pc = adr;
414 break;
415 case 0x35: /* DIS TCNTI */
416 tirq_en=0;
417 tirq_pend=0;
418 clk++;
419 break;
420 case 0x36: /* JT0 */
421 clk+=2;
422 dat=ROM(pc);
423 if (get_voice_status())
424 pc=(pc & 0xF00) | dat;
425 else
426 pc++;
427 break;
428 case 0x37: /* CPL A */
429 acc = acc ^ 0xFF;
430 clk++;
431 break;
432 case 0x38: /* ILL */
433 clk++;
434 illegal(op);
435 break;
436 case 0x39: /* OUTL P1,A */
437 clk+=2;
438 write_p1(acc);
439 break;
440 case 0x3A: /* OUTL P2,A */
441 clk+=2;
442 p2=acc;
443 break;
444 case 0x3B: /* ILL */
445 clk++;
446 illegal(op);
447 break;
448 case 0x3C: /* MOVD P4,A */
449 clk+=2;
450 write_PB(0,acc);
451 break;
452 case 0x3D: /* MOVD P5,A */
453 clk+=2;
454 write_PB(1,acc);
455 break;
456 case 0x3E: /* MOVD P6,A */
457 clk+=2;
458 write_PB(2,acc);
459 break;
460 case 0x3F: /* MOVD P7,A */
461 clk+=2;
462 write_PB(3,acc);
463 break;
464 case 0x40: /* ORL A,@Ri */
465 clk++;
466 acc = acc | intRAM[intRAM[reg_pnt] & 0x3F];
467 break;
468 case 0x41: /* ORL A,@Ri */
469 clk++;
470 acc = acc | intRAM[intRAM[reg_pnt+1] & 0x3F];
471 break;
472 case 0x42: /* MOV A,T */
473 clk++;
474 acc = itimer;
475 break;
476 case 0x43: /* ORL A,#data */
477 clk+=2;
478 acc = acc | ROM(pc++);
479 break;
480 case 0x44: /* JMP */
481 pc=ROM(pc) | 0x200 | A11;
482 clk+=2;
483 break;
484 case 0x45: /* STRT CNT */
485 /* printf("START: %d=%d\n",master_clk/22,itimer); */
486 count_on=1;
487 clk++;
488 break;
489 case 0x46: /* JNT1 */
490 clk+=2;
491 dat = ROM(pc);
492 if (!read_t1())
493 pc=(pc & 0xF00) | dat;
494 else
495 pc++;
496 break;
497 case 0x47: /* SWAP A */
498 clk++;
499 dat=(acc & 0xF0) >> 4;
500 acc = acc << 4;
501 acc = acc | dat;
502 break;
503 case 0x48: /* ORL A,Rr */
504 clk++;
505 acc = acc | intRAM[reg_pnt];
506 break;
507 case 0x49: /* ORL A,Rr */
508 clk++;
509 acc = acc | intRAM[reg_pnt+1];
510 break;
511 case 0x4A: /* ORL A,Rr */
512 clk++;
513 acc = acc | intRAM[reg_pnt+2];
514 break;
515 case 0x4B: /* ORL A,Rr */
516 clk++;
517 acc = acc | intRAM[reg_pnt+3];
518 break;
519 case 0x4C: /* ORL A,Rr */
520 clk++;
521 acc = acc | intRAM[reg_pnt+4];
522 break;
523 case 0x4D: /* ORL A,Rr */
524 clk++;
525 acc = acc | intRAM[reg_pnt+5];
526 break;
527 case 0x4E: /* ORL A,Rr */
528 clk++;
529 acc = acc | intRAM[reg_pnt+6];
530 break;
531 case 0x4F: /* ORL A,Rr */
532 clk++;
533 acc = acc | intRAM[reg_pnt+7];
534 break;
535
536 case 0x50: /* ANL A,@Ri */
537 acc = acc & intRAM[intRAM[reg_pnt] & 0x3F];
538 clk++;
539 break;
540 case 0x51: /* ANL A,@Ri */
541 acc = acc & intRAM[intRAM[reg_pnt+1] & 0x3F];
542 clk++;
543 break;
544 case 0x52: /* JBb address */
545 clk+=2;
546 dat=ROM(pc);
547 if (acc & 0x04)
548 pc=(pc & 0xF00) | dat;
549 else
550 pc++;
551 break;
552 case 0x53: /* ANL A,#data */
553 clk+=2;
554 acc = acc & ROM(pc++);
555 break;
556 case 0x54: /* CALL */
557 make_psw();
558 adr = ROM(pc) | 0x200 | A11;
559 pc++;
560 clk+=2;
561 push(pc & 0xFF);
562 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
563 pc = adr;
564 break;
565 case 0x55: /* STRT T */
566 timer_on=1;
567 clk++;
568 break;
569 case 0x56: /* JT1 */
570 clk+=2;
571 dat = ROM(pc);
572 if (read_t1())
573 pc=(pc & 0xF00) | dat;
574 else
575 pc++;
576 break;
577 case 0x57: /* DA A */
578 clk++;
579 if (((acc & 0x0F) > 0x09) || ac) {
580 if (acc>0xf9) cy=1;
581 acc += 6;
582 }
583 dat = (acc & 0xF0) >> 4;
584 if ((dat > 9) || cy) {
585 dat+=6;
586 cy=1;
587 }
588 acc = (acc & 0x0F) | (dat << 4);
589 break;
590 case 0x58: /* ANL A,Rr */
591 clk++;
592 acc = acc & intRAM[reg_pnt];
593 break;
594 case 0x59: /* ANL A,Rr */
595 clk++;
596 acc = acc & intRAM[reg_pnt+1];
597 break;
598 case 0x5A: /* ANL A,Rr */
599 clk++;
600 acc = acc & intRAM[reg_pnt+2];
601 break;
602 case 0x5B: /* ANL A,Rr */
603 clk++;
604 acc = acc & intRAM[reg_pnt+3];
605 break;
606 case 0x5C: /* ANL A,Rr */
607 clk++;
608 acc = acc & intRAM[reg_pnt+4];
609 break;
610 case 0x5D: /* ANL A,Rr */
611 clk++;
612 acc = acc & intRAM[reg_pnt+5];
613 break;
614 case 0x5E: /* ANL A,Rr */
615 clk++;
616 acc = acc & intRAM[reg_pnt+6];
617 break;
618 case 0x5F: /* ANL A,Rr */
619 clk++;
620 acc = acc & intRAM[reg_pnt+7];
621 break;
622
623 case 0x60: /* ADD A,@Ri */
624 clk++;
625 cy=ac=0;
626 dat=intRAM[intRAM[reg_pnt] & 0x3F];
627 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
628 temp=acc+dat;
629 if (temp > 0xFF) cy=1;
630 acc=(temp & 0xFF);
631 break;
632 case 0x61: /* ADD A,@Ri */
633 clk++;
634 cy=ac=0;
635 dat=intRAM[intRAM[reg_pnt+1] & 0x3F];
636 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
637 temp=acc+dat;
638 if (temp > 0xFF) cy=1;
639 acc=(temp & 0xFF);
640 break;
641 case 0x62: /* MOV T,A */
642 clk++;
643 itimer=acc;
644 break;
645 case 0x63: /* ILL */
646 clk++;
647 illegal(op);
648 break;
649 case 0x64: /* JMP */
650 pc=ROM(pc) | 0x300 | A11;
651 clk+=2;
652 break;
653 case 0x65: /* STOP TCNT */
654 clk++;
655 /* printf("STOP %d\n",master_clk/22); */
656 count_on=timer_on=0;
657 break;
658 case 0x66: /* ILL */
659 clk++;
660 illegal(op);
661 break;
662 case 0x67: /* RRC A */
663 dat=cy;
664 cy=acc & 0x01;
665 acc = acc >> 1;
666 if (dat)
667 acc = acc | 0x80;
668 else
669 acc = acc & 0x7F;
670 clk++;
671 break;
672 case 0x68: /* ADD A,Rr */
673 clk++;
674 cy=ac=0;
675 dat=intRAM[reg_pnt];
676 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
677 temp=acc+dat;
678 if (temp > 0xFF) cy=1;
679 acc=(temp & 0xFF);
680 break;
681 case 0x69: /* ADD A,Rr */
682 clk++;
683 cy=ac=0;
684 dat=intRAM[reg_pnt+1];
685 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
686 temp=acc+dat;
687 if (temp > 0xFF) cy=1;
688 acc=(temp & 0xFF);
689 break;
690 case 0x6A: /* ADD A,Rr */
691 clk++;
692 cy=ac=0;
693 dat=intRAM[reg_pnt+2];
694 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
695 temp=acc+dat;
696 if (temp > 0xFF) cy=1;
697 acc=(temp & 0xFF);
698 break;
699 case 0x6B: /* ADD A,Rr */
700 clk++;
701 cy=ac=0;
702 dat=intRAM[reg_pnt+3];
703 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
704 temp=acc+dat;
705 if (temp > 0xFF) cy=1;
706 acc=(temp & 0xFF);
707 break;
708 case 0x6C: /* ADD A,Rr */
709 clk++;
710 cy=ac=0;
711 dat=intRAM[reg_pnt+4];
712 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
713 temp=acc+dat;
714 if (temp > 0xFF) cy=1;
715 acc=(temp & 0xFF);
716 break;
717 case 0x6D: /* ADD A,Rr */
718 clk++;
719 cy=ac=0;
720 dat=intRAM[reg_pnt+5];
721 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
722 temp=acc+dat;
723 if (temp > 0xFF) cy=1;
724 acc=(temp & 0xFF);
725 break;
726 case 0x6E: /* ADD A,Rr */
727 clk++;
728 cy=ac=0;
729 dat=intRAM[reg_pnt+6];
730 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
731 temp=acc+dat;
732 if (temp > 0xFF) cy=1;
733 acc=(temp & 0xFF);
734 break;
735 case 0x6F: /* ADD A,Rr */
736 clk++;
737 cy=ac=0;
738 dat=intRAM[reg_pnt+7];
739 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
740 temp=acc+dat;
741 if (temp > 0xFF) cy=1;
742 acc=(temp & 0xFF);
743 break;
744 case 0x70: /* ADDC A,@Ri */
745 clk++;
746 ac=0;
747 dat=intRAM[intRAM[reg_pnt] & 0x3F];
748 if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40;
749 temp=acc+dat+cy;
750 cy=0;
751 if (temp > 0xFF) cy=1;
752 acc=(temp & 0xFF);
753 break;
754 case 0x71: /* ADDC A,@Ri */
755 clk++;
756 ac=0;
757 dat=intRAM[intRAM[reg_pnt+1] & 0x3F];
758 if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40;
759 temp=acc+dat+cy;
760 cy=0;
761 if (temp > 0xFF) cy=1;
762 acc=(temp & 0xFF);
763 break;
764
765 case 0x72: /* JBb address */
766 clk+=2;
767 dat=ROM(pc);
768 if (acc & 0x08)
769 pc=(pc & 0xF00) | dat;
770 else
771 pc++;
772 break;
773 case 0x73: /* ILL */
774 clk++;
775 illegal(op);
776 break;
777 case 0x74: /* CALL */
778 make_psw();
779 adr = ROM(pc) | 0x300 | A11;
780 pc++;
781 clk+=2;
782 push(pc & 0xFF);
783 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
784 pc = adr;
785 break;
786 case 0x75: /* EN CLK */
787 clk++;
788 undef(op);
789 break;
790 case 0x76: /* JF1 address */
791 clk+=2;
792 dat=ROM(pc);
793 if (f1)
794 pc=(pc & 0xF00) | dat;
795 else
796 pc++;
797 break;
798 case 0x77: /* RR A */
799 clk++;
800 dat=acc & 0x01;
801 acc = acc >> 1;
802 if (dat)
803 acc = acc | 0x80;
804 else
805 acc = acc & 0x7f;
806 break;
807
808 case 0x78: /* ADDC A,Rr */
809 clk++;
810 ac=0;
811 dat=intRAM[reg_pnt];
812 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
813 temp=acc+dat+cy;
814 cy=0;
815 if (temp > 0xFF) cy=1;
816 acc=(temp & 0xFF);
817 break;
818 case 0x79: /* ADDC A,Rr */
819 clk++;
820 ac=0;
821 dat=intRAM[reg_pnt+1];
822 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
823 temp=acc+dat+cy;
824 cy=0;
825 if (temp > 0xFF) cy=1;
826 acc=(temp & 0xFF);
827 break;
828 case 0x7A: /* ADDC A,Rr */
829 clk++;
830 ac=0;
831 dat=intRAM[reg_pnt+2];
832 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
833 temp=acc+dat+cy;
834 cy=0;
835 if (temp > 0xFF) cy=1;
836 acc=(temp & 0xFF);
837 break;
838 case 0x7B: /* ADDC A,Rr */
839 clk++;
840 ac=0;
841 dat=intRAM[reg_pnt+3];
842 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
843 temp=acc+dat+cy;
844 cy=0;
845 if (temp > 0xFF) cy=1;
846 acc=(temp & 0xFF);
847 break;
848 case 0x7C: /* ADDC A,Rr */
849 clk++;
850 ac=0;
851 dat=intRAM[reg_pnt+4];
852 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
853 temp=acc+dat+cy;
854 cy=0;
855 if (temp > 0xFF) cy=1;
856 acc=(temp & 0xFF);
857 break;
858 case 0x7D: /* ADDC A,Rr */
859 clk++;
860 ac=0;
861 dat=intRAM[reg_pnt+5];
862 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
863 temp=acc+dat+cy;
864 cy=0;
865 if (temp > 0xFF) cy=1;
866 acc=(temp & 0xFF);
867 break;
868 case 0x7E: /* ADDC A,Rr */
869 clk++;
870 ac=0;
871 dat=intRAM[reg_pnt+6];
872 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
873 temp=acc+dat+cy;
874 cy=0;
875 if (temp > 0xFF) cy=1;
876 acc=(temp & 0xFF);
877 break;
878 case 0x7F: /* ADDC A,Rr */
879 clk++;
880 ac=0;
881 dat=intRAM[reg_pnt+7];
882 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
883 temp=acc+dat+cy;
884 cy=0;
885 if (temp > 0xFF) cy=1;
886 acc=(temp & 0xFF);
887 break;
888
889 case 0x80: /* MOVX A,@Ri */
890 acc=ext_read(intRAM[reg_pnt]);
891 clk+=2;
892 break;
893 case 0x81: /* MOVX A,@Ri */
894 acc=ext_read(intRAM[reg_pnt+1]);
895 clk+=2;
896 break;
897 case 0x82: /* ILL */
898 clk++;
899 illegal(op);
900 break;
901 case 0x83: /* RET */
902 clk+=2;
903 pc = ((pull() & 0x0F) << 8);
904 pc = pc | pull();
905 break;
906 case 0x84: /* JMP */
907 pc=ROM(pc) | 0x400 | A11;
908 clk+=2;
909 break;
910 case 0x85: /* CLR F0 */
911 clk++;
912 f0=0;
913 break;
914 case 0x86: /* JNI address */
915 clk+=2;
916 dat=ROM(pc);
917 if (int_clk > 0)
918 pc=(pc & 0xF00) | dat;
919 else
920 pc++;
921 break;
922 case 0x87: /* ILL */
923 illegal(op);
924 clk++;
925 break;
926 case 0x88: /* BUS,#data */
927 clk+=2;
928 undef(op);
929 break;
930 case 0x89: /* ORL Pp,#data */
931 write_p1(p1 | ROM(pc++));
932 clk+=2;
933 break;
934 case 0x8A: /* ORL Pp,#data */
935 p2 = p2 | ROM(pc++);
936 clk+=2;
937 break;
938 case 0x8B: /* ILL */
939 illegal(op);
940 clk++;
941 break;
942 case 0x8C: /* ORLD P4,A */
943 write_PB(0,read_PB(0)|acc);
944 clk+=2;
945 break;
946 case 0x8D: /* ORLD P5,A */
947 write_PB(1,read_PB(1)|acc);
948 clk+=2;
949 break;
950 case 0x8E: /* ORLD P6,A */
951 write_PB(2,read_PB(2)|acc);
952 clk+=2;
953 break;
954 case 0x8F: /* ORLD P7,A */
955 write_PB(3,read_PB(3)|acc);
956 clk+=2;
957 break;
958 case 0x90: /* MOVX @Ri,A */
959 ext_write(acc,intRAM[reg_pnt]);
960 clk+=2;
961 break;
962 case 0x91: /* MOVX @Ri,A */
963 ext_write(acc,intRAM[reg_pnt+1]);
964 clk+=2;
965 break;
966 case 0x92: /* JBb address */
967 clk+=2;
968 dat=ROM(pc);
969 if (acc & 0x10)
970 pc=(pc & 0xF00) | dat;
971 else
972 pc++;
973 break;
974 case 0x93: /* RETR*/
975 /* printf("RETR %d\n",master_clk/22); */
976 clk+=2;
977 dat=pull();
978 pc = (dat & 0x0F) << 8;
979 cy = (dat & 0x80) >> 7;
980 ac = dat & 0x40;
981 f0 = dat & 0x20;
982 bs = dat & 0x10;
983 if (bs)
984 reg_pnt=24;
985 else
986 reg_pnt=0;
987 pc = pc | pull();
988 irq_ex=0;
989 A11=A11ff;
990 break;
991 case 0x94: /* CALL */
992 make_psw();
993 adr = ROM(pc) | 0x400 | A11;
994 pc++;
995 clk+=2;
996 push(pc & 0xFF);
997 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
998 pc = adr;
999 break;
1000 case 0x95: /* CPL F0 */
1001 f0 = f0 ^ 0x20;
1002 clk++;
1003 break;
1004 case 0x96: /* JNZ address */
1005 clk+=2;
1006 dat=ROM(pc);
1007 if (acc != 0)
1008 pc=(pc & 0xF00) | dat;
1009 else
1010 pc++;
1011 break;
1012 case 0x97: /* CLR C */
1013 cy=0;
1014 clk++;
1015 break;
1016 case 0x98: /* ANL BUS,#data */
1017 clk+=2;
1018 undef(op);
1019 break;
1020 case 0x99: /* ANL Pp,#data */
1021 write_p1(p1 & ROM(pc++));
1022 clk+=2;
1023 break;
1024 case 0x9A: /* ANL Pp,#data */
1025 p2 = p2 & ROM(pc++);
1026 clk+=2;
1027 break;
1028 case 0x9B: /* ILL */
1029 illegal(op);
1030 clk++;
1031 break;
1032 case 0x9C: /* ANLD P4,A */
1033 write_PB(0,read_PB(0)&acc);
1034 clk+=2;
1035 break;
1036 case 0x9D: /* ANLD P5,A */
1037 write_PB(1,read_PB(1)&acc);
1038 clk+=2;
1039 break;
1040 case 0x9E: /* ANLD P6,A */
1041 write_PB(2,read_PB(2)&acc);
1042 clk+=2;
1043 break;
1044 case 0x9F: /* ANLD P7,A */
1045 write_PB(3,read_PB(3)&acc);
1046 clk+=2;
1047 break;
1048 case 0xA0: /* MOV @Ri,A */
1049 intRAM[intRAM[reg_pnt] & 0x3F]=acc;
1050 clk++;
1051 break;
1052 case 0xA1: /* MOV @Ri,A */
1053 intRAM[intRAM[reg_pnt+1] & 0x3F]=acc;
1054 clk++;
1055 break;
1056 case 0xA2: /* ILL */
1057 clk++;
1058 illegal(op);
1059 break;
1060 case 0xA3: /* MOVP A,@A */
1061 acc=ROM((pc & 0xF00) | acc);
1062 clk+=2;
1063 break;
1064 case 0xA4: /* JMP */
1065 pc=ROM(pc) | 0x500 | A11;
1066 clk+=2;
1067 break;
1068 case 0xA5: /* CLR F1 */
1069 clk++;
1070 f1=0;
1071 break;
1072 case 0xA6: /* ILL */
1073 illegal(op);
1074 clk++;
1075 break;
1076 case 0xA7: /* CPL C */
1077 cy = cy ^ 0x01;
1078 clk++;
1079 break;
1080 case 0xA8: /* MOV Rr,A */
1081 intRAM[reg_pnt] = acc;
1082 clk++;
1083 break;
1084 case 0xA9: /* MOV Rr,A */
1085 intRAM[reg_pnt+1] = acc;
1086 clk++;
1087 break;
1088 case 0xAA: /* MOV Rr,A */
1089 intRAM[reg_pnt+2] = acc;
1090 clk++;
1091 break;
1092 case 0xAB: /* MOV Rr,A */
1093 intRAM[reg_pnt+3] = acc;
1094 clk++;
1095 break;
1096 case 0xAC: /* MOV Rr,A */
1097 intRAM[reg_pnt+4] = acc;
1098 clk++;
1099 break;
1100 case 0xAD: /* MOV Rr,A */
1101 intRAM[reg_pnt+5] = acc;
1102 clk++;
1103 break;
1104 case 0xAE: /* MOV Rr,A */
1105 intRAM[reg_pnt+6] = acc;
1106 clk++;
1107 break;
1108 case 0xAF: /* MOV Rr,A */
1109 intRAM[reg_pnt+7] = acc;
1110 clk++;
1111 break;
1112 case 0xB0: /* MOV @Ri,#data */
1113 intRAM[intRAM[reg_pnt] & 0x3F]=ROM(pc++);
1114 clk+=2;
1115 break;
1116 case 0xB1: /* MOV @Ri,#data */
1117 intRAM[intRAM[reg_pnt+1] & 0x3F]=ROM(pc++);
1118 clk+=2;
1119 break;
1120 case 0xB2: /* JBb address */
1121 clk+=2;
1122 dat=ROM(pc);
1123 if (acc & 0x20)
1124 pc=(pc & 0xF00) | dat;
1125 else
1126 pc++;
1127 break;
1128 case 0xB3: /* JMPP @A */
1129 adr = (pc & 0xF00) | acc;
1130 pc=(pc & 0xF00) | ROM(adr);
1131 clk+=2;
1132 break;
1133 case 0xB4: /* CALL */
1134 make_psw();
1135 adr = ROM(pc) | 0x500 | A11;
1136 pc++;
1137 clk+=2;
1138 push(pc & 0xFF);
1139 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
1140 pc = adr;
1141 break;
1142 case 0xB5: /* CPL F1 */
1143 f1 = f1 ^ 0x01;
1144 clk++;
1145 break;
1146 case 0xB6: /* JF0 address */
1147 clk+=2;
1148 dat=ROM(pc);
1149 if (f0)
1150 pc=(pc & 0xF00) | dat;
1151 else
1152 pc++;
1153 break;
1154 case 0xB7: /* ILL */
1155 clk++;
1156 illegal(op);
1157 break;
1158 case 0xB8: /* MOV Rr,#data */
1159 intRAM[reg_pnt]=ROM(pc++);
1160 clk+=2;
1161 break;
1162 case 0xB9: /* MOV Rr,#data */
1163 intRAM[reg_pnt+1]=ROM(pc++);
1164 clk+=2;
1165 break;
1166 case 0xBA: /* MOV Rr,#data */
1167 intRAM[reg_pnt+2]=ROM(pc++);
1168 clk+=2;
1169 break;
1170 case 0xBB: /* MOV Rr,#data */
1171 intRAM[reg_pnt+3]=ROM(pc++);
1172 clk+=2;
1173 break;
1174 case 0xBC: /* MOV Rr,#data */
1175 intRAM[reg_pnt+4]=ROM(pc++);
1176 clk+=2;
1177 break;
1178 case 0xBD: /* MOV Rr,#data */
1179 intRAM[reg_pnt+5]=ROM(pc++);
1180 clk+=2;
1181 break;
1182 case 0xBE: /* MOV Rr,#data */
1183 intRAM[reg_pnt+6]=ROM(pc++);
1184 clk+=2;
1185 break;
1186 case 0xBF: /* MOV Rr,#data */
1187 intRAM[reg_pnt+7]=ROM(pc++);
1188 clk+=2;
1189 break;
1190 case 0xC0: /* ILL */
1191 illegal(op);
1192 clk++;
1193 break;
1194 case 0xC1: /* ILL */
1195 illegal(op);
1196 clk++;
1197 break;
1198 case 0xC2: /* ILL */
1199 illegal(op);
1200 clk++;
1201 break;
1202 case 0xC3: /* ILL */
1203 illegal(op);
1204 clk++;
1205 break;
1206 case 0xC4: /* JMP */
1207 pc=ROM(pc) | 0x600 | A11;
1208 clk+=2;
1209 break;
1210 case 0xC5: /* SEL RB0 */
1211 bs=reg_pnt=0;
1212 clk++;
1213 break;
1214 case 0xC6: /* JZ address */
1215 clk+=2;
1216 dat=ROM(pc);
1217 if (acc == 0)
1218 pc=(pc & 0xF00) | dat;
1219 else
1220 pc++;
1221 break;
1222 case 0xC7: /* MOV A,PSW */
1223 clk++;
1224 make_psw();
1225 acc=psw;
1226 break;
1227 case 0xC8: /* DEC Rr */
1228 intRAM[reg_pnt]--;
1229 clk++;
1230 break;
1231 case 0xC9: /* DEC Rr */
1232 intRAM[reg_pnt+1]--;
1233 clk++;
1234 break;
1235 case 0xCA: /* DEC Rr */
1236 intRAM[reg_pnt+2]--;
1237 clk++;
1238 break;
1239 case 0xCB: /* DEC Rr */
1240 intRAM[reg_pnt+3]--;
1241 clk++;
1242 break;
1243 case 0xCC: /* DEC Rr */
1244 intRAM[reg_pnt+4]--;
1245 clk++;
1246 break;
1247 case 0xCD: /* DEC Rr */
1248 intRAM[reg_pnt+5]--;
1249 clk++;
1250 break;
1251 case 0xCE: /* DEC Rr */
1252 intRAM[reg_pnt+6]--;
1253 clk++;
1254 break;
1255 case 0xCF: /* DEC Rr */
1256 intRAM[reg_pnt+7]--;
1257 clk++;
1258 break;
1259 case 0xD0: /* XRL A,@Ri */
1260 acc = acc ^ intRAM[intRAM[reg_pnt] & 0x3F];
1261 clk++;
1262 break;
1263 case 0xD1: /* XRL A,@Ri */
1264 acc = acc ^ intRAM[intRAM[reg_pnt+1] & 0x3F];
1265 clk++;
1266 break;
1267 case 0xD2: /* JBb address */
1268 clk+=2;
1269 dat = ROM(pc);
1270 if (acc & 0x40)
1271 pc=(pc & 0xF00) | dat;
1272 else
1273 pc++;
1274 break;
1275 case 0xD3: /* XRL A,#data */
1276 clk+=2;
1277 acc = acc ^ ROM(pc++);
1278 break;
1279 case 0xD4: /* CALL */
1280 make_psw();
1281 adr = ROM(pc) | 0x600 | A11;
1282 pc++;
1283 clk+=2;
1284 push(pc & 0xFF);
1285 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
1286 pc = adr;
1287 break;
1288 case 0xD5: /* SEL RB1 */
1289 bs=0x10;
1290 reg_pnt=24;
1291 clk++;
1292 break;
1293 case 0xD6: /* ILL */
1294 illegal(op);
1295 clk++;
1296 break;
1297 case 0xD7: /* MOV PSW,A */
1298 psw=acc;
1299 clk++;
1300 cy = (psw & 0x80) >> 7;
1301 ac = psw & 0x40;
1302 f0 = psw & 0x20;
1303 bs = psw & 0x10;
1304 if (bs)
1305 reg_pnt = 24;
1306 else
1307 reg_pnt = 0;
1308 sp = (psw & 0x07) << 1;
1309 sp+=8;
1310 break;
1311 case 0xD8: /* XRL A,Rr */
1312 acc = acc ^ intRAM[reg_pnt];
1313 clk++;
1314 break;
1315 case 0xD9: /* XRL A,Rr */
1316 acc = acc ^ intRAM[reg_pnt+1];
1317 clk++;
1318 break;
1319 case 0xDA: /* XRL A,Rr */
1320 acc = acc ^ intRAM[reg_pnt+2];
1321 clk++;
1322 break;
1323 case 0xDB: /* XRL A,Rr */
1324 acc = acc ^ intRAM[reg_pnt+3];
1325 clk++;
1326 break;
1327 case 0xDC: /* XRL A,Rr */
1328 acc = acc ^ intRAM[reg_pnt+4];
1329 clk++;
1330 break;
1331 case 0xDD: /* XRL A,Rr */
1332 acc = acc ^ intRAM[reg_pnt+5];
1333 clk++;
1334 break;
1335 case 0xDE: /* XRL A,Rr */
1336 acc = acc ^ intRAM[reg_pnt+6];
1337 clk++;
1338 break;
1339 case 0xDF: /* XRL A,Rr */
1340 acc = acc ^ intRAM[reg_pnt+7];
1341 clk++;
1342 break;
1343 case 0xE0: /* ILL */
1344 clk++;
1345 illegal(op);
1346 break;
1347 case 0xE1: /* ILL */
1348 clk++;
1349 illegal(op);
1350 break;
1351 case 0xE2: /* ILL */
1352 clk++;
1353 illegal(op);
1354 break;
1355 case 0xE3: /* MOVP3 A,@A */
1356
1357 adr = 0x300 | acc;
1358 acc=ROM(adr);
1359 clk+=2;
1360 break;
1361 case 0xE4: /* JMP */
1362 pc=ROM(pc) | 0x700 | A11;
1363 clk+=2;
1364 break;
1365 case 0xE5: /* SEL MB0 */
1366 A11=0;
1367 A11ff = 0;
1368 clk++;
1369 break;
1370 case 0xE6: /* JNC address */
1371 clk+=2;
1372 dat=ROM(pc);
1373 if (!cy)
1374 pc=(pc & 0xF00) | dat;
1375 else
1376 pc++;
1377 break;
1378 case 0xE7: /* RL A */
1379 clk++;
1380 dat=acc & 0x80;
1381 acc = acc << 1;
1382 if (dat)
1383 acc = acc | 0x01;
1384 else
1385 acc = acc & 0xFE;
1386 break;
1387 case 0xE8: /* DJNZ Rr,address */
1388 clk+=2;
1389 intRAM[reg_pnt]--;
1390 dat=ROM(pc);
1391 if (intRAM[reg_pnt] != 0) {
1392 pc = pc & 0xF00;
1393 pc = pc | dat;
1394 } else pc++;
1395 break;
1396 case 0xE9: /* DJNZ Rr,address */
1397 clk+=2;
1398 intRAM[reg_pnt+1]--;
1399 dat=ROM(pc);
1400 if (intRAM[reg_pnt+1] != 0) {
1401 pc = pc & 0xF00;
1402 pc = pc | dat;
1403 } else pc++;
1404 break;
1405 case 0xEA: /* DJNZ Rr,address */
1406 clk+=2;
1407 intRAM[reg_pnt+2]--;
1408 dat=ROM(pc);
1409 if (intRAM[reg_pnt+2] != 0) {
1410 pc = pc & 0xF00;
1411 pc = pc | dat;
1412 } else pc++;
1413 break;
1414 case 0xEB: /* DJNZ Rr,address */
1415 clk+=2;
1416 intRAM[reg_pnt+3]--;
1417 dat=ROM(pc);
1418 if (intRAM[reg_pnt+3] != 0) {
1419 pc = pc & 0xF00;
1420 pc = pc | dat;
1421 } else pc++;
1422 break;
1423 case 0xEC: /* DJNZ Rr,address */
1424 clk+=2;
1425 intRAM[reg_pnt+4]--;
1426 dat=ROM(pc);
1427 if (intRAM[reg_pnt+4] != 0) {
1428 pc = pc & 0xF00;
1429 pc = pc | dat;
1430 } else pc++;
1431 break;
1432 case 0xED: /* DJNZ Rr,address */
1433 clk+=2;
1434 intRAM[reg_pnt+5]--;
1435 dat=ROM(pc);
1436 if (intRAM[reg_pnt+5] != 0) {
1437 pc = pc & 0xF00;
1438 pc = pc | dat;
1439 } else pc++;
1440 break;
1441 case 0xEE: /* DJNZ Rr,address */
1442 clk+=2;
1443 intRAM[reg_pnt+6]--;
1444 dat=ROM(pc);
1445 if (intRAM[reg_pnt+6] != 0) {
1446 pc = pc & 0xF00;
1447 pc = pc | dat;
1448 } else pc++;
1449 break;
1450 case 0xEF: /* DJNZ Rr,address */
1451 clk+=2;
1452 intRAM[reg_pnt+7]--;
1453 dat=ROM(pc);
1454 if (intRAM[reg_pnt+7] != 0) {
1455 pc = pc & 0xF00;
1456 pc = pc | dat;
1457 } else pc++;
1458 break;
1459 case 0xF0: /* MOV A,@Ri */
1460 clk++;
1461 acc=intRAM[intRAM[reg_pnt] & 0x3F];
1462 break;
1463 case 0xF1: /* MOV A,@Ri */
1464 clk++;
1465 acc=intRAM[intRAM[reg_pnt + 1] & 0x3F];
1466 break;
1467 case 0xF2: /* JBb address */
1468 clk+=2;
1469 dat=ROM(pc);
1470 if (acc & 0x80)
1471 pc=(pc & 0xF00) | dat;
1472 else
1473 pc++;
1474 break;
1475 case 0xF3: /* ILL */
1476 illegal(op);
1477 clk++;
1478 break;
1479 case 0xF4: /* CALL */
1480 clk+=2;
1481 make_psw();
1482 adr = ROM(pc) | 0x700 | A11;
1483 pc++;
1484 push(pc & 0xFF);
1485 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
1486 pc = adr;
1487 break;
1488 case 0xF5: /* SEL MB1 */
1489 if (irq_ex) {
1490 A11ff = 0x800;
1491 }
1492 else
1493 {
1494 A11=0x800;
1495 A11ff = 0x800;
1496 }
1497 clk++;
1498 break;
1499 case 0xF6: /* JC address */
1500 clk+=2;
1501 dat=ROM(pc);
1502 if (cy)
1503 pc=(pc & 0xF00) | dat;
1504 else
1505 pc++;
1506 break;
1507 case 0xF7: /* RLC A */
1508 dat=cy;
1509 cy=(acc & 0x80) >> 7;
1510 acc = acc << 1;
1511 if (dat)
1512 acc = acc | 0x01;
1513 else
1514 acc = acc & 0xFE;
1515 clk++;
1516 break;
1517 case 0xF8: /* MOV A,Rr */
1518 clk++;
1519 acc = intRAM[reg_pnt];
1520 break;
1521 case 0xF9: /* MOV A,Rr */
1522 clk++;
1523 acc = intRAM[reg_pnt + 1];
1524 break;
1525 case 0xFA: /* MOV A,Rr */
1526 clk++;
1527 acc = intRAM[reg_pnt + 2];
1528 break;
1529 case 0xFB: /* MOV A,Rr */
1530 clk++;
1531 acc = intRAM[reg_pnt + 3];
1532 break;
1533 case 0xFC: /* MOV A,Rr */
1534 clk++;
1535 acc = intRAM[reg_pnt + 4];
1536 break;
1537 case 0xFD: /* MOV A,Rr */
1538 clk++;
1539 acc = intRAM[reg_pnt + 5];
1540 break;
1541 case 0xFE: /* MOV A,Rr */
1542 clk++;
1543 acc = intRAM[reg_pnt + 6];
1544 break;
1545 case 0xFF: /* MOV A,Rr */
1546 clk++;
1547 acc = intRAM[reg_pnt + 7];
1548 break;
1549 }
1550
1551
1552 master_clk+=clk;
1553 h_clk+=clk;
1554 clk_counter+=clk;
1555
1556 /* flag for JNI */
1557 if (int_clk > clk)
1558 int_clk -= clk;
1559 else
1560 int_clk = 0;
1561
1562 /* pending IRQs */
1563 if (xirq_pend)
1564 ext_IRQ();
1565 if (tirq_pend)
1566 tim_IRQ();
1567
1568 if (h_clk > LINECNT-1)
1569 {
1570 h_clk-=LINECNT;
1571 if (enahirq && (VDCwrite[0xA0] & 0x01))
1572 ext_IRQ();
1573
1574 if (count_on && mstate == 0)
1575 {
1576 itimer++;
1577 if (itimer == 0)
1578 {
1579 t_flag=1;
1580 tim_IRQ();
1581 draw_region();
1582 }
1583 }
1584 }
1585
1586 if (timer_on)
1587 {
1588 master_count+=clk;
1589 if (master_count > 31)
1590 {
1591 master_count-=31;
1592 itimer++;
1593 if (itimer == 0)
1594 {
1595 t_flag=1;
1596 tim_IRQ();
1597 }
1598 }
1599 }
1600
1601 if ((mstate==0) && (master_clk > VBLCLK))
1602 {
1603 handle_vbl();
1604 }
1605 if ((mstate==1) && (master_clk > evblclk))
1606 {
1607 handle_evbl();
1608 if (app_data.crc == 0xA7344D1F) handle_evbll(); /* Atlantis */
1609 break;
1610 }
1611
1612 if (app_data.debug)
1613 break;
1614 if (pc==app_data.breakpoint)
1615 break;
1616 }
1617 }
1618