1 /*
2 * Copyright © 2006, 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
26 */
27
28 #ifndef CAIRO_DRM_I915_PRIVATE_H
29 #define CAIRO_DRM_I915_PRIVATE_H
30
31 #include "cairo-types-private.h"
32
33 #include "cairo-drm-private.h"
34 #include "cairo-drm-intel-private.h"
35 #include "cairo-drm-intel-command-private.h"
36 #include "cairo-drm-intel-ioctl-private.h"
37 #include "cairo-freelist-private.h"
38
39 #include <setjmp.h>
40
41 #define I915_VERBOSE 1
42
43 #define I915_MAX_TEX_INDIRECT 4
44 #define I915_MAX_TEX_INSN 32
45 #define I915_MAX_ALU_INSN 64
46 #define I915_MAX_DECL_INSN 27
47 #define I915_MAX_TEMPORARY 16
48
49 /* Each instruction is 3 dwords long, though most don't require all
50 * this space. Maximum of 123 instructions. Smaller maxes per insn
51 * type.
52 */
53 #define _3DSTATE_PIXEL_SHADER_PROGRAM (CMD_3D|(0x1d<<24)|(0x5<<16))
54
55 #define REG_TYPE_R 0 /* temporary regs, no need to
56 * dcl, must be written before
57 * read -- Preserved between
58 * phases.
59 */
60 #define REG_TYPE_T 1 /* Interpolated values, must be
61 * dcl'ed before use.
62 *
63 * 0..7: texture coord,
64 * 8: diffuse spec,
65 * 9: specular color,
66 * 10: fog parameter in w.
67 */
68 #define REG_TYPE_CONST 2 /* Restriction: only one const
69 * can be referenced per
70 * instruction, though it may be
71 * selected for multiple inputs.
72 * Constants not initialized
73 * default to zero.
74 */
75 #define REG_TYPE_S 3 /* sampler */
76 #define REG_TYPE_OC 4 /* output color (rgba) */
77 #define REG_TYPE_OD 5 /* output depth (w), xyz are
78 * temporaries. If not written,
79 * interpolated depth is used?
80 */
81 #define REG_TYPE_U 6 /* unpreserved temporaries */
82 #define REG_TYPE_MASK 0x7
83 #define REG_TYPE_SHIFT 4
84 #define REG_NR_MASK 0xf
85
86 /* REG_TYPE_T:
87 */
88 #define T_TEX0 0
89 #define T_TEX1 1
90 #define T_TEX2 2
91 #define T_TEX3 3
92 #define T_TEX4 4
93 #define T_TEX5 5
94 #define T_TEX6 6
95 #define T_TEX7 7
96 #define T_DIFFUSE 8
97 #define T_SPECULAR 9
98 #define T_FOG_W 10 /* interpolated fog is in W coord */
99
100 /* Arithmetic instructions */
101
102 /* .replicate_swizzle == selection and replication of a particular
103 * scalar channel, ie., .xxxx, .yyyy, .zzzz or .wwww
104 */
105 #define A0_NOP (0x0<<24) /* no operation */
106 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */
107 #define A0_MOV (0x2<<24) /* dst = src0 */
108 #define A0_MUL (0x3<<24) /* dst = src0 * src1 */
109 #define A0_MAD (0x4<<24) /* dst = src0 * src1 + src2 */
110 #define A0_DP2ADD (0x5<<24) /* dst.xyzw = src0.xy dot src1.xy + src2.replicate_swizzle */
111 #define A0_DP3 (0x6<<24) /* dst.xyzw = src0.xyz dot src1.xyz */
112 #define A0_DP4 (0x7<<24) /* dst.xyzw = src0.xyzw dot src1.xyzw */
113 #define A0_FRC (0x8<<24) /* dst = src0 - floor(src0) */
114 #define A0_RCP (0x9<<24) /* dst.xyzw = 1/(src0.replicate_swizzle) */
115 #define A0_RSQ (0xa<<24) /* dst.xyzw = 1/(sqrt(abs(src0.replicate_swizzle))) */
116 #define A0_EXP (0xb<<24) /* dst.xyzw = exp2(src0.replicate_swizzle) */
117 #define A0_LOG (0xc<<24) /* dst.xyzw = log2(abs(src0.replicate_swizzle)) */
118 #define A0_CMP (0xd<<24) /* dst = (src0 >= 0.0) ? src1 : src2 */
119 #define A0_MIN (0xe<<24) /* dst = (src0 < src1) ? src0 : src1 */
120 #define A0_MAX (0xf<<24) /* dst = (src0 >= src1) ? src0 : src1 */
121 #define A0_FLR (0x10<<24) /* dst = floor(src0) */
122 #define A0_MOD (0x11<<24) /* dst = src0 fmod 1.0 */
123 #define A0_TRC (0x12<<24) /* dst = int(src0) */
124 #define A0_SGE (0x13<<24) /* dst = src0 >= src1 ? 1.0 : 0.0 */
125 #define A0_SLT (0x14<<24) /* dst = src0 < src1 ? 1.0 : 0.0 */
126 #define A0_DEST_SATURATE (1<<22)
127 #define A0_DEST_TYPE_SHIFT 19
128 /* Allow: R, OC, OD, U */
129 #define A0_DEST_NR_SHIFT 14
130 /* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */
131 #define A0_DEST_CHANNEL_X (1<<10)
132 #define A0_DEST_CHANNEL_Y (2<<10)
133 #define A0_DEST_CHANNEL_Z (4<<10)
134 #define A0_DEST_CHANNEL_W (8<<10)
135 #define A0_DEST_CHANNEL_ALL (0xf<<10)
136 #define A0_DEST_CHANNEL_SHIFT 10
137 #define A0_SRC0_TYPE_SHIFT 7
138 #define A0_SRC0_NR_SHIFT 2
139
140 #define A0_DEST_CHANNEL_XY (A0_DEST_CHANNEL_X|A0_DEST_CHANNEL_Y)
141 #define A0_DEST_CHANNEL_XYZ (A0_DEST_CHANNEL_XY|A0_DEST_CHANNEL_Z)
142
143 #define SRC_X 0
144 #define SRC_Y 1
145 #define SRC_Z 2
146 #define SRC_W 3
147 #define SRC_ZERO 4
148 #define SRC_ONE 5
149
150 #define A1_SRC0_CHANNEL_X_NEGATE (1<<31)
151 #define A1_SRC0_CHANNEL_X_SHIFT 28
152 #define A1_SRC0_CHANNEL_Y_NEGATE (1<<27)
153 #define A1_SRC0_CHANNEL_Y_SHIFT 24
154 #define A1_SRC0_CHANNEL_Z_NEGATE (1<<23)
155 #define A1_SRC0_CHANNEL_Z_SHIFT 20
156 #define A1_SRC0_CHANNEL_W_NEGATE (1<<19)
157 #define A1_SRC0_CHANNEL_W_SHIFT 16
158 #define A1_SRC1_TYPE_SHIFT 13
159 #define A1_SRC1_NR_SHIFT 8
160 #define A1_SRC1_CHANNEL_X_NEGATE (1<<7)
161 #define A1_SRC1_CHANNEL_X_SHIFT 4
162 #define A1_SRC1_CHANNEL_Y_NEGATE (1<<3)
163 #define A1_SRC1_CHANNEL_Y_SHIFT 0
164
165 #define A2_SRC1_CHANNEL_Z_NEGATE (1<<31)
166 #define A2_SRC1_CHANNEL_Z_SHIFT 28
167 #define A2_SRC1_CHANNEL_W_NEGATE (1<<27)
168 #define A2_SRC1_CHANNEL_W_SHIFT 24
169 #define A2_SRC2_TYPE_SHIFT 21
170 #define A2_SRC2_NR_SHIFT 16
171 #define A2_SRC2_CHANNEL_X_NEGATE (1<<15)
172 #define A2_SRC2_CHANNEL_X_SHIFT 12
173 #define A2_SRC2_CHANNEL_Y_NEGATE (1<<11)
174 #define A2_SRC2_CHANNEL_Y_SHIFT 8
175 #define A2_SRC2_CHANNEL_Z_NEGATE (1<<7)
176 #define A2_SRC2_CHANNEL_Z_SHIFT 4
177 #define A2_SRC2_CHANNEL_W_NEGATE (1<<3)
178 #define A2_SRC2_CHANNEL_W_SHIFT 0
179
180 /* Texture instructions */
181 #define T0_TEXLD (0x15<<24) /* Sample texture using predeclared
182 * sampler and address, and output
183 * filtered texel data to destination
184 * register */
185 #define T0_TEXLDP (0x16<<24) /* Same as texld but performs a
186 * perspective divide of the texture
187 * coordinate .xyz values by .w before
188 * sampling. */
189 #define T0_TEXLDB (0x17<<24) /* Same as texld but biases the
190 * computed LOD by w. Only S4.6 two's
191 * comp is used. This implies that a
192 * float to fixed conversion is
193 * done. */
194 #define T0_TEXKILL (0x18<<24) /* Does not perform a sampling
195 * operation. Simply kills the pixel
196 * if any channel of the address
197 * register is < 0.0. */
198 #define T0_DEST_TYPE_SHIFT 19
199 /* Allow: R, OC, OD, U */
200 /* Note: U (unpreserved) regs do not retain their values between
201 * phases (cannot be used for feedback)
202 *
203 * Note: oC and OD registers can only be used as the destination of a
204 * texture instruction once per phase (this is an implementation
205 * restriction).
206 */
207 #define T0_DEST_NR_SHIFT 14
208 /* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */
209 #define T0_SAMPLER_NR_SHIFT 0 /* This field ignored for TEXKILL */
210 #define T0_SAMPLER_NR_MASK (0xf<<0)
211
212 #define T1_ADDRESS_REG_TYPE_SHIFT 24 /* Reg to use as texture coord */
213 /* Allow R, T, OC, OD -- R, OC, OD are 'dependent' reads, new program phase */
214 #define T1_ADDRESS_REG_NR_SHIFT 17
215 #define T2_MBZ 0
216
217 /* Declaration instructions */
218 #define D0_DCL (0x19<<24) /* Declare a t (interpolated attrib)
219 * register or an s (sampler)
220 * register. */
221 #define D0_SAMPLE_TYPE_SHIFT 22
222 #define D0_SAMPLE_TYPE_2D (0x0<<22)
223 #define D0_SAMPLE_TYPE_CUBE (0x1<<22)
224 #define D0_SAMPLE_TYPE_VOLUME (0x2<<22)
225 #define D0_SAMPLE_TYPE_MASK (0x3<<22)
226
227 #define D0_TYPE_SHIFT 19
228 /* Allow: T, S */
229 #define D0_NR_SHIFT 14
230 /* Allow T: 0..10, S: 0..15 */
231 #define D0_CHANNEL_X (1<<10)
232 #define D0_CHANNEL_Y (2<<10)
233 #define D0_CHANNEL_Z (4<<10)
234 #define D0_CHANNEL_W (8<<10)
235 #define D0_CHANNEL_ALL (0xf<<10)
236 #define D0_CHANNEL_NONE (0<<10)
237
238 #define D0_CHANNEL_XY (D0_CHANNEL_X|D0_CHANNEL_Y)
239 #define D0_CHANNEL_XYZ (D0_CHANNEL_XY|D0_CHANNEL_Z)
240
241 /* I915 Errata: Do not allow (xz), (xw), (xzw) combinations for diffuse
242 * or specular declarations.
243 *
244 * For T dcls, only allow: (x), (xy), (xyz), (w), (xyzw)
245 *
246 * Must be zero for S (sampler) dcls
247 */
248 #define D1_MBZ 0
249 #define D2_MBZ 0
250
251
252 /* MASK_* are the unshifted bitmasks of the destination mask in arithmetic
253 * operations
254 */
255 #define MASK_X 0x1
256 #define MASK_Y 0x2
257 #define MASK_Z 0x4
258 #define MASK_W 0x8
259 #define MASK_XYZ (MASK_X | MASK_Y | MASK_Z)
260 #define MASK_XYZW (MASK_XYZ | MASK_W)
261 #define MASK_SATURATE 0x10
262
263 /* Temporary, undeclared regs. Preserved between phases */
264 #define FS_R0 ((REG_TYPE_R << REG_TYPE_SHIFT) | 0)
265 #define FS_R1 ((REG_TYPE_R << REG_TYPE_SHIFT) | 1)
266 #define FS_R2 ((REG_TYPE_R << REG_TYPE_SHIFT) | 2)
267 #define FS_R3 ((REG_TYPE_R << REG_TYPE_SHIFT) | 3)
268
269 /* Texture coordinate regs. Must be declared. */
270 #define FS_T0 ((REG_TYPE_T << REG_TYPE_SHIFT) | 0)
271 #define FS_T1 ((REG_TYPE_T << REG_TYPE_SHIFT) | 1)
272 #define FS_T2 ((REG_TYPE_T << REG_TYPE_SHIFT) | 2)
273 #define FS_T3 ((REG_TYPE_T << REG_TYPE_SHIFT) | 3)
274 #define FS_T4 ((REG_TYPE_T << REG_TYPE_SHIFT) | 4)
275 #define FS_T5 ((REG_TYPE_T << REG_TYPE_SHIFT) | 5)
276 #define FS_T6 ((REG_TYPE_T << REG_TYPE_SHIFT) | 6)
277 #define FS_T7 ((REG_TYPE_T << REG_TYPE_SHIFT) | 7)
278 #define FS_T8 ((REG_TYPE_T << REG_TYPE_SHIFT) | 8)
279 #define FS_T9 ((REG_TYPE_T << REG_TYPE_SHIFT) | 9)
280 #define FS_T10 ((REG_TYPE_T << REG_TYPE_SHIFT) | 10)
281
282 /* Constant values */
283 #define FS_C0 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 0)
284 #define FS_C1 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 1)
285 #define FS_C2 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 2)
286 #define FS_C3 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 3)
287 #define FS_C4 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 4)
288 #define FS_C5 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 5)
289 #define FS_C6 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 6)
290 #define FS_C7 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 7)
291
292 /* Sampler regs */
293 #define FS_S0 ((REG_TYPE_S << REG_TYPE_SHIFT) | 0)
294 #define FS_S1 ((REG_TYPE_S << REG_TYPE_SHIFT) | 1)
295 #define FS_S2 ((REG_TYPE_S << REG_TYPE_SHIFT) | 2)
296 #define FS_S3 ((REG_TYPE_S << REG_TYPE_SHIFT) | 3)
297
298 /* Output color */
299 #define FS_OC ((REG_TYPE_OC << REG_TYPE_SHIFT) | 0)
300
301 /* Output depth */
302 #define FS_OD ((REG_TYPE_OD << REG_TYPE_SHIFT) | 0)
303
304 /* Unpreserved temporary regs */
305 #define FS_U0 ((REG_TYPE_U << REG_TYPE_SHIFT) | 0)
306 #define FS_U1 ((REG_TYPE_U << REG_TYPE_SHIFT) | 1)
307 #define FS_U2 ((REG_TYPE_U << REG_TYPE_SHIFT) | 2)
308 #define FS_U3 ((REG_TYPE_U << REG_TYPE_SHIFT) | 3)
309
310 #define X_CHANNEL_SHIFT (REG_TYPE_SHIFT + 3)
311 #define Y_CHANNEL_SHIFT (X_CHANNEL_SHIFT + 4)
312 #define Z_CHANNEL_SHIFT (Y_CHANNEL_SHIFT + 4)
313 #define W_CHANNEL_SHIFT (Z_CHANNEL_SHIFT + 4)
314
315 #define REG_CHANNEL_MASK 0xf
316
317 #define REG_NR(reg) ((reg) & REG_NR_MASK)
318 #define REG_TYPE(reg) (((reg) >> REG_TYPE_SHIFT) & REG_TYPE_MASK)
319 #define REG_X(reg) (((reg) >> X_CHANNEL_SHIFT) & REG_CHANNEL_MASK)
320 #define REG_Y(reg) (((reg) >> Y_CHANNEL_SHIFT) & REG_CHANNEL_MASK)
321 #define REG_Z(reg) (((reg) >> Z_CHANNEL_SHIFT) & REG_CHANNEL_MASK)
322 #define REG_W(reg) (((reg) >> W_CHANNEL_SHIFT) & REG_CHANNEL_MASK)
323
324 enum i915_fs_channel {
325 X_CHANNEL_VAL = 0,
326 Y_CHANNEL_VAL,
327 Z_CHANNEL_VAL,
328 W_CHANNEL_VAL,
329 ZERO_CHANNEL_VAL,
330 ONE_CHANNEL_VAL,
331
332 NEG_X_CHANNEL_VAL = X_CHANNEL_VAL | 0x8,
333 NEG_Y_CHANNEL_VAL = Y_CHANNEL_VAL | 0x8,
334 NEG_Z_CHANNEL_VAL = Z_CHANNEL_VAL | 0x8,
335 NEG_W_CHANNEL_VAL = W_CHANNEL_VAL | 0x8,
336 NEG_ONE_CHANNEL_VAL = ONE_CHANNEL_VAL | 0x8
337 };
338
339 #define i915_fs_operand(reg, x, y, z, w) \
340 (reg) | \
341 (x##_CHANNEL_VAL << X_CHANNEL_SHIFT) | \
342 (y##_CHANNEL_VAL << Y_CHANNEL_SHIFT) | \
343 (z##_CHANNEL_VAL << Z_CHANNEL_SHIFT) | \
344 (w##_CHANNEL_VAL << W_CHANNEL_SHIFT)
345
346 /*
347 * Construct an operand description for using a register with no swizzling
348 */
349 #define i915_fs_operand_reg(reg) \
350 i915_fs_operand(reg, X, Y, Z, W)
351
352 #define i915_fs_operand_reg_negate(reg) \
353 i915_fs_operand(reg, NEG_X, NEG_Y, NEG_Z, NEG_W)
354
355 /*
356 * Returns an operand containing (0.0, 0.0, 0.0, 0.0).
357 */
358 #define i915_fs_operand_zero() i915_fs_operand(FS_R0, ZERO, ZERO, ZERO, ZERO)
359
360 /*
361 * Returns an unused operand
362 */
363 #define i915_fs_operand_none() i915_fs_operand_zero()
364
365 /*
366 * Returns an operand containing (1.0, 1.0, 1.0, 1.0).
367 */
368 #define i915_fs_operand_one() i915_fs_operand(FS_R0, ONE, ONE, ONE, ONE)
369
370 #define i915_get_hardware_channel_val(val, shift, negate) \
371 (((val & 0x7) << shift) | ((val & 0x8) ? negate : 0))
372
373 /*
374 * Outputs a fragment shader command to declare a sampler or texture register.
375 */
376 #define i915_fs_dcl(reg) \
377 do { \
378 OUT_DWORD (D0_DCL | \
379 (REG_TYPE(reg) << D0_TYPE_SHIFT) | \
380 (REG_NR(reg) << D0_NR_SHIFT) | \
381 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \
382 OUT_DWORD (0); \
383 OUT_DWORD (0); \
384 } while (0)
385
386 #define i915_fs_texld(dest_reg, sampler_reg, address_reg) \
387 do { \
388 OUT_DWORD (T0_TEXLD | \
389 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \
390 (REG_NR(dest_reg) << T0_DEST_NR_SHIFT) | \
391 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \
392 OUT_DWORD((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
393 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
394 OUT_DWORD (0); \
395 } while (0)
396
397 #define i915_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \
398 _i915_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2)
399
400 #define i915_fs_arith(op, dest_reg, operand0, operand1, operand2) \
401 _i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
402
403 #define _i915_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \
404 do { \
405 /* Set up destination register and write mask */ \
406 OUT_DWORD (cmd | \
407 (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \
408 (REG_NR(dest_reg) << A0_DEST_NR_SHIFT) | \
409 (((dest_mask) & ~MASK_SATURATE) << A0_DEST_CHANNEL_SHIFT) | \
410 (((dest_mask) & MASK_SATURATE) ? A0_DEST_SATURATE : 0) | \
411 /* Set up operand 0 */ \
412 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
413 (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \
414 OUT_DWORD (i915_get_hardware_channel_val(REG_X(operand0), \
415 A1_SRC0_CHANNEL_X_SHIFT, \
416 A1_SRC0_CHANNEL_X_NEGATE) | \
417 i915_get_hardware_channel_val(REG_Y(operand0), \
418 A1_SRC0_CHANNEL_Y_SHIFT, \
419 A1_SRC0_CHANNEL_Y_NEGATE) | \
420 i915_get_hardware_channel_val(REG_Z(operand0), \
421 A1_SRC0_CHANNEL_Z_SHIFT, \
422 A1_SRC0_CHANNEL_Z_NEGATE) | \
423 i915_get_hardware_channel_val(REG_W(operand0), \
424 A1_SRC0_CHANNEL_W_SHIFT, \
425 A1_SRC0_CHANNEL_W_NEGATE) | \
426 /* Set up operand 1 */ \
427 (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \
428 (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \
429 i915_get_hardware_channel_val(REG_X(operand1), \
430 A1_SRC1_CHANNEL_X_SHIFT, \
431 A1_SRC1_CHANNEL_X_NEGATE) | \
432 i915_get_hardware_channel_val(REG_Y(operand1), \
433 A1_SRC1_CHANNEL_Y_SHIFT, \
434 A1_SRC1_CHANNEL_Y_NEGATE)); \
435 OUT_DWORD (i915_get_hardware_channel_val(REG_Z(operand1), \
436 A2_SRC1_CHANNEL_Z_SHIFT, \
437 A2_SRC1_CHANNEL_Z_NEGATE) | \
438 i915_get_hardware_channel_val(REG_W(operand1), \
439 A2_SRC1_CHANNEL_W_SHIFT, \
440 A2_SRC1_CHANNEL_W_NEGATE) | \
441 /* Set up operand 2 */ \
442 (REG_TYPE(operand2) << A2_SRC2_TYPE_SHIFT) | \
443 (REG_NR(operand2) << A2_SRC2_NR_SHIFT) | \
444 i915_get_hardware_channel_val(REG_X(operand2), \
445 A2_SRC2_CHANNEL_X_SHIFT, \
446 A2_SRC2_CHANNEL_X_NEGATE) | \
447 i915_get_hardware_channel_val(REG_Y(operand2), \
448 A2_SRC2_CHANNEL_Y_SHIFT, \
449 A2_SRC2_CHANNEL_Y_NEGATE) | \
450 i915_get_hardware_channel_val(REG_Z(operand2), \
451 A2_SRC2_CHANNEL_Z_SHIFT, \
452 A2_SRC2_CHANNEL_Z_NEGATE) | \
453 i915_get_hardware_channel_val(REG_W(operand2), \
454 A2_SRC2_CHANNEL_W_SHIFT, \
455 A2_SRC2_CHANNEL_W_NEGATE)); \
456 } while (0)
457
458 #define _i915_fs_arith(cmd, dest_reg, operand0, operand1, operand2) do {\
459 /* Set up destination register and write mask */ \
460 OUT_DWORD (cmd | \
461 (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \
462 (REG_NR(dest_reg) << A0_DEST_NR_SHIFT) | \
463 (A0_DEST_CHANNEL_ALL) | \
464 /* Set up operand 0 */ \
465 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \
466 (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \
467 OUT_DWORD (i915_get_hardware_channel_val(REG_X(operand0), \
468 A1_SRC0_CHANNEL_X_SHIFT, \
469 A1_SRC0_CHANNEL_X_NEGATE) | \
470 i915_get_hardware_channel_val(REG_Y(operand0), \
471 A1_SRC0_CHANNEL_Y_SHIFT, \
472 A1_SRC0_CHANNEL_Y_NEGATE) | \
473 i915_get_hardware_channel_val(REG_Z(operand0), \
474 A1_SRC0_CHANNEL_Z_SHIFT, \
475 A1_SRC0_CHANNEL_Z_NEGATE) | \
476 i915_get_hardware_channel_val(REG_W(operand0), \
477 A1_SRC0_CHANNEL_W_SHIFT, \
478 A1_SRC0_CHANNEL_W_NEGATE) | \
479 /* Set up operand 1 */ \
480 (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \
481 (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \
482 i915_get_hardware_channel_val(REG_X(operand1), \
483 A1_SRC1_CHANNEL_X_SHIFT, \
484 A1_SRC1_CHANNEL_X_NEGATE) | \
485 i915_get_hardware_channel_val(REG_Y(operand1), \
486 A1_SRC1_CHANNEL_Y_SHIFT, \
487 A1_SRC1_CHANNEL_Y_NEGATE)); \
488 OUT_DWORD (i915_get_hardware_channel_val(REG_Z(operand1), \
489 A2_SRC1_CHANNEL_Z_SHIFT, \
490 A2_SRC1_CHANNEL_Z_NEGATE) | \
491 i915_get_hardware_channel_val(REG_W(operand1), \
492 A2_SRC1_CHANNEL_W_SHIFT, \
493 A2_SRC1_CHANNEL_W_NEGATE) | \
494 /* Set up operand 2 */ \
495 (REG_TYPE(operand2) << A2_SRC2_TYPE_SHIFT) | \
496 (REG_NR(operand2) << A2_SRC2_NR_SHIFT) | \
497 i915_get_hardware_channel_val(REG_X(operand2), \
498 A2_SRC2_CHANNEL_X_SHIFT, \
499 A2_SRC2_CHANNEL_X_NEGATE) | \
500 i915_get_hardware_channel_val(REG_Y(operand2), \
501 A2_SRC2_CHANNEL_Y_SHIFT, \
502 A2_SRC2_CHANNEL_Y_NEGATE) | \
503 i915_get_hardware_channel_val(REG_Z(operand2), \
504 A2_SRC2_CHANNEL_Z_SHIFT, \
505 A2_SRC2_CHANNEL_Z_NEGATE) | \
506 i915_get_hardware_channel_val(REG_W(operand2), \
507 A2_SRC2_CHANNEL_W_SHIFT, \
508 A2_SRC2_CHANNEL_W_NEGATE)); \
509 } while (0)
510
511 #define i915_fs_mov(dest_reg, operand0) \
512 i915_fs_arith(MOV, dest_reg, \
513 operand0, \
514 i915_fs_operand_none(), \
515 i915_fs_operand_none())
516
517 #define i915_fs_mov_masked(dest_reg, dest_mask, operand0) \
518 i915_fs_arith_masked (MOV, dest_reg, dest_mask, \
519 operand0, \
520 i915_fs_operand_none(), \
521 i915_fs_operand_none())
522
523
524 #define i915_fs_frc(dest_reg, operand0) \
525 i915_fs_arith (FRC, dest_reg, \
526 operand0, \
527 i915_fs_operand_none(), \
528 i915_fs_operand_none())
529
530 /* Add operand0 and operand1 and put the result in dest_reg */
531 #define i915_fs_add(dest_reg, operand0, operand1) \
532 i915_fs_arith (ADD, dest_reg, \
533 operand0, operand1, \
534 i915_fs_operand_none())
535
536 /* Multiply operand0 and operand1 and put the result in dest_reg */
537 #define i915_fs_mul(dest_reg, operand0, operand1) \
538 i915_fs_arith (MUL, dest_reg, \
539 operand0, operand1, \
540 i915_fs_operand_none())
541
542 /* Computes 1/sqrt(operand0.replicate_swizzle) puts the result in dest_reg */
543 #define i915_fs_rsq(dest_reg, dest_mask, operand0) \
544 do { \
545 if (dest_mask) { \
546 i915_fs_arith_masked (RSQ, dest_reg, dest_mask, \
547 operand0, \
548 i915_fs_operand_none (), \
549 i915_fs_operand_none ()); \
550 } else { \
551 i915_fs_arith (RSQ, dest_reg, \
552 operand0, \
553 i915_fs_operand_none (), \
554 i915_fs_operand_none ()); \
555 } \
556 } while (0)
557
558 /* Puts the minimum of operand0 and operand1 in dest_reg */
559 #define i915_fs_min(dest_reg, operand0, operand1) \
560 i915_fs_arith (MIN, dest_reg, \
561 operand0, operand1, \
562 i915_fs_operand_none())
563
564 /* Puts the maximum of operand0 and operand1 in dest_reg */
565 #define i915_fs_max(dest_reg, operand0, operand1) \
566 i915_fs_arith (MAX, dest_reg, \
567 operand0, operand1, \
568 i915_fs_operand_none())
569
570 #define i915_fs_cmp(dest_reg, operand0, operand1, operand2) \
571 i915_fs_arith (CMP, dest_reg, operand0, operand1, operand2)
572
573 /* Perform operand0 * operand1 + operand2 and put the result in dest_reg */
574 #define i915_fs_mad(dest_reg, dest_mask, op0, op1, op2) \
575 do { \
576 if (dest_mask) { \
577 i915_fs_arith_masked (MAD, dest_reg, dest_mask, op0, op1, op2); \
578 } else { \
579 i915_fs_arith (MAD, dest_reg, op0, op1, op2); \
580 } \
581 } while (0)
582
583 #define i915_fs_dp2add(dest_reg, dest_mask, op0, op1, op2) \
584 do { \
585 if (dest_mask) { \
586 i915_fs_arith_masked (DP2ADD, dest_reg, dest_mask, op0, op1, op2); \
587 } else { \
588 i915_fs_arith (DP2ADD, dest_reg, op0, op1, op2); \
589 } \
590 } while (0)
591
592 /*
593 * Perform a 3-component dot-product of operand0 and operand1 and put the
594 * resulting scalar in the channels of dest_reg specified by the dest_mask.
595 */
596 #define i915_fs_dp3(dest_reg, dest_mask, op0, op1) \
597 do { \
598 if (dest_mask) { \
599 i915_fs_arith_masked (DP3, dest_reg, dest_mask, \
600 op0, op1,\
601 i915_fs_operand_none()); \
602 } else { \
603 i915_fs_arith (DP3, dest_reg, op0, op1,\
604 i915_fs_operand_none()); \
605 } \
606 } while (0)
607
608 static inline uint32_t cairo_const
i915_fs_operand_pure_alpha(int pure)609 i915_fs_operand_pure_alpha (int pure)
610 {
611 if (pure & (1 << 3))
612 return i915_fs_operand_one ();
613 else
614 return i915_fs_operand_zero ();
615 }
616
617 #define I915_TILING_DEFAULT I915_TILING_Y
618 #define I915_BO_CACHE_BUCKETS 13 /* cache surfaces up to 16 MiB */
619
620 typedef struct i915_surface i915_surface_t;
621 typedef struct i915_device i915_device_t;
622 typedef struct i915_shader i915_shader_t;
623
624 typedef void (*i915_add_rectangle_func_t) (const i915_shader_t *shader,
625 int x, int y,
626 int w, int h);
627
628 #define IMAGE_CACHE_WIDTH 1024
629 #define IMAGE_CACHE_HEIGHT 1024
630
631 typedef struct i915_image_private {
632 cairo_rtree_node_t node;
633 intel_buffer_cache_t *container;
634 } i915_image_private_t;
635
636 #define I915_BATCH_SIZE (128*1024)
637 #define I915_VBO_SIZE (512*1024)
638 #define I915_MAX_RELOCS 2048
639
640 enum {
641 I915_DEBUG_EXEC = 0x1,
642 I915_DEBUG_SYNC = 0x2,
643 I915_DEBUG_BATCH = 0x4,
644 I915_DEBUG_BUFFER = 0x8,
645 I915_DEBUG_BUFFER_CACHE = 0x10,
646 I915_DEBUG_BUFFER_ALLOC = 0x20,
647 I915_DEBUG_GLYPHS = 0x40,
648 I915_DEBUG_MAP = 0x80,
649 I915_DEBUG_THROTTLE = 0x100,
650 };
651
652 struct i915_device {
653 intel_device_t intel;
654
655 cairo_bool_t debug;
656
657 i915_shader_t *shader; /* note: only valid during geometry emission */
658
659 struct i915_batch {
660 intel_bo_t *target_bo[I915_MAX_RELOCS];
661 size_t gtt_avail_size;
662 size_t est_gtt_size;
663 size_t total_gtt_size;
664
665 uint16_t fences;
666 uint16_t fences_avail;
667 uint16_t reloc_count;
668 uint16_t exec_count;
669 uint16_t used;
670
671 struct drm_i915_gem_exec_object2 exec[I915_MAX_RELOCS];
672 struct drm_i915_gem_relocation_entry reloc[I915_MAX_RELOCS];
673 } batch;
674
675 uint32_t vbo;
676 uint32_t vbo_offset;
677 uint32_t vbo_used;
678 uint32_t vbo_max_index;
679 uint32_t vertex_index;
680 uint32_t vertex_count;
681 uint32_t floats_per_vertex;
682 uint32_t rectangle_size;
683 intel_bo_t *last_vbo;
684 uint32_t last_vbo_offset;
685 uint32_t last_vbo_space;
686
687 i915_surface_t *current_target;
688 uint32_t current_size;
689 uint32_t current_diffuse;
690 uint32_t current_colorbuf;
691 uint32_t *current_source;
692 uint32_t *current_mask;
693 uint32_t *current_clip;
694 uint32_t current_program;
695 uint32_t current_texcoords;
696 uint32_t current_blend;
697 uint32_t current_constants[8*4];
698 uint32_t current_n_constants;
699 uint32_t current_samplers[2*4];
700 uint32_t current_maps[4*4];
701 uint32_t current_n_samplers;
702 uint32_t current_n_maps;
703 uint32_t last_source_fragment;
704 uint32_t clear_alpha;
705
706 cairo_list_t image_caches[2];
707
708 uint32_t batch_header[13];
709 uint32_t batch_base[I915_BATCH_SIZE / sizeof (uint32_t)];
710 uint8_t vbo_base[I915_VBO_SIZE];
711 };
712
713 enum {
714 CURRENT_SOURCE = 0x1,
715 CURRENT_MASK = 0x2,
716 CURRENT_CLIP = 0x4
717 };
718
719 typedef enum {
720 VS_ZERO,
721 VS_CONSTANT,
722 VS_LINEAR,
723 VS_TEXTURE,
724 VS_TEXTURE_16,
725 } i915_vertex_shader_t;
726
727 typedef enum {
728 FS_ZERO,
729 FS_ONE,
730 FS_PURE,
731 FS_CONSTANT,
732 FS_DIFFUSE,
733 FS_LINEAR,
734 FS_RADIAL,
735 FS_TEXTURE,
736 FS_YUV,
737 FS_SPANS,
738 } i915_fragment_shader_t;
739
740 #define FS_DETAILS_SHIFT 4
741
742 typedef enum {
743 PATTERN_BASE,
744 PATTERN_CONSTANT,
745 PATTERN_LINEAR,
746 PATTERN_RADIAL,
747 PATTERN_TEXTURE,
748 } i915_shader_channel_t;
749
750 struct i915_surface {
751 intel_surface_t intel;
752
753 uint32_t map0, map1;
754 uint32_t colorbuf;
755
756 cairo_bool_t deferred_clear;
757 uint32_t offset;
758 uint32_t is_current_texture;
759
760 i915_image_private_t *cache;
761
762 intel_bo_t *stencil;
763 uint32_t stencil_stride;
764 uint32_t stencil_offset;
765 };
766
767 typedef enum {
768 NONE = 0,
769 YUV_I420,
770 /* XXX */
771 YUV_YV12,
772 YUV_YUY2,
773 YUV_UYVY,
774 } i915_packed_pixel_t;
775
776 /* read-only container */
777 #define I915_PACKED_PIXEL_SURFACE_TYPE 0x1000
778 typedef struct i915_packed_pixel_surface {
779 cairo_surface_t base;
780
781 i915_packed_pixel_t pixel;
782
783 i915_device_t *device;
784 intel_bo_t *bo;
785 uint32_t is_current_texture;
786
787 uint32_t offset[4];
788 uint32_t stride[4];
789 uint32_t width[4];
790 uint32_t height[4];
791 uint32_t map0[4], map1[4];
792 } i915_packed_pixel_surface_t;
793
794 struct i915_shader {
795 i915_device_t *device;
796 i915_surface_t *target;
797
798 cairo_operator_t op;
799 uint32_t blend;
800 float opacity;
801 cairo_content_t content;
802
803 cairo_bool_t committed;
804 cairo_bool_t need_combine;
805
806 i915_add_rectangle_func_t add_rectangle;
807
808 union i915_shader_channel {
809 struct {
810 i915_vertex_shader_t vertex;
811 i915_fragment_shader_t fragment;
812 i915_shader_channel_t pattern;
813 } type;
814 struct i915_shader_base {
815 i915_vertex_shader_t vertex;
816 i915_fragment_shader_t fragment;
817 i915_shader_channel_t pattern;
818 uint32_t texfmt;
819 cairo_content_t content;
820 uint32_t mode;
821 intel_bo_t *bo;
822 uint32_t n_samplers;
823 uint32_t offset[4];
824 uint32_t map[2*4];
825 uint32_t sampler[2];
826 cairo_matrix_t matrix;
827 } base;
828 struct i915_shader_solid {
829 struct i915_shader_base base;
830 cairo_color_t color;
831 int pure;
832 } solid;
833 struct i915_shader_linear {
834 struct i915_shader_base base;
835 struct {
836 float red, green, blue, alpha;
837 } color0, color1;
838 float dx, dy, offset;
839 } linear;
840 struct i915_shader_radial {
841 struct i915_shader_base base;
842 float constants[8];
843 } radial;
844 struct i915_shader_surface {
845 struct i915_shader_base base;
846 i915_packed_pixel_t pixel;
847 } surface;
848 } source, mask, clip, dst;
849
850 jmp_buf unwind;
851 };
852
853 enum i915_shader_linear_mode {
854 /* XXX REFLECT */
855 LINEAR_TEXTURE,
856 LINEAR_NONE,
857 LINEAR_REPEAT,
858 LINEAR_PAD,
859 };
860
861 enum i915_shader_radial_mode {
862 RADIAL_ONE,
863 RADIAL_TWO
864 };
865
866 typedef cairo_status_t
867 (*i915_spans_func_t) (void *closure,
868 cairo_span_renderer_t *renderer,
869 const cairo_rectangle_int_t *extents);
870
871 cairo_private cairo_status_t
872 i915_clip_and_composite_spans (i915_surface_t *dst,
873 cairo_operator_t op,
874 const cairo_pattern_t *pattern,
875 cairo_antialias_t antialias,
876 i915_spans_func_t draw_func,
877 void *draw_closure,
878 const cairo_composite_rectangles_t*extents,
879 cairo_clip_t *clip,
880 double opacity);
881
882 cairo_private cairo_surface_t *
883 i915_surface_create_internal (cairo_drm_device_t *base_dev,
884 cairo_format_t format,
885 int width, int height,
886 uint32_t tiling,
887 cairo_bool_t gpu_target);
888
889 cairo_private i915_surface_t *
890 i915_surface_create_from_cacheable_image_internal (i915_device_t *device,
891 cairo_image_surface_t *image);
892
893 cairo_private void
894 i915_surface_scaled_font_fini (cairo_scaled_font_t *scaled_font);
895
896 cairo_private cairo_int_status_t
897 i915_surface_glyphs (void *abstract_surface,
898 cairo_operator_t op,
899 const cairo_pattern_t *source,
900 cairo_glyph_t *glyphs,
901 int num_glyphs,
902 cairo_scaled_font_t *scaled_font,
903 cairo_clip_t *clip,
904 int *num_remaining);
905
906 static inline int cairo_const
i915_tiling_height(uint32_t tiling,int height)907 i915_tiling_height (uint32_t tiling, int height)
908 {
909 switch (tiling) {
910 default:
911 case I915_TILING_NONE: return (height + 1) & -2;
912 case I915_TILING_X: return (height + 7) & -8;
913 case I915_TILING_Y: return (height + 31) & -32;
914 }
915 }
916
917 static inline uint32_t cairo_const
i915_tiling_stride(int format,uint32_t stride)918 i915_tiling_stride (int format, uint32_t stride)
919 {
920 uint32_t tile_width;
921
922 /* use 64B alignment so that the buffer may be used as a scanout */
923 if (format == I915_TILING_NONE)
924 return (stride + 63) & -64;
925
926 tile_width = 512;
927 /* XXX Currently the kernel enforces a tile_width of 512 for TILING_Y.
928
929 <jbarnes> the docs are a bit confused on that front
930 <jbarnes> once we enable it on 915 we'll find out what the tile width size should be in the fence setup
931 <jbarnes> it could be that 915 has y tiling but that the minimum width is 512 or something
932 <jbarnes> yeah it's probably 128 on 915 also
933 <jbarnes> it's just that we haven't tested
934 <jbarnes> but I wasn't thinking that the tile widths were the same
935 <jbarnes> only that in order to fence y tiles on 915 you needed pitch to be a multiple of 4 y tiles (or something like that)
936
937 tile_width = format == I915_TILING_Y ? 128 : 512;
938 */
939
940 /* needs a pot tile width */
941 while (tile_width < stride)
942 tile_width <<= 1;
943
944 return tile_width;
945 }
946
947 static inline uint32_t cairo_const
i915_tiling_size(uint32_t tiling,uint32_t size)948 i915_tiling_size (uint32_t tiling, uint32_t size)
949 {
950 uint32_t fence;
951
952 if (tiling == I915_TILING_NONE)
953 return (size + 4095) & -4096;
954
955 fence = 1024 * 1024; /* 1 MiB */
956 while (fence < size)
957 fence <<= 1;
958
959 return fence;
960 }
961
962 static inline cairo_bool_t cairo_const
i915_texture_filter_is_nearest(cairo_filter_t filter)963 i915_texture_filter_is_nearest (cairo_filter_t filter)
964 {
965 switch (filter) {
966 case CAIRO_FILTER_BEST:
967 case CAIRO_FILTER_GOOD:
968 case CAIRO_FILTER_BILINEAR:
969 case CAIRO_FILTER_GAUSSIAN:
970 return FALSE;
971 default:
972 case CAIRO_FILTER_FAST:
973 case CAIRO_FILTER_NEAREST:
974 return TRUE;
975 }
976 }
977
978 static inline uint32_t cairo_const
i915_texture_filter(cairo_filter_t filter)979 i915_texture_filter (cairo_filter_t filter)
980 {
981 switch (filter) {
982 case CAIRO_FILTER_BEST:
983 case CAIRO_FILTER_GOOD:
984 case CAIRO_FILTER_BILINEAR:
985 case CAIRO_FILTER_GAUSSIAN:
986 return
987 (FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
988 (FILTER_LINEAR << SS2_MIN_FILTER_SHIFT);
989 default:
990 case CAIRO_FILTER_FAST:
991 case CAIRO_FILTER_NEAREST:
992 return
993 (FILTER_NEAREST << SS2_MAG_FILTER_SHIFT) |
994 (FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
995 }
996 }
997
998 static inline uint32_t cairo_const
i915_texture_extend(cairo_extend_t extend)999 i915_texture_extend (cairo_extend_t extend)
1000 {
1001 switch (extend) {
1002 default:
1003 case CAIRO_EXTEND_NONE:
1004 return
1005 (TEXCOORDMODE_CLAMP_BORDER << SS3_TCX_ADDR_MODE_SHIFT) |
1006 (TEXCOORDMODE_CLAMP_BORDER << SS3_TCY_ADDR_MODE_SHIFT);
1007 case CAIRO_EXTEND_REPEAT:
1008 return
1009 (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT) |
1010 (TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT);
1011 case CAIRO_EXTEND_PAD:
1012 return
1013 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
1014 (TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT);
1015 case CAIRO_EXTEND_REFLECT:
1016 return
1017 (TEXCOORDMODE_MIRROR << SS3_TCX_ADDR_MODE_SHIFT) |
1018 (TEXCOORDMODE_MIRROR << SS3_TCY_ADDR_MODE_SHIFT);
1019 }
1020 }
1021
1022 static inline uint32_t cairo_const
BUF_tiling(uint32_t tiling)1023 BUF_tiling (uint32_t tiling)
1024 {
1025 switch (tiling) {
1026 default:
1027 case I915_TILING_NONE: return 0;
1028 case I915_TILING_X: return BUF_3D_TILED_SURFACE | BUF_3D_TILE_WALK_X;
1029 case I915_TILING_Y: return BUF_3D_TILED_SURFACE | BUF_3D_TILE_WALK_Y;
1030 }
1031 }
1032
1033 #define OUT_DWORD(dword) i915_batch_emit_dword (device, dword)
1034 #define OUT_RELOC(surface, read, write) i915_batch_emit_reloc (device, to_intel_bo (surface->intel.drm.bo), surface->offset, read, write, FALSE)
1035 #define OUT_RELOC_FENCED(surface, read, write) i915_batch_emit_reloc (device, to_intel_bo (surface->intel.drm.bo), surface->offset, read, write, TRUE)
1036
1037 #define FS_LOCALS \
1038 uint32_t *_shader_start
1039
1040 #define FS_BEGIN() \
1041 do { \
1042 _shader_start = BATCH_PTR (device); \
1043 OUT_DWORD (_3DSTATE_PIXEL_SHADER_PROGRAM); \
1044 } while (0)
1045
1046 #define FS_END() \
1047 do { \
1048 *_shader_start |= BATCH_PTR (device) - _shader_start - 2; \
1049 } while (0);
1050
1051 static inline int32_t
i915_batch_space(i915_device_t * device)1052 i915_batch_space (i915_device_t *device)
1053 {
1054 /* leave room for RECTLIST(4) + MI_BUFFER_END + MI_NOOP */
1055 return sizeof (device->batch_base) - (device->batch.used << 2) - 32;
1056 }
1057
1058 static inline cairo_bool_t
i915_check_aperture_size(const i915_device_t * device,int relocs,size_t est_size,size_t size)1059 i915_check_aperture_size (const i915_device_t *device, int relocs, size_t est_size, size_t size)
1060 {
1061 return device->batch.reloc_count + relocs < I915_MAX_RELOCS - 2 &&
1062 device->batch.est_gtt_size + est_size <= device->batch.gtt_avail_size &&
1063 device->batch.total_gtt_size + size <= device->intel.gtt_avail_size;
1064 }
1065
1066 static inline cairo_bool_t
i915_check_aperture(const i915_device_t * device,intel_bo_t ** bo_array,int count)1067 i915_check_aperture (const i915_device_t *device, intel_bo_t **bo_array, int count)
1068 {
1069 uint32_t relocs = 0, est_size = 0, size = 0;
1070
1071 while (count--) {
1072 const intel_bo_t *bo = *bo_array++;
1073 if (bo->exec == NULL) {
1074 relocs++;
1075 size += bo->base.size;
1076 if (!bo->busy)
1077 est_size += bo->base.size;
1078 }
1079 }
1080
1081 return i915_check_aperture_size (device, relocs, est_size, size);
1082 }
1083
1084 static inline cairo_bool_t
i915_check_aperture_and_fences(const i915_device_t * device,intel_bo_t ** bo_array,int count)1085 i915_check_aperture_and_fences (const i915_device_t *device, intel_bo_t **bo_array, int count)
1086 {
1087 uint32_t relocs = 0, est_size = 0, size = 0;
1088 uint32_t fences = 0;
1089
1090 while (count--) {
1091 const intel_bo_t *bo = *bo_array++;
1092 if (bo->exec == NULL) {
1093 relocs++;
1094 size += bo->base.size;
1095 if (!bo->busy)
1096 est_size += bo->base.size;
1097 if (bo->tiling != I915_TILING_NONE)
1098 fences++;
1099 } else if (bo->tiling != I915_TILING_NONE) {
1100 if ((bo->exec->flags & EXEC_OBJECT_NEEDS_FENCE) == 0)
1101 fences++;
1102 }
1103 }
1104
1105 return i915_check_aperture_size (device, relocs, est_size, size) &&
1106 device->batch.fences + fences <= device->batch.fences_avail;
1107 }
1108
1109 #define BATCH_PTR(device) &(device)->batch_base[(device)->batch.used]
1110 static inline void
i915_batch_emit_dword(i915_device_t * device,uint32_t dword)1111 i915_batch_emit_dword (i915_device_t *device, uint32_t dword)
1112 {
1113 device->batch_base[device->batch.used++] = dword;
1114 }
1115
1116 cairo_private void
1117 i915_batch_add_reloc (i915_device_t *device, uint32_t pos,
1118 intel_bo_t *bo,
1119 uint32_t offset,
1120 uint32_t read_domains,
1121 uint32_t write_domain,
1122 cairo_bool_t needs_fence);
1123
1124 static inline void
i915_batch_fill_reloc(i915_device_t * device,uint32_t pos,intel_bo_t * bo,uint32_t offset,uint32_t read_domains,uint32_t write_domain)1125 i915_batch_fill_reloc (i915_device_t *device, uint32_t pos,
1126 intel_bo_t *bo,
1127 uint32_t offset,
1128 uint32_t read_domains,
1129 uint32_t write_domain)
1130 {
1131 i915_batch_add_reloc (device, pos,
1132 bo, offset,
1133 read_domains, write_domain,
1134 FALSE);
1135 device->batch_base[pos] = bo->offset + offset;
1136 }
1137
1138 static inline void
i915_batch_emit_reloc(i915_device_t * device,intel_bo_t * bo,uint32_t offset,uint32_t read_domains,uint32_t write_domain,cairo_bool_t needs_fence)1139 i915_batch_emit_reloc (i915_device_t *device,
1140 intel_bo_t *bo,
1141 uint32_t offset,
1142 uint32_t read_domains,
1143 uint32_t write_domain,
1144 cairo_bool_t needs_fence)
1145 {
1146 i915_batch_add_reloc (device, device->batch.used,
1147 bo, offset,
1148 read_domains, write_domain,
1149 needs_fence);
1150 i915_batch_emit_dword (device, bo->offset + offset);
1151 }
1152
1153 cairo_private void
1154 i915_vbo_flush (i915_device_t *device);
1155
1156 cairo_private void
1157 i915_vbo_finish (i915_device_t *device);
1158
1159 cairo_private cairo_status_t
1160 i915_batch_flush (i915_device_t *device);
1161
1162 static inline float *
i915_add_rectangle(i915_device_t * device)1163 i915_add_rectangle (i915_device_t *device)
1164 {
1165 float *vertices;
1166 uint32_t size;
1167
1168 assert (device->floats_per_vertex);
1169 assert (device->rectangle_size == 3*device->floats_per_vertex*sizeof(float));
1170
1171 size = device->rectangle_size;
1172 if (unlikely (device->vbo_offset + size > I915_VBO_SIZE))
1173 i915_vbo_finish (device);
1174
1175 vertices = (float *) (device->vbo_base + device->vbo_offset);
1176 device->vbo_used = device->vbo_offset += size;
1177 device->vertex_count += 3;
1178 return vertices;
1179 }
1180
1181 static inline i915_device_t *
i915_device(i915_surface_t * surface)1182 i915_device (i915_surface_t *surface)
1183 {
1184 return (i915_device_t *) surface->intel.drm.base.device;
1185 }
1186
1187 cairo_private cairo_status_t
1188 i915_surface_clear (i915_surface_t *dst);
1189
1190 cairo_private void
1191 i915_set_dst (i915_device_t *device, i915_surface_t *dst);
1192
1193 cairo_private void
1194 i915_shader_init (i915_shader_t *shader,
1195 i915_surface_t *dst,
1196 cairo_operator_t op,
1197 double opacity);
1198
1199 cairo_private cairo_status_t
1200 i915_shader_acquire_pattern (i915_shader_t *shader,
1201 union i915_shader_channel *src,
1202 const cairo_pattern_t *pattern,
1203 const cairo_rectangle_int_t *extents);
1204
1205 cairo_private void
1206 i915_shader_set_clip (i915_shader_t *shader,
1207 cairo_clip_t *clip);
1208
1209 cairo_private int
1210 i915_shader_num_texcoords (const i915_shader_t *shader);
1211
1212 static inline double cairo_const
i915_shader_linear_texcoord(const struct i915_shader_linear * l,double src_x,double src_y)1213 i915_shader_linear_texcoord (const struct i915_shader_linear *l,
1214 double src_x, double src_y)
1215 {
1216 return l->dx * src_x + l->dy * src_y + l->offset;
1217 }
1218
1219 cairo_private cairo_status_t
1220 i915_shader_commit (i915_shader_t *shader,
1221 i915_device_t *device);
1222
1223 cairo_private void
1224 i915_shader_fini (i915_shader_t *shader);
1225
1226 cairo_private cairo_status_t
1227 i915_fixup_unbounded (i915_surface_t *dst,
1228 const cairo_composite_rectangles_t *extents,
1229 cairo_clip_t *clip);
1230
1231 static inline cairo_bool_t
i915_surface_needs_tiling(i915_surface_t * dst)1232 i915_surface_needs_tiling (i915_surface_t *dst)
1233 {
1234 return dst->intel.drm.width > 2048 || dst->intel.drm.height > 2048;
1235 }
1236
1237 cairo_private cairo_status_t
1238 i915_surface_copy_subimage (i915_device_t *device,
1239 i915_surface_t *src,
1240 const cairo_rectangle_int_t *extents,
1241 cairo_bool_t flush,
1242 i915_surface_t **clone_out);
1243
1244 static inline uint32_t
pack_float(float f)1245 pack_float (float f)
1246 {
1247 union {
1248 float f;
1249 uint32_t ui;
1250 } t;
1251 t.f = f;
1252 return t.ui;
1253 }
1254
1255 static inline cairo_status_t
i915_surface_fallback_flush(i915_surface_t * surface)1256 i915_surface_fallback_flush (i915_surface_t *surface)
1257 {
1258 cairo_status_t status;
1259
1260 if (unlikely (surface->intel.drm.fallback != NULL))
1261 return intel_surface_flush (&surface->intel, 0);
1262
1263 status = CAIRO_STATUS_SUCCESS;
1264 if (unlikely (surface->deferred_clear))
1265 status = i915_surface_clear (surface);
1266
1267 return status;
1268 }
1269
1270 #endif /* CAIRO_DRM_I915_PRIVATE_H */
1271