1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <assert.h>
32 #include <stdbool.h>
33 #include <stdint.h>
34 #include <stdio.h>
35 #include <stdlib.h>
36 #include <string.h>
37 #ifdef HAVE_VALGRIND
38 #include <memcheck.h>
39 #include <valgrind.h>
40 #define VG(x) x
41 #else
42 #define VG(x) ((void)0)
43 #endif
44
45 #include "c11/threads.h"
46 #ifndef _WIN32
47 #include <amdgpu.h>
48 #include <xf86drm.h>
49 #endif
50 #include "compiler/shader_enums.h"
51 #include "util/bitscan.h"
52 #include "util/cnd_monotonic.h"
53 #include "util/list.h"
54 #include "util/macros.h"
55 #include "util/rwlock.h"
56 #include "util/xmlconfig.h"
57 #include "vk_alloc.h"
58 #include "vk_debug_report.h"
59 #include "vk_device.h"
60 #include "vk_format.h"
61 #include "vk_instance.h"
62 #include "vk_log.h"
63 #include "vk_physical_device.h"
64 #include "vk_shader_module.h"
65 #include "vk_command_buffer.h"
66 #include "vk_queue.h"
67 #include "vk_util.h"
68
69 #include "ac_binary.h"
70 #include "ac_gpu_info.h"
71 #include "ac_shader_util.h"
72 #include "ac_sqtt.h"
73 #include "ac_surface.h"
74 #include "radv_constants.h"
75 #include "radv_descriptor_set.h"
76 #include "radv_radeon_winsys.h"
77 #include "radv_shader.h"
78 #include "sid.h"
79
80 /* Pre-declarations needed for WSI entrypoints */
81 struct wl_surface;
82 struct wl_display;
83 typedef struct xcb_connection_t xcb_connection_t;
84 typedef uint32_t xcb_visualid_t;
85 typedef uint32_t xcb_window_t;
86
87 #include <vulkan/vk_android_native_buffer.h>
88 #include <vulkan/vk_icd.h>
89 #include <vulkan/vulkan.h>
90 #include <vulkan/vulkan_android.h>
91
92 #include "radv_entrypoints.h"
93
94 #include "wsi_common.h"
95
96 #ifdef __cplusplus
97 extern "C"
98 {
99 #endif
100
101 /* Helper to determine if we should compile
102 * any of the Android AHB support.
103 *
104 * To actually enable the ext we also need
105 * the necessary kernel support.
106 */
107 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
108 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
109 #include <vndk/hardware_buffer.h>
110 #else
111 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
112 #endif
113
114 #ifdef _WIN32
115 #define RADV_SUPPORT_CALIBRATED_TIMESTAMPS 0
116 #else
117 #define RADV_SUPPORT_CALIBRATED_TIMESTAMPS 1
118 #endif
119
120 #ifdef _WIN32
121 #define radv_printflike(a, b)
122 #else
123 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
124 #endif
125
126 static inline uint32_t
align_u32(uint32_t v,uint32_t a)127 align_u32(uint32_t v, uint32_t a)
128 {
129 assert(a != 0 && a == (a & -a));
130 return (v + a - 1) & ~(a - 1);
131 }
132
133 static inline uint32_t
align_u32_npot(uint32_t v,uint32_t a)134 align_u32_npot(uint32_t v, uint32_t a)
135 {
136 return (v + a - 1) / a * a;
137 }
138
139 static inline uint64_t
align_u64(uint64_t v,uint64_t a)140 align_u64(uint64_t v, uint64_t a)
141 {
142 assert(a != 0 && a == (a & -a));
143 return (v + a - 1) & ~(a - 1);
144 }
145
146 static inline int32_t
align_i32(int32_t v,int32_t a)147 align_i32(int32_t v, int32_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 /** Alignment must be a power of 2. */
154 static inline bool
radv_is_aligned(uintmax_t n,uintmax_t a)155 radv_is_aligned(uintmax_t n, uintmax_t a)
156 {
157 assert(a == (a & -a));
158 return (n & (a - 1)) == 0;
159 }
160
161 static inline uint32_t
round_up_u32(uint32_t v,uint32_t a)162 round_up_u32(uint32_t v, uint32_t a)
163 {
164 return (v + a - 1) / a;
165 }
166
167 static inline uint64_t
round_up_u64(uint64_t v,uint64_t a)168 round_up_u64(uint64_t v, uint64_t a)
169 {
170 return (v + a - 1) / a;
171 }
172
173 static inline uint32_t
radv_minify(uint32_t n,uint32_t levels)174 radv_minify(uint32_t n, uint32_t levels)
175 {
176 if (unlikely(n == 0))
177 return 0;
178 else
179 return MAX2(n >> levels, 1);
180 }
181 static inline float
radv_clamp_f(float f,float min,float max)182 radv_clamp_f(float f, float min, float max)
183 {
184 assert(min < max);
185
186 if (f > max)
187 return max;
188 else if (f < min)
189 return min;
190 else
191 return f;
192 }
193
194 static inline bool
radv_clear_mask(uint32_t * inout_mask,uint32_t clear_mask)195 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
196 {
197 if (*inout_mask & clear_mask) {
198 *inout_mask &= ~clear_mask;
199 return true;
200 } else {
201 return false;
202 }
203 }
204
205 /* Whenever we generate an error, pass it through this function. Useful for
206 * debugging, where we can break on it. Only call at error site, not when
207 * propagating errors. Might be useful to plug in a stack trace here.
208 */
209
210 struct radv_image_view;
211 struct radv_instance;
212
213 void radv_loge(const char *format, ...) radv_printflike(1, 2);
214 void radv_loge_v(const char *format, va_list va);
215 void radv_logi(const char *format, ...) radv_printflike(1, 2);
216 void radv_logi_v(const char *format, va_list va);
217
218 /* A non-fatal assert. Useful for debugging. */
219 #ifdef NDEBUG
220 #define radv_assert(x) \
221 do { \
222 } while (0)
223 #else
224 #define radv_assert(x) \
225 do { \
226 if (unlikely(!(x))) \
227 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
228 } while (0)
229 #endif
230
231 int radv_get_instance_entrypoint_index(const char *name);
232 int radv_get_device_entrypoint_index(const char *name);
233 int radv_get_physical_device_entrypoint_index(const char *name);
234
235 const char *radv_get_instance_entry_name(int index);
236 const char *radv_get_physical_device_entry_name(int index);
237 const char *radv_get_device_entry_name(int index);
238
239 struct radv_physical_device {
240 struct vk_physical_device vk;
241
242 /* Link in radv_instance::physical_devices */
243 struct list_head link;
244
245 struct radv_instance *instance;
246
247 struct radeon_winsys *ws;
248 struct radeon_info rad_info;
249 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
250 uint8_t driver_uuid[VK_UUID_SIZE];
251 uint8_t device_uuid[VK_UUID_SIZE];
252 uint8_t cache_uuid[VK_UUID_SIZE];
253
254 int local_fd;
255 int master_fd;
256 struct wsi_device wsi_device;
257
258 bool out_of_order_rast_allowed;
259
260 /* Whether DCC should be enabled for MSAA textures. */
261 bool dcc_msaa_allowed;
262
263 /* Whether to enable NGG. */
264 bool use_ngg;
265
266 /* Whether to enable NGG culling. */
267 bool use_ngg_culling;
268
269 /* Whether to enable NGG streamout. */
270 bool use_ngg_streamout;
271
272 /* Number of threads per wave. */
273 uint8_t ps_wave_size;
274 uint8_t cs_wave_size;
275 uint8_t ge_wave_size;
276
277 /* Whether to use the LLVM compiler backend */
278 bool use_llvm;
279
280 /* This is the drivers on-disk cache used as a fallback as opposed to
281 * the pipeline cache defined by apps.
282 */
283 struct disk_cache *disk_cache;
284
285 VkPhysicalDeviceMemoryProperties memory_properties;
286 enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
287 enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
288 unsigned heaps;
289
290 #ifndef _WIN32
291 int available_nodes;
292 drmPciBusInfo bus_info;
293
294 dev_t primary_devid;
295 dev_t render_devid;
296 #endif
297
298 nir_shader_compiler_options nir_options;
299 };
300
301 struct radv_instance {
302 struct vk_instance vk;
303
304 VkAllocationCallbacks alloc;
305
306 uint64_t debug_flags;
307 uint64_t perftest_flags;
308
309 bool physical_devices_enumerated;
310 struct list_head physical_devices;
311
312 struct driOptionCache dri_options;
313 struct driOptionCache available_dri_options;
314
315 /**
316 * Workarounds for game bugs.
317 */
318 bool enable_mrt_output_nan_fixup;
319 bool disable_tc_compat_htile_in_general;
320 bool disable_shrink_image_store;
321 bool absolute_depth_bias;
322 bool report_apu_as_dgpu;
323 bool disable_htile_layers;
324 };
325
326 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
327 void radv_finish_wsi(struct radv_physical_device *physical_device);
328
329 struct cache_entry;
330
331 struct radv_pipeline_cache {
332 struct vk_object_base base;
333 struct radv_device *device;
334 mtx_t mutex;
335 VkPipelineCacheCreateFlags flags;
336
337 uint32_t total_size;
338 uint32_t table_size;
339 uint32_t kernel_count;
340 struct cache_entry **hash_table;
341 bool modified;
342
343 VkAllocationCallbacks alloc;
344 };
345
346 struct radv_shader_binary;
347 struct radv_shader_variant;
348 struct radv_pipeline_shader_stack_size;
349
350 void radv_pipeline_cache_init(struct radv_pipeline_cache *cache, struct radv_device *device);
351 void radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
352 bool radv_pipeline_cache_load(struct radv_pipeline_cache *cache, const void *data, size_t size);
353
354 bool radv_create_shader_variants_from_pipeline_cache(
355 struct radv_device *device, struct radv_pipeline_cache *cache, const unsigned char *sha1,
356 struct radv_shader_variant **variants, struct radv_pipeline_shader_stack_size **stack_sizes,
357 uint32_t *num_stack_sizes, bool *found_in_application_cache);
358
359 void radv_pipeline_cache_insert_shaders(
360 struct radv_device *device, struct radv_pipeline_cache *cache, const unsigned char *sha1,
361 struct radv_shader_variant **variants, struct radv_shader_binary *const *binaries,
362 const struct radv_pipeline_shader_stack_size *stack_sizes, uint32_t num_stack_sizes);
363
364 enum radv_blit_ds_layout {
365 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
366 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
367 RADV_BLIT_DS_LAYOUT_COUNT,
368 };
369
370 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout)371 radv_meta_blit_ds_to_type(VkImageLayout layout)
372 {
373 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
374 : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
375 }
376
377 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)378 radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
379 {
380 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
381 : VK_IMAGE_LAYOUT_GENERAL;
382 }
383
384 enum radv_meta_dst_layout {
385 RADV_META_DST_LAYOUT_GENERAL,
386 RADV_META_DST_LAYOUT_OPTIMAL,
387 RADV_META_DST_LAYOUT_COUNT,
388 };
389
390 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout)391 radv_meta_dst_layout_from_layout(VkImageLayout layout)
392 {
393 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL
394 : RADV_META_DST_LAYOUT_OPTIMAL;
395 }
396
397 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)398 radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
399 {
400 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
401 : VK_IMAGE_LAYOUT_GENERAL;
402 }
403
404 struct radv_meta_state {
405 VkAllocationCallbacks alloc;
406
407 struct radv_pipeline_cache cache;
408
409 /*
410 * For on-demand pipeline creation, makes sure that
411 * only one thread tries to build a pipeline at the same time.
412 */
413 mtx_t mtx;
414
415 /**
416 * Use array element `i` for images with `2^i` samples.
417 */
418 struct {
419 VkRenderPass render_pass[NUM_META_FS_KEYS];
420 VkPipeline color_pipelines[NUM_META_FS_KEYS];
421
422 VkRenderPass depthstencil_rp;
423 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
424 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
425 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
426
427 VkPipeline depth_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
428 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
429 VkPipeline depthstencil_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
430 } clear[MAX_SAMPLES_LOG2];
431
432 VkPipelineLayout clear_color_p_layout;
433 VkPipelineLayout clear_depth_p_layout;
434 VkPipelineLayout clear_depth_unrestricted_p_layout;
435
436 /* Optimized compute fast HTILE clear for stencil or depth only. */
437 VkPipeline clear_htile_mask_pipeline;
438 VkPipelineLayout clear_htile_mask_p_layout;
439 VkDescriptorSetLayout clear_htile_mask_ds_layout;
440
441 /* Copy VRS into HTILE. */
442 VkPipeline copy_vrs_htile_pipeline;
443 VkPipelineLayout copy_vrs_htile_p_layout;
444 VkDescriptorSetLayout copy_vrs_htile_ds_layout;
445
446 /* Clear DCC with comp-to-single. */
447 VkPipeline clear_dcc_comp_to_single_pipeline[2]; /* 0: 1x, 1: 2x/4x/8x */
448 VkPipelineLayout clear_dcc_comp_to_single_p_layout;
449 VkDescriptorSetLayout clear_dcc_comp_to_single_ds_layout;
450
451 struct {
452 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
453
454 /** Pipeline that blits from a 1D image. */
455 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
456
457 /** Pipeline that blits from a 2D image. */
458 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
459
460 /** Pipeline that blits from a 3D image. */
461 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
462
463 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
464 VkPipeline depth_only_1d_pipeline;
465 VkPipeline depth_only_2d_pipeline;
466 VkPipeline depth_only_3d_pipeline;
467
468 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
469 VkPipeline stencil_only_1d_pipeline;
470 VkPipeline stencil_only_2d_pipeline;
471 VkPipeline stencil_only_3d_pipeline;
472 VkPipelineLayout pipeline_layout;
473 VkDescriptorSetLayout ds_layout;
474 } blit;
475
476 struct {
477 VkPipelineLayout p_layouts[5];
478 VkDescriptorSetLayout ds_layouts[5];
479 VkPipeline pipelines[5][NUM_META_FS_KEYS];
480
481 VkPipeline depth_only_pipeline[5];
482
483 VkPipeline stencil_only_pipeline[5];
484 } blit2d[MAX_SAMPLES_LOG2];
485
486 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
487 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
488 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
489
490 struct {
491 VkPipelineLayout img_p_layout;
492 VkDescriptorSetLayout img_ds_layout;
493 VkPipeline pipeline;
494 VkPipeline pipeline_3d;
495 } itob;
496 struct {
497 VkPipelineLayout img_p_layout;
498 VkDescriptorSetLayout img_ds_layout;
499 VkPipeline pipeline;
500 VkPipeline pipeline_3d;
501 } btoi;
502 struct {
503 VkPipelineLayout img_p_layout;
504 VkDescriptorSetLayout img_ds_layout;
505 VkPipeline pipeline;
506 } btoi_r32g32b32;
507 struct {
508 VkPipelineLayout img_p_layout;
509 VkDescriptorSetLayout img_ds_layout;
510 VkPipeline pipeline[MAX_SAMPLES_LOG2];
511 VkPipeline pipeline_3d;
512 } itoi;
513 struct {
514 VkPipelineLayout img_p_layout;
515 VkDescriptorSetLayout img_ds_layout;
516 VkPipeline pipeline;
517 } itoi_r32g32b32;
518 struct {
519 VkPipelineLayout img_p_layout;
520 VkDescriptorSetLayout img_ds_layout;
521 VkPipeline pipeline[MAX_SAMPLES_LOG2];
522 VkPipeline pipeline_3d;
523 } cleari;
524 struct {
525 VkPipelineLayout img_p_layout;
526 VkDescriptorSetLayout img_ds_layout;
527 VkPipeline pipeline;
528 } cleari_r32g32b32;
529
530 struct {
531 VkPipelineLayout p_layout;
532 VkPipeline pipeline[NUM_META_FS_KEYS];
533 VkRenderPass pass[NUM_META_FS_KEYS];
534 } resolve;
535
536 struct {
537 VkDescriptorSetLayout ds_layout;
538 VkPipelineLayout p_layout;
539 struct {
540 VkPipeline pipeline;
541 VkPipeline i_pipeline;
542 VkPipeline srgb_pipeline;
543 } rc[MAX_SAMPLES_LOG2];
544
545 VkPipeline depth_zero_pipeline;
546 struct {
547 VkPipeline average_pipeline;
548 VkPipeline max_pipeline;
549 VkPipeline min_pipeline;
550 } depth[MAX_SAMPLES_LOG2];
551
552 VkPipeline stencil_zero_pipeline;
553 struct {
554 VkPipeline max_pipeline;
555 VkPipeline min_pipeline;
556 } stencil[MAX_SAMPLES_LOG2];
557 } resolve_compute;
558
559 struct {
560 VkDescriptorSetLayout ds_layout;
561 VkPipelineLayout p_layout;
562
563 struct {
564 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
565 VkPipeline pipeline[NUM_META_FS_KEYS];
566 } rc[MAX_SAMPLES_LOG2];
567
568 VkRenderPass depth_render_pass;
569 VkPipeline depth_zero_pipeline;
570 struct {
571 VkPipeline average_pipeline;
572 VkPipeline max_pipeline;
573 VkPipeline min_pipeline;
574 } depth[MAX_SAMPLES_LOG2];
575
576 VkRenderPass stencil_render_pass;
577 VkPipeline stencil_zero_pipeline;
578 struct {
579 VkPipeline max_pipeline;
580 VkPipeline min_pipeline;
581 } stencil[MAX_SAMPLES_LOG2];
582 } resolve_fragment;
583
584 struct {
585 VkPipelineLayout p_layout;
586 VkPipeline decompress_pipeline;
587 VkPipeline resummarize_pipeline;
588 VkRenderPass pass;
589 } depth_decomp[MAX_SAMPLES_LOG2];
590
591 VkDescriptorSetLayout expand_depth_stencil_compute_ds_layout;
592 VkPipelineLayout expand_depth_stencil_compute_p_layout;
593 VkPipeline expand_depth_stencil_compute_pipeline;
594
595 struct {
596 VkPipelineLayout p_layout;
597 VkPipeline cmask_eliminate_pipeline;
598 VkPipeline fmask_decompress_pipeline;
599 VkPipeline dcc_decompress_pipeline;
600 VkRenderPass pass;
601
602 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
603 VkPipelineLayout dcc_decompress_compute_p_layout;
604 VkPipeline dcc_decompress_compute_pipeline;
605 } fast_clear_flush;
606
607 struct {
608 VkPipelineLayout fill_p_layout;
609 VkPipelineLayout copy_p_layout;
610 VkDescriptorSetLayout fill_ds_layout;
611 VkDescriptorSetLayout copy_ds_layout;
612 VkPipeline fill_pipeline;
613 VkPipeline copy_pipeline;
614 } buffer;
615
616 struct {
617 VkDescriptorSetLayout ds_layout;
618 VkPipelineLayout p_layout;
619 VkPipeline occlusion_query_pipeline;
620 VkPipeline pipeline_statistics_query_pipeline;
621 VkPipeline tfb_query_pipeline;
622 VkPipeline timestamp_query_pipeline;
623 } query;
624
625 struct {
626 VkDescriptorSetLayout ds_layout;
627 VkPipelineLayout p_layout;
628 VkPipeline pipeline[MAX_SAMPLES_LOG2];
629 } fmask_expand;
630
631 struct {
632 VkDescriptorSetLayout ds_layout;
633 VkPipelineLayout p_layout;
634 VkPipeline pipeline[32];
635 } dcc_retile;
636
637 struct {
638 VkPipelineLayout leaf_p_layout;
639 VkPipeline leaf_pipeline;
640 VkPipelineLayout internal_p_layout;
641 VkPipeline internal_pipeline;
642 VkPipelineLayout copy_p_layout;
643 VkPipeline copy_pipeline;
644 } accel_struct_build;
645 };
646
647 /* queue types */
648 #define RADV_QUEUE_GENERAL 0
649 #define RADV_QUEUE_COMPUTE 1
650 #define RADV_QUEUE_TRANSFER 2
651
652 /* Not a real queue family */
653 #define RADV_QUEUE_FOREIGN 3
654
655 #define RADV_MAX_QUEUE_FAMILIES 3
656
657 #define RADV_NUM_HW_CTX (RADEON_CTX_PRIORITY_REALTIME + 1)
658
659 struct radv_deferred_queue_submission;
660
661 enum ring_type radv_queue_family_to_ring(int f);
662
663 struct radv_queue {
664 struct vk_queue vk;
665 struct radv_device *device;
666 struct radeon_winsys_ctx *hw_ctx;
667 enum radeon_ctx_priority priority;
668
669 uint32_t scratch_size_per_wave;
670 uint32_t scratch_waves;
671 uint32_t compute_scratch_size_per_wave;
672 uint32_t compute_scratch_waves;
673 uint32_t esgs_ring_size;
674 uint32_t gsvs_ring_size;
675 bool has_tess_rings;
676 bool has_gds;
677 bool has_gds_oa;
678 bool has_sample_positions;
679
680 struct radeon_winsys_bo *scratch_bo;
681 struct radeon_winsys_bo *descriptor_bo;
682 struct radeon_winsys_bo *compute_scratch_bo;
683 struct radeon_winsys_bo *esgs_ring_bo;
684 struct radeon_winsys_bo *gsvs_ring_bo;
685 struct radeon_winsys_bo *tess_rings_bo;
686 struct radeon_winsys_bo *gds_bo;
687 struct radeon_winsys_bo *gds_oa_bo;
688 struct radeon_cmdbuf *initial_preamble_cs;
689 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
690 struct radeon_cmdbuf *continue_preamble_cs;
691
692 struct list_head pending_submissions;
693 mtx_t pending_mutex;
694
695 mtx_t thread_mutex;
696 struct u_cnd_monotonic thread_cond;
697 struct radv_deferred_queue_submission *thread_submission;
698 thrd_t submission_thread;
699 bool thread_exit;
700 bool thread_running;
701 bool cond_created;
702 };
703
704 #define RADV_BORDER_COLOR_COUNT 4096
705 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
706
707 struct radv_device_border_color_data {
708 bool used[RADV_BORDER_COLOR_COUNT];
709
710 struct radeon_winsys_bo *bo;
711 VkClearColorValue *colors_gpu_ptr;
712
713 /* Mutex is required to guarantee vkCreateSampler thread safety
714 * given that we are writing to a buffer and checking color occupation */
715 mtx_t mutex;
716 };
717
718 enum radv_force_vrs {
719 RADV_FORCE_VRS_NONE = 0,
720 RADV_FORCE_VRS_2x2,
721 RADV_FORCE_VRS_2x1,
722 RADV_FORCE_VRS_1x2,
723 };
724
725 struct radv_device {
726 struct vk_device vk;
727
728 struct radv_instance *instance;
729 struct radeon_winsys *ws;
730
731 struct radeon_winsys_ctx *hw_ctx[RADV_NUM_HW_CTX];
732 struct radv_meta_state meta_state;
733
734 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
735 int queue_count[RADV_MAX_QUEUE_FAMILIES];
736 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
737
738 bool pbb_allowed;
739 uint32_t tess_offchip_block_dw_size;
740 uint32_t scratch_waves;
741 uint32_t dispatch_initiator;
742
743 uint32_t gs_table_depth;
744
745 /* MSAA sample locations.
746 * The first index is the sample index.
747 * The second index is the coordinate: X, Y. */
748 float sample_locations_1x[1][2];
749 float sample_locations_2x[2][2];
750 float sample_locations_4x[4][2];
751 float sample_locations_8x[8][2];
752
753 /* GFX7 and later */
754 uint32_t gfx_init_size_dw;
755 struct radeon_winsys_bo *gfx_init;
756
757 struct radeon_winsys_bo *trace_bo;
758 uint32_t *trace_id_ptr;
759
760 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
761 bool keep_shader_info;
762
763 struct radv_physical_device *physical_device;
764
765 /* Backup in-memory cache to be used if the app doesn't provide one */
766 struct radv_pipeline_cache *mem_cache;
767
768 /*
769 * use different counters so MSAA MRTs get consecutive surface indices,
770 * even if MASK is allocated in between.
771 */
772 uint32_t image_mrt_offset_counter;
773 uint32_t fmask_mrt_offset_counter;
774
775 struct list_head shader_arenas;
776 uint8_t shader_free_list_mask;
777 struct list_head shader_free_lists[RADV_SHADER_ALLOC_NUM_FREE_LISTS];
778 struct list_head shader_block_obj_pool;
779 mtx_t shader_arena_mutex;
780
781 /* For detecting VM faults reported by dmesg. */
782 uint64_t dmesg_timestamp;
783
784 /* Whether the app has enabled the robustBufferAccess/robustBufferAccess2 features. */
785 bool robust_buffer_access;
786 bool robust_buffer_access2;
787
788 /* Whether gl_FragCoord.z should be adjusted for VRS due to a hw bug
789 * on some GFX10.3 chips.
790 */
791 bool adjust_frag_coord_z;
792
793 /* Whether the driver uses a global BO list. */
794 bool use_global_bo_list;
795
796 /* Whether attachment VRS is enabled. */
797 bool attachment_vrs_enabled;
798
799 /* Whether shader image 32-bit float atomics are enabled. */
800 bool image_float32_atomics;
801
802 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
803 int force_aniso;
804
805 struct radv_device_border_color_data border_color_data;
806
807 /* Condition variable for legacy timelines, to notify waiters when a
808 * new point gets submitted. */
809 struct u_cnd_monotonic timeline_cond;
810
811 /* Thread trace. */
812 struct ac_thread_trace_data thread_trace;
813
814 /* Trap handler. */
815 struct radv_shader_variant *trap_handler_shader;
816 struct radeon_winsys_bo *tma_bo; /* Trap Memory Address */
817 uint32_t *tma_ptr;
818
819 /* Overallocation. */
820 bool overallocation_disallowed;
821 uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
822 mtx_t overallocation_mutex;
823
824 /* Track the number of device loss occurs. */
825 int lost;
826
827 /* Whether the user forced VRS rates on GFX10.3+. */
828 enum radv_force_vrs force_vrs;
829
830 /* Depth image for VRS when not bound by the app. */
831 struct {
832 struct radv_image *image;
833 struct radv_buffer *buffer; /* HTILE */
834 struct radv_device_memory *mem;
835 } vrs;
836
837 struct u_rwlock vs_prologs_lock;
838 struct hash_table *vs_prologs;
839
840 struct radv_shader_prolog *simple_vs_prologs[MAX_VERTEX_ATTRIBS];
841 struct radv_shader_prolog *instance_rate_vs_prologs[816];
842 };
843
844 VkResult _radv_device_set_lost(struct radv_device *device, const char *file, int line,
845 const char *msg, ...) radv_printflike(4, 5);
846
847 #define radv_device_set_lost(dev, ...) _radv_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__)
848
849 static inline bool
radv_device_is_lost(const struct radv_device * device)850 radv_device_is_lost(const struct radv_device *device)
851 {
852 return unlikely(p_atomic_read(&device->lost));
853 }
854
855 struct radv_device_memory {
856 struct vk_object_base base;
857 struct radeon_winsys_bo *bo;
858 /* for dedicated allocations */
859 struct radv_image *image;
860 struct radv_buffer *buffer;
861 uint32_t heap_index;
862 uint64_t alloc_size;
863 void *map;
864 void *user_ptr;
865
866 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
867 struct AHardwareBuffer *android_hardware_buffer;
868 #endif
869 };
870
871 void radv_device_memory_init(struct radv_device_memory *mem, struct radv_device *device,
872 struct radeon_winsys_bo *bo);
873 void radv_device_memory_finish(struct radv_device_memory *mem);
874
875 struct radv_descriptor_range {
876 uint64_t va;
877 uint32_t size;
878 };
879
880 struct radv_descriptor_set_header {
881 struct vk_object_base base;
882 const struct radv_descriptor_set_layout *layout;
883 uint32_t size;
884 uint32_t buffer_count;
885
886 struct radeon_winsys_bo *bo;
887 uint64_t va;
888 uint32_t *mapped_ptr;
889 struct radv_descriptor_range *dynamic_descriptors;
890 };
891
892 struct radv_descriptor_set {
893 struct radv_descriptor_set_header header;
894
895 struct radeon_winsys_bo *descriptors[];
896 };
897
898 struct radv_push_descriptor_set {
899 struct radv_descriptor_set_header set;
900 uint32_t capacity;
901 };
902
903 struct radv_descriptor_pool_entry {
904 uint32_t offset;
905 uint32_t size;
906 struct radv_descriptor_set *set;
907 };
908
909 struct radv_descriptor_pool {
910 struct vk_object_base base;
911 struct radeon_winsys_bo *bo;
912 uint8_t *host_bo;
913 uint8_t *mapped_ptr;
914 uint64_t current_offset;
915 uint64_t size;
916
917 uint8_t *host_memory_base;
918 uint8_t *host_memory_ptr;
919 uint8_t *host_memory_end;
920
921 uint32_t entry_count;
922 uint32_t max_entry_count;
923 struct radv_descriptor_pool_entry entries[0];
924 };
925
926 struct radv_descriptor_update_template_entry {
927 VkDescriptorType descriptor_type;
928
929 /* The number of descriptors to update */
930 uint32_t descriptor_count;
931
932 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
933 uint32_t dst_offset;
934
935 /* In dwords. Not valid/used for dynamic descriptors */
936 uint32_t dst_stride;
937
938 uint32_t buffer_offset;
939
940 /* Only valid for combined image samplers and samplers */
941 uint8_t has_sampler;
942 uint8_t sampler_offset;
943
944 /* In bytes */
945 size_t src_offset;
946 size_t src_stride;
947
948 /* For push descriptors */
949 const uint32_t *immutable_samplers;
950 };
951
952 struct radv_descriptor_update_template {
953 struct vk_object_base base;
954 uint32_t entry_count;
955 VkPipelineBindPoint bind_point;
956 struct radv_descriptor_update_template_entry entry[0];
957 };
958
959 struct radv_buffer {
960 struct vk_object_base base;
961 VkDeviceSize size;
962
963 VkBufferUsageFlags usage;
964 VkBufferCreateFlags flags;
965
966 /* Set when bound */
967 struct radeon_winsys_bo *bo;
968 VkDeviceSize offset;
969
970 bool shareable;
971 };
972
973 void radv_buffer_init(struct radv_buffer *buffer, struct radv_device *device,
974 struct radeon_winsys_bo *bo, uint64_t size, uint64_t offset);
975 void radv_buffer_finish(struct radv_buffer *buffer);
976
977 enum radv_dynamic_state_bits {
978 RADV_DYNAMIC_VIEWPORT = 1ull << 0,
979 RADV_DYNAMIC_SCISSOR = 1ull << 1,
980 RADV_DYNAMIC_LINE_WIDTH = 1ull << 2,
981 RADV_DYNAMIC_DEPTH_BIAS = 1ull << 3,
982 RADV_DYNAMIC_BLEND_CONSTANTS = 1ull << 4,
983 RADV_DYNAMIC_DEPTH_BOUNDS = 1ull << 5,
984 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1ull << 6,
985 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1ull << 7,
986 RADV_DYNAMIC_STENCIL_REFERENCE = 1ull << 8,
987 RADV_DYNAMIC_DISCARD_RECTANGLE = 1ull << 9,
988 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1ull << 10,
989 RADV_DYNAMIC_LINE_STIPPLE = 1ull << 11,
990 RADV_DYNAMIC_CULL_MODE = 1ull << 12,
991 RADV_DYNAMIC_FRONT_FACE = 1ull << 13,
992 RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1ull << 14,
993 RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1ull << 15,
994 RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1ull << 16,
995 RADV_DYNAMIC_DEPTH_COMPARE_OP = 1ull << 17,
996 RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1ull << 18,
997 RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1ull << 19,
998 RADV_DYNAMIC_STENCIL_OP = 1ull << 20,
999 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1ull << 21,
1000 RADV_DYNAMIC_FRAGMENT_SHADING_RATE = 1ull << 22,
1001 RADV_DYNAMIC_PATCH_CONTROL_POINTS = 1ull << 23,
1002 RADV_DYNAMIC_RASTERIZER_DISCARD_ENABLE = 1ull << 24,
1003 RADV_DYNAMIC_DEPTH_BIAS_ENABLE = 1ull << 25,
1004 RADV_DYNAMIC_LOGIC_OP = 1ull << 26,
1005 RADV_DYNAMIC_PRIMITIVE_RESTART_ENABLE = 1ull << 27,
1006 RADV_DYNAMIC_COLOR_WRITE_ENABLE = 1ull << 28,
1007 RADV_DYNAMIC_VERTEX_INPUT = 1ull << 29,
1008 RADV_DYNAMIC_ALL = (1ull << 30) - 1,
1009 };
1010
1011 enum radv_cmd_dirty_bits {
1012 /* Keep the dynamic state dirty bits in sync with
1013 * enum radv_dynamic_state_bits */
1014 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1ull << 0,
1015 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1ull << 1,
1016 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1ull << 2,
1017 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1ull << 3,
1018 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1ull << 4,
1019 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1ull << 5,
1020 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1ull << 6,
1021 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1ull << 7,
1022 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1ull << 8,
1023 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1ull << 9,
1024 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1ull << 10,
1025 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1ull << 11,
1026 RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1ull << 12,
1027 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1ull << 13,
1028 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1ull << 14,
1029 RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1ull << 15,
1030 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1ull << 16,
1031 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1ull << 17,
1032 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1ull << 18,
1033 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1ull << 19,
1034 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1ull << 20,
1035 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1ull << 21,
1036 RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE = 1ull << 22,
1037 RADV_CMD_DIRTY_DYNAMIC_PATCH_CONTROL_POINTS = 1ull << 23,
1038 RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE = 1ull << 24,
1039 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE = 1ull << 25,
1040 RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP = 1ull << 26,
1041 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE = 1ull << 27,
1042 RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE = 1ull << 28,
1043 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT = 1ull << 29,
1044 RADV_CMD_DIRTY_DYNAMIC_ALL = (1ull << 30) - 1,
1045 RADV_CMD_DIRTY_PIPELINE = 1ull << 30,
1046 RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 31,
1047 RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 32,
1048 RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 33,
1049 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 34,
1050 };
1051
1052 enum radv_cmd_flush_bits {
1053 /* Instruction cache. */
1054 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
1055 /* Scalar L1 cache. */
1056 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
1057 /* Vector L1 cache. */
1058 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
1059 /* L2 cache + L2 metadata cache writeback & invalidate.
1060 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1061 RADV_CMD_FLAG_INV_L2 = 1 << 3,
1062 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1063 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1064 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1065 RADV_CMD_FLAG_WB_L2 = 1 << 4,
1066 /* Invalidate the metadata cache. To be used when the DCC/HTILE metadata
1067 * changed and we want to read an image from shaders. */
1068 RADV_CMD_FLAG_INV_L2_METADATA = 1 << 5,
1069 /* Framebuffer caches */
1070 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 6,
1071 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 7,
1072 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 8,
1073 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 9,
1074 /* Engine synchronization. */
1075 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 10,
1076 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 11,
1077 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 12,
1078 RADV_CMD_FLAG_VGT_FLUSH = 1 << 13,
1079 /* Pipeline query controls. */
1080 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 14,
1081 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 15,
1082 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 16,
1083
1084 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER =
1085 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1086 RADV_CMD_FLAG_FLUSH_AND_INV_DB | RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
1087 };
1088
1089 struct radv_vertex_binding {
1090 struct radv_buffer *buffer;
1091 VkDeviceSize offset;
1092 VkDeviceSize size;
1093 VkDeviceSize stride;
1094 };
1095
1096 struct radv_streamout_binding {
1097 struct radv_buffer *buffer;
1098 VkDeviceSize offset;
1099 VkDeviceSize size;
1100 };
1101
1102 struct radv_streamout_state {
1103 /* Mask of bound streamout buffers. */
1104 uint8_t enabled_mask;
1105
1106 /* External state that comes from the last vertex stage, it must be
1107 * set explicitely when binding a new graphics pipeline.
1108 */
1109 uint16_t stride_in_dw[MAX_SO_BUFFERS];
1110 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
1111
1112 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1113 uint32_t hw_enabled_mask;
1114
1115 /* State of VGT_STRMOUT_(CONFIG|EN) */
1116 bool streamout_enabled;
1117 };
1118
1119 struct radv_viewport_state {
1120 uint32_t count;
1121 VkViewport viewports[MAX_VIEWPORTS];
1122 struct {
1123 float scale[3];
1124 float translate[3];
1125 } xform[MAX_VIEWPORTS];
1126 };
1127
1128 struct radv_scissor_state {
1129 uint32_t count;
1130 VkRect2D scissors[MAX_SCISSORS];
1131 };
1132
1133 struct radv_discard_rectangle_state {
1134 uint32_t count;
1135 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
1136 };
1137
1138 struct radv_sample_locations_state {
1139 VkSampleCountFlagBits per_pixel;
1140 VkExtent2D grid_size;
1141 uint32_t count;
1142 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
1143 };
1144
1145 struct radv_dynamic_state {
1146 /**
1147 * Bitmask of (1ull << VK_DYNAMIC_STATE_*).
1148 * Defines the set of saved dynamic state.
1149 */
1150 uint64_t mask;
1151
1152 struct radv_viewport_state viewport;
1153
1154 struct radv_scissor_state scissor;
1155
1156 float line_width;
1157
1158 struct {
1159 float bias;
1160 float clamp;
1161 float slope;
1162 } depth_bias;
1163
1164 float blend_constants[4];
1165
1166 struct {
1167 float min;
1168 float max;
1169 } depth_bounds;
1170
1171 struct {
1172 uint32_t front;
1173 uint32_t back;
1174 } stencil_compare_mask;
1175
1176 struct {
1177 uint32_t front;
1178 uint32_t back;
1179 } stencil_write_mask;
1180
1181 struct {
1182 struct {
1183 VkStencilOp fail_op;
1184 VkStencilOp pass_op;
1185 VkStencilOp depth_fail_op;
1186 VkCompareOp compare_op;
1187 } front;
1188
1189 struct {
1190 VkStencilOp fail_op;
1191 VkStencilOp pass_op;
1192 VkStencilOp depth_fail_op;
1193 VkCompareOp compare_op;
1194 } back;
1195 } stencil_op;
1196
1197 struct {
1198 uint32_t front;
1199 uint32_t back;
1200 } stencil_reference;
1201
1202 struct radv_discard_rectangle_state discard_rectangle;
1203
1204 struct radv_sample_locations_state sample_location;
1205
1206 struct {
1207 uint32_t factor;
1208 uint16_t pattern;
1209 } line_stipple;
1210
1211 VkCullModeFlags cull_mode;
1212 VkFrontFace front_face;
1213 unsigned primitive_topology;
1214
1215 bool depth_test_enable;
1216 bool depth_write_enable;
1217 VkCompareOp depth_compare_op;
1218 bool depth_bounds_test_enable;
1219 bool stencil_test_enable;
1220
1221 struct {
1222 VkExtent2D size;
1223 VkFragmentShadingRateCombinerOpKHR combiner_ops[2];
1224 } fragment_shading_rate;
1225
1226 bool depth_bias_enable;
1227 bool primitive_restart_enable;
1228 bool rasterizer_discard_enable;
1229
1230 unsigned logic_op;
1231
1232 uint32_t color_write_enable;
1233 };
1234
1235 extern const struct radv_dynamic_state default_dynamic_state;
1236
1237 const char *radv_get_debug_option_name(int id);
1238
1239 const char *radv_get_perftest_option_name(int id);
1240
1241 int radv_get_int_debug_option(const char *name, int default_value);
1242
1243 struct radv_color_buffer_info {
1244 uint64_t cb_color_base;
1245 uint64_t cb_color_cmask;
1246 uint64_t cb_color_fmask;
1247 uint64_t cb_dcc_base;
1248 uint32_t cb_color_slice;
1249 uint32_t cb_color_view;
1250 uint32_t cb_color_info;
1251 uint32_t cb_color_attrib;
1252 uint32_t cb_color_attrib2; /* GFX9 and later */
1253 uint32_t cb_color_attrib3; /* GFX10 and later */
1254 uint32_t cb_dcc_control;
1255 uint32_t cb_color_cmask_slice;
1256 uint32_t cb_color_fmask_slice;
1257 union {
1258 uint32_t cb_color_pitch; // GFX6-GFX8
1259 uint32_t cb_mrt_epitch; // GFX9+
1260 };
1261 };
1262
1263 struct radv_ds_buffer_info {
1264 uint64_t db_z_read_base;
1265 uint64_t db_stencil_read_base;
1266 uint64_t db_z_write_base;
1267 uint64_t db_stencil_write_base;
1268 uint64_t db_htile_data_base;
1269 uint32_t db_depth_info;
1270 uint32_t db_z_info;
1271 uint32_t db_stencil_info;
1272 uint32_t db_depth_view;
1273 uint32_t db_depth_size;
1274 uint32_t db_depth_slice;
1275 uint32_t db_htile_surface;
1276 uint32_t pa_su_poly_offset_db_fmt_cntl;
1277 uint32_t db_z_info2; /* GFX9 only */
1278 uint32_t db_stencil_info2; /* GFX9 only */
1279 };
1280
1281 void radv_initialise_color_surface(struct radv_device *device, struct radv_color_buffer_info *cb,
1282 struct radv_image_view *iview);
1283 void radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_info *ds,
1284 struct radv_image_view *iview);
1285 void radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_buffer,
1286 struct radv_ds_buffer_info *ds);
1287
1288 /**
1289 * Attachment state when recording a renderpass instance.
1290 *
1291 * The clear value is valid only if there exists a pending clear.
1292 */
1293 struct radv_attachment_state {
1294 VkImageAspectFlags pending_clear_aspects;
1295 uint32_t cleared_views;
1296 VkClearValue clear_value;
1297 VkImageLayout current_layout;
1298 VkImageLayout current_stencil_layout;
1299 bool current_in_render_loop;
1300 bool disable_dcc;
1301 struct radv_sample_locations_state sample_location;
1302
1303 union {
1304 struct radv_color_buffer_info cb;
1305 struct radv_ds_buffer_info ds;
1306 };
1307 struct radv_image_view *iview;
1308 };
1309
1310 struct radv_descriptor_state {
1311 struct radv_descriptor_set *sets[MAX_SETS];
1312 uint32_t dirty;
1313 uint32_t valid;
1314 struct radv_push_descriptor_set push_set;
1315 bool push_dirty;
1316 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1317 };
1318
1319 struct radv_subpass_sample_locs_state {
1320 uint32_t subpass_idx;
1321 struct radv_sample_locations_state sample_location;
1322 };
1323
1324 enum rgp_flush_bits {
1325 RGP_FLUSH_WAIT_ON_EOP_TS = 0x1,
1326 RGP_FLUSH_VS_PARTIAL_FLUSH = 0x2,
1327 RGP_FLUSH_PS_PARTIAL_FLUSH = 0x4,
1328 RGP_FLUSH_CS_PARTIAL_FLUSH = 0x8,
1329 RGP_FLUSH_PFP_SYNC_ME = 0x10,
1330 RGP_FLUSH_SYNC_CP_DMA = 0x20,
1331 RGP_FLUSH_INVAL_VMEM_L0 = 0x40,
1332 RGP_FLUSH_INVAL_ICACHE = 0x80,
1333 RGP_FLUSH_INVAL_SMEM_L0 = 0x100,
1334 RGP_FLUSH_FLUSH_L2 = 0x200,
1335 RGP_FLUSH_INVAL_L2 = 0x400,
1336 RGP_FLUSH_FLUSH_CB = 0x800,
1337 RGP_FLUSH_INVAL_CB = 0x1000,
1338 RGP_FLUSH_FLUSH_DB = 0x2000,
1339 RGP_FLUSH_INVAL_DB = 0x4000,
1340 RGP_FLUSH_INVAL_L1 = 0x8000,
1341 };
1342
1343 struct radv_cmd_state {
1344 /* Vertex descriptors */
1345 uint64_t vb_va;
1346
1347 bool predicating;
1348 uint64_t dirty;
1349
1350 uint32_t prefetch_L2_mask;
1351
1352 struct radv_pipeline *pipeline;
1353 struct radv_pipeline *emitted_pipeline;
1354 struct radv_pipeline *compute_pipeline;
1355 struct radv_pipeline *emitted_compute_pipeline;
1356 struct radv_pipeline *rt_pipeline; /* emitted = emitted_compute_pipeline */
1357 struct radv_framebuffer *framebuffer;
1358 struct radv_render_pass *pass;
1359 const struct radv_subpass *subpass;
1360 struct radv_dynamic_state dynamic;
1361 struct radv_vs_input_state dynamic_vs_input;
1362 struct radv_attachment_state *attachments;
1363 struct radv_streamout_state streamout;
1364 VkRect2D render_area;
1365
1366 uint32_t num_subpass_sample_locs;
1367 struct radv_subpass_sample_locs_state *subpass_sample_locs;
1368
1369 /* Index buffer */
1370 struct radv_buffer *index_buffer;
1371 uint64_t index_offset;
1372 uint32_t index_type;
1373 uint32_t max_index_count;
1374 uint64_t index_va;
1375 int32_t last_index_type;
1376
1377 int32_t last_primitive_reset_en;
1378 uint32_t last_primitive_reset_index;
1379 enum radv_cmd_flush_bits flush_bits;
1380 unsigned active_occlusion_queries;
1381 bool perfect_occlusion_queries_enabled;
1382 unsigned active_pipeline_queries;
1383 unsigned active_pipeline_gds_queries;
1384 uint32_t trace_id;
1385 uint32_t last_ia_multi_vgt_param;
1386
1387 uint32_t last_num_instances;
1388 uint32_t last_first_instance;
1389 uint32_t last_vertex_offset;
1390 uint32_t last_drawid;
1391
1392 uint32_t last_sx_ps_downconvert;
1393 uint32_t last_sx_blend_opt_epsilon;
1394 uint32_t last_sx_blend_opt_control;
1395
1396 /* Whether CP DMA is busy/idle. */
1397 bool dma_is_busy;
1398
1399 /* Whether any images that are not L2 coherent are dirty from the CB. */
1400 bool rb_noncoherent_dirty;
1401
1402 /* Conditional rendering info. */
1403 uint8_t predication_op; /* 32-bit or 64-bit predicate value */
1404 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1405 uint64_t predication_va;
1406
1407 /* Inheritance info. */
1408 VkQueryPipelineStatisticFlags inherited_pipeline_statistics;
1409
1410 bool context_roll_without_scissor_emitted;
1411
1412 /* SQTT related state. */
1413 uint32_t current_event_type;
1414 uint32_t num_events;
1415 uint32_t num_layout_transitions;
1416 bool pending_sqtt_barrier_end;
1417 enum rgp_flush_bits sqtt_flush_bits;
1418
1419 /* NGG culling state. */
1420 uint32_t last_nggc_settings;
1421 int8_t last_nggc_settings_sgpr_idx;
1422 bool last_nggc_skip;
1423
1424 uint8_t cb_mip[MAX_RTS];
1425
1426 /* Whether DRAW_{INDEX}_INDIRECT_MULTI is emitted. */
1427 bool uses_draw_indirect_multi;
1428
1429 uint32_t rt_stack_size;
1430
1431 struct radv_shader_prolog *emitted_vs_prolog;
1432 uint32_t *emitted_vs_prolog_key;
1433 uint32_t emitted_vs_prolog_key_hash;
1434 uint32_t vbo_misaligned_mask;
1435 uint32_t vbo_bound_mask;
1436 };
1437
1438 struct radv_cmd_pool {
1439 struct vk_object_base base;
1440 VkAllocationCallbacks alloc;
1441 struct list_head cmd_buffers;
1442 struct list_head free_cmd_buffers;
1443 uint32_t queue_family_index;
1444 };
1445
1446 struct radv_cmd_buffer_upload {
1447 uint8_t *map;
1448 unsigned offset;
1449 uint64_t size;
1450 struct radeon_winsys_bo *upload_bo;
1451 struct list_head list;
1452 };
1453
1454 enum radv_cmd_buffer_status {
1455 RADV_CMD_BUFFER_STATUS_INVALID,
1456 RADV_CMD_BUFFER_STATUS_INITIAL,
1457 RADV_CMD_BUFFER_STATUS_RECORDING,
1458 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1459 RADV_CMD_BUFFER_STATUS_PENDING,
1460 };
1461
1462 struct radv_cmd_buffer {
1463 struct vk_command_buffer vk;
1464
1465 struct radv_device *device;
1466
1467 struct radv_cmd_pool *pool;
1468 struct list_head pool_link;
1469
1470 VkCommandBufferUsageFlags usage_flags;
1471 VkCommandBufferLevel level;
1472 enum radv_cmd_buffer_status status;
1473 struct radeon_cmdbuf *cs;
1474 struct radv_cmd_state state;
1475 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1476 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1477 uint32_t queue_family_index;
1478
1479 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1480 VkShaderStageFlags push_constant_stages;
1481 struct radv_descriptor_set_header meta_push_descriptors;
1482
1483 struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
1484
1485 struct radv_cmd_buffer_upload upload;
1486
1487 uint32_t scratch_size_per_wave_needed;
1488 uint32_t scratch_waves_wanted;
1489 uint32_t compute_scratch_size_per_wave_needed;
1490 uint32_t compute_scratch_waves_wanted;
1491 uint32_t esgs_ring_size_needed;
1492 uint32_t gsvs_ring_size_needed;
1493 bool tess_rings_needed;
1494 bool gds_needed; /* for GFX10 streamout and NGG GS queries */
1495 bool gds_oa_needed; /* for GFX10 streamout */
1496 bool sample_positions_needed;
1497
1498 VkResult record_result;
1499
1500 uint64_t gfx9_fence_va;
1501 uint32_t gfx9_fence_idx;
1502 uint64_t gfx9_eop_bug_va;
1503
1504 /**
1505 * Whether a query pool has been resetted and we have to flush caches.
1506 */
1507 bool pending_reset_query;
1508
1509 /**
1510 * Bitmask of pending active query flushes.
1511 */
1512 enum radv_cmd_flush_bits active_query_flush_bits;
1513 };
1514
1515 struct radv_image;
1516 struct radv_image_view;
1517
1518 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1519
1520 void si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs);
1521 void si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs);
1522
1523 void cik_create_gfx_config(struct radv_device *device);
1524
1525 void si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors,
1526 const VkViewport *viewports, bool can_use_guardband);
1527 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw,
1528 bool indirect_draw, bool count_from_stream_output,
1529 uint32_t draw_vertex_count, unsigned topology,
1530 bool prim_restart_enable);
1531 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, bool is_mec,
1532 unsigned event, unsigned event_flags, unsigned dst_sel,
1533 unsigned data_sel, uint64_t va, uint32_t new_fence,
1534 uint64_t gfx9_eop_bug_va);
1535
1536 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, uint32_t ref,
1537 uint32_t mask);
1538 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class,
1539 uint32_t *fence_ptr, uint64_t va, bool is_mec,
1540 enum radv_cmd_flush_bits flush_bits,
1541 enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va);
1542 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1543 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visible,
1544 unsigned pred_op, uint64_t va);
1545 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t dest_va,
1546 uint64_t size);
1547 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va, unsigned size);
1548 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size,
1549 unsigned value);
1550 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1551
1552 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1553
1554 unsigned radv_instance_rate_prolog_index(unsigned num_attributes, uint32_t instance_rate_inputs);
1555 uint32_t radv_hash_vs_prolog(const void *key_);
1556 bool radv_cmp_vs_prolog(const void *a_, const void *b_);
1557
1558 bool radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer, unsigned size,
1559 unsigned *out_offset, void **ptr);
1560 void radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1561 const struct radv_subpass *subpass);
1562 void radv_cmd_buffer_restore_subpass(struct radv_cmd_buffer *cmd_buffer,
1563 const struct radv_subpass *subpass);
1564 bool radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer, unsigned size,
1565 const void *data, unsigned *out_offset);
1566
1567 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1568 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1569 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1570 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1571 VkImageAspectFlags aspects,
1572 VkResolveModeFlagBits resolve_mode);
1573 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1574 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1575 VkImageAspectFlags aspects,
1576 VkResolveModeFlagBits resolve_mode);
1577 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1578 unsigned radv_get_default_max_sample_dist(int log_samples);
1579 void radv_device_init_msaa(struct radv_device *device);
1580 VkResult radv_device_init_vrs_state(struct radv_device *device);
1581
1582 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1583 const struct radv_image_view *iview,
1584 VkClearDepthStencilValue ds_clear_value,
1585 VkImageAspectFlags aspects);
1586
1587 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1588 const struct radv_image_view *iview, int cb_idx,
1589 uint32_t color_values[2]);
1590
1591 bool radv_image_use_dcc_image_stores(const struct radv_device *device,
1592 const struct radv_image *image);
1593 bool radv_image_use_dcc_predication(const struct radv_device *device,
1594 const struct radv_image *image);
1595
1596 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
1597 const VkImageSubresourceRange *range, bool value);
1598
1599 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
1600 const VkImageSubresourceRange *range, bool value);
1601 enum radv_cmd_flush_bits radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1602 VkAccessFlags src_flags,
1603 const struct radv_image *image);
1604 enum radv_cmd_flush_bits radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1605 VkAccessFlags dst_flags,
1606 const struct radv_image *image);
1607 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
1608 struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
1609 uint32_t value);
1610 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1611 bool radv_get_memory_fd(struct radv_device *device, struct radv_device_memory *memory, int *pFD);
1612 void radv_free_memory(struct radv_device *device, const VkAllocationCallbacks *pAllocator,
1613 struct radv_device_memory *mem);
1614
1615 static inline void
radv_emit_shader_pointer_head(struct radeon_cmdbuf * cs,unsigned sh_offset,unsigned pointer_count,bool use_32bit_pointers)1616 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs, unsigned sh_offset, unsigned pointer_count,
1617 bool use_32bit_pointers)
1618 {
1619 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1620 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1621 }
1622
1623 static inline void
radv_emit_shader_pointer_body(struct radv_device * device,struct radeon_cmdbuf * cs,uint64_t va,bool use_32bit_pointers)1624 radv_emit_shader_pointer_body(struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va,
1625 bool use_32bit_pointers)
1626 {
1627 radeon_emit(cs, va);
1628
1629 if (use_32bit_pointers) {
1630 assert(va == 0 || (va >> 32) == device->physical_device->rad_info.address32_hi);
1631 } else {
1632 radeon_emit(cs, va >> 32);
1633 }
1634 }
1635
1636 static inline void
radv_emit_shader_pointer(struct radv_device * device,struct radeon_cmdbuf * cs,uint32_t sh_offset,uint64_t va,bool global)1637 radv_emit_shader_pointer(struct radv_device *device, struct radeon_cmdbuf *cs, uint32_t sh_offset,
1638 uint64_t va, bool global)
1639 {
1640 bool use_32bit_pointers = !global;
1641
1642 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1643 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1644 }
1645
1646 static inline struct radv_descriptor_state *
radv_get_descriptors_state(struct radv_cmd_buffer * cmd_buffer,VkPipelineBindPoint bind_point)1647 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bind_point)
1648 {
1649 switch (bind_point) {
1650 case VK_PIPELINE_BIND_POINT_GRAPHICS:
1651 case VK_PIPELINE_BIND_POINT_COMPUTE:
1652 return &cmd_buffer->descriptors[bind_point];
1653 case VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR:
1654 return &cmd_buffer->descriptors[2];
1655 default:
1656 unreachable("Unhandled bind point");
1657 }
1658 }
1659
1660 void
1661 radv_get_viewport_xform(const VkViewport *viewport, float scale[3], float translate[3]);
1662
1663 /*
1664 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1665 *
1666 * Limitations: Can't call normal dispatch functions without binding or rebinding
1667 * the compute pipeline.
1668 */
1669 void radv_unaligned_dispatch(struct radv_cmd_buffer *cmd_buffer, uint32_t x, uint32_t y,
1670 uint32_t z);
1671
1672 void radv_indirect_dispatch(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *bo,
1673 uint64_t va);
1674
1675 struct radv_event {
1676 struct vk_object_base base;
1677 struct radeon_winsys_bo *bo;
1678 uint64_t *map;
1679 };
1680
1681 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1682 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1683 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1684 #define RADV_HASH_SHADER_LLVM (1 << 4)
1685 #define RADV_HASH_SHADER_KEEP_STATISTICS (1 << 8)
1686 #define RADV_HASH_SHADER_USE_NGG_CULLING (1 << 13)
1687 #define RADV_HASH_SHADER_ROBUST_BUFFER_ACCESS (1 << 14)
1688 #define RADV_HASH_SHADER_ROBUST_BUFFER_ACCESS2 (1 << 15)
1689 #define RADV_HASH_SHADER_FORCE_EMULATE_RT (1 << 16)
1690
1691 struct radv_pipeline_key;
1692
1693 void radv_hash_shaders(unsigned char *hash, const VkPipelineShaderStageCreateInfo **stages,
1694 const struct radv_pipeline_layout *layout,
1695 const struct radv_pipeline_key *key, uint32_t flags);
1696
1697 void radv_hash_rt_shaders(unsigned char *hash, const VkRayTracingPipelineCreateInfoKHR *pCreateInfo,
1698 uint32_t flags);
1699
1700 uint32_t radv_get_hash_flags(const struct radv_device *device, bool stats);
1701
1702 bool radv_rt_pipeline_has_dynamic_stack_size(const VkRayTracingPipelineCreateInfoKHR *pCreateInfo);
1703
1704 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1705
1706 #define radv_foreach_stage(stage, stage_bits) \
1707 for (gl_shader_stage stage, __tmp = (gl_shader_stage)((stage_bits)&RADV_STAGE_MASK); \
1708 stage = ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
1709
1710 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1711 unsigned radv_format_meta_fs_key(struct radv_device *device, VkFormat format);
1712
1713 struct radv_multisample_state {
1714 uint32_t db_eqaa;
1715 uint32_t pa_sc_mode_cntl_0;
1716 uint32_t pa_sc_mode_cntl_1;
1717 uint32_t pa_sc_aa_config;
1718 uint32_t pa_sc_aa_mask[2];
1719 unsigned num_samples;
1720 };
1721
1722 struct radv_vrs_state {
1723 uint32_t pa_cl_vrs_cntl;
1724 };
1725
1726 struct radv_prim_vertex_count {
1727 uint8_t min;
1728 uint8_t incr;
1729 };
1730
1731 struct radv_ia_multi_vgt_param_helpers {
1732 uint32_t base;
1733 bool partial_es_wave;
1734 uint8_t primgroup_size;
1735 bool ia_switch_on_eoi;
1736 bool partial_vs_wave;
1737 };
1738
1739 struct radv_binning_state {
1740 uint32_t pa_sc_binner_cntl_0;
1741 };
1742
1743 #define SI_GS_PER_ES 128
1744
1745 enum radv_pipeline_type {
1746 RADV_PIPELINE_GRAPHICS,
1747 /* Compute pipeline (incl raytracing pipeline) */
1748 RADV_PIPELINE_COMPUTE,
1749 /* Pipeline library. This can't actually run and merely is a partial pipeline. */
1750 RADV_PIPELINE_LIBRARY
1751 };
1752
1753 struct radv_pipeline_group_handle {
1754 uint32_t handles[2];
1755 };
1756
1757 struct radv_pipeline_shader_stack_size {
1758 uint32_t recursive_size;
1759 /* anyhit + intersection */
1760 uint32_t non_recursive_size;
1761 };
1762
1763 struct radv_pipeline {
1764 struct vk_object_base base;
1765 enum radv_pipeline_type type;
1766
1767 struct radv_device *device;
1768 struct radv_dynamic_state dynamic_state;
1769
1770 bool need_indirect_descriptor_sets;
1771 struct radv_shader_variant *shaders[MESA_SHADER_STAGES];
1772 struct radv_shader_variant *gs_copy_shader;
1773 VkShaderStageFlags active_stages;
1774
1775 struct radeon_cmdbuf cs;
1776 uint32_t ctx_cs_hash;
1777 struct radeon_cmdbuf ctx_cs;
1778
1779 uint32_t binding_stride[MAX_VBS];
1780
1781 uint8_t attrib_bindings[MAX_VERTEX_ATTRIBS];
1782 uint32_t attrib_ends[MAX_VERTEX_ATTRIBS];
1783 uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS];
1784
1785 bool use_per_attribute_vb_descs;
1786 bool can_use_simple_input;
1787 uint8_t last_vertex_attrib_bit;
1788 uint8_t next_vertex_stage : 8;
1789 uint32_t vb_desc_usage_mask;
1790 uint32_t vb_desc_alloc_size;
1791
1792 uint32_t user_data_0[MESA_SHADER_STAGES];
1793 union {
1794 struct {
1795 struct radv_multisample_state ms;
1796 struct radv_binning_state binning;
1797 struct radv_vrs_state vrs;
1798 uint32_t spi_baryc_cntl;
1799 unsigned esgs_ring_size;
1800 unsigned gsvs_ring_size;
1801 uint32_t vtx_base_sgpr;
1802 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1803 uint8_t vtx_emit_num;
1804 bool uses_drawid;
1805 bool uses_baseinstance;
1806 bool can_use_guardband;
1807 uint64_t needed_dynamic_state;
1808 bool disable_out_of_order_rast_for_occlusion;
1809 unsigned tess_patch_control_points;
1810 unsigned pa_su_sc_mode_cntl;
1811 unsigned db_depth_control;
1812 unsigned pa_cl_clip_cntl;
1813 unsigned cb_color_control;
1814 bool uses_dynamic_stride;
1815 bool uses_conservative_overestimate;
1816
1817 /* Used for rbplus */
1818 uint32_t col_format;
1819 uint32_t cb_target_mask;
1820
1821 /* Whether the pipeline uses NGG (GFX10+). */
1822 bool is_ngg;
1823 bool has_ngg_culling;
1824
1825 /* Last pre-PS API stage */
1826 gl_shader_stage last_vgt_api_stage;
1827 } graphics;
1828 struct {
1829 struct radv_pipeline_group_handle *rt_group_handles;
1830 struct radv_pipeline_shader_stack_size *rt_stack_sizes;
1831 bool dynamic_stack_size;
1832 uint32_t group_count;
1833 } compute;
1834 struct {
1835 unsigned stage_count;
1836 VkPipelineShaderStageCreateInfo *stages;
1837 unsigned group_count;
1838 VkRayTracingShaderGroupCreateInfoKHR *groups;
1839 } library;
1840 };
1841
1842 unsigned max_waves;
1843 unsigned scratch_bytes_per_wave;
1844
1845 /* Not NULL if graphics pipeline uses streamout. */
1846 struct radv_shader_variant *streamout_shader;
1847
1848 /* Unique pipeline hash identifier. */
1849 uint64_t pipeline_hash;
1850
1851 /* Pipeline layout info. */
1852 uint32_t push_constant_size;
1853 uint32_t dynamic_offset_count;
1854 };
1855
1856 static inline bool
radv_pipeline_has_gs(const struct radv_pipeline * pipeline)1857 radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1858 {
1859 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1860 }
1861
1862 static inline bool
radv_pipeline_has_tess(const struct radv_pipeline * pipeline)1863 radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1864 {
1865 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1866 }
1867
1868 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline);
1869
1870 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1871
1872 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1873 gl_shader_stage stage, int idx);
1874
1875 struct radv_shader_variant *radv_get_shader(const struct radv_pipeline *pipeline,
1876 gl_shader_stage stage);
1877
1878 struct radv_graphics_pipeline_create_info {
1879 bool use_rectlist;
1880 bool db_depth_clear;
1881 bool db_stencil_clear;
1882 bool depth_compress_disable;
1883 bool stencil_compress_disable;
1884 bool resummarize_enable;
1885 uint32_t custom_blend_mode;
1886 };
1887
1888 VkResult radv_graphics_pipeline_create(VkDevice device, VkPipelineCache cache,
1889 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1890 const struct radv_graphics_pipeline_create_info *extra,
1891 const VkAllocationCallbacks *alloc, VkPipeline *pPipeline);
1892
1893 VkResult radv_compute_pipeline_create(VkDevice _device, VkPipelineCache _cache,
1894 const VkComputePipelineCreateInfo *pCreateInfo,
1895 const VkAllocationCallbacks *pAllocator,
1896 const uint8_t *custom_hash,
1897 struct radv_pipeline_shader_stack_size *rt_stack_sizes,
1898 uint32_t rt_group_count, VkPipeline *pPipeline);
1899
1900 void radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pipeline,
1901 const VkAllocationCallbacks *allocator);
1902
1903 struct radv_binning_settings {
1904 unsigned context_states_per_bin; /* allowed range: [1, 6] */
1905 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
1906 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
1907 };
1908
1909 struct radv_binning_settings radv_get_binning_settings(const struct radv_physical_device *pdev);
1910
1911 struct vk_format_description;
1912 uint32_t radv_translate_buffer_dataformat(const struct util_format_description *desc,
1913 int first_non_void);
1914 uint32_t radv_translate_buffer_numformat(const struct util_format_description *desc,
1915 int first_non_void);
1916 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1917 void radv_translate_vertex_format(const struct radv_physical_device *pdevice, VkFormat format,
1918 const struct util_format_description *desc, unsigned *dfmt,
1919 unsigned *nfmt, bool *post_shuffle,
1920 enum radv_vs_input_alpha_adjust *alpha_adjust);
1921 uint32_t radv_translate_colorformat(VkFormat format);
1922 uint32_t radv_translate_color_numformat(VkFormat format, const struct util_format_description *desc,
1923 int first_non_void);
1924 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1925 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1926 uint32_t radv_translate_dbformat(VkFormat format);
1927 uint32_t radv_translate_tex_dataformat(VkFormat format, const struct util_format_description *desc,
1928 int first_non_void);
1929 uint32_t radv_translate_tex_numformat(VkFormat format, const struct util_format_description *desc,
1930 int first_non_void);
1931 bool radv_format_pack_clear_color(VkFormat format, uint32_t clear_vals[2],
1932 VkClearColorValue *value);
1933 bool radv_is_storage_image_format_supported(struct radv_physical_device *physical_device,
1934 VkFormat format);
1935 bool radv_is_colorbuffer_format_supported(const struct radv_physical_device *pdevice,
1936 VkFormat format, bool *blendable);
1937 bool radv_dcc_formats_compatible(VkFormat format1, VkFormat format2, bool *sign_reinterpret);
1938 bool radv_is_atomic_format_supported(VkFormat format);
1939 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1940
1941 struct radv_image_plane {
1942 VkFormat format;
1943 struct radeon_surf surface;
1944 };
1945
1946 struct radv_image {
1947 struct vk_object_base base;
1948 VkImageType type;
1949 /* The original VkFormat provided by the client. This may not match any
1950 * of the actual surface formats.
1951 */
1952 VkFormat vk_format;
1953 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1954 struct ac_surf_info info;
1955 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1956 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1957
1958 VkDeviceSize size;
1959 uint32_t alignment;
1960
1961 unsigned queue_family_mask;
1962 bool exclusive;
1963 bool shareable;
1964 bool l2_coherent;
1965 bool dcc_sign_reinterpret;
1966 bool support_comp_to_single;
1967
1968 /* Set when bound */
1969 struct radeon_winsys_bo *bo;
1970 VkDeviceSize offset;
1971 bool tc_compatible_cmask;
1972
1973 uint64_t clear_value_offset;
1974 uint64_t fce_pred_offset;
1975 uint64_t dcc_pred_offset;
1976
1977 /*
1978 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1979 * stored at this offset is UINT_MAX, the driver will emit
1980 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1981 * SET_CONTEXT_REG packet.
1982 */
1983 uint64_t tc_compat_zrange_offset;
1984
1985 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1986 VkDeviceMemory owned_memory;
1987
1988 unsigned plane_count;
1989 struct radv_image_plane planes[0];
1990 };
1991
1992 /* Whether the image has a htile that is known consistent with the contents of
1993 * the image and is allowed to be in compressed form.
1994 *
1995 * If this is false reads that don't use the htile should be able to return
1996 * correct results.
1997 */
1998 bool radv_layout_is_htile_compressed(const struct radv_device *device,
1999 const struct radv_image *image, VkImageLayout layout,
2000 bool in_render_loop, unsigned queue_mask);
2001
2002 bool radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_image *image,
2003 unsigned level, VkImageLayout layout, bool in_render_loop,
2004 unsigned queue_mask);
2005
2006 bool radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_image *image,
2007 unsigned level, VkImageLayout layout, bool in_render_loop,
2008 unsigned queue_mask);
2009
2010 bool radv_layout_fmask_compressed(const struct radv_device *device, const struct radv_image *image,
2011 VkImageLayout layout, unsigned queue_mask);
2012
2013 /**
2014 * Return whether the image has CMASK metadata for color surfaces.
2015 */
2016 static inline bool
radv_image_has_cmask(const struct radv_image * image)2017 radv_image_has_cmask(const struct radv_image *image)
2018 {
2019 return image->planes[0].surface.cmask_offset;
2020 }
2021
2022 /**
2023 * Return whether the image has FMASK metadata for color surfaces.
2024 */
2025 static inline bool
radv_image_has_fmask(const struct radv_image * image)2026 radv_image_has_fmask(const struct radv_image *image)
2027 {
2028 return image->planes[0].surface.fmask_offset;
2029 }
2030
2031 /**
2032 * Return whether the image has DCC metadata for color surfaces.
2033 */
2034 static inline bool
radv_image_has_dcc(const struct radv_image * image)2035 radv_image_has_dcc(const struct radv_image *image)
2036 {
2037 return !(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) &&
2038 image->planes[0].surface.meta_offset;
2039 }
2040
2041 /**
2042 * Return whether the image is TC-compatible CMASK.
2043 */
2044 static inline bool
radv_image_is_tc_compat_cmask(const struct radv_image * image)2045 radv_image_is_tc_compat_cmask(const struct radv_image *image)
2046 {
2047 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
2048 }
2049
2050 /**
2051 * Return whether DCC metadata is enabled for a level.
2052 */
2053 static inline bool
radv_dcc_enabled(const struct radv_image * image,unsigned level)2054 radv_dcc_enabled(const struct radv_image *image, unsigned level)
2055 {
2056 return radv_image_has_dcc(image) && level < image->planes[0].surface.num_meta_levels;
2057 }
2058
2059 /**
2060 * Return whether the image has CB metadata.
2061 */
2062 static inline bool
radv_image_has_CB_metadata(const struct radv_image * image)2063 radv_image_has_CB_metadata(const struct radv_image *image)
2064 {
2065 return radv_image_has_cmask(image) || radv_image_has_fmask(image) || radv_image_has_dcc(image);
2066 }
2067
2068 /**
2069 * Return whether the image has HTILE metadata for depth surfaces.
2070 */
2071 static inline bool
radv_image_has_htile(const struct radv_image * image)2072 radv_image_has_htile(const struct radv_image *image)
2073 {
2074 return image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER &&
2075 image->planes[0].surface.meta_size;
2076 }
2077
2078 /**
2079 * Return whether the image has VRS HTILE metadata for depth surfaces
2080 */
2081 static inline bool
radv_image_has_vrs_htile(const struct radv_device * device,const struct radv_image * image)2082 radv_image_has_vrs_htile(const struct radv_device *device, const struct radv_image *image)
2083 {
2084 /* Any depth buffer can potentially use VRS. */
2085 return device->attachment_vrs_enabled && radv_image_has_htile(image) &&
2086 (image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT);
2087 }
2088
2089 /**
2090 * Return whether HTILE metadata is enabled for a level.
2091 */
2092 static inline bool
radv_htile_enabled(const struct radv_image * image,unsigned level)2093 radv_htile_enabled(const struct radv_image *image, unsigned level)
2094 {
2095 return radv_image_has_htile(image) && level < image->planes[0].surface.num_meta_levels;
2096 }
2097
2098 /**
2099 * Return whether the image is TC-compatible HTILE.
2100 */
2101 static inline bool
radv_image_is_tc_compat_htile(const struct radv_image * image)2102 radv_image_is_tc_compat_htile(const struct radv_image *image)
2103 {
2104 return radv_image_has_htile(image) &&
2105 (image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE);
2106 }
2107
2108 /**
2109 * Return whether the entire HTILE buffer can be used for depth in order to
2110 * improve HiZ Z-Range precision.
2111 */
2112 static inline bool
radv_image_tile_stencil_disabled(const struct radv_device * device,const struct radv_image * image)2113 radv_image_tile_stencil_disabled(const struct radv_device *device, const struct radv_image *image)
2114 {
2115 if (device->physical_device->rad_info.chip_class >= GFX9) {
2116 return !vk_format_has_stencil(image->vk_format) && !radv_image_has_vrs_htile(device, image);
2117 } else {
2118 /* Due to a hw bug, TILE_STENCIL_DISABLE must be set to 0 for
2119 * the TC-compat ZRANGE issue even if no stencil is used.
2120 */
2121 return !vk_format_has_stencil(image->vk_format) && !radv_image_is_tc_compat_htile(image);
2122 }
2123 }
2124
2125 static inline bool
radv_image_has_clear_value(const struct radv_image * image)2126 radv_image_has_clear_value(const struct radv_image *image)
2127 {
2128 return image->clear_value_offset != 0;
2129 }
2130
2131 static inline uint64_t
radv_image_get_fast_clear_va(const struct radv_image * image,uint32_t base_level)2132 radv_image_get_fast_clear_va(const struct radv_image *image, uint32_t base_level)
2133 {
2134 assert(radv_image_has_clear_value(image));
2135
2136 uint64_t va = radv_buffer_get_va(image->bo);
2137 va += image->offset + image->clear_value_offset + base_level * 8;
2138 return va;
2139 }
2140
2141 static inline uint64_t
radv_image_get_fce_pred_va(const struct radv_image * image,uint32_t base_level)2142 radv_image_get_fce_pred_va(const struct radv_image *image, uint32_t base_level)
2143 {
2144 assert(image->fce_pred_offset != 0);
2145
2146 uint64_t va = radv_buffer_get_va(image->bo);
2147 va += image->offset + image->fce_pred_offset + base_level * 8;
2148 return va;
2149 }
2150
2151 static inline uint64_t
radv_image_get_dcc_pred_va(const struct radv_image * image,uint32_t base_level)2152 radv_image_get_dcc_pred_va(const struct radv_image *image, uint32_t base_level)
2153 {
2154 assert(image->dcc_pred_offset != 0);
2155
2156 uint64_t va = radv_buffer_get_va(image->bo);
2157 va += image->offset + image->dcc_pred_offset + base_level * 8;
2158 return va;
2159 }
2160
2161 static inline uint64_t
radv_get_tc_compat_zrange_va(const struct radv_image * image,uint32_t base_level)2162 radv_get_tc_compat_zrange_va(const struct radv_image *image, uint32_t base_level)
2163 {
2164 assert(image->tc_compat_zrange_offset != 0);
2165
2166 uint64_t va = radv_buffer_get_va(image->bo);
2167 va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
2168 return va;
2169 }
2170
2171 static inline uint64_t
radv_get_ds_clear_value_va(const struct radv_image * image,uint32_t base_level)2172 radv_get_ds_clear_value_va(const struct radv_image *image, uint32_t base_level)
2173 {
2174 assert(radv_image_has_clear_value(image));
2175
2176 uint64_t va = radv_buffer_get_va(image->bo);
2177 va += image->offset + image->clear_value_offset + base_level * 8;
2178 return va;
2179 }
2180
2181 static inline uint32_t
radv_get_htile_initial_value(const struct radv_device * device,const struct radv_image * image)2182 radv_get_htile_initial_value(const struct radv_device *device, const struct radv_image *image)
2183 {
2184 uint32_t initial_value;
2185
2186 if (radv_image_tile_stencil_disabled(device, image)) {
2187 /* Z only (no stencil):
2188 *
2189 * |31 18|17 4|3 0|
2190 * +---------+---------+-------+
2191 * | Max Z | Min Z | ZMask |
2192 */
2193 initial_value = 0xfffc000f;
2194 } else {
2195 /* Z and stencil:
2196 *
2197 * |31 12|11 10|9 8|7 6|5 4|3 0|
2198 * +-----------+-----+------+-----+-----+-------+
2199 * | Z Range | | SMem | SR1 | SR0 | ZMask |
2200 *
2201 * SR0/SR1 contains the stencil test results. Initializing
2202 * SR0/SR1 to 0x3 means the stencil test result is unknown.
2203 *
2204 * Z, stencil and 4 bit VRS encoding:
2205 * |31 12|11 10|9 8|7 6|5 4|3 0|
2206 * +-----------+------------+------+------------+-----+-------+
2207 * | Z Range | VRS y-rate | SMem | VRS x-rate | SR0 | ZMask |
2208 */
2209 if (radv_image_has_vrs_htile(device, image)) {
2210 /* Initialize the VRS x-rate value at 0, so the hw interprets it as 1 sample. */
2211 initial_value = 0xfffff33f;
2212 } else {
2213 initial_value = 0xfffff3ff;
2214 }
2215 }
2216
2217 return initial_value;
2218 }
2219
2220 static inline bool
radv_image_get_iterate256(struct radv_device * device,struct radv_image * image)2221 radv_image_get_iterate256(struct radv_device *device, struct radv_image *image)
2222 {
2223 /* ITERATE_256 is required for depth or stencil MSAA images that are TC-compatible HTILE. */
2224 return device->physical_device->rad_info.chip_class >= GFX10 &&
2225 (image->usage & (VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT |
2226 VK_IMAGE_USAGE_TRANSFER_DST_BIT)) &&
2227 radv_image_is_tc_compat_htile(image) &&
2228 image->info.samples > 1;
2229 }
2230
2231 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family,
2232 uint32_t queue_family);
2233
2234 static inline uint32_t
radv_get_layerCount(const struct radv_image * image,const VkImageSubresourceRange * range)2235 radv_get_layerCount(const struct radv_image *image, const VkImageSubresourceRange *range)
2236 {
2237 return range->layerCount == VK_REMAINING_ARRAY_LAYERS
2238 ? image->info.array_size - range->baseArrayLayer
2239 : range->layerCount;
2240 }
2241
2242 static inline uint32_t
radv_get_levelCount(const struct radv_image * image,const VkImageSubresourceRange * range)2243 radv_get_levelCount(const struct radv_image *image, const VkImageSubresourceRange *range)
2244 {
2245 return range->levelCount == VK_REMAINING_MIP_LEVELS ? image->info.levels - range->baseMipLevel
2246 : range->levelCount;
2247 }
2248
2249 bool radv_image_is_renderable(struct radv_device *device, struct radv_image *image);
2250
2251 struct radeon_bo_metadata;
2252 void radv_init_metadata(struct radv_device *device, struct radv_image *image,
2253 struct radeon_bo_metadata *metadata);
2254
2255 void radv_image_override_offset_stride(struct radv_device *device, struct radv_image *image,
2256 uint64_t offset, uint32_t stride);
2257
2258 union radv_descriptor {
2259 struct {
2260 uint32_t plane0_descriptor[8];
2261 uint32_t fmask_descriptor[8];
2262 };
2263 struct {
2264 uint32_t plane_descriptors[3][8];
2265 };
2266 };
2267
2268 struct radv_image_view {
2269 struct vk_object_base base;
2270 struct radv_image *image; /**< VkImageViewCreateInfo::image */
2271
2272 VkImageViewType type;
2273 VkImageAspectFlags aspect_mask;
2274 VkFormat vk_format;
2275 unsigned plane_id;
2276 uint32_t base_layer;
2277 uint32_t layer_count;
2278 uint32_t base_mip;
2279 uint32_t level_count;
2280 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2281
2282 /* Whether the image iview supports fast clear. */
2283 bool support_fast_clear;
2284
2285 union radv_descriptor descriptor;
2286
2287 /* Descriptor for use as a storage image as opposed to a sampled image.
2288 * This has a few differences for cube maps (e.g. type).
2289 */
2290 union radv_descriptor storage_descriptor;
2291 };
2292
2293 struct radv_image_create_info {
2294 const VkImageCreateInfo *vk_info;
2295 bool scanout;
2296 bool no_metadata_planes;
2297 const struct radeon_bo_metadata *bo_metadata;
2298 };
2299
2300 VkResult
2301 radv_image_create_layout(struct radv_device *device, struct radv_image_create_info create_info,
2302 const struct VkImageDrmFormatModifierExplicitCreateInfoEXT *mod_info,
2303 struct radv_image *image);
2304
2305 VkResult radv_image_create(VkDevice _device, const struct radv_image_create_info *info,
2306 const VkAllocationCallbacks *alloc, VkImage *pImage);
2307
2308 bool radv_are_formats_dcc_compatible(const struct radv_physical_device *pdev, const void *pNext,
2309 VkFormat format, VkImageCreateFlags flags,
2310 bool *sign_reinterpret);
2311
2312 bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format);
2313
2314 VkResult radv_image_from_gralloc(VkDevice device_h, const VkImageCreateInfo *base_info,
2315 const VkNativeBufferANDROID *gralloc_info,
2316 const VkAllocationCallbacks *alloc, VkImage *out_image_h);
2317 uint64_t radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create,
2318 const VkImageUsageFlags vk_usage);
2319 VkResult radv_import_ahb_memory(struct radv_device *device, struct radv_device_memory *mem,
2320 unsigned priority,
2321 const VkImportAndroidHardwareBufferInfoANDROID *info);
2322 VkResult radv_create_ahb_memory(struct radv_device *device, struct radv_device_memory *mem,
2323 unsigned priority, const VkMemoryAllocateInfo *pAllocateInfo);
2324
2325 VkFormat radv_select_android_external_format(const void *next, VkFormat default_format);
2326
2327 bool radv_android_gralloc_supports_format(VkFormat format, VkImageUsageFlagBits usage);
2328
2329 struct radv_image_view_extra_create_info {
2330 bool disable_compression;
2331 bool enable_compression;
2332 };
2333
2334 void radv_image_view_init(struct radv_image_view *view, struct radv_device *device,
2335 const VkImageViewCreateInfo *pCreateInfo,
2336 const struct radv_image_view_extra_create_info *extra_create_info);
2337 void radv_image_view_finish(struct radv_image_view *iview);
2338
2339 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
2340
2341 struct radv_sampler_ycbcr_conversion {
2342 struct vk_object_base base;
2343 VkFormat format;
2344 VkSamplerYcbcrModelConversion ycbcr_model;
2345 VkSamplerYcbcrRange ycbcr_range;
2346 VkComponentMapping components;
2347 VkChromaLocation chroma_offsets[2];
2348 VkFilter chroma_filter;
2349 };
2350
2351 struct radv_buffer_view {
2352 struct vk_object_base base;
2353 struct radeon_winsys_bo *bo;
2354 VkFormat vk_format;
2355 uint64_t range; /**< VkBufferViewCreateInfo::range */
2356 uint32_t state[4];
2357 };
2358 void radv_buffer_view_init(struct radv_buffer_view *view, struct radv_device *device,
2359 const VkBufferViewCreateInfo *pCreateInfo);
2360 void radv_buffer_view_finish(struct radv_buffer_view *view);
2361
2362 static inline struct VkExtent3D
radv_sanitize_image_extent(const VkImageType imageType,const struct VkExtent3D imageExtent)2363 radv_sanitize_image_extent(const VkImageType imageType, const struct VkExtent3D imageExtent)
2364 {
2365 switch (imageType) {
2366 case VK_IMAGE_TYPE_1D:
2367 return (VkExtent3D){imageExtent.width, 1, 1};
2368 case VK_IMAGE_TYPE_2D:
2369 return (VkExtent3D){imageExtent.width, imageExtent.height, 1};
2370 case VK_IMAGE_TYPE_3D:
2371 return imageExtent;
2372 default:
2373 unreachable("invalid image type");
2374 }
2375 }
2376
2377 static inline struct VkOffset3D
radv_sanitize_image_offset(const VkImageType imageType,const struct VkOffset3D imageOffset)2378 radv_sanitize_image_offset(const VkImageType imageType, const struct VkOffset3D imageOffset)
2379 {
2380 switch (imageType) {
2381 case VK_IMAGE_TYPE_1D:
2382 return (VkOffset3D){imageOffset.x, 0, 0};
2383 case VK_IMAGE_TYPE_2D:
2384 return (VkOffset3D){imageOffset.x, imageOffset.y, 0};
2385 case VK_IMAGE_TYPE_3D:
2386 return imageOffset;
2387 default:
2388 unreachable("invalid image type");
2389 }
2390 }
2391
2392 static inline bool
radv_image_extent_compare(const struct radv_image * image,const VkExtent3D * extent)2393 radv_image_extent_compare(const struct radv_image *image, const VkExtent3D *extent)
2394 {
2395 if (extent->width != image->info.width || extent->height != image->info.height ||
2396 extent->depth != image->info.depth)
2397 return false;
2398 return true;
2399 }
2400
2401 struct radv_sampler {
2402 struct vk_object_base base;
2403 uint32_t state[4];
2404 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
2405 uint32_t border_color_slot;
2406 };
2407
2408 struct radv_framebuffer {
2409 struct vk_object_base base;
2410 uint32_t width;
2411 uint32_t height;
2412 uint32_t layers;
2413
2414 bool imageless;
2415
2416 uint32_t attachment_count;
2417 struct radv_image_view *attachments[0];
2418 };
2419
2420 struct radv_subpass_barrier {
2421 VkPipelineStageFlags src_stage_mask;
2422 VkAccessFlags src_access_mask;
2423 VkAccessFlags dst_access_mask;
2424 };
2425
2426 void radv_emit_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2427 const struct radv_subpass_barrier *barrier);
2428
2429 struct radv_subpass_attachment {
2430 uint32_t attachment;
2431 VkImageLayout layout;
2432 VkImageLayout stencil_layout;
2433 bool in_render_loop;
2434 };
2435
2436 struct radv_subpass {
2437 uint32_t attachment_count;
2438 struct radv_subpass_attachment *attachments;
2439
2440 uint32_t input_count;
2441 uint32_t color_count;
2442 struct radv_subpass_attachment *input_attachments;
2443 struct radv_subpass_attachment *color_attachments;
2444 struct radv_subpass_attachment *resolve_attachments;
2445 struct radv_subpass_attachment *depth_stencil_attachment;
2446 struct radv_subpass_attachment *ds_resolve_attachment;
2447 struct radv_subpass_attachment *vrs_attachment;
2448 VkResolveModeFlagBits depth_resolve_mode;
2449 VkResolveModeFlagBits stencil_resolve_mode;
2450
2451 /** Subpass has at least one color resolve attachment */
2452 bool has_color_resolve;
2453
2454 /** Subpass has at least one color attachment */
2455 bool has_color_att;
2456
2457 struct radv_subpass_barrier start_barrier;
2458
2459 uint32_t view_mask;
2460
2461 VkSampleCountFlagBits color_sample_count;
2462 VkSampleCountFlagBits depth_sample_count;
2463 VkSampleCountFlagBits max_sample_count;
2464
2465 /* Whether the subpass has ingoing/outgoing external dependencies. */
2466 bool has_ingoing_dep;
2467 bool has_outgoing_dep;
2468 };
2469
2470 uint32_t radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2471
2472 struct radv_render_pass_attachment {
2473 VkFormat format;
2474 uint32_t samples;
2475 VkAttachmentLoadOp load_op;
2476 VkAttachmentLoadOp stencil_load_op;
2477 VkImageLayout initial_layout;
2478 VkImageLayout final_layout;
2479 VkImageLayout stencil_initial_layout;
2480 VkImageLayout stencil_final_layout;
2481
2482 /* The subpass id in which the attachment will be used first/last. */
2483 uint32_t first_subpass_idx;
2484 uint32_t last_subpass_idx;
2485 };
2486
2487 struct radv_render_pass {
2488 struct vk_object_base base;
2489 uint32_t attachment_count;
2490 uint32_t subpass_count;
2491 struct radv_subpass_attachment *subpass_attachments;
2492 struct radv_render_pass_attachment *attachments;
2493 struct radv_subpass_barrier end_barrier;
2494 struct radv_subpass subpasses[0];
2495 };
2496
2497 VkResult radv_device_init_meta(struct radv_device *device);
2498 void radv_device_finish_meta(struct radv_device *device);
2499
2500 struct radv_query_pool {
2501 struct vk_object_base base;
2502 struct radeon_winsys_bo *bo;
2503 uint32_t stride;
2504 uint32_t availability_offset;
2505 uint64_t size;
2506 char *ptr;
2507 VkQueryType type;
2508 uint32_t pipeline_stats_mask;
2509 };
2510
2511 typedef enum {
2512 RADV_SEMAPHORE_NONE,
2513 RADV_SEMAPHORE_SYNCOBJ,
2514 RADV_SEMAPHORE_TIMELINE_SYNCOBJ,
2515 RADV_SEMAPHORE_TIMELINE,
2516 } radv_semaphore_kind;
2517
2518 struct radv_deferred_queue_submission;
2519
2520 struct radv_timeline_waiter {
2521 struct list_head list;
2522 struct radv_deferred_queue_submission *submission;
2523 uint64_t value;
2524 };
2525
2526 struct radv_timeline_point {
2527 struct list_head list;
2528
2529 uint64_t value;
2530 uint32_t syncobj;
2531
2532 /* Separate from the list to accomodate CPU wait being async, as well
2533 * as prevent point deletion during submission. */
2534 unsigned wait_count;
2535 };
2536
2537 struct radv_timeline {
2538 mtx_t mutex;
2539
2540 uint64_t highest_signaled;
2541 uint64_t highest_submitted;
2542
2543 struct list_head points;
2544
2545 /* Keep free points on hand so we do not have to recreate syncobjs all
2546 * the time. */
2547 struct list_head free_points;
2548
2549 /* Submissions that are deferred waiting for a specific value to be
2550 * submitted. */
2551 struct list_head waiters;
2552 };
2553
2554 struct radv_timeline_syncobj {
2555 /* Keep syncobj first, so common-code can just handle this as
2556 * non-timeline syncobj. */
2557 uint32_t syncobj;
2558 uint64_t max_point; /* max submitted point. */
2559 };
2560
2561 struct radv_semaphore_part {
2562 radv_semaphore_kind kind;
2563 union {
2564 uint32_t syncobj;
2565 struct radv_timeline timeline;
2566 struct radv_timeline_syncobj timeline_syncobj;
2567 };
2568 };
2569
2570 struct radv_semaphore {
2571 struct vk_object_base base;
2572 struct radv_semaphore_part permanent;
2573 struct radv_semaphore_part temporary;
2574 };
2575
2576 bool radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs);
2577
2578 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bind_point,
2579 struct radv_descriptor_set *set, unsigned idx);
2580
2581 void radv_update_descriptor_sets(struct radv_device *device, struct radv_cmd_buffer *cmd_buffer,
2582 VkDescriptorSet overrideSet, uint32_t descriptorWriteCount,
2583 const VkWriteDescriptorSet *pDescriptorWrites,
2584 uint32_t descriptorCopyCount,
2585 const VkCopyDescriptorSet *pDescriptorCopies);
2586
2587 void radv_update_descriptor_set_with_template(struct radv_device *device,
2588 struct radv_cmd_buffer *cmd_buffer,
2589 struct radv_descriptor_set *set,
2590 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2591 const void *pData);
2592
2593 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2594 VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout _layout,
2595 uint32_t set, uint32_t descriptorWriteCount,
2596 const VkWriteDescriptorSet *pDescriptorWrites);
2597
2598 uint32_t radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2599 const VkImageSubresourceRange *range, uint32_t value);
2600
2601 uint32_t radv_init_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
2602 const VkImageSubresourceRange *range);
2603
2604 typedef enum {
2605 RADV_FENCE_NONE,
2606 RADV_FENCE_SYNCOBJ,
2607 } radv_fence_kind;
2608
2609 struct radv_fence_part {
2610 radv_fence_kind kind;
2611
2612 /* DRM syncobj handle for syncobj-based fences. */
2613 uint32_t syncobj;
2614 };
2615
2616 struct radv_fence {
2617 struct vk_object_base base;
2618 struct radv_fence_part permanent;
2619 struct radv_fence_part temporary;
2620 };
2621
2622 /* radv_nir_to_llvm.c */
2623 struct radv_shader_args;
2624
2625 void llvm_compile_shader(struct radv_device *device, unsigned shader_count,
2626 struct nir_shader *const *shaders, struct radv_shader_binary **binary,
2627 struct radv_shader_args *args);
2628
2629 /* radv_shader_info.h */
2630 struct radv_shader_info;
2631
2632 void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir,
2633 const struct radv_pipeline_layout *layout,
2634 const struct radv_pipeline_key *pipeline_key,
2635 struct radv_shader_info *info);
2636
2637 void radv_nir_shader_info_init(struct radv_shader_info *info);
2638
2639 bool radv_thread_trace_init(struct radv_device *device);
2640 void radv_thread_trace_finish(struct radv_device *device);
2641 bool radv_begin_thread_trace(struct radv_queue *queue);
2642 bool radv_end_thread_trace(struct radv_queue *queue);
2643 bool radv_get_thread_trace(struct radv_queue *queue, struct ac_thread_trace *thread_trace);
2644 void radv_emit_thread_trace_userdata(const struct radv_device *device, struct radeon_cmdbuf *cs,
2645 const void *data, uint32_t num_dwords);
2646 bool radv_is_instruction_timing_enabled(void);
2647
2648 /* radv_sqtt_layer_.c */
2649 struct radv_barrier_data {
2650 union {
2651 struct {
2652 uint16_t depth_stencil_expand : 1;
2653 uint16_t htile_hiz_range_expand : 1;
2654 uint16_t depth_stencil_resummarize : 1;
2655 uint16_t dcc_decompress : 1;
2656 uint16_t fmask_decompress : 1;
2657 uint16_t fast_clear_eliminate : 1;
2658 uint16_t fmask_color_expand : 1;
2659 uint16_t init_mask_ram : 1;
2660 uint16_t reserved : 8;
2661 };
2662 uint16_t all;
2663 } layout_transitions;
2664 };
2665
2666 /**
2667 * Value for the reason field of an RGP barrier start marker originating from
2668 * the Vulkan client (does not include PAL-defined values). (Table 15)
2669 */
2670 enum rgp_barrier_reason {
2671 RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF,
2672
2673 /* External app-generated barrier reasons, i.e. API synchronization
2674 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2675 */
2676 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001,
2677 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002,
2678 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003,
2679
2680 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2681 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2682 */
2683 RGP_BARRIER_INTERNAL_BASE = 0xC0000000,
2684 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0,
2685 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1,
2686 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2,
2687 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3
2688 };
2689
2690 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2691 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2692 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
2693 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
2694 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
2695 VkImageAspectFlagBits aspects);
2696 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
2697 void radv_describe_begin_render_pass_resolve(struct radv_cmd_buffer *cmd_buffer);
2698 void radv_describe_end_render_pass_resolve(struct radv_cmd_buffer *cmd_buffer);
2699 void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer,
2700 enum rgp_barrier_reason reason);
2701 void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer);
2702 void radv_describe_barrier_end_delayed(struct radv_cmd_buffer *cmd_buffer);
2703 void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer,
2704 const struct radv_barrier_data *barrier);
2705
2706 uint64_t radv_get_current_time(void);
2707
2708 static inline uint32_t
si_conv_gl_prim_to_vertices(unsigned gl_prim)2709 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2710 {
2711 switch (gl_prim) {
2712 case 0: /* GL_POINTS */
2713 return 1;
2714 case 1: /* GL_LINES */
2715 case 3: /* GL_LINE_STRIP */
2716 return 2;
2717 case 4: /* GL_TRIANGLES */
2718 case 5: /* GL_TRIANGLE_STRIP */
2719 return 3;
2720 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2721 return 4;
2722 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2723 return 6;
2724 case 7: /* GL_QUADS */
2725 return V_028A6C_TRISTRIP;
2726 default:
2727 assert(0);
2728 return 0;
2729 }
2730 }
2731
2732 static inline uint32_t
si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)2733 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
2734 {
2735 switch (topology) {
2736 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
2737 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
2738 return V_028A6C_POINTLIST;
2739 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
2740 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
2741 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
2742 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
2743 return V_028A6C_LINESTRIP;
2744 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
2745 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
2746 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
2747 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
2748 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
2749 return V_028A6C_TRISTRIP;
2750 default:
2751 assert(0);
2752 return 0;
2753 }
2754 }
2755
2756 struct radv_extra_render_pass_begin_info {
2757 bool disable_dcc;
2758 };
2759
2760 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
2761 const VkRenderPassBeginInfo *pRenderPassBegin,
2762 const struct radv_extra_render_pass_begin_info *extra_info);
2763 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
2764
2765 static inline uint32_t
si_translate_prim(unsigned topology)2766 si_translate_prim(unsigned topology)
2767 {
2768 switch (topology) {
2769 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
2770 return V_008958_DI_PT_POINTLIST;
2771 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
2772 return V_008958_DI_PT_LINELIST;
2773 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
2774 return V_008958_DI_PT_LINESTRIP;
2775 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
2776 return V_008958_DI_PT_TRILIST;
2777 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
2778 return V_008958_DI_PT_TRISTRIP;
2779 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
2780 return V_008958_DI_PT_TRIFAN;
2781 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
2782 return V_008958_DI_PT_LINELIST_ADJ;
2783 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
2784 return V_008958_DI_PT_LINESTRIP_ADJ;
2785 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
2786 return V_008958_DI_PT_TRILIST_ADJ;
2787 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
2788 return V_008958_DI_PT_TRISTRIP_ADJ;
2789 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
2790 return V_008958_DI_PT_PATCH;
2791 default:
2792 assert(0);
2793 return 0;
2794 }
2795 }
2796
2797 static inline uint32_t
si_translate_stencil_op(enum VkStencilOp op)2798 si_translate_stencil_op(enum VkStencilOp op)
2799 {
2800 switch (op) {
2801 case VK_STENCIL_OP_KEEP:
2802 return V_02842C_STENCIL_KEEP;
2803 case VK_STENCIL_OP_ZERO:
2804 return V_02842C_STENCIL_ZERO;
2805 case VK_STENCIL_OP_REPLACE:
2806 return V_02842C_STENCIL_REPLACE_TEST;
2807 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
2808 return V_02842C_STENCIL_ADD_CLAMP;
2809 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
2810 return V_02842C_STENCIL_SUB_CLAMP;
2811 case VK_STENCIL_OP_INVERT:
2812 return V_02842C_STENCIL_INVERT;
2813 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
2814 return V_02842C_STENCIL_ADD_WRAP;
2815 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
2816 return V_02842C_STENCIL_SUB_WRAP;
2817 default:
2818 return 0;
2819 }
2820 }
2821
2822 static inline uint32_t
si_translate_blend_logic_op(VkLogicOp op)2823 si_translate_blend_logic_op(VkLogicOp op)
2824 {
2825 switch (op) {
2826 case VK_LOGIC_OP_CLEAR:
2827 return V_028808_ROP3_CLEAR;
2828 case VK_LOGIC_OP_AND:
2829 return V_028808_ROP3_AND;
2830 case VK_LOGIC_OP_AND_REVERSE:
2831 return V_028808_ROP3_AND_REVERSE;
2832 case VK_LOGIC_OP_COPY:
2833 return V_028808_ROP3_COPY;
2834 case VK_LOGIC_OP_AND_INVERTED:
2835 return V_028808_ROP3_AND_INVERTED;
2836 case VK_LOGIC_OP_NO_OP:
2837 return V_028808_ROP3_NO_OP;
2838 case VK_LOGIC_OP_XOR:
2839 return V_028808_ROP3_XOR;
2840 case VK_LOGIC_OP_OR:
2841 return V_028808_ROP3_OR;
2842 case VK_LOGIC_OP_NOR:
2843 return V_028808_ROP3_NOR;
2844 case VK_LOGIC_OP_EQUIVALENT:
2845 return V_028808_ROP3_EQUIVALENT;
2846 case VK_LOGIC_OP_INVERT:
2847 return V_028808_ROP3_INVERT;
2848 case VK_LOGIC_OP_OR_REVERSE:
2849 return V_028808_ROP3_OR_REVERSE;
2850 case VK_LOGIC_OP_COPY_INVERTED:
2851 return V_028808_ROP3_COPY_INVERTED;
2852 case VK_LOGIC_OP_OR_INVERTED:
2853 return V_028808_ROP3_OR_INVERTED;
2854 case VK_LOGIC_OP_NAND:
2855 return V_028808_ROP3_NAND;
2856 case VK_LOGIC_OP_SET:
2857 return V_028808_ROP3_SET;
2858 default:
2859 unreachable("Unhandled logic op");
2860 }
2861 }
2862
2863 /**
2864 * Helper used for debugging compiler issues by enabling/disabling LLVM for a
2865 * specific shader stage (developers only).
2866 */
2867 static inline bool
radv_use_llvm_for_stage(struct radv_device * device,UNUSED gl_shader_stage stage)2868 radv_use_llvm_for_stage(struct radv_device *device, UNUSED gl_shader_stage stage)
2869 {
2870 return device->physical_device->use_llvm;
2871 }
2872
2873 struct radv_acceleration_structure {
2874 struct vk_object_base base;
2875
2876 struct radeon_winsys_bo *bo;
2877 uint64_t mem_offset;
2878 uint64_t size;
2879 };
2880
2881 static inline uint64_t
radv_accel_struct_get_va(const struct radv_acceleration_structure * accel)2882 radv_accel_struct_get_va(const struct radv_acceleration_structure *accel)
2883 {
2884 return radv_buffer_get_va(accel->bo) + accel->mem_offset;
2885 }
2886
2887 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2888 VK_FROM_HANDLE(__radv_type, __name, __handle)
2889
2890 VK_DEFINE_HANDLE_CASTS(radv_cmd_buffer, vk.base, VkCommandBuffer,
2891 VK_OBJECT_TYPE_COMMAND_BUFFER)
2892 VK_DEFINE_HANDLE_CASTS(radv_device, vk.base, VkDevice, VK_OBJECT_TYPE_DEVICE)
2893 VK_DEFINE_HANDLE_CASTS(radv_instance, vk.base, VkInstance, VK_OBJECT_TYPE_INSTANCE)
2894 VK_DEFINE_HANDLE_CASTS(radv_physical_device, vk.base, VkPhysicalDevice,
2895 VK_OBJECT_TYPE_PHYSICAL_DEVICE)
2896 VK_DEFINE_HANDLE_CASTS(radv_queue, vk.base, VkQueue, VK_OBJECT_TYPE_QUEUE)
2897 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_acceleration_structure, base,
2898 VkAccelerationStructureKHR,
2899 VK_OBJECT_TYPE_ACCELERATION_STRUCTURE_KHR)
2900 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, base, VkCommandPool,
2901 VK_OBJECT_TYPE_COMMAND_POOL)
2902 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, base, VkBuffer, VK_OBJECT_TYPE_BUFFER)
2903 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, base, VkBufferView,
2904 VK_OBJECT_TYPE_BUFFER_VIEW)
2905 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, base, VkDescriptorPool,
2906 VK_OBJECT_TYPE_DESCRIPTOR_POOL)
2907 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, header.base, VkDescriptorSet,
2908 VK_OBJECT_TYPE_DESCRIPTOR_SET)
2909 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, base,
2910 VkDescriptorSetLayout,
2911 VK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT)
2912 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, base,
2913 VkDescriptorUpdateTemplate,
2914 VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE)
2915 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, base, VkDeviceMemory,
2916 VK_OBJECT_TYPE_DEVICE_MEMORY)
2917 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, base, VkFence, VK_OBJECT_TYPE_FENCE)
2918 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_event, base, VkEvent, VK_OBJECT_TYPE_EVENT)
2919 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, base, VkFramebuffer,
2920 VK_OBJECT_TYPE_FRAMEBUFFER)
2921 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image, base, VkImage, VK_OBJECT_TYPE_IMAGE)
2922 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, base, VkImageView,
2923 VK_OBJECT_TYPE_IMAGE_VIEW);
2924 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, base, VkPipelineCache,
2925 VK_OBJECT_TYPE_PIPELINE_CACHE)
2926 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, base, VkPipeline,
2927 VK_OBJECT_TYPE_PIPELINE)
2928 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, base, VkPipelineLayout,
2929 VK_OBJECT_TYPE_PIPELINE_LAYOUT)
2930 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, base, VkQueryPool,
2931 VK_OBJECT_TYPE_QUERY_POOL)
2932 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, base, VkRenderPass,
2933 VK_OBJECT_TYPE_RENDER_PASS)
2934 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, base, VkSampler,
2935 VK_OBJECT_TYPE_SAMPLER)
2936 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, base,
2937 VkSamplerYcbcrConversion,
2938 VK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION)
2939 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, base, VkSemaphore,
2940 VK_OBJECT_TYPE_SEMAPHORE)
2941
2942 #ifdef __cplusplus
2943 }
2944 #endif
2945
2946 #endif /* RADV_PRIVATE_H */
2947