1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/bitset.h"
29 #include "util/format/u_format.h"
30 #include "util/u_inlines.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd5_emit.h"
37 #include "fd5_format.h"
38 #include "fd5_program.h"
39 #include "fd5_texture.h"
40
41 #include "ir3_cache.h"
42
43 void
fd5_emit_shader(struct fd_ringbuffer * ring,const struct ir3_shader_variant * so)44 fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
45 {
46 const struct ir3_info *si = &so->info;
47 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
48 enum a4xx_state_src src;
49 uint32_t i, sz, *bin;
50
51 if (FD_DBG(DIRECT)) {
52 sz = si->sizedwords;
53 src = SS4_DIRECT;
54 bin = fd_bo_map(so->bo);
55 } else {
56 sz = 0;
57 src = SS4_INDIRECT;
58 bin = NULL;
59 }
60
61 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
62 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
63 CP_LOAD_STATE4_0_STATE_SRC(src) |
64 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
65 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
66 if (bin) {
67 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
68 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
69 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
70 } else {
71 OUT_RELOC(ring, so->bo, 0, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
72 }
73
74 /* for how clever coverity is, it is sometimes rather dull, and
75 * doesn't realize that the only case where bin==NULL, sz==0:
76 */
77 assume(bin || (sz == 0));
78
79 for (i = 0; i < sz; i++) {
80 OUT_RING(ring, bin[i]);
81 }
82 }
83
84 /* TODO maybe some of this we could pre-compute once rather than having
85 * so much draw-time logic?
86 */
87 static void
emit_stream_out(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,struct ir3_shader_linkage * l)88 emit_stream_out(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
89 struct ir3_shader_linkage *l)
90 {
91 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
92 unsigned ncomp[PIPE_MAX_SO_BUFFERS] = {0};
93 unsigned prog[align(l->max_loc, 2) / 2];
94
95 memset(prog, 0, sizeof(prog));
96
97 for (unsigned i = 0; i < strmout->num_outputs; i++) {
98 const struct ir3_stream_output *out = &strmout->output[i];
99 unsigned k = out->register_index;
100 unsigned idx;
101
102 ncomp[out->output_buffer] += out->num_components;
103
104 /* linkage map sorted by order frag shader wants things, so
105 * a bit less ideal here..
106 */
107 for (idx = 0; idx < l->cnt; idx++)
108 if (l->var[idx].regid == v->outputs[k].regid)
109 break;
110
111 debug_assert(idx < l->cnt);
112
113 for (unsigned j = 0; j < out->num_components; j++) {
114 unsigned c = j + out->start_component;
115 unsigned loc = l->var[idx].loc + c;
116 unsigned off = j + out->dst_offset; /* in dwords */
117
118 if (loc & 1) {
119 prog[loc / 2] |= A5XX_VPC_SO_PROG_B_EN |
120 A5XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
121 A5XX_VPC_SO_PROG_B_OFF(off * 4);
122 } else {
123 prog[loc / 2] |= A5XX_VPC_SO_PROG_A_EN |
124 A5XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
125 A5XX_VPC_SO_PROG_A_OFF(off * 4);
126 }
127 }
128 }
129
130 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * ARRAY_SIZE(prog)));
131 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL);
132 OUT_RING(ring, A5XX_VPC_SO_BUF_CNTL_ENABLE |
133 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) |
134 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) |
135 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) |
136 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3));
137 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(0));
138 OUT_RING(ring, ncomp[0]);
139 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(1));
140 OUT_RING(ring, ncomp[1]);
141 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(2));
142 OUT_RING(ring, ncomp[2]);
143 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(3));
144 OUT_RING(ring, ncomp[3]);
145 OUT_RING(ring, REG_A5XX_VPC_SO_CNTL);
146 OUT_RING(ring, A5XX_VPC_SO_CNTL_ENABLE);
147 for (unsigned i = 0; i < ARRAY_SIZE(prog); i++) {
148 OUT_RING(ring, REG_A5XX_VPC_SO_PROG);
149 OUT_RING(ring, prog[i]);
150 }
151 }
152
153 struct stage {
154 const struct ir3_shader_variant *v;
155 const struct ir3_info *i;
156 /* const sizes are in units of 4 * vec4 */
157 uint8_t constoff;
158 uint8_t constlen;
159 /* instr sizes are in units of 16 instructions */
160 uint8_t instroff;
161 uint8_t instrlen;
162 };
163
164 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES };
165
166 static void
setup_stages(struct fd5_emit * emit,struct stage * s)167 setup_stages(struct fd5_emit *emit, struct stage *s)
168 {
169 unsigned i;
170
171 s[VS].v = fd5_emit_get_vp(emit);
172 s[FS].v = fd5_emit_get_fp(emit);
173
174 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
175
176 for (i = 0; i < MAX_STAGES; i++) {
177 if (s[i].v) {
178 s[i].i = &s[i].v->info;
179 /* constlen is in units of 4 * vec4: */
180 assert(s[i].v->constlen % 4 == 0);
181 s[i].constlen = s[i].v->constlen / 4;
182 /* instrlen is already in units of 16 instr.. although
183 * probably we should ditch that and not make the compiler
184 * care about instruction group size of a3xx vs a5xx
185 */
186 s[i].instrlen = s[i].v->instrlen;
187 } else {
188 s[i].i = NULL;
189 s[i].constlen = 0;
190 s[i].instrlen = 0;
191 }
192 }
193
194 /* NOTE: at least for gles2, blob partitions VS at bottom of const
195 * space and FS taking entire remaining space. We probably don't
196 * need to do that the same way, but for now mimic what the blob
197 * does to make it easier to diff against register values from blob
198 *
199 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
200 * is run from external memory.
201 */
202 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
203 /* prioritize FS for internal memory: */
204 if (s[FS].instrlen < 64) {
205 /* if FS can fit, kick VS out to external memory: */
206 s[VS].instrlen = 0;
207 } else if (s[VS].instrlen < 64) {
208 /* otherwise if VS can fit, kick out FS: */
209 s[FS].instrlen = 0;
210 } else {
211 /* neither can fit, run both from external memory: */
212 s[VS].instrlen = 0;
213 s[FS].instrlen = 0;
214 }
215 }
216
217 unsigned constoff = 0;
218 for (i = 0; i < MAX_STAGES; i++) {
219 s[i].constoff = constoff;
220 constoff += s[i].constlen;
221 }
222
223 s[VS].instroff = 0;
224 s[FS].instroff = 64 - s[FS].instrlen;
225 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
226 }
227
228 static inline uint32_t
next_regid(uint32_t reg,uint32_t increment)229 next_regid(uint32_t reg, uint32_t increment)
230 {
231 if (VALIDREG(reg))
232 return reg + increment;
233 else
234 return regid(63, 0);
235 }
236 void
fd5_program_emit(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd5_emit * emit)237 fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
238 struct fd5_emit *emit)
239 {
240 struct stage s[MAX_STAGES];
241 uint32_t pos_regid, psize_regid, color_regid[8];
242 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid,
243 samp_mask_regid;
244 uint32_t ij_regid[IJ_COUNT], vertex_regid, instance_regid, clip0_regid,
245 clip1_regid;
246 enum a3xx_threadsize fssz;
247 uint8_t psize_loc = ~0;
248 int i, j;
249
250 setup_stages(emit, s);
251
252 bool do_streamout = (s[VS].v->shader->stream_output.num_outputs > 0);
253 uint8_t clip_mask = s[VS].v->clip_mask,
254 cull_mask = s[VS].v->cull_mask;
255 uint8_t clip_cull_mask = clip_mask | cull_mask;
256
257 clip_mask &= ctx->rasterizer->clip_plane_enable;
258
259 fssz = (s[FS].i->double_threadsize) ? FOUR_QUADS : TWO_QUADS;
260
261 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
262 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
263 clip0_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_CLIP_DIST0);
264 clip1_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_CLIP_DIST1);
265 vertex_regid =
266 ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
267 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
268
269 if (s[FS].v->color0_mrt) {
270 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
271 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
272 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
273 } else {
274 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
275 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
276 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
277 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
278 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
279 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
280 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
281 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
282 }
283
284 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
285 samp_mask_regid =
286 ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
287 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
288 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
289 zwcoord_regid = next_regid(coord_regid, 2);
290 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
291 ij_regid[i] = ir3_find_sysval_regid(
292 s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
293
294 /* we could probably divide this up into things that need to be
295 * emitted if frag-prog is dirty vs if vert-prog is dirty..
296 */
297
298 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
299 OUT_RING(ring, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
300 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
301 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED));
302 OUT_RING(ring, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
303 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
304 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED));
305 OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
306 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
307 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
308 OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
309 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
310 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
311 OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
312 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
313 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
314
315 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
316 OUT_RING(ring, 0x00000000);
317
318 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
319 OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen) |
320 COND(s[VS].v && s[VS].v->has_ssbo,
321 A5XX_HLSQ_VS_CNTL_SSBO_ENABLE));
322 OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen) |
323 COND(s[FS].v && s[FS].v->has_ssbo,
324 A5XX_HLSQ_FS_CNTL_SSBO_ENABLE));
325 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen) |
326 COND(s[HS].v && s[HS].v->has_ssbo,
327 A5XX_HLSQ_HS_CNTL_SSBO_ENABLE));
328 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen) |
329 COND(s[DS].v && s[DS].v->has_ssbo,
330 A5XX_HLSQ_DS_CNTL_SSBO_ENABLE));
331 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen) |
332 COND(s[GS].v && s[GS].v->has_ssbo,
333 A5XX_HLSQ_GS_CNTL_SSBO_ENABLE));
334
335 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
336 OUT_RING(ring, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
337 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
338 COND(s[VS].v, A5XX_SP_VS_CONFIG_ENABLED));
339 OUT_RING(ring, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
340 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
341 COND(s[FS].v, A5XX_SP_FS_CONFIG_ENABLED));
342 OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
343 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
344 COND(s[HS].v, A5XX_SP_HS_CONFIG_ENABLED));
345 OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
346 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
347 COND(s[DS].v, A5XX_SP_DS_CONFIG_ENABLED));
348 OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
349 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
350 COND(s[GS].v, A5XX_SP_GS_CONFIG_ENABLED));
351
352 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
353 OUT_RING(ring, 0x00000000);
354
355 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
356 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
357 OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
358
359 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
360 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
361 OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
362
363 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
364 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
365 OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
366
367 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
368 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
369 OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
370
371 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
372 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
373 OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
374
375 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
376 OUT_RING(ring, 0x00000000); /* HLSQ_CS_CONSTLEN */
377 OUT_RING(ring, 0x00000000); /* HLSQ_CS_INSTRLEN */
378
379 OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
380 OUT_RING(
381 ring,
382 A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
383 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
384 0x6 | /* XXX seems to be always set? */
385 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(s[VS].v)) |
386 COND(s[VS].v->need_pixlod, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
387
388 /* If we have streamout, link against the real FS in the binning program,
389 * rather than the dummy FS used for binning pass state, to ensure the
390 * OUTLOC's match. Depending on whether we end up doing sysmem or gmem, the
391 * actual streamout could happen with either the binning pass or draw pass
392 * program, but the same streamout stateobj is used in either case:
393 */
394 const struct ir3_shader_variant *link_fs = s[FS].v;
395 if (do_streamout && emit->binning_pass)
396 link_fs = emit->prog->fs;
397 struct ir3_shader_linkage l = {0};
398 ir3_link_shaders(&l, s[VS].v, link_fs, true);
399
400 uint8_t clip0_loc = l.clip0_loc;
401 uint8_t clip1_loc = l.clip1_loc;
402
403 OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
404 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
405 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
406 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
407 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
408
409 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
410 ir3_link_stream_out(&l, s[VS].v);
411
412 /* a5xx appends pos/psize to end of the linkage map: */
413 if (VALIDREG(pos_regid))
414 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
415
416 if (VALIDREG(psize_regid)) {
417 psize_loc = l.max_loc;
418 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
419 }
420
421 /* Handle the case where clip/cull distances aren't read by the FS. Make
422 * sure to avoid adding an output with an empty writemask if the user
423 * disables all the clip distances in the API so that the slot is unused.
424 */
425 if (clip0_loc == 0xff && VALIDREG(clip0_regid) &&
426 (clip_cull_mask & 0xf) != 0) {
427 clip0_loc = l.max_loc;
428 ir3_link_add(&l, clip0_regid, clip_cull_mask & 0xf, l.max_loc);
429 }
430
431 if (clip1_loc == 0xff && VALIDREG(clip1_regid) &&
432 (clip_cull_mask >> 4) != 0) {
433 clip1_loc = l.max_loc;
434 ir3_link_add(&l, clip1_regid, clip_cull_mask >> 4, l.max_loc);
435 }
436
437 /* If we have stream-out, we use the full shader for binning
438 * pass, rather than the optimized binning pass one, so that we
439 * have all the varying outputs available for xfb. So streamout
440 * state should always be derived from the non-binning pass
441 * program:
442 */
443 if (do_streamout && !emit->binning_pass)
444 emit_stream_out(ring, s[VS].v, &l);
445
446 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
447 uint32_t reg = 0;
448
449 OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
450
451 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
452 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
453 j++;
454
455 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
456 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
457 j++;
458
459 OUT_RING(ring, reg);
460 }
461
462 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
463 uint32_t reg = 0;
464
465 OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
466
467 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
468 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
469 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
470 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
471
472 OUT_RING(ring, reg);
473 }
474
475 OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2);
476 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
477
478 if (s[VS].instrlen)
479 fd5_emit_shader(ring, s[VS].v);
480
481 // TODO depending on other bits in this reg (if any) set somewhere else?
482 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
483 OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
484
485 OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
486 OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
487
488 OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
489 OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) |
490 COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
491 0x10000); // XXX
492
493 fd5_context(ctx)->max_loc = l.max_loc;
494
495 if (emit->binning_pass) {
496 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
497 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
498 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
499 } else {
500 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
501 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
502 }
503
504 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
505 OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
506 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS) |
507 0x00000880); /* XXX HLSQ_CONTROL_0 */
508 OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
509 OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
510 A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
511 A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
512 A5XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
513 OUT_RING(
514 ring,
515 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
516 A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
517 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(
518 ij_regid[IJ_PERSP_CENTROID]) |
519 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(
520 ij_regid[IJ_LINEAR_CENTROID]));
521 OUT_RING(
522 ring,
523 A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
524 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
525 A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
526 A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
527
528 OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
529 OUT_RING(
530 ring,
531 COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
532 0x40006 | /* XXX set pretty much everywhere */
533 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
534 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
535 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
536 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(s[FS].v)) |
537 COND(s[FS].v->need_pixlod, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
538
539 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
540 OUT_RING(ring, 0x020fffff); /* XXX */
541
542 OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
543 OUT_RING(ring, 0x0000ffff); /* XXX */
544
545 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
546 OUT_RING(ring, 0x00000010); /* XXX */
547
548 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
549 OUT_RING(ring,
550 CONDREG(ij_regid[IJ_PERSP_PIXEL], A5XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
551 CONDREG(ij_regid[IJ_PERSP_CENTROID],
552 A5XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
553 CONDREG(ij_regid[IJ_PERSP_SAMPLE],
554 A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
555 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
556 CONDREG(ij_regid[IJ_LINEAR_CENTROID],
557 A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID) |
558 CONDREG(ij_regid[IJ_LINEAR_SAMPLE],
559 A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
560 COND(s[FS].v->fragcoord_compmask != 0,
561 A5XX_GRAS_CNTL_COORD_MASK(s[FS].v->fragcoord_compmask) |
562 A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
563 COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
564 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL));
565
566 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
567 OUT_RING(
568 ring,
569 CONDREG(ij_regid[IJ_PERSP_PIXEL],
570 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
571 CONDREG(ij_regid[IJ_PERSP_CENTROID],
572 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
573 CONDREG(ij_regid[IJ_PERSP_SAMPLE],
574 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
575 CONDREG(ij_regid[IJ_LINEAR_PIXEL],
576 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
577 CONDREG(ij_regid[IJ_LINEAR_CENTROID],
578 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID) |
579 CONDREG(ij_regid[IJ_LINEAR_SAMPLE],
580 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
581 COND(s[FS].v->fragcoord_compmask != 0,
582 A5XX_RB_RENDER_CONTROL0_COORD_MASK(s[FS].v->fragcoord_compmask) |
583 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
584 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
585 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL));
586 OUT_RING(ring,
587 CONDREG(samp_mask_regid, A5XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
588 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS) |
589 CONDREG(samp_id_regid, A5XX_RB_RENDER_CONTROL1_SAMPLEID));
590
591 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
592 for (i = 0; i < 8; i++) {
593 OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
594 COND(color_regid[i] & HALF_REG_ID,
595 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
596 }
597
598 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
599 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
600 A5XX_VPC_PACK_PSIZELOC(psize_loc));
601
602 if (!emit->binning_pass) {
603 uint32_t vinterp[8], vpsrepl[8];
604
605 memset(vinterp, 0, sizeof(vinterp));
606 memset(vpsrepl, 0, sizeof(vpsrepl));
607
608 /* looks like we need to do int varyings in the frag
609 * shader on a5xx (no flatshad reg? or a420.0 bug?):
610 *
611 * (sy)(ss)nop
612 * (sy)ldlv.u32 r0.x,l[r0.x], 1
613 * ldlv.u32 r0.y,l[r0.x+1], 1
614 * (ss)bary.f (ei)r63.x, 0, r0.x
615 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
616 * (rpt5)nop
617 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
618 *
619 * Possibly on later a5xx variants we'll be able to use
620 * something like the code below instead of workaround
621 * in the shader:
622 */
623 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
624 for (j = -1;
625 (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count;) {
626 /* NOTE: varyings are packed, so if compmask is 0xb
627 * then first, third, and fourth component occupy
628 * three consecutive varying slots:
629 */
630 unsigned compmask = s[FS].v->inputs[j].compmask;
631
632 uint32_t inloc = s[FS].v->inputs[j].inloc;
633
634 if (s[FS].v->inputs[j].flat ||
635 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
636 uint32_t loc = inloc;
637
638 for (i = 0; i < 4; i++) {
639 if (compmask & (1 << i)) {
640 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
641 // flatshade[loc / 32] |= 1 << (loc % 32);
642 loc++;
643 }
644 }
645 }
646
647 bool coord_mode = emit->sprite_coord_mode;
648 if (ir3_point_sprite(s[FS].v, j, emit->sprite_coord_enable,
649 &coord_mode)) {
650 /* mask is two 2-bit fields, where:
651 * '01' -> S
652 * '10' -> T
653 * '11' -> 1 - T (flip mode)
654 */
655 unsigned mask = coord_mode ? 0b1101 : 0b1001;
656 uint32_t loc = inloc;
657 if (compmask & 0x1) {
658 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
659 loc++;
660 }
661 if (compmask & 0x2) {
662 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
663 loc++;
664 }
665 if (compmask & 0x4) {
666 /* .z <- 0.0f */
667 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
668 loc++;
669 }
670 if (compmask & 0x8) {
671 /* .w <- 1.0f */
672 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
673 loc++;
674 }
675 }
676 }
677
678 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
679 for (i = 0; i < 8; i++)
680 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
681
682 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
683 for (i = 0; i < 8; i++)
684 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
685 }
686
687 OUT_PKT4(ring, REG_A5XX_GRAS_VS_CL_CNTL, 1);
688 OUT_RING(ring, A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(clip_mask) |
689 A5XX_GRAS_VS_CL_CNTL_CULL_MASK(cull_mask));
690
691 OUT_PKT4(ring, REG_A5XX_VPC_CLIP_CNTL, 1);
692 OUT_RING(ring, A5XX_VPC_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
693 A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
694 A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
695
696 OUT_PKT4(ring, REG_A5XX_PC_CLIP_CNTL, 1);
697 OUT_RING(ring, A5XX_PC_CLIP_CNTL_CLIP_MASK(clip_mask));
698
699 if (!emit->binning_pass)
700 if (s[FS].instrlen)
701 fd5_emit_shader(ring, s[FS].v);
702
703 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5);
704 OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
705 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid) | 0xfc0000);
706 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
707 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_3 */
708 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
709 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
710 }
711
712 static struct ir3_program_state *
fd5_program_create(void * data,struct ir3_shader_variant * bs,struct ir3_shader_variant * vs,struct ir3_shader_variant * hs,struct ir3_shader_variant * ds,struct ir3_shader_variant * gs,struct ir3_shader_variant * fs,const struct ir3_cache_key * key)713 fd5_program_create(void *data, struct ir3_shader_variant *bs,
714 struct ir3_shader_variant *vs, struct ir3_shader_variant *hs,
715 struct ir3_shader_variant *ds, struct ir3_shader_variant *gs,
716 struct ir3_shader_variant *fs,
717 const struct ir3_cache_key *key) in_dt
718 {
719 struct fd_context *ctx = fd_context(data);
720 struct fd5_program_state *state = CALLOC_STRUCT(fd5_program_state);
721
722 tc_assert_driver_thread(ctx->tc);
723
724 state->bs = bs;
725 state->vs = vs;
726 state->fs = fs;
727
728 return &state->base;
729 }
730
731 static void
fd5_program_destroy(void * data,struct ir3_program_state * state)732 fd5_program_destroy(void *data, struct ir3_program_state *state)
733 {
734 struct fd5_program_state *so = fd5_program_state(state);
735 free(so);
736 }
737
738 static const struct ir3_cache_funcs cache_funcs = {
739 .create_state = fd5_program_create,
740 .destroy_state = fd5_program_destroy,
741 };
742
743 void
fd5_prog_init(struct pipe_context * pctx)744 fd5_prog_init(struct pipe_context *pctx)
745 {
746 struct fd_context *ctx = fd_context(pctx);
747
748 ctx->shader_cache = ir3_cache_create(&cache_funcs, ctx);
749 ir3_prog_init(pctx);
750 fd_prog_init(pctx);
751 }
752