1 /**************************************************************************
2  *
3  * Copyright 2017 Advanced Micro Devices, Inc.
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 #include "pipe/p_video_codec.h"
29 #include "radeon_vcn_enc.h"
30 #include "radeon_video.h"
31 #include "radeon_temporal.h"
32 #include "si_pipe.h"
33 #include "util/u_video.h"
34 
35 #include <stdio.h>
36 
37 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
38 #define RENCODE_FW_INTERFACE_MINOR_VERSION 2
39 
40 #define RENCODE_IB_PARAM_SESSION_INFO              0x00000001
41 #define RENCODE_IB_PARAM_TASK_INFO                 0x00000002
42 #define RENCODE_IB_PARAM_SESSION_INIT              0x00000003
43 #define RENCODE_IB_PARAM_LAYER_CONTROL             0x00000004
44 #define RENCODE_IB_PARAM_LAYER_SELECT              0x00000005
45 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
46 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x00000007
47 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x00000008
48 #define RENCODE_IB_PARAM_QUALITY_PARAMS            0x00000009
49 #define RENCODE_IB_PARAM_SLICE_HEADER              0x0000000a
50 #define RENCODE_IB_PARAM_ENCODE_PARAMS             0x0000000b
51 #define RENCODE_IB_PARAM_INTRA_REFRESH             0x0000000c
52 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER     0x0000000d
53 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER    0x0000000e
54 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER           0x00000010
55 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU        0x00000020
56 
57 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL        0x00100001
58 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC            0x00100002
59 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER    0x00100003
60 
61 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL        0x00200001
62 #define RENCODE_H264_IB_PARAM_SPEC_MISC            0x00200002
63 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS        0x00200003
64 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER    0x00200004
65 
radeon_enc_session_info(struct radeon_encoder * enc)66 static void radeon_enc_session_info(struct radeon_encoder *enc)
67 {
68    RADEON_ENC_BEGIN(enc->cmd.session_info);
69    RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
70    RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
71    RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE);
72    RADEON_ENC_END();
73 }
74 
radeon_enc_task_info(struct radeon_encoder * enc,bool need_feedback)75 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
76 {
77    enc->enc_pic.task_info.task_id++;
78 
79    if (need_feedback)
80       enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
81    else
82       enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
83 
84    RADEON_ENC_BEGIN(enc->cmd.task_info);
85    enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++];
86    RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
87    RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
88    RADEON_ENC_END();
89 }
90 
radeon_enc_session_init(struct radeon_encoder * enc)91 static void radeon_enc_session_init(struct radeon_encoder *enc)
92 {
93    enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
94    enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
95    enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
96    enc->enc_pic.session_init.padding_width =
97       enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
98    enc->enc_pic.session_init.padding_height =
99       enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
100    enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
101    enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
102 
103    RADEON_ENC_BEGIN(enc->cmd.session_init);
104    RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
105    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
106    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
107    RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
108    RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
109    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
110    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
111    RADEON_ENC_END();
112 }
113 
radeon_enc_session_init_hevc(struct radeon_encoder * enc)114 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
115 {
116    enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
117    enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
118    enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
119    enc->enc_pic.session_init.padding_width =
120       enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
121    enc->enc_pic.session_init.padding_height =
122       enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
123    enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
124    enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
125 
126    RADEON_ENC_BEGIN(enc->cmd.session_init);
127    RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
128    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
129    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
130    RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
131    RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
132    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
133    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
134    RADEON_ENC_END();
135 }
136 
radeon_enc_layer_control(struct radeon_encoder * enc)137 static void radeon_enc_layer_control(struct radeon_encoder *enc)
138 {
139    enc->enc_pic.layer_ctrl.max_num_temporal_layers = enc->enc_pic.num_temporal_layers;
140    enc->enc_pic.layer_ctrl.num_temporal_layers = enc->enc_pic.num_temporal_layers;
141 
142    RADEON_ENC_BEGIN(enc->cmd.layer_control);
143    RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
144    RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
145    RADEON_ENC_END();
146 }
147 
radeon_enc_layer_select(struct radeon_encoder * enc)148 static void radeon_enc_layer_select(struct radeon_encoder *enc)
149 {
150    enc->enc_pic.layer_sel.temporal_layer_index = enc->enc_pic.temporal_id;
151 
152    RADEON_ENC_BEGIN(enc->cmd.layer_select);
153    RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
154    RADEON_ENC_END();
155 }
156 
radeon_enc_slice_control(struct radeon_encoder * enc)157 static void radeon_enc_slice_control(struct radeon_encoder *enc)
158 {
159    enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
160    enc->enc_pic.slice_ctrl.num_mbs_per_slice =
161       align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
162 
163    RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
164    RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
165    RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
166    RADEON_ENC_END();
167 }
168 
radeon_enc_slice_control_hevc(struct radeon_encoder * enc)169 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
170 {
171    enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
172    enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
173       align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
174    enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
175       enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
176 
177    RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
178    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
179    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
180    RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
181    RADEON_ENC_END();
182 }
183 
radeon_enc_spec_misc(struct radeon_encoder * enc)184 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
185 {
186    enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
187    enc->enc_pic.spec_misc.cabac_enable = 0;
188    enc->enc_pic.spec_misc.cabac_init_idc = 0;
189    enc->enc_pic.spec_misc.half_pel_enabled = 1;
190    enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
191    enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
192    enc->enc_pic.spec_misc.level_idc = enc->base.level;
193 
194    RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
195    RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
196    RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
197    RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
198    RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
199    RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
200    RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
201    RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
202    RADEON_ENC_END();
203 }
204 
radeon_enc_spec_misc_hevc(struct radeon_encoder * enc)205 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
206 {
207    RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
208    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
209    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
210    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
211    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
212    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
213    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
214    RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
215    RADEON_ENC_END();
216 }
217 
radeon_enc_rc_session_init(struct radeon_encoder * enc)218 static void radeon_enc_rc_session_init(struct radeon_encoder *enc)
219 {
220    RADEON_ENC_BEGIN(enc->cmd.rc_session_init);
221    RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
222    RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
223    RADEON_ENC_END();
224 }
225 
radeon_enc_rc_layer_init(struct radeon_encoder * enc)226 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
227 {
228    unsigned int i = enc->enc_pic.temporal_id;
229    RADEON_ENC_BEGIN(enc->cmd.rc_layer_init);
230    RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].target_bit_rate);
231    RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bit_rate);
232    RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_num);
233    RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_den);
234    RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].vbv_buffer_size);
235    RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture);
236    RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer);
237    RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional);
238    RADEON_ENC_END();
239 }
240 
radeon_enc_deblocking_filter_h264(struct radeon_encoder * enc)241 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
242 {
243    enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
244    enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
245    enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
246    enc->enc_pic.h264_deblock.cb_qp_offset = 0;
247    enc->enc_pic.h264_deblock.cr_qp_offset = 0;
248 
249    RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264);
250    RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
251    RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
252    RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
253    RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
254    RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
255    RADEON_ENC_END();
256 }
257 
radeon_enc_deblocking_filter_hevc(struct radeon_encoder * enc)258 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc)
259 {
260    RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
261    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
262    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
263    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
264    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
265    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
266    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
267    RADEON_ENC_END();
268 }
269 
radeon_enc_quality_params(struct radeon_encoder * enc)270 static void radeon_enc_quality_params(struct radeon_encoder *enc)
271 {
272    enc->enc_pic.quality_params.vbaq_mode = 0;
273    enc->enc_pic.quality_params.scene_change_sensitivity = 0;
274    enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
275 
276    RADEON_ENC_BEGIN(enc->cmd.quality_params);
277    RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
278    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
279    RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
280    RADEON_ENC_END();
281 }
282 
radeon_enc_nalu_sps(struct radeon_encoder * enc)283 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
284 {
285    RADEON_ENC_BEGIN(enc->cmd.nalu);
286    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
287    uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
288    radeon_enc_reset(enc);
289    radeon_enc_set_emulation_prevention(enc, false);
290    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
291    radeon_enc_code_fixed_bits(enc, 0x67, 8);
292    radeon_enc_byte_align(enc);
293    radeon_enc_set_emulation_prevention(enc, true);
294    radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
295    radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline
296    radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
297    radeon_enc_code_ue(enc, 0x0);
298 
299    if (enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 ||
300        enc->enc_pic.spec_misc.profile_idc == 122 || enc->enc_pic.spec_misc.profile_idc == 244 ||
301        enc->enc_pic.spec_misc.profile_idc == 44  || enc->enc_pic.spec_misc.profile_idc == 83 ||
302        enc->enc_pic.spec_misc.profile_idc == 86  || enc->enc_pic.spec_misc.profile_idc == 118 ||
303        enc->enc_pic.spec_misc.profile_idc == 128 || enc->enc_pic.spec_misc.profile_idc == 138) {
304       radeon_enc_code_ue(enc, 0x1);
305       radeon_enc_code_ue(enc, 0x0);
306       radeon_enc_code_ue(enc, 0x0);
307       radeon_enc_code_fixed_bits(enc, 0x0, 2);
308    }
309 
310    radeon_enc_code_ue(enc, 1);
311    radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
312 
313    if (enc->enc_pic.pic_order_cnt_type == 0)
314       radeon_enc_code_ue(enc, 1);
315 
316    radeon_enc_code_ue(enc, (enc->base.max_references + 1));
317    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
318                               1);
319    radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
320    radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
321    bool progressive_only = true;
322    radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
323 
324    if (!progressive_only)
325       radeon_enc_code_fixed_bits(enc, 0x0, 1);
326 
327    radeon_enc_code_fixed_bits(enc, 0x1, 1);
328 
329    if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right  != 0) ||
330        (enc->enc_pic.crop_top  != 0) || (enc->enc_pic.crop_bottom != 0)) {
331       radeon_enc_code_fixed_bits(enc, 0x1, 1);
332       radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
333       radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
334       radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
335       radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
336    } else
337       radeon_enc_code_fixed_bits(enc, 0x0, 1);
338 
339    radeon_enc_code_fixed_bits(enc, 0x1, 1);
340    radeon_enc_code_fixed_bits(enc, 0x0, 1);
341    radeon_enc_code_fixed_bits(enc, 0x0, 1);
342    radeon_enc_code_fixed_bits(enc, 0x0, 1);
343    radeon_enc_code_fixed_bits(enc, 0x0, 1);
344    radeon_enc_code_fixed_bits(enc, 0x0, 1);
345    radeon_enc_code_fixed_bits(enc, 0x0, 1);
346    radeon_enc_code_fixed_bits(enc, 0x0, 1);
347    radeon_enc_code_fixed_bits(enc, 0x0, 1);
348    radeon_enc_code_fixed_bits(enc, 0x1, 1);
349    radeon_enc_code_fixed_bits(enc, 0x1, 1);
350    radeon_enc_code_ue(enc, 0x0);
351    radeon_enc_code_ue(enc, 0x0);
352    radeon_enc_code_ue(enc, 16);
353    radeon_enc_code_ue(enc, 16);
354    radeon_enc_code_ue(enc, 0x0);
355    radeon_enc_code_ue(enc, (enc->base.max_references + 1));
356 
357    radeon_enc_code_fixed_bits(enc, 0x1, 1);
358 
359    radeon_enc_byte_align(enc);
360    radeon_enc_flush_headers(enc);
361    *size_in_bytes = (enc->bits_output + 7) / 8;
362    RADEON_ENC_END();
363 }
364 
radeon_enc_nalu_sps_hevc(struct radeon_encoder * enc)365 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
366 {
367    RADEON_ENC_BEGIN(enc->cmd.nalu);
368    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
369    uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
370    int i;
371 
372    radeon_enc_reset(enc);
373    radeon_enc_set_emulation_prevention(enc, false);
374    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
375    radeon_enc_code_fixed_bits(enc, 0x4201, 16);
376    radeon_enc_byte_align(enc);
377    radeon_enc_set_emulation_prevention(enc, true);
378    radeon_enc_code_fixed_bits(enc, 0x0, 4);
379    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
380    radeon_enc_code_fixed_bits(enc, 0x1, 1);
381    radeon_enc_code_fixed_bits(enc, 0x0, 2);
382    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
383    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
384    radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
385    radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
386    radeon_enc_code_fixed_bits(enc, 0x0, 16);
387    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
388 
389    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
390       radeon_enc_code_fixed_bits(enc, 0x0, 2);
391 
392    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
393       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
394          radeon_enc_code_fixed_bits(enc, 0x0, 2);
395    }
396 
397    radeon_enc_code_ue(enc, 0x0);
398    radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
399    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
400    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
401 
402    if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right  != 0) ||
403        (enc->enc_pic.crop_top  != 0) || (enc->enc_pic.crop_bottom != 0)) {
404       radeon_enc_code_fixed_bits(enc, 0x1, 1);
405       radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
406       radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
407       radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
408       radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
409    } else if (enc->enc_pic.session_init.padding_width  != 0 ||
410               enc->enc_pic.session_init.padding_height != 0) {
411       radeon_enc_code_fixed_bits(enc, 0x1, 1);
412       radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
413       radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
414       radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
415       radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
416    } else
417       radeon_enc_code_fixed_bits(enc, 0x0, 1);
418 
419    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
420    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
421    radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
422    radeon_enc_code_fixed_bits(enc, 0x0, 1);
423    radeon_enc_code_ue(enc, 1);
424    radeon_enc_code_ue(enc, 0x0);
425    radeon_enc_code_ue(enc, 0x0);
426    radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
427    // Only support CTBSize 64
428    radeon_enc_code_ue(enc,
429                       6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
430    radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
431    radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
432    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
433    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
434 
435    radeon_enc_code_fixed_bits(enc, 0x0, 1);
436    radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
437    radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
438    radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
439 
440    radeon_enc_code_ue(enc, 1);
441    radeon_enc_code_ue(enc, 1);
442    radeon_enc_code_ue(enc, 0);
443    radeon_enc_code_ue(enc, 0);
444    radeon_enc_code_fixed_bits(enc, 0x1, 1);
445 
446    radeon_enc_code_fixed_bits(enc, 0x0, 1);
447 
448    radeon_enc_code_fixed_bits(enc, 0, 1);
449    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
450 
451    radeon_enc_code_fixed_bits(enc, 0x0, 1);
452 
453    radeon_enc_code_fixed_bits(enc, 0x0, 1);
454 
455    radeon_enc_code_fixed_bits(enc, 0x1, 1);
456 
457    radeon_enc_byte_align(enc);
458    radeon_enc_flush_headers(enc);
459    *size_in_bytes = (enc->bits_output + 7) / 8;
460    RADEON_ENC_END();
461 }
462 
radeon_enc_nalu_prefix(struct radeon_encoder * enc)463 static void radeon_enc_nalu_prefix(struct radeon_encoder *enc)
464 {
465    uint nalRefIdc = enc->enc_pic.is_idr ? 3 : 0;
466 
467    rvcn_temporal_layer_pattern_table_t table_info;
468    table_info = rvcn_temporal_layer_pattern_tables[enc->enc_pic.layer_ctrl.num_temporal_layers];
469 
470    if (enc->enc_pic.pic_order_cnt == 0)
471       enc->enc_pic.temporal_layer_pattern_index = 0;
472    else if(enc->enc_pic.temporal_layer_pattern_index == (table_info.pattern_size - 1))
473       enc->enc_pic.temporal_layer_pattern_index = 1;
474    else
475       enc->enc_pic.temporal_layer_pattern_index++;
476 
477    rvcn_temporal_layer_pattern_entry_t pattern =
478       table_info.pattern_table[enc->enc_pic.temporal_layer_pattern_index];
479 
480    RADEON_ENC_BEGIN(enc->cmd.nalu);
481    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX);
482    uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
483    radeon_enc_reset(enc);
484    radeon_enc_set_emulation_prevention(enc, false);
485    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
486    radeon_enc_code_fixed_bits(enc, 0x0, 1);
487    radeon_enc_code_fixed_bits(enc, nalRefIdc, 2);
488    radeon_enc_code_fixed_bits(enc, 14, 5);
489    radeon_enc_byte_align(enc);
490    radeon_enc_set_emulation_prevention(enc, true);
491    radeon_enc_code_fixed_bits(enc, 0x1, 1);
492    radeon_enc_code_fixed_bits(enc, enc->enc_pic.is_idr ? 0x1 : 0x0, 1);
493    radeon_enc_code_fixed_bits(enc, 0x0, 6);
494    radeon_enc_code_fixed_bits(enc, 0x1, 1);
495    radeon_enc_code_fixed_bits(enc, 0x0, 3);
496    radeon_enc_code_fixed_bits(enc, 0x0, 4);
497    radeon_enc_code_fixed_bits(enc, pattern.temporal_id, 3);
498    radeon_enc_code_fixed_bits(enc, 0x0, 1);
499    radeon_enc_code_fixed_bits(enc, 0x0, 1);
500    radeon_enc_code_fixed_bits(enc, 0x0, 1);
501    radeon_enc_code_fixed_bits(enc, 0x3, 2);
502 
503    if(nalRefIdc != 0)
504    {
505       radeon_enc_code_fixed_bits(enc, 0x0, 1);
506       radeon_enc_code_fixed_bits(enc, 0x0, 1);
507       radeon_enc_code_fixed_bits(enc, 0x1, 1);
508       radeon_enc_byte_align(enc);
509    }
510 
511    radeon_enc_flush_headers(enc);
512    *size_in_bytes = (enc->bits_output + 7) / 8;
513    RADEON_ENC_END();
514 }
515 
radeon_enc_nalu_sei(struct radeon_encoder * enc)516 static void radeon_enc_nalu_sei(struct radeon_encoder *enc)
517 {
518    unsigned number_of_layers;
519 
520    rvcn_temporal_layer_pattern_table_t table_info;
521    table_info = rvcn_temporal_layer_pattern_tables[enc->enc_pic.layer_ctrl.num_temporal_layers - 1];
522    number_of_layers = table_info.pattern_size;
523 
524    RADEON_ENC_BEGIN(enc->cmd.nalu);
525    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SEI);
526    unsigned *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
527    radeon_enc_reset(enc);
528    radeon_enc_set_emulation_prevention(enc, false);
529 
530    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
531    radeon_enc_code_fixed_bits(enc, 0x6, 8);
532    radeon_enc_byte_align(enc);
533 
534    radeon_enc_set_emulation_prevention(enc, true);
535 
536    /* save the current position for later */
537    unsigned position = enc->cs.current.cdw;
538    unsigned shifter = enc->shifter;
539    unsigned bits_in_shifter = enc->bits_in_shifter;
540    unsigned num_zeros = enc->num_zeros;
541    unsigned byte_index = enc->byte_index;
542    unsigned bits_output = enc->bits_output;
543    bool emulation_prevention = enc->emulation_prevention;
544 
545    /* temporarily fill out the payload type and size */
546    radeon_enc_code_fixed_bits(enc, 24, 8);
547    radeon_enc_code_fixed_bits(enc, 0, 8);
548 
549    unsigned svc_start_offset = enc->bits_size;
550 
551    radeon_enc_code_fixed_bits(enc, 0x0, 1);
552    radeon_enc_code_fixed_bits(enc, 0x0, 1);
553    radeon_enc_code_fixed_bits(enc, 0x0, 1);
554    radeon_enc_code_ue(enc, number_of_layers - 1);
555 
556    for(int i = 0; i < number_of_layers; i++ )
557    {
558       rvcn_temporal_layer_pattern_entry_t pattern = table_info.pattern_table[i];
559       radeon_enc_code_ue(enc, i);
560       radeon_enc_code_fixed_bits(enc, 0x0, 6);
561       radeon_enc_code_fixed_bits(enc, 0x0, 1);
562       radeon_enc_code_fixed_bits(enc, 0x0, 3);
563       radeon_enc_code_fixed_bits(enc, 0x0, 4);
564       radeon_enc_code_fixed_bits(enc, pattern.temporal_id, 3);
565       radeon_enc_code_fixed_bits(enc, 0x0, 1);
566       radeon_enc_code_fixed_bits(enc, 0x0, 1);
567       radeon_enc_code_fixed_bits(enc, 0x0, 1);
568       radeon_enc_code_fixed_bits(enc, 0x0, 1);
569       radeon_enc_code_fixed_bits(enc, 0x0, 1);
570       radeon_enc_code_fixed_bits(enc, 0x0, 1);
571       radeon_enc_code_fixed_bits(enc, 0x0, 1);
572       radeon_enc_code_fixed_bits(enc, 0x0, 1);
573       radeon_enc_code_fixed_bits(enc, 0x0, 1);
574       radeon_enc_code_fixed_bits(enc, 0x0, 1);
575       radeon_enc_code_fixed_bits(enc, 0x0, 1);
576       radeon_enc_code_fixed_bits(enc, 0x0, 1);
577       radeon_enc_code_fixed_bits(enc, 0x0, 1);
578       radeon_enc_code_ue(enc, 0);
579       radeon_enc_code_ue(enc, 0);
580    }
581    unsigned svc_size = ((enc->bits_size - svc_start_offset) + 7) / 8;
582    unsigned aligned = (32 - enc->bits_in_shifter) % 8;
583    if (aligned > 0)
584       radeon_enc_code_fixed_bits(enc, 0x1, 1);
585    radeon_enc_byte_align(enc);
586 
587    radeon_enc_code_fixed_bits(enc, 0x1, 1);
588    radeon_enc_byte_align(enc);
589 
590    /* store our current state, and go to the beginning to write the size */
591    unsigned position2 = enc->cs.current.cdw;
592    unsigned shifter2 = enc->shifter;
593    unsigned bits_in_shifter2 = enc->bits_in_shifter;
594    unsigned num_zeros2 = enc->num_zeros;
595    unsigned byte_index2 = enc->byte_index;
596    unsigned bits_output2 = enc->bits_output;
597    bool emulation_prevention2 = enc->emulation_prevention;
598 
599    enc->cs.current.cdw = position;
600    enc->shifter = shifter;
601    enc->bits_in_shifter = bits_in_shifter;
602    enc->num_zeros = num_zeros;
603    enc->byte_index = byte_index;
604    enc->bits_output = bits_output;
605    enc->emulation_prevention = emulation_prevention;
606 
607    radeon_enc_output_one_byte(enc, 24);
608    radeon_enc_output_one_byte(enc, svc_size);
609 
610    /* restore our state */
611    enc->cs.current.cdw = position2;
612    enc->shifter = shifter2;
613    enc->bits_in_shifter = bits_in_shifter2;
614    enc->num_zeros = num_zeros2;
615    enc->byte_index = byte_index2;
616    enc->bits_output = bits_output2;
617    enc->emulation_prevention = emulation_prevention2;
618 
619    radeon_enc_flush_headers(enc);
620 
621    *size_in_bytes = (enc->bits_output + 7) / 8;
622    RADEON_ENC_END();
623 }
624 
radeon_enc_nalu_pps(struct radeon_encoder * enc)625 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
626 {
627    RADEON_ENC_BEGIN(enc->cmd.nalu);
628    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
629    uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
630    radeon_enc_reset(enc);
631    radeon_enc_set_emulation_prevention(enc, false);
632    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
633    radeon_enc_code_fixed_bits(enc, 0x68, 8);
634    radeon_enc_byte_align(enc);
635    radeon_enc_set_emulation_prevention(enc, true);
636    radeon_enc_code_ue(enc, 0x0);
637    radeon_enc_code_ue(enc, 0x0);
638    radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
639    radeon_enc_code_fixed_bits(enc, 0x0, 1);
640    radeon_enc_code_ue(enc, 0x0);
641    radeon_enc_code_ue(enc, 0x0);
642    radeon_enc_code_ue(enc, 0x0);
643    radeon_enc_code_fixed_bits(enc, 0x0, 1);
644    radeon_enc_code_fixed_bits(enc, 0x0, 2);
645    radeon_enc_code_se(enc, 0x0);
646    radeon_enc_code_se(enc, 0x0);
647    radeon_enc_code_se(enc, 0x0);
648    radeon_enc_code_fixed_bits(enc, 0x1, 1);
649    radeon_enc_code_fixed_bits(enc, 0x0, 1);
650    radeon_enc_code_fixed_bits(enc, 0x0, 1);
651 
652    radeon_enc_code_fixed_bits(enc, 0x1, 1);
653 
654    radeon_enc_byte_align(enc);
655    radeon_enc_flush_headers(enc);
656    *size_in_bytes = (enc->bits_output + 7) / 8;
657    RADEON_ENC_END();
658 }
659 
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)660 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
661 {
662    RADEON_ENC_BEGIN(enc->cmd.nalu);
663    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
664    uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
665    radeon_enc_reset(enc);
666    radeon_enc_set_emulation_prevention(enc, false);
667    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
668    radeon_enc_code_fixed_bits(enc, 0x4401, 16);
669    radeon_enc_byte_align(enc);
670    radeon_enc_set_emulation_prevention(enc, true);
671    radeon_enc_code_ue(enc, 0x0);
672    radeon_enc_code_ue(enc, 0x0);
673    radeon_enc_code_fixed_bits(enc, 0x1, 1);
674    radeon_enc_code_fixed_bits(enc, 0x0, 4);
675    radeon_enc_code_fixed_bits(enc, 0x0, 1);
676    radeon_enc_code_fixed_bits(enc, 0x1, 1);
677    radeon_enc_code_ue(enc, 0x0);
678    radeon_enc_code_ue(enc, 0x0);
679    radeon_enc_code_se(enc, 0x0);
680    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
681    radeon_enc_code_fixed_bits(enc, 0x0, 1);
682    if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
683       radeon_enc_code_fixed_bits(enc, 0x0, 1);
684    else {
685       radeon_enc_code_fixed_bits(enc, 0x1, 1);
686       radeon_enc_code_ue(enc, 0x0);
687    }
688    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
689    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
690    radeon_enc_code_fixed_bits(enc, 0x0, 1);
691    radeon_enc_code_fixed_bits(enc, 0x0, 2);
692    radeon_enc_code_fixed_bits(enc, 0x0, 1);
693    radeon_enc_code_fixed_bits(enc, 0x0, 1);
694    radeon_enc_code_fixed_bits(enc, 0x0, 1);
695    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
696    radeon_enc_code_fixed_bits(enc, 0x1, 1);
697    radeon_enc_code_fixed_bits(enc, 0x0, 1);
698    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
699 
700    if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
701       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
702       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
703    }
704 
705    radeon_enc_code_fixed_bits(enc, 0x0, 1);
706    radeon_enc_code_fixed_bits(enc, 0x0, 1);
707    radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
708    radeon_enc_code_fixed_bits(enc, 0x0, 2);
709 
710    radeon_enc_code_fixed_bits(enc, 0x1, 1);
711 
712    radeon_enc_byte_align(enc);
713    radeon_enc_flush_headers(enc);
714    *size_in_bytes = (enc->bits_output + 7) / 8;
715    RADEON_ENC_END();
716 }
717 
radeon_enc_nalu_vps(struct radeon_encoder * enc)718 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
719 {
720    RADEON_ENC_BEGIN(enc->cmd.nalu);
721    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
722    uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
723    int i;
724 
725    radeon_enc_reset(enc);
726    radeon_enc_set_emulation_prevention(enc, false);
727    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
728    radeon_enc_code_fixed_bits(enc, 0x4001, 16);
729    radeon_enc_byte_align(enc);
730    radeon_enc_set_emulation_prevention(enc, true);
731 
732    radeon_enc_code_fixed_bits(enc, 0x0, 4);
733    radeon_enc_code_fixed_bits(enc, 0x3, 2);
734    radeon_enc_code_fixed_bits(enc, 0x0, 6);
735    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
736    radeon_enc_code_fixed_bits(enc, 0x1, 1);
737    radeon_enc_code_fixed_bits(enc, 0xffff, 16);
738    radeon_enc_code_fixed_bits(enc, 0x0, 2);
739    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
740    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
741    radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
742    radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
743    radeon_enc_code_fixed_bits(enc, 0x0, 16);
744    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
745 
746    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
747       radeon_enc_code_fixed_bits(enc, 0x0, 2);
748 
749    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
750       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
751          radeon_enc_code_fixed_bits(enc, 0x0, 2);
752    }
753 
754    radeon_enc_code_fixed_bits(enc, 0x0, 1);
755    radeon_enc_code_ue(enc, 0x1);
756    radeon_enc_code_ue(enc, 0x0);
757    radeon_enc_code_ue(enc, 0x0);
758 
759    radeon_enc_code_fixed_bits(enc, 0x0, 6);
760    radeon_enc_code_ue(enc, 0x0);
761    radeon_enc_code_fixed_bits(enc, 0x0, 1);
762    radeon_enc_code_fixed_bits(enc, 0x0, 1);
763 
764    radeon_enc_code_fixed_bits(enc, 0x1, 1);
765 
766    radeon_enc_byte_align(enc);
767    radeon_enc_flush_headers(enc);
768    *size_in_bytes = (enc->bits_output + 7) / 8;
769    RADEON_ENC_END();
770 }
771 
radeon_enc_nalu_aud_hevc(struct radeon_encoder * enc)772 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
773 {
774    RADEON_ENC_BEGIN(enc->cmd.nalu);
775    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
776    uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
777    radeon_enc_reset(enc);
778    radeon_enc_set_emulation_prevention(enc, false);
779    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
780    radeon_enc_code_fixed_bits(enc, 0x0, 1);
781    radeon_enc_code_fixed_bits(enc, 35, 6);
782    radeon_enc_code_fixed_bits(enc, 0x0, 6);
783    radeon_enc_code_fixed_bits(enc, 0x1, 3);
784    radeon_enc_byte_align(enc);
785    radeon_enc_set_emulation_prevention(enc, true);
786    switch (enc->enc_pic.picture_type) {
787    case PIPE_H2645_ENC_PICTURE_TYPE_I:
788    case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
789       radeon_enc_code_fixed_bits(enc, 0x00, 3);
790       break;
791    case PIPE_H2645_ENC_PICTURE_TYPE_P:
792       radeon_enc_code_fixed_bits(enc, 0x01, 3);
793       break;
794    case PIPE_H2645_ENC_PICTURE_TYPE_B:
795       radeon_enc_code_fixed_bits(enc, 0x02, 3);
796       break;
797    default:
798       radeon_enc_code_fixed_bits(enc, 0x02, 3);
799    }
800 
801    radeon_enc_code_fixed_bits(enc, 0x1, 1);
802 
803    radeon_enc_byte_align(enc);
804    radeon_enc_flush_headers(enc);
805    *size_in_bytes = (enc->bits_output + 7) / 8;
806    RADEON_ENC_END();
807 }
808 
radeon_enc_slice_header(struct radeon_encoder * enc)809 static void radeon_enc_slice_header(struct radeon_encoder *enc)
810 {
811    uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
812    uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
813    unsigned int inst_index = 0;
814    unsigned int cdw_start = 0;
815    unsigned int cdw_filled = 0;
816    unsigned int bits_copied = 0;
817    RADEON_ENC_BEGIN(enc->cmd.slice_header);
818    radeon_enc_reset(enc);
819    radeon_enc_set_emulation_prevention(enc, false);
820 
821    cdw_start = enc->cs.current.cdw;
822    if (enc->enc_pic.is_idr)
823       radeon_enc_code_fixed_bits(enc, 0x65, 8);
824    else if (enc->enc_pic.not_referenced)
825       radeon_enc_code_fixed_bits(enc, 0x01, 8);
826    else
827       radeon_enc_code_fixed_bits(enc, 0x41, 8);
828 
829    radeon_enc_flush_headers(enc);
830    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
831    num_bits[inst_index] = enc->bits_output - bits_copied;
832    bits_copied = enc->bits_output;
833    inst_index++;
834 
835    instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
836    inst_index++;
837 
838    switch (enc->enc_pic.picture_type) {
839    case PIPE_H2645_ENC_PICTURE_TYPE_I:
840    case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
841       radeon_enc_code_fixed_bits(enc, 0x08, 7);
842       break;
843    case PIPE_H2645_ENC_PICTURE_TYPE_P:
844    case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
845       radeon_enc_code_fixed_bits(enc, 0x06, 5);
846       break;
847    case PIPE_H2645_ENC_PICTURE_TYPE_B:
848       radeon_enc_code_fixed_bits(enc, 0x07, 5);
849       break;
850    default:
851       radeon_enc_code_fixed_bits(enc, 0x08, 7);
852    }
853 
854    radeon_enc_code_ue(enc, 0x0);
855    radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
856 
857    if (enc->enc_pic.h264_enc_params.input_picture_structure !=
858        RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
859       radeon_enc_code_fixed_bits(enc, 0x1, 1);
860       radeon_enc_code_fixed_bits(enc,
861                                  enc->enc_pic.h264_enc_params.input_picture_structure ==
862                                        RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
863                                     ? 1
864                                     : 0,
865                                  1);
866    }
867 
868    if (enc->enc_pic.is_idr)
869       radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
870 
871    enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
872 
873    if (enc->enc_pic.pic_order_cnt_type == 0)
874       radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
875 
876    if (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) {
877       radeon_enc_code_fixed_bits(enc, 0x0, 1);
878 
879       if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
880          radeon_enc_code_fixed_bits(enc, 0x1, 1);
881          radeon_enc_code_ue(enc, 0x0);
882          radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
883          radeon_enc_code_ue(enc, 0x3);
884       } else
885          radeon_enc_code_fixed_bits(enc, 0x0, 1);
886    }
887 
888    if (enc->enc_pic.is_idr) {
889       radeon_enc_code_fixed_bits(enc, 0x0, 1);
890       radeon_enc_code_fixed_bits(enc, 0x0, 1);
891    } else
892       radeon_enc_code_fixed_bits(enc, 0x0, 1);
893 
894    if ((enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) &&
895        (enc->enc_pic.spec_misc.cabac_enable))
896       radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
897 
898    radeon_enc_flush_headers(enc);
899    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
900    num_bits[inst_index] = enc->bits_output - bits_copied;
901    bits_copied = enc->bits_output;
902    inst_index++;
903 
904    instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
905    inst_index++;
906 
907    radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1 : 0);
908 
909    if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
910       radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
911       radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
912    }
913 
914    radeon_enc_flush_headers(enc);
915    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
916    num_bits[inst_index] = enc->bits_output - bits_copied;
917    bits_copied = enc->bits_output;
918    inst_index++;
919 
920    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
921 
922    cdw_filled = enc->cs.current.cdw - cdw_start;
923    for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
924       RADEON_ENC_CS(0x00000000);
925 
926    for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
927       RADEON_ENC_CS(instruction[j]);
928       RADEON_ENC_CS(num_bits[j]);
929    }
930 
931    RADEON_ENC_END();
932 }
933 
radeon_enc_slice_header_hevc(struct radeon_encoder * enc)934 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
935 {
936    uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
937    uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
938    unsigned int inst_index = 0;
939    unsigned int cdw_start = 0;
940    unsigned int cdw_filled = 0;
941    unsigned int bits_copied = 0;
942    RADEON_ENC_BEGIN(enc->cmd.slice_header);
943    radeon_enc_reset(enc);
944    radeon_enc_set_emulation_prevention(enc, false);
945 
946    cdw_start = enc->cs.current.cdw;
947    radeon_enc_code_fixed_bits(enc, 0x0, 1);
948    radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
949    radeon_enc_code_fixed_bits(enc, 0x0, 6);
950    radeon_enc_code_fixed_bits(enc, 0x1, 3);
951 
952    radeon_enc_flush_headers(enc);
953    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
954    num_bits[inst_index] = enc->bits_output - bits_copied;
955    bits_copied = enc->bits_output;
956    inst_index++;
957 
958    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
959    inst_index++;
960 
961    if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
962       radeon_enc_code_fixed_bits(enc, 0x0, 1);
963 
964    radeon_enc_code_ue(enc, 0x0);
965 
966    radeon_enc_flush_headers(enc);
967    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
968    num_bits[inst_index] = enc->bits_output - bits_copied;
969    bits_copied = enc->bits_output;
970    inst_index++;
971 
972    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
973    inst_index++;
974 
975    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
976    inst_index++;
977 
978    switch (enc->enc_pic.picture_type) {
979    case PIPE_H2645_ENC_PICTURE_TYPE_I:
980    case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
981       radeon_enc_code_ue(enc, 0x2);
982       break;
983    case PIPE_H2645_ENC_PICTURE_TYPE_P:
984    case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
985       radeon_enc_code_ue(enc, 0x1);
986       break;
987    case PIPE_H2645_ENC_PICTURE_TYPE_B:
988       radeon_enc_code_ue(enc, 0x0);
989       break;
990    default:
991       radeon_enc_code_ue(enc, 0x1);
992    }
993 
994    if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
995       radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
996       if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
997          radeon_enc_code_fixed_bits(enc, 0x1, 1);
998       else {
999          radeon_enc_code_fixed_bits(enc, 0x0, 1);
1000          radeon_enc_code_fixed_bits(enc, 0x0, 1);
1001          radeon_enc_code_ue(enc, 0x0);
1002          radeon_enc_code_ue(enc, 0x0);
1003       }
1004    }
1005 
1006    if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
1007        (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
1008       radeon_enc_code_fixed_bits(enc, 0x0, 1);
1009       radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
1010       radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
1011    }
1012 
1013    radeon_enc_flush_headers(enc);
1014    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1015    num_bits[inst_index] = enc->bits_output - bits_copied;
1016    bits_copied = enc->bits_output;
1017    inst_index++;
1018 
1019    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
1020    inst_index++;
1021 
1022    if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
1023        (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
1024       radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
1025                                  1);
1026 
1027       radeon_enc_flush_headers(enc);
1028       instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1029       num_bits[inst_index] = enc->bits_output - bits_copied;
1030       bits_copied = enc->bits_output;
1031       inst_index++;
1032    }
1033 
1034    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
1035 
1036    cdw_filled = enc->cs.current.cdw - cdw_start;
1037    for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
1038       RADEON_ENC_CS(0x00000000);
1039 
1040    for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
1041       RADEON_ENC_CS(instruction[j]);
1042       RADEON_ENC_CS(num_bits[j]);
1043    }
1044 
1045    RADEON_ENC_END();
1046 }
1047 
radeon_enc_ctx(struct radeon_encoder * enc)1048 static void radeon_enc_ctx(struct radeon_encoder *enc)
1049 {
1050    enc->enc_pic.ctx_buf.swizzle_mode = 0;
1051    enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
1052    enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
1053    enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
1054 
1055    RADEON_ENC_BEGIN(enc->cmd.ctx);
1056    RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
1057    RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
1058    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
1059    RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
1060    RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
1061    /* reconstructed_picture_1_luma_offset */
1062    RADEON_ENC_CS(0x00000000);
1063    /* reconstructed_picture_1_chroma_offset */
1064    RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
1065    /* reconstructed_picture_2_luma_offset */
1066    RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
1067    /* reconstructed_picture_2_chroma_offset */
1068    RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
1069 
1070    for (int i = 0; i < 136; i++)
1071       RADEON_ENC_CS(0x00000000);
1072 
1073    RADEON_ENC_END();
1074 }
1075 
radeon_enc_bitstream(struct radeon_encoder * enc)1076 static void radeon_enc_bitstream(struct radeon_encoder *enc)
1077 {
1078    enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
1079    enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
1080    enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
1081 
1082    RADEON_ENC_BEGIN(enc->cmd.bitstream);
1083    RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
1084    RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
1085    RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
1086    RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
1087    RADEON_ENC_END();
1088 }
1089 
radeon_enc_feedback(struct radeon_encoder * enc)1090 static void radeon_enc_feedback(struct radeon_encoder *enc)
1091 {
1092    enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
1093    enc->enc_pic.fb_buf.feedback_buffer_size = 16;
1094    enc->enc_pic.fb_buf.feedback_data_size = 40;
1095 
1096    RADEON_ENC_BEGIN(enc->cmd.feedback);
1097    RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
1098    RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
1099    RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
1100    RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
1101    RADEON_ENC_END();
1102 }
1103 
radeon_enc_intra_refresh(struct radeon_encoder * enc)1104 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
1105 {
1106    enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
1107    enc->enc_pic.intra_ref.offset = 0;
1108    enc->enc_pic.intra_ref.region_size = 0;
1109 
1110    RADEON_ENC_BEGIN(enc->cmd.intra_refresh);
1111    RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
1112    RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
1113    RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
1114    RADEON_ENC_END();
1115 }
1116 
radeon_enc_rc_per_pic(struct radeon_encoder * enc)1117 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
1118 {
1119    RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
1120    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
1121    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
1122    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
1123    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
1124    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
1125    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
1126    RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
1127    RADEON_ENC_END();
1128 }
1129 
radeon_enc_encode_params(struct radeon_encoder * enc)1130 static void radeon_enc_encode_params(struct radeon_encoder *enc)
1131 {
1132    switch (enc->enc_pic.picture_type) {
1133    case PIPE_H2645_ENC_PICTURE_TYPE_I:
1134    case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
1135       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1136       break;
1137    case PIPE_H2645_ENC_PICTURE_TYPE_P:
1138       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1139       break;
1140    case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
1141       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1142       break;
1143    case PIPE_H2645_ENC_PICTURE_TYPE_B:
1144       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1145       break;
1146    default:
1147       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1148    }
1149 
1150    if (enc->luma->meta_offset) {
1151       RVID_ERR("DCC surfaces not supported.\n");
1152       return;
1153    }
1154 
1155    enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1156    enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1157    enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1158    enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
1159 
1160    if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR)
1161       enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1162    else
1163       enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1164 
1165    enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1166 
1167    RADEON_ENC_BEGIN(enc->cmd.enc_params);
1168    RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1169    RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1170    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1171    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1172    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1173    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1174    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1175    RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1176    RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1177    RADEON_ENC_END();
1178 }
1179 
radeon_enc_encode_params_hevc(struct radeon_encoder * enc)1180 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
1181 {
1182    switch (enc->enc_pic.picture_type) {
1183    case PIPE_H2645_ENC_PICTURE_TYPE_I:
1184    case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
1185       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1186       break;
1187    case PIPE_H2645_ENC_PICTURE_TYPE_P:
1188       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1189       break;
1190    case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
1191       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1192       break;
1193    case PIPE_H2645_ENC_PICTURE_TYPE_B:
1194       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1195       break;
1196    default:
1197       enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1198    }
1199 
1200    if (enc->luma->meta_offset) {
1201       RVID_ERR("DCC surfaces not supported.\n");
1202       return;
1203    }
1204 
1205    enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1206    enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1207    enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1208    enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
1209 
1210    if (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
1211       enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1212    else
1213       enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1214 
1215    enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1216 
1217    RADEON_ENC_BEGIN(enc->cmd.enc_params);
1218    RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1219    RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1220    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1221    RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1222    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1223    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1224    RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1225    RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1226    RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1227    RADEON_ENC_END();
1228 }
1229 
radeon_enc_encode_params_h264(struct radeon_encoder * enc)1230 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1231 {
1232    enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1233    enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1234    enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1235    enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1236 
1237    RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
1238    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1239    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1240    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1241    RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1242    RADEON_ENC_END();
1243 }
1244 
radeon_enc_op_init(struct radeon_encoder * enc)1245 static void radeon_enc_op_init(struct radeon_encoder *enc)
1246 {
1247    RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1248    RADEON_ENC_END();
1249 }
1250 
radeon_enc_op_close(struct radeon_encoder * enc)1251 static void radeon_enc_op_close(struct radeon_encoder *enc)
1252 {
1253    RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1254    RADEON_ENC_END();
1255 }
1256 
radeon_enc_op_enc(struct radeon_encoder * enc)1257 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1258 {
1259    RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1260    RADEON_ENC_END();
1261 }
1262 
radeon_enc_op_init_rc(struct radeon_encoder * enc)1263 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1264 {
1265    RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1266    RADEON_ENC_END();
1267 }
1268 
radeon_enc_op_init_rc_vbv(struct radeon_encoder * enc)1269 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1270 {
1271    RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1272    RADEON_ENC_END();
1273 }
1274 
radeon_enc_op_speed(struct radeon_encoder * enc)1275 static void radeon_enc_op_speed(struct radeon_encoder *enc)
1276 {
1277    RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
1278    RADEON_ENC_END();
1279 }
1280 
begin(struct radeon_encoder * enc)1281 static void begin(struct radeon_encoder *enc)
1282 {
1283    unsigned i;
1284 
1285    enc->session_info(enc);
1286    enc->total_task_size = 0;
1287    enc->task_info(enc, enc->need_feedback);
1288    enc->op_init(enc);
1289 
1290    enc->session_init(enc);
1291    enc->slice_control(enc);
1292    enc->spec_misc(enc);
1293    enc->deblocking_filter(enc);
1294 
1295    enc->layer_control(enc);
1296    enc->rc_session_init(enc);
1297    enc->quality_params(enc);
1298 
1299    i = 0;
1300    do {
1301       enc->enc_pic.temporal_id = i;
1302       enc->layer_select(enc);
1303       enc->rc_layer_init(enc);
1304       enc->layer_select(enc);
1305       enc->rc_per_pic(enc);
1306    } while (++i < enc->enc_pic.num_temporal_layers);
1307 
1308    enc->op_init_rc(enc);
1309    enc->op_init_rc_vbv(enc);
1310    *enc->p_task_size = (enc->total_task_size);
1311 }
1312 
radeon_enc_headers_h264(struct radeon_encoder * enc)1313 static void radeon_enc_headers_h264(struct radeon_encoder *enc)
1314 {
1315    if (enc->enc_pic.layer_ctrl.num_temporal_layers > 1)
1316       enc->nalu_prefix(enc);
1317    if (enc->enc_pic.is_idr) {
1318       if (enc->enc_pic.layer_ctrl.num_temporal_layers > 1)
1319          enc->nalu_sei(enc);
1320       enc->nalu_sps(enc);
1321       enc->nalu_pps(enc);
1322    }
1323    enc->slice_header(enc);
1324    enc->encode_params(enc);
1325    enc->encode_params_codec_spec(enc);
1326 }
1327 
radeon_enc_headers_hevc(struct radeon_encoder * enc)1328 static void radeon_enc_headers_hevc(struct radeon_encoder *enc)
1329 {
1330    enc->nalu_aud(enc);
1331    if (enc->enc_pic.is_idr) {
1332       enc->nalu_vps(enc);
1333       enc->nalu_pps(enc);
1334       enc->nalu_sps(enc);
1335    }
1336    enc->slice_header(enc);
1337    enc->encode_params(enc);
1338 }
1339 
encode(struct radeon_encoder * enc)1340 static void encode(struct radeon_encoder *enc)
1341 {
1342    enc->session_info(enc);
1343    enc->total_task_size = 0;
1344    enc->task_info(enc, enc->need_feedback);
1345 
1346    enc->encode_headers(enc);
1347    enc->ctx(enc);
1348    enc->bitstream(enc);
1349    enc->feedback(enc);
1350    enc->intra_refresh(enc);
1351 
1352    enc->op_preset(enc);
1353    enc->op_enc(enc);
1354    *enc->p_task_size = (enc->total_task_size);
1355 }
1356 
destroy(struct radeon_encoder * enc)1357 static void destroy(struct radeon_encoder *enc)
1358 {
1359    enc->session_info(enc);
1360    enc->total_task_size = 0;
1361    enc->task_info(enc, enc->need_feedback);
1362    enc->op_close(enc);
1363    *enc->p_task_size = (enc->total_task_size);
1364 }
1365 
radeon_enc_1_2_init(struct radeon_encoder * enc)1366 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1367 {
1368    enc->begin = begin;
1369    enc->encode = encode;
1370    enc->destroy = destroy;
1371    enc->session_info = radeon_enc_session_info;
1372    enc->task_info = radeon_enc_task_info;
1373    enc->layer_control = radeon_enc_layer_control;
1374    enc->layer_select = radeon_enc_layer_select;
1375    enc->rc_session_init = radeon_enc_rc_session_init;
1376    enc->rc_layer_init = radeon_enc_rc_layer_init;
1377    enc->quality_params = radeon_enc_quality_params;
1378    enc->ctx = radeon_enc_ctx;
1379    enc->bitstream = radeon_enc_bitstream;
1380    enc->feedback = radeon_enc_feedback;
1381    enc->intra_refresh = radeon_enc_intra_refresh;
1382    enc->rc_per_pic = radeon_enc_rc_per_pic;
1383    enc->encode_params = radeon_enc_encode_params;
1384    enc->op_init = radeon_enc_op_init;
1385    enc->op_close = radeon_enc_op_close;
1386    enc->op_enc = radeon_enc_op_enc;
1387    enc->op_init_rc = radeon_enc_op_init_rc;
1388    enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
1389    enc->op_preset = radeon_enc_op_speed;
1390 
1391    if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1392       enc->session_init = radeon_enc_session_init;
1393       enc->slice_control = radeon_enc_slice_control;
1394       enc->spec_misc = radeon_enc_spec_misc;
1395       enc->deblocking_filter = radeon_enc_deblocking_filter_h264;
1396       enc->nalu_sps = radeon_enc_nalu_sps;
1397       enc->nalu_pps = radeon_enc_nalu_pps;
1398       enc->slice_header = radeon_enc_slice_header;
1399       enc->encode_params = radeon_enc_encode_params;
1400       enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
1401       enc->encode_headers = radeon_enc_headers_h264;
1402       enc->nalu_prefix = radeon_enc_nalu_prefix;
1403       enc->nalu_sei = radeon_enc_nalu_sei;
1404    } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1405       enc->session_init = radeon_enc_session_init_hevc;
1406       enc->slice_control = radeon_enc_slice_control_hevc;
1407       enc->spec_misc = radeon_enc_spec_misc_hevc;
1408       enc->deblocking_filter = radeon_enc_deblocking_filter_hevc;
1409       enc->nalu_sps = radeon_enc_nalu_sps_hevc;
1410       enc->nalu_pps = radeon_enc_nalu_pps_hevc;
1411       enc->nalu_vps = radeon_enc_nalu_vps;
1412       enc->nalu_aud = radeon_enc_nalu_aud_hevc;
1413       enc->slice_header = radeon_enc_slice_header_hevc;
1414       enc->encode_params = radeon_enc_encode_params_hevc;
1415       enc->encode_headers = radeon_enc_headers_hevc;
1416    }
1417 
1418    enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
1419    enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
1420    enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
1421    enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
1422    enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
1423    enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
1424    enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
1425    enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
1426    enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
1427    enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
1428    enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
1429    enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
1430    enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
1431    enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
1432    enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
1433    enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
1434    enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
1435    enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
1436    enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
1437    enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
1438    enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
1439    enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
1440    enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
1441 
1442    enc->enc_pic.session_info.interface_version =
1443       ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1444        (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1445 }
1446