1 //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file describes the general parts of a Subtarget.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/CodeGen/TargetSubtargetInfo.h"
14
15 using namespace llvm;
16
TargetSubtargetInfo(const Triple & TT,StringRef CPU,StringRef TuneCPU,StringRef FS,ArrayRef<SubtargetFeatureKV> PF,ArrayRef<SubtargetSubTypeKV> PD,const MCWriteProcResEntry * WPR,const MCWriteLatencyEntry * WL,const MCReadAdvanceEntry * RA,const InstrStage * IS,const unsigned * OC,const unsigned * FP)17 TargetSubtargetInfo::TargetSubtargetInfo(
18 const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
19 ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
20 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
21 const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
22 const unsigned *FP)
23 : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
24
25 TargetSubtargetInfo::~TargetSubtargetInfo() = default;
26
enableAtomicExpand() const27 bool TargetSubtargetInfo::enableAtomicExpand() const {
28 return true;
29 }
30
enableIndirectBrExpand() const31 bool TargetSubtargetInfo::enableIndirectBrExpand() const {
32 return false;
33 }
34
enableMachineScheduler() const35 bool TargetSubtargetInfo::enableMachineScheduler() const {
36 return false;
37 }
38
enableJoinGlobalCopies() const39 bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
40 return enableMachineScheduler();
41 }
42
enableRALocalReassignment(CodeGenOpt::Level OptLevel) const43 bool TargetSubtargetInfo::enableRALocalReassignment(
44 CodeGenOpt::Level OptLevel) const {
45 return true;
46 }
47
enableAdvancedRASplitCost() const48 bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
49 return false;
50 }
51
enablePostRAScheduler() const52 bool TargetSubtargetInfo::enablePostRAScheduler() const {
53 return getSchedModel().PostRAScheduler;
54 }
55
enablePostRAMachineScheduler() const56 bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {
57 return enableMachineScheduler() && enablePostRAScheduler();
58 }
59
useAA() const60 bool TargetSubtargetInfo::useAA() const {
61 return false;
62 }
63
mirFileLoaded(MachineFunction & MF) const64 void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }
65