1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/PPCMCTargetDesc.h"
10 #include "TargetInfo/PowerPCTargetInfo.h"
11 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
12 #include "llvm/MC/MCFixedLenDisassembler.h"
13 #include "llvm/MC/MCInst.h"
14 #include "llvm/MC/MCSubtargetInfo.h"
15 #include "llvm/Support/Endian.h"
16 #include "llvm/Support/TargetRegistry.h"
17
18 using namespace llvm;
19
20 DEFINE_PPC_REGCLASSES;
21
22 #define DEBUG_TYPE "ppc-disassembler"
23
24 typedef MCDisassembler::DecodeStatus DecodeStatus;
25
26 namespace {
27 class PPCDisassembler : public MCDisassembler {
28 bool IsLittleEndian;
29
30 public:
PPCDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx,bool IsLittleEndian)31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
32 bool IsLittleEndian)
33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
34
35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
36 ArrayRef<uint8_t> Bytes, uint64_t Address,
37 raw_ostream &CStream) const override;
38 };
39 } // end anonymous namespace
40
createPPCDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)41 static MCDisassembler *createPPCDisassembler(const Target &T,
42 const MCSubtargetInfo &STI,
43 MCContext &Ctx) {
44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
45 }
46
createPPCLEDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)47 static MCDisassembler *createPPCLEDisassembler(const Target &T,
48 const MCSubtargetInfo &STI,
49 MCContext &Ctx) {
50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
51 }
52
LLVMInitializePowerPCDisassembler()53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() {
54 // Register the disassembler for each target.
55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(),
56 createPPCDisassembler);
57 TargetRegistry::RegisterMCDisassembler(getThePPC32LETarget(),
58 createPPCLEDisassembler);
59 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),
60 createPPCDisassembler);
61 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),
62 createPPCLEDisassembler);
63 }
64
decodeCondBrTarget(MCInst & Inst,unsigned Imm,uint64_t,const void *)65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
66 uint64_t /*Address*/,
67 const void * /*Decoder*/) {
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
69 return MCDisassembler::Success;
70 }
71
decodeDirectBrTarget(MCInst & Inst,unsigned Imm,uint64_t,const void *)72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
73 uint64_t /*Address*/,
74 const void * /*Decoder*/) {
75 int32_t Offset = SignExtend32<24>(Imm);
76 Inst.addOperand(MCOperand::createImm(Offset));
77 return MCDisassembler::Success;
78 }
79
80 // FIXME: These can be generated by TableGen from the existing register
81 // encoding values!
82
83 template <std::size_t N>
decodeRegisterClass(MCInst & Inst,uint64_t RegNo,const MCPhysReg (& Regs)[N])84 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
85 const MCPhysReg (&Regs)[N]) {
86 assert(RegNo < N && "Invalid register number");
87 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
88 return MCDisassembler::Success;
89 }
90
DecodeCRRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)91 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
92 uint64_t Address,
93 const void *Decoder) {
94 return decodeRegisterClass(Inst, RegNo, CRRegs);
95 }
96
DecodeCRBITRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)97 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
98 uint64_t Address,
99 const void *Decoder) {
100 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
101 }
102
DecodeF4RCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)103 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
104 uint64_t Address,
105 const void *Decoder) {
106 return decodeRegisterClass(Inst, RegNo, FRegs);
107 }
108
DecodeF8RCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)109 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
110 uint64_t Address,
111 const void *Decoder) {
112 return decodeRegisterClass(Inst, RegNo, FRegs);
113 }
114
DecodeVFRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)115 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
116 uint64_t Address,
117 const void *Decoder) {
118 return decodeRegisterClass(Inst, RegNo, VFRegs);
119 }
120
DecodeVRRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)121 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
122 uint64_t Address,
123 const void *Decoder) {
124 return decodeRegisterClass(Inst, RegNo, VRegs);
125 }
126
DecodeVSRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)127 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
128 uint64_t Address,
129 const void *Decoder) {
130 return decodeRegisterClass(Inst, RegNo, VSRegs);
131 }
132
DecodeVSFRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)133 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
134 uint64_t Address,
135 const void *Decoder) {
136 return decodeRegisterClass(Inst, RegNo, VSFRegs);
137 }
138
DecodeVSSRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)139 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
140 uint64_t Address,
141 const void *Decoder) {
142 return decodeRegisterClass(Inst, RegNo, VSSRegs);
143 }
144
DecodeGPRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)145 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
146 uint64_t Address,
147 const void *Decoder) {
148 return decodeRegisterClass(Inst, RegNo, RRegs);
149 }
150
DecodeGPRC_NOR0RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)151 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
152 uint64_t Address,
153 const void *Decoder) {
154 return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
155 }
156
DecodeG8RCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)157 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
158 uint64_t Address,
159 const void *Decoder) {
160 return decodeRegisterClass(Inst, RegNo, XRegs);
161 }
162
DecodeG8pRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)163 static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo,
164 uint64_t Address,
165 const void *Decoder) {
166 return decodeRegisterClass(Inst, RegNo, XRegs);
167 }
168
DecodeG8RC_NOX0RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)169 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
170 uint64_t Address,
171 const void *Decoder) {
172 return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
173 }
174
175 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
176 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
177
DecodeSPERCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)178 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
179 uint64_t Address,
180 const void *Decoder) {
181 return decodeRegisterClass(Inst, RegNo, SPERegs);
182 }
183
DecodeACCRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)184 static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
185 uint64_t Address,
186 const void *Decoder) {
187 return decodeRegisterClass(Inst, RegNo, ACCRegs);
188 }
189
DecodeVSRpRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)190 static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
191 uint64_t Address,
192 const void *Decoder) {
193 return decodeRegisterClass(Inst, RegNo, VSRpRegs);
194 }
195
196 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
197 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
198
199 template<unsigned N>
decodeUImmOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)200 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
201 int64_t Address, const void *Decoder) {
202 assert(isUInt<N>(Imm) && "Invalid immediate");
203 Inst.addOperand(MCOperand::createImm(Imm));
204 return MCDisassembler::Success;
205 }
206
207 template<unsigned N>
decodeSImmOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)208 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
209 int64_t Address, const void *Decoder) {
210 assert(isUInt<N>(Imm) && "Invalid immediate");
211 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
212 return MCDisassembler::Success;
213 }
214
decodeImmZeroOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)215 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
216 int64_t Address, const void *Decoder) {
217 if (Imm != 0)
218 return MCDisassembler::Fail;
219 Inst.addOperand(MCOperand::createImm(Imm));
220 return MCDisassembler::Success;
221 }
222
decodeVSRpEvenOperands(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)223 static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
224 uint64_t Address,
225 const void *Decoder) {
226 if (RegNo & 1)
227 return MCDisassembler::Fail;
228 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
229 return MCDisassembler::Success;
230 }
231
decodeMemRIOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)232 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
233 int64_t Address, const void *Decoder) {
234 // Decode the memri field (imm, reg), which has the low 16-bits as the
235 // displacement and the next 5 bits as the register #.
236
237 uint64_t Base = Imm >> 16;
238 uint64_t Disp = Imm & 0xFFFF;
239
240 assert(Base < 32 && "Invalid base register");
241
242 switch (Inst.getOpcode()) {
243 default: break;
244 case PPC::LBZU:
245 case PPC::LHAU:
246 case PPC::LHZU:
247 case PPC::LWZU:
248 case PPC::LFSU:
249 case PPC::LFDU:
250 // Add the tied output operand.
251 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
252 break;
253 case PPC::STBU:
254 case PPC::STHU:
255 case PPC::STWU:
256 case PPC::STFSU:
257 case PPC::STFDU:
258 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
259 break;
260 }
261
262 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
263 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
264 return MCDisassembler::Success;
265 }
266
decodeMemRIXOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)267 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
268 int64_t Address, const void *Decoder) {
269 // Decode the memrix field (imm, reg), which has the low 14-bits as the
270 // displacement and the next 5 bits as the register #.
271
272 uint64_t Base = Imm >> 14;
273 uint64_t Disp = Imm & 0x3FFF;
274
275 assert(Base < 32 && "Invalid base register");
276
277 if (Inst.getOpcode() == PPC::LDU)
278 // Add the tied output operand.
279 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
280 else if (Inst.getOpcode() == PPC::STDU)
281 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
282
283 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
284 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
285 return MCDisassembler::Success;
286 }
287
decodeMemRIHashOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)288 static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
289 int64_t Address,
290 const void *Decoder) {
291 // Decode the memrix field for a hash store or hash check operation.
292 // The field is composed of a register and an immediate value that is 6 bits
293 // and covers the range -8 to -512. The immediate is always negative and 2s
294 // complement which is why we sign extend a 7 bit value.
295 const uint64_t Base = Imm >> 6;
296 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
297
298 assert(Base < 32 && "Invalid base register");
299
300 Inst.addOperand(MCOperand::createImm(Disp));
301 Inst.addOperand(MCOperand::createReg(RRegs[Base]));
302 return MCDisassembler::Success;
303 }
304
decodeMemRIX16Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)305 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
306 int64_t Address, const void *Decoder) {
307 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
308 // displacement with 16-byte aligned, and the next 5 bits as the register #.
309
310 uint64_t Base = Imm >> 12;
311 uint64_t Disp = Imm & 0xFFF;
312
313 assert(Base < 32 && "Invalid base register");
314
315 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
316 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
317 return MCDisassembler::Success;
318 }
319
decodeMemRI34PCRelOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)320 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
321 int64_t Address,
322 const void *Decoder) {
323 // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
324 // displacement, and the next 5 bits as an immediate 0.
325 uint64_t Base = Imm >> 34;
326 uint64_t Disp = Imm & 0x3FFFFFFFFUL;
327
328 assert(Base < 32 && "Invalid base register");
329
330 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
331 return decodeImmZeroOperand(Inst, Base, Address, Decoder);
332 }
333
decodeMemRI34Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)334 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
335 int64_t Address,
336 const void *Decoder) {
337 // Decode the memri34 field (imm, reg), which has the low 34-bits as the
338 // displacement, and the next 5 bits as the register #.
339 uint64_t Base = Imm >> 34;
340 uint64_t Disp = Imm & 0x3FFFFFFFFUL;
341
342 assert(Base < 32 && "Invalid base register");
343
344 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
345 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
346 return MCDisassembler::Success;
347 }
348
decodeSPE8Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)349 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
350 int64_t Address, const void *Decoder) {
351 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
352 // displacement with 8-byte aligned, and the next 5 bits as the register #.
353
354 uint64_t Base = Imm >> 5;
355 uint64_t Disp = Imm & 0x1F;
356
357 assert(Base < 32 && "Invalid base register");
358
359 Inst.addOperand(MCOperand::createImm(Disp << 3));
360 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
361 return MCDisassembler::Success;
362 }
363
decodeSPE4Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)364 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
365 int64_t Address, const void *Decoder) {
366 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
367 // displacement with 4-byte aligned, and the next 5 bits as the register #.
368
369 uint64_t Base = Imm >> 5;
370 uint64_t Disp = Imm & 0x1F;
371
372 assert(Base < 32 && "Invalid base register");
373
374 Inst.addOperand(MCOperand::createImm(Disp << 2));
375 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
376 return MCDisassembler::Success;
377 }
378
decodeSPE2Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)379 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
380 int64_t Address, const void *Decoder) {
381 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
382 // displacement with 2-byte aligned, and the next 5 bits as the register #.
383
384 uint64_t Base = Imm >> 5;
385 uint64_t Disp = Imm & 0x1F;
386
387 assert(Base < 32 && "Invalid base register");
388
389 Inst.addOperand(MCOperand::createImm(Disp << 1));
390 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
391 return MCDisassembler::Success;
392 }
393
decodeCRBitMOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)394 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
395 int64_t Address, const void *Decoder) {
396 // The cr bit encoding is 0x80 >> cr_reg_num.
397
398 unsigned Zeros = countTrailingZeros(Imm);
399 assert(Zeros < 8 && "Invalid CR bit value");
400
401 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
402 return MCDisassembler::Success;
403 }
404
405 #include "PPCGenDisassemblerTables.inc"
406
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const407 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
408 ArrayRef<uint8_t> Bytes,
409 uint64_t Address,
410 raw_ostream &CS) const {
411 auto *ReadFunc = IsLittleEndian ? support::endian::read32le
412 : support::endian::read32be;
413
414 // If this is an 8-byte prefixed instruction, handle it here.
415 // Note: prefixed instructions aren't technically 8-byte entities - the prefix
416 // appears in memory at an address 4 bytes prior to that of the base
417 // instruction regardless of endianness. So we read the two pieces and
418 // rebuild the 8-byte instruction.
419 // TODO: In this function we call decodeInstruction several times with
420 // different decoder tables. It may be possible to only call once by
421 // looking at the top 6 bits of the instruction.
422 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) {
423 uint32_t Prefix = ReadFunc(Bytes.data());
424 uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
425 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
426 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
427 this, STI);
428 if (result != MCDisassembler::Fail) {
429 Size = 8;
430 return result;
431 }
432 }
433
434 // Get the four bytes of the instruction.
435 Size = 4;
436 if (Bytes.size() < 4) {
437 Size = 0;
438 return MCDisassembler::Fail;
439 }
440
441 // Read the instruction in the proper endianness.
442 uint64_t Inst = ReadFunc(Bytes.data());
443
444 if (STI.getFeatureBits()[PPC::FeatureSPE]) {
445 DecodeStatus result =
446 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
447 if (result != MCDisassembler::Fail)
448 return result;
449 }
450
451 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
452 }
453