1//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 jump, return, call, and related instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Control Flow Instructions. 15// 16 17// Return instructions. 18// 19// The X86retflag return instructions are variadic because we may add ST0 and 20// ST1 arguments when returning values on the x87 stack. 21let isTerminator = 1, isReturn = 1, isBarrier = 1, 22 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { 23 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops), 24 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>; 25 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops), 26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>; 27 def RETW : I <0xC3, RawFrm, (outs), (ins), 28 "ret{w}", []>, OpSize16; 29 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 30 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>; 31 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>; 33 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), 34 "ret{w}\t$amt", []>, OpSize16; 35 def LRETL : I <0xCB, RawFrm, (outs), (ins), 36 "{l}ret{l|f}", []>, OpSize32; 37 def LRETQ : RI <0xCB, RawFrm, (outs), (ins), 38 "{l}ret{|f}q", []>, Requires<[In64BitMode]>; 39 def LRETW : I <0xCB, RawFrm, (outs), (ins), 40 "{l}ret{w|f}", []>, OpSize16; 41 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 42 "{l}ret{l|f}\t$amt", []>, OpSize32; 43 def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 44 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>; 45 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 46 "{l}ret{w|f}\t$amt", []>, OpSize16; 47 48 // The machine return from interrupt instruction, but sometimes we need to 49 // perform a post-epilogue stack adjustment. Codegen emits the pseudo form 50 // which expands to include an SP adjustment if necessary. 51 def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>, 52 OpSize16; 53 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32; 54 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; 55 let isCodeGenOnly = 1 in 56 def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>; 57 def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>; 58} 59 60// Unconditional branches. 61let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 62 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), 63 "jmp\t$dst", [(br bb:$dst)]>; 64 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { 65 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst), 66 "jmp\t$dst", []>, OpSize16; 67 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst), 68 "jmp\t$dst", []>, OpSize32; 69 } 70} 71 72// Conditional Branches. 73let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump], 74 isCodeGenOnly = 1, ForceDisassemble = 1 in { 75 def JCC_1 : Ii8PCRel <0x70, AddCCFrm, (outs), 76 (ins brtarget8:$dst, ccode:$cond), 77 "j${cond}\t$dst", 78 [(X86brcond bb:$dst, timm:$cond, EFLAGS)]>; 79 let hasSideEffects = 0 in { 80 def JCC_2 : Ii16PCRel<0x80, AddCCFrm, (outs), 81 (ins brtarget16:$dst, ccode:$cond), 82 "j${cond}\t$dst", 83 []>, OpSize16, TB; 84 def JCC_4 : Ii32PCRel<0x80, AddCCFrm, (outs), 85 (ins brtarget32:$dst, ccode:$cond), 86 "j${cond}\t$dst", 87 []>, TB, OpSize32; 88 } 89} 90 91def : InstAlias<"jo\t$dst", (JCC_1 brtarget8:$dst, 0), 0>; 92def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst, 1), 0>; 93def : InstAlias<"jb\t$dst", (JCC_1 brtarget8:$dst, 2), 0>; 94def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst, 3), 0>; 95def : InstAlias<"je\t$dst", (JCC_1 brtarget8:$dst, 4), 0>; 96def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst, 5), 0>; 97def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst, 6), 0>; 98def : InstAlias<"ja\t$dst", (JCC_1 brtarget8:$dst, 7), 0>; 99def : InstAlias<"js\t$dst", (JCC_1 brtarget8:$dst, 8), 0>; 100def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst, 9), 0>; 101def : InstAlias<"jp\t$dst", (JCC_1 brtarget8:$dst, 10), 0>; 102def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>; 103def : InstAlias<"jl\t$dst", (JCC_1 brtarget8:$dst, 12), 0>; 104def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>; 105def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>; 106def : InstAlias<"jg\t$dst", (JCC_1 brtarget8:$dst, 15), 0>; 107 108// jcx/jecx/jrcx instructions. 109let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in { 110 // These are the 32-bit versions of this instruction for the asmparser. In 111 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is 112 // jecxz. 113 let Uses = [CX] in 114 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 115 "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>; 116 let Uses = [ECX] in 117 def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 118 "jecxz\t$dst", []>, AdSize32; 119 120 let Uses = [RCX] in 121 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 122 "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>; 123} 124 125// Indirect branches 126let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 127 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst", 128 [(brind GR16:$dst)]>, Requires<[Not64BitMode]>, 129 OpSize16, Sched<[WriteJump]>; 130 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst", 131 [(brind (loadi16 addr:$dst))]>, Requires<[Not64BitMode]>, 132 OpSize16, Sched<[WriteJumpLd]>; 133 134 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", 135 [(brind GR32:$dst)]>, Requires<[Not64BitMode]>, 136 OpSize32, Sched<[WriteJump]>; 137 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", 138 [(brind (loadi32 addr:$dst))]>, Requires<[Not64BitMode]>, 139 OpSize32, Sched<[WriteJumpLd]>; 140 141 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", 142 [(brind GR64:$dst)]>, Requires<[In64BitMode]>, 143 Sched<[WriteJump]>; 144 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", 145 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>, 146 Sched<[WriteJumpLd]>; 147 148 // Win64 wants indirect jumps leaving the function to have a REX_W prefix. 149 // These are switched from TAILJMPr/m64_REX in MCInstLower. 150 let isCodeGenOnly = 1, hasREX_WPrefix = 1 in { 151 def JMP64r_REX : I<0xFF, MRM4r, (outs), (ins GR64:$dst), 152 "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJump]>; 153 let mayLoad = 1 in 154 def JMP64m_REX : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), 155 "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJumpLd]>; 156 157 } 158 159 // Non-tracking jumps for IBT, use with caution. 160 let isCodeGenOnly = 1 in { 161 def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst", 162 [(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>, 163 OpSize16, Sched<[WriteJump]>, NOTRACK; 164 165 def JMP16m_NT : I<0xFF, MRM4m, (outs), (ins i16mem : $dst), "jmp{w}\t{*}$dst", 166 [(X86NoTrackBrind (loadi16 addr : $dst))]>, 167 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>, 168 NOTRACK; 169 170 def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst", 171 [(X86NoTrackBrind GR32 : $dst)]>, Requires<[Not64BitMode]>, 172 OpSize32, Sched<[WriteJump]>, NOTRACK; 173 def JMP32m_NT : I<0xFF, MRM4m, (outs), (ins i32mem : $dst), "jmp{l}\t{*}$dst", 174 [(X86NoTrackBrind (loadi32 addr : $dst))]>, 175 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>, 176 NOTRACK; 177 178 def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst", 179 [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>, 180 Sched<[WriteJump]>, NOTRACK; 181 def JMP64m_NT : I<0xFF, MRM4m, (outs), (ins i64mem : $dst), "jmp{q}\t{*}$dst", 182 [(X86NoTrackBrind(loadi64 addr : $dst))]>, 183 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK; 184 } 185 186 let Predicates = [Not64BitMode], AsmVariantName = "att" in { 187 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), 188 (ins i16imm:$off, i16imm:$seg), 189 "ljmp{w}\t$seg, $off", []>, 190 OpSize16, Sched<[WriteJump]>; 191 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), 192 (ins i32imm:$off, i16imm:$seg), 193 "ljmp{l}\t$seg, $off", []>, 194 OpSize32, Sched<[WriteJump]>; 195 } 196 let mayLoad = 1 in { 197 def FARJMP64m : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst), 198 "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>; 199 200 let AsmVariantName = "att" in 201 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), 202 "ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; 203 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), 204 "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; 205 } 206} 207 208// Loop instructions 209let isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 210def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>; 211def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>; 212def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>; 213} 214 215//===----------------------------------------------------------------------===// 216// Call Instructions... 217// 218let isCall = 1 in 219 // All calls clobber the non-callee saved registers. ESP is marked as 220 // a use to prevent stack-pointer assignments that appear immediately 221 // before calls from potentially appearing dead. Uses for argument 222 // registers are added manually. 223 let Uses = [ESP, SSP] in { 224 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, 225 (outs), (ins i32imm_brtarget:$dst), 226 "call{l}\t$dst", []>, OpSize32, 227 Requires<[Not64BitMode]>, Sched<[WriteJump]>; 228 let hasSideEffects = 0 in 229 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, 230 (outs), (ins i16imm_brtarget:$dst), 231 "call{w}\t$dst", []>, OpSize16, 232 Sched<[WriteJump]>; 233 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst), 234 "call{w}\t{*}$dst", [(X86call GR16:$dst)]>, 235 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>; 236 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst), 237 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>, 238 OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, 239 Sched<[WriteJumpLd]>; 240 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), 241 "call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32, 242 Requires<[Not64BitMode,NotUseIndirectThunkCalls]>, 243 Sched<[WriteJump]>; 244 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), 245 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>, 246 OpSize32, 247 Requires<[Not64BitMode,FavorMemIndirectCall, 248 NotUseIndirectThunkCalls]>, 249 Sched<[WriteJumpLd]>; 250 251 // Non-tracking calls for IBT, use with caution. 252 let isCodeGenOnly = 1 in { 253 def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst), 254 "call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>, 255 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; 256 def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst), 257 "call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>, 258 OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, 259 Sched<[WriteJumpLd]>, NOTRACK; 260 def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst), 261 "call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>, 262 OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; 263 def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst), 264 "call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>, 265 OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>, 266 Sched<[WriteJumpLd]>, NOTRACK; 267 } 268 269 let Predicates = [Not64BitMode], AsmVariantName = "att" in { 270 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), 271 (ins i16imm:$off, i16imm:$seg), 272 "lcall{w}\t$seg, $off", []>, 273 OpSize16, Sched<[WriteJump]>; 274 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), 275 (ins i32imm:$off, i16imm:$seg), 276 "lcall{l}\t$seg, $off", []>, 277 OpSize32, Sched<[WriteJump]>; 278 } 279 280 let mayLoad = 1 in { 281 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), 282 "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; 283 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), 284 "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; 285 } 286 } 287 288 289// Tail call stuff. 290let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 291 isCodeGenOnly = 1, Uses = [ESP, SSP] in { 292 def TCRETURNdi : PseudoI<(outs), (ins i32imm_brtarget:$dst, i32imm:$offset), 293 []>, Sched<[WriteJump]>, NotMemoryFoldable; 294 def TCRETURNri : PseudoI<(outs), (ins ptr_rc_tailcall:$dst, i32imm:$offset), 295 []>, Sched<[WriteJump]>, NotMemoryFoldable; 296 let mayLoad = 1 in 297 def TCRETURNmi : PseudoI<(outs), (ins i32mem_TC:$dst, i32imm:$offset), 298 []>, Sched<[WriteJumpLd]>; 299 300 def TAILJMPd : PseudoI<(outs), (ins i32imm_brtarget:$dst), 301 []>, Sched<[WriteJump]>; 302 303 def TAILJMPr : PseudoI<(outs), (ins ptr_rc_tailcall:$dst), 304 []>, Sched<[WriteJump]>; 305 let mayLoad = 1 in 306 def TAILJMPm : PseudoI<(outs), (ins i32mem_TC:$dst), 307 []>, Sched<[WriteJumpLd]>; 308} 309 310// Conditional tail calls are similar to the above, but they are branches 311// rather than barriers, and they use EFLAGS. 312let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, 313 isCodeGenOnly = 1, SchedRW = [WriteJump] in 314 let Uses = [ESP, EFLAGS, SSP] in { 315 def TCRETURNdicc : PseudoI<(outs), 316 (ins i32imm_brtarget:$dst, i32imm:$offset, i32imm:$cond), 317 []>; 318 319 // This gets substituted to a conditional jump instruction in MC lowering. 320 def TAILJMPd_CC : PseudoI<(outs), (ins i32imm_brtarget:$dst, i32imm:$cond), []>; 321} 322 323 324//===----------------------------------------------------------------------===// 325// Call Instructions... 326// 327 328// RSP is marked as a use to prevent stack-pointer assignments that appear 329// immediately before calls from potentially appearing dead. Uses for argument 330// registers are added manually. 331let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { 332 // NOTE: this pattern doesn't match "X86call imm", because we do not know 333 // that the offset between an arbitrary immediate and the call will fit in 334 // the 32-bit pcrel field that we have. 335 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, 336 (outs), (ins i64i32imm_brtarget:$dst), 337 "call{q}\t$dst", []>, OpSize32, 338 Requires<[In64BitMode]>; 339 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), 340 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>, 341 Requires<[In64BitMode,NotUseIndirectThunkCalls]>; 342 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), 343 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>, 344 Requires<[In64BitMode,FavorMemIndirectCall, 345 NotUseIndirectThunkCalls]>; 346 347 // Non-tracking calls for IBT, use with caution. 348 let isCodeGenOnly = 1 in { 349 def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst), 350 "call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>, 351 Requires<[In64BitMode]>, NOTRACK; 352 def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst), 353 "call{q}\t{*}$dst", 354 [(X86NoTrackCall(loadi64 addr : $dst))]>, 355 Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK; 356 } 357 358 let mayLoad = 1 in 359 def FARCALL64m : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst), 360 "lcall{q}\t{*}$dst", []>; 361} 362 363let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 364 isCodeGenOnly = 1, Uses = [RSP, SSP] in { 365 def TCRETURNdi64 : PseudoI<(outs), 366 (ins i64i32imm_brtarget:$dst, i32imm:$offset), 367 []>, Sched<[WriteJump]>; 368 def TCRETURNri64 : PseudoI<(outs), 369 (ins ptr_rc_tailcall:$dst, i32imm:$offset), 370 []>, Sched<[WriteJump]>, NotMemoryFoldable; 371 let mayLoad = 1 in 372 def TCRETURNmi64 : PseudoI<(outs), 373 (ins i64mem_TC:$dst, i32imm:$offset), 374 []>, Sched<[WriteJumpLd]>, NotMemoryFoldable; 375 376 def TAILJMPd64 : PseudoI<(outs), (ins i64i32imm_brtarget:$dst), 377 []>, Sched<[WriteJump]>; 378 379 def TAILJMPr64 : PseudoI<(outs), (ins ptr_rc_tailcall:$dst), 380 []>, Sched<[WriteJump]>; 381 382 let mayLoad = 1 in 383 def TAILJMPm64 : PseudoI<(outs), (ins i64mem_TC:$dst), 384 []>, Sched<[WriteJumpLd]>; 385 386 // Win64 wants indirect jumps leaving the function to have a REX_W prefix. 387 let hasREX_WPrefix = 1 in { 388 def TAILJMPr64_REX : PseudoI<(outs), (ins ptr_rc_tailcall:$dst), 389 []>, Sched<[WriteJump]>; 390 391 let mayLoad = 1 in 392 def TAILJMPm64_REX : PseudoI<(outs), (ins i64mem_TC:$dst), 393 []>, Sched<[WriteJumpLd]>; 394 } 395} 396 397let isPseudo = 1, isCall = 1, isCodeGenOnly = 1, 398 Uses = [RSP, SSP], 399 usesCustomInserter = 1, 400 SchedRW = [WriteJump] in { 401 def INDIRECT_THUNK_CALL32 : 402 PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>, 403 Requires<[Not64BitMode,UseIndirectThunkCalls]>; 404 405 def INDIRECT_THUNK_CALL64 : 406 PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>, 407 Requires<[In64BitMode,UseIndirectThunkCalls]>; 408 409 // Indirect thunk variant of indirect tail calls. 410 let isTerminator = 1, isReturn = 1, isBarrier = 1 in { 411 def INDIRECT_THUNK_TCRETURN64 : 412 PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>; 413 def INDIRECT_THUNK_TCRETURN32 : 414 PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>; 415 } 416} 417 418let isPseudo = 1, isCall = 1, isCodeGenOnly = 1, 419 Uses = [RSP, SSP], 420 SchedRW = [WriteJump] in { 421 def CALL64m_RVMARKER : 422 PseudoI<(outs), (ins i32imm:$sel, i64mem:$dst), [(X86call_rvmarker timm:$sel, (loadi64 addr:$dst))]>, 423 Requires<[In64BitMode]>; 424 425 def CALL64r_RVMARKER : 426 PseudoI<(outs), (ins i32imm:$sel, GR64:$dst), [(X86call_rvmarker timm:$sel, GR64:$dst)]>, 427 Requires<[In64BitMode]>; 428 429 def CALL64pcrel32_RVMARKER : 430 PseudoI<(outs), (ins i32imm:$sel, i64i32imm_brtarget:$dst), []>, 431 Requires<[In64BitMode]>; 432} 433 434// Conditional tail calls are similar to the above, but they are branches 435// rather than barriers, and they use EFLAGS. 436let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, 437 isCodeGenOnly = 1, SchedRW = [WriteJump] in 438 let Uses = [RSP, EFLAGS, SSP] in { 439 def TCRETURNdi64cc : PseudoI<(outs), 440 (ins i64i32imm_brtarget:$dst, i32imm:$offset, 441 i32imm:$cond), []>; 442 443 // This gets substituted to a conditional jump instruction in MC lowering. 444 def TAILJMPd64_CC : PseudoI<(outs), 445 (ins i64i32imm_brtarget:$dst, i32imm:$cond), []>; 446} 447