1; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
2; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx810 -verify-machineinstrs | FileCheck --check-prefix=GCN %s
3; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX9 %s
4
5; Testing for failures in divergence calculations when divergent intrinsic is lowered during instruction selection
6
7@0 = external dso_local addrspace(4) constant [4 x <4 x float>]
8
9; GCN-LABEL: {{^}}_amdgpu_ps_main:
10; GCN-NOT: v_readfirstlane
11; PRE-GFX9: flat_load_dword
12; GFX9: global_load
13define dllexport amdgpu_ps void @_amdgpu_ps_main(i32 inreg %arg) local_unnamed_addr #0 {
14.entry:
15  %tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %arg) #1
16  %tmp1 = bitcast float %tmp to i32
17  %tmp2 = srem i32 %tmp1, 4
18  %tmp3 = select i1 false, i32 undef, i32 %tmp2
19  %tmp4 = sext i32 %tmp3 to i64
20  %tmp5 = getelementptr [4 x <4 x float>], [4 x <4 x float>] addrspace(4)* @0, i64 0, i64 %tmp4
21  %tmp6 = load <4 x float>, <4 x float> addrspace(4)* %tmp5, align 16
22  %tmp7 = extractelement <4 x float> %tmp6, i32 3
23  %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7) #1
24  call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> undef, <2 x half> %tmp8, i1 true, i1 true) #2
25  ret void
26}
27
28declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
29declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
30declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #2
31
32attributes #0 = { nounwind "InitialPSInputAddr"="0" }
33attributes #1 = { nounwind readnone speculatable }
34attributes #2 = { nounwind }
35