1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s 3 4; CHECK-LABEL: {{^}}phi1: 5; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0 6; CHECK: ; %bb.1: ; %ELSE 7; CHECK: s_xor_b32 s{{[0-9]}}, [[DST]] 8define amdgpu_ps void @phi1(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { 9main_body: 10 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 11 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0 12 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0) 13 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0) 14 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0) 15 %tmp24 = fptosi float %tmp22 to i32 16 %tmp25 = icmp ne i32 %tmp24, 0 17 br i1 %tmp25, label %ENDIF, label %ELSE 18 19ELSE: ; preds = %main_body 20 %tmp26 = fsub float -0.000000e+00, %tmp21 21 br label %ENDIF 22 23ENDIF: ; preds = %ELSE, %main_body 24 %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ] 25 %tmp27 = fadd float %temp.0, %tmp23 26 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0 27 ret void 28} 29 30; Make sure this program doesn't crash 31; CHECK-LABEL: {{^}}phi2: 32define amdgpu_ps void @phi2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 { 33main_body: 34 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 35 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0 36 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0) 37 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0) 38 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 36, i32 0) 39 %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 40, i32 0) 40 %tmp25 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 48, i32 0) 41 %tmp26 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 52, i32 0) 42 %tmp27 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 56, i32 0) 43 %tmp28 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 64, i32 0) 44 %tmp29 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 68, i32 0) 45 %tmp30 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 72, i32 0) 46 %tmp31 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 76, i32 0) 47 %tmp32 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 80, i32 0) 48 %tmp33 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 84, i32 0) 49 %tmp34 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 88, i32 0) 50 %tmp35 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 92, i32 0) 51 %tmp36 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %arg2, i32 0 52 %tmp37 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp36, !tbaa !0 53 %tmp38 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg1, i32 0 54 %tmp39 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp38, !tbaa !0 55 %i.i = extractelement <2 x i32> %arg5, i32 0 56 %j.i = extractelement <2 x i32> %arg5, i32 1 57 %i.f.i = bitcast i32 %i.i to float 58 %j.f.i = bitcast i32 %j.i to float 59 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #1 60 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #1 61 %i.i19 = extractelement <2 x i32> %arg5, i32 0 62 %j.i20 = extractelement <2 x i32> %arg5, i32 1 63 %i.f.i21 = bitcast i32 %i.i19 to float 64 %j.f.i22 = bitcast i32 %j.i20 to float 65 %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 1, i32 0, i32 %arg3) #1 66 %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 1, i32 0, i32 %arg3) #1 67 %i.i13 = extractelement <2 x i32> %arg5, i32 0 68 %j.i14 = extractelement <2 x i32> %arg5, i32 1 69 %i.f.i15 = bitcast i32 %i.i13 to float 70 %j.f.i16 = bitcast i32 %j.i14 to float 71 %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 1, i32 %arg3) #1 72 %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 1, i32 %arg3) #1 73 %i.i7 = extractelement <2 x i32> %arg5, i32 0 74 %j.i8 = extractelement <2 x i32> %arg5, i32 1 75 %i.f.i9 = bitcast i32 %i.i7 to float 76 %j.f.i10 = bitcast i32 %j.i8 to float 77 %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 1, i32 %arg3) #1 78 %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 1, i32 %arg3) #1 79 %i.i1 = extractelement <2 x i32> %arg5, i32 0 80 %j.i2 = extractelement <2 x i32> %arg5, i32 1 81 %i.f.i3 = bitcast i32 %i.i1 to float 82 %j.f.i4 = bitcast i32 %j.i2 to float 83 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 1, i32 %arg3) #1 84 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 1, i32 %arg3) #1 85 %tmp39.bc = bitcast <4 x i32> %tmp39 to <4 x i32> 86 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i24, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i1 0, i32 0, i32 0) 87 %tmp50 = extractelement <4 x float> %tmp1, i32 2 88 %tmp51 = call float @llvm.fabs.f32(float %tmp50) 89 %tmp52 = fmul float %p2.i18, %p2.i18 90 %tmp53 = fmul float %p2.i12, %p2.i12 91 %tmp54 = fadd float %tmp53, %tmp52 92 %tmp55 = fmul float %p2.i6, %p2.i6 93 %tmp56 = fadd float %tmp54, %tmp55 94 %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56) 95 %tmp58 = fmul float %p2.i18, %tmp57 96 %tmp59 = fmul float %p2.i12, %tmp57 97 %tmp60 = fmul float %p2.i6, %tmp57 98 %tmp61 = fmul float %tmp58, %tmp22 99 %tmp62 = fmul float %tmp59, %tmp23 100 %tmp63 = fadd float %tmp62, %tmp61 101 %tmp64 = fmul float %tmp60, %tmp24 102 %tmp65 = fadd float %tmp63, %tmp64 103 %tmp66 = fsub float -0.000000e+00, %tmp25 104 %tmp67 = fmul float %tmp65, %tmp51 105 %tmp68 = fadd float %tmp67, %tmp66 106 %tmp69 = fmul float %tmp26, %tmp68 107 %tmp70 = fmul float %tmp27, %tmp68 108 %tmp71 = call float @llvm.fabs.f32(float %tmp69) 109 %tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71 110 %tmp73 = sext i1 %tmp72 to i32 111 %tmp74 = bitcast i32 %tmp73 to float 112 %tmp75 = bitcast float %tmp74 to i32 113 %tmp76 = icmp ne i32 %tmp75, 0 114 br i1 %tmp76, label %IF, label %ENDIF 115 116IF: ; preds = %main_body 117 %tmp77 = fsub float -0.000000e+00, %tmp69 118 %tmp78 = call float @llvm.exp2.f32(float %tmp77) 119 %tmp79 = fsub float -0.000000e+00, %tmp78 120 %tmp80 = fadd float 1.000000e+00, %tmp79 121 %tmp81 = fdiv float 1.000000e+00, %tmp69 122 %tmp82 = fmul float %tmp80, %tmp81 123 %tmp83 = fmul float %tmp31, %tmp82 124 br label %ENDIF 125 126ENDIF: ; preds = %IF, %main_body 127 %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ] 128 %tmp84 = call float @llvm.fabs.f32(float %tmp70) 129 %tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84 130 %tmp86 = sext i1 %tmp85 to i32 131 %tmp87 = bitcast i32 %tmp86 to float 132 %tmp88 = bitcast float %tmp87 to i32 133 %tmp89 = icmp ne i32 %tmp88, 0 134 br i1 %tmp89, label %IF25, label %ENDIF24 135 136IF25: ; preds = %ENDIF 137 %tmp90 = fsub float -0.000000e+00, %tmp70 138 %tmp91 = call float @llvm.exp2.f32(float %tmp90) 139 %tmp92 = fsub float -0.000000e+00, %tmp91 140 %tmp93 = fadd float 1.000000e+00, %tmp92 141 %tmp94 = fdiv float 1.000000e+00, %tmp70 142 %tmp95 = fmul float %tmp93, %tmp94 143 %tmp96 = fmul float %tmp35, %tmp95 144 br label %ENDIF24 145 146ENDIF24: ; preds = %IF25, %ENDIF 147 %temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ] 148 %tmp97 = fmul float %tmp28, %temp4.0 149 %tmp98 = fmul float %tmp29, %temp4.0 150 %tmp99 = fmul float %tmp30, %temp4.0 151 %tmp100 = fmul float %tmp32, %temp8.0 152 %tmp101 = fadd float %tmp100, %tmp97 153 %tmp102 = fmul float %tmp33, %temp8.0 154 %tmp103 = fadd float %tmp102, %tmp98 155 %tmp104 = fmul float %tmp34, %temp8.0 156 %tmp105 = fadd float %tmp104, %tmp99 157 %tmp106 = call float @llvm.pow.f32(float %tmp51, float %tmp21) 158 %tmp107 = fsub float -0.000000e+00, %tmp101 159 %tmp108 = fmul float %tmp107, %tmp106 160 %tmp109 = fsub float -0.000000e+00, %tmp103 161 %tmp110 = fmul float %tmp109, %tmp106 162 %tmp111 = fsub float -0.000000e+00, %tmp105 163 %tmp112 = fmul float %tmp111, %tmp106 164 %tmp113 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp108, float %tmp110) 165 %tmp115 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp112, float 1.000000e+00) 166 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp113, <2 x half> %tmp115, i1 true, i1 true) #0 167 ret void 168} 169 170; We just want to make sure the program doesn't crash 171; CHECK-LABEL: {{^}}loop: 172define amdgpu_ps void @loop(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { 173main_body: 174 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 175 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0 176 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0) 177 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 4, i32 0) 178 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 8, i32 0) 179 %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 12, i32 0) 180 %tmp25 = fptosi float %tmp24 to i32 181 %tmp26 = bitcast i32 %tmp25 to float 182 %tmp27 = bitcast float %tmp26 to i32 183 br label %LOOP 184 185LOOP: ; preds = %ENDIF, %main_body 186 %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ] 187 %temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ] 188 %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ] 189 %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp36, %ENDIF ] 190 %tmp28 = bitcast float %temp8.0 to i32 191 %tmp29 = icmp sge i32 %tmp28, %tmp27 192 %tmp30 = sext i1 %tmp29 to i32 193 %tmp31 = bitcast i32 %tmp30 to float 194 %tmp32 = bitcast float %tmp31 to i32 195 %tmp33 = icmp ne i32 %tmp32, 0 196 br i1 %tmp33, label %IF, label %ENDIF 197 198IF: ; preds = %LOOP 199 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00, i1 true, i1 true) #0 200 ret void 201 202ENDIF: ; preds = %LOOP 203 %tmp34 = bitcast float %temp8.0 to i32 204 %tmp35 = add i32 %tmp34, 1 205 %tmp36 = bitcast i32 %tmp35 to float 206 br label %LOOP 207} 208 209; This checks for a bug in the FixSGPRCopies pass where VReg96 210; registers were being identified as an SGPR regclass which was causing 211; an assertion failure. 212 213; CHECK-LABEL: {{^}}sample_v3: 214; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5 215; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7 216; CHECK: s_branch 217 218; CHECK: BB{{[0-9]+_[0-9]+}}: 219; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11 220; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13 221 222; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}} 223; CHECK: exp 224; CHECK: s_endpgm 225define amdgpu_ps void @sample_v3([17 x <4 x i32>] addrspace(4)* inreg %arg, [32 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <8 x i32>] addrspace(4)* inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { 226entry: 227 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0 228 %tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0 229 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 16, i32 0) 230 %tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0 231 %tmp24 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp23, !tbaa !0 232 %tmp25 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 0 233 %tmp26 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp25, !tbaa !0 234 %tmp27 = fcmp oeq float %tmp22, 0.000000e+00 235 %tmp26.bc = bitcast <4 x i32> %tmp26 to <4 x i32> 236 br i1 %tmp27, label %if, label %else 237 238if: ; preds = %entry 239 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36D6000000000000, float 0x36DA000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0) 240 %val.if.0 = extractelement <4 x float> %tmp1, i32 0 241 %val.if.1 = extractelement <4 x float> %tmp1, i32 1 242 %val.if.2 = extractelement <4 x float> %tmp1, i32 2 243 br label %endif 244 245else: ; preds = %entry 246 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36C4000000000000, float 0x36CC000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0) 247 %val.else.0 = extractelement <4 x float> %tmp2, i32 0 248 %val.else.1 = extractelement <4 x float> %tmp2, i32 1 249 %val.else.2 = extractelement <4 x float> %tmp2, i32 2 250 br label %endif 251 252endif: ; preds = %else, %if 253 %val.0 = phi float [ %val.if.0, %if ], [ %val.else.0, %else ] 254 %val.1 = phi float [ %val.if.1, %if ], [ %val.else.1, %else ] 255 %val.2 = phi float [ %val.if.2, %if ], [ %val.else.2, %else ] 256 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %val.0, float %val.1, float %val.2, float 0.000000e+00, i1 true, i1 true) #0 257 ret void 258} 259 260; CHECK-LABEL: {{^}}copy1: 261; CHECK: buffer_load_dword 262; CHECK: v_add 263; CHECK: s_endpgm 264define amdgpu_kernel void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) { 265entry: 266 %tmp = load float, float addrspace(1)* %in0 267 %tmp1 = fcmp oeq float %tmp, 0.000000e+00 268 br i1 %tmp1, label %if0, label %endif 269 270if0: ; preds = %entry 271 %tmp2 = bitcast float %tmp to i32 272 %tmp3 = fcmp olt float %tmp, 0.000000e+00 273 br i1 %tmp3, label %if1, label %endif 274 275if1: ; preds = %if0 276 %tmp4 = add i32 %tmp2, 1 277 br label %endif 278 279endif: ; preds = %if1, %if0, %entry 280 %tmp5 = phi i32 [ 0, %entry ], [ %tmp2, %if0 ], [ %tmp4, %if1 ] 281 %tmp6 = bitcast i32 %tmp5 to float 282 store float %tmp6, float addrspace(1)* %out 283 ret void 284} 285 286; This test is just checking that we don't crash / assertion fail. 287; CHECK-LABEL: {{^}}copy2: 288; CHECK: s_endpgm 289define amdgpu_ps void @copy2([17 x <4 x i32>] addrspace(4)* inreg %arg, [32 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <8 x i32>] addrspace(4)* inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { 290entry: 291 br label %LOOP68 292 293LOOP68: ; preds = %ENDIF69, %entry 294 %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ] 295 %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ] 296 %g = icmp eq i32 0, %t 297 %l = bitcast float %temp4.7 to i32 298 br i1 %g, label %IF70, label %ENDIF69 299 300IF70: ; preds = %LOOP68 301 %q = icmp ne i32 %l, 13 302 %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00 303 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0 304 ret void 305 306ENDIF69: ; preds = %LOOP68 307 %u = add i32 %l, %t 308 %v = bitcast i32 %u to float 309 %x = add i32 %t, -1 310 br label %LOOP68 311} 312 313; This test checks that image_sample resource descriptors aren't loaded into 314; vgprs. The verifier will fail if this happens. 315; CHECK-LABEL:{{^}}sample_rsrc 316 317; CHECK: s_cmp_eq_u32 318; CHECK: s_cbranch_scc0 [[END:BB[0-9]+_[0-9]+]] 319 320; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}} 321 322; [[END]]: 323; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}} 324; CHECK: s_endpgm 325define amdgpu_ps void @sample_rsrc([6 x <4 x i32>] addrspace(4)* inreg %arg, [17 x <4 x i32>] addrspace(4)* inreg %arg1, [16 x <4 x i32>] addrspace(4)* inreg %arg2, [32 x <8 x i32>] addrspace(4)* inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { 326bb: 327 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i32 0, i32 0 328 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !3 329 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp22, i32 16, i32 0) 330 %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(4)* %arg3, i32 0, i32 0 331 %tmp26 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp25, !tbaa !3 332 %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(4)* %arg2, i32 0, i32 0 333 %tmp28 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp27, !tbaa !3 334 %i.i = extractelement <2 x i32> %arg7, i32 0 335 %j.i = extractelement <2 x i32> %arg7, i32 1 336 %i.f.i = bitcast i32 %i.i to float 337 %j.f.i = bitcast i32 %j.i to float 338 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #0 339 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #0 340 %i.i1 = extractelement <2 x i32> %arg7, i32 0 341 %j.i2 = extractelement <2 x i32> %arg7, i32 1 342 %i.f.i3 = bitcast i32 %i.i1 to float 343 %j.f.i4 = bitcast i32 %j.i2 to float 344 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #0 345 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #0 346 %tmp31 = bitcast float %tmp23 to i32 347 %tmp36 = icmp ne i32 %tmp31, 0 348 br i1 %tmp36, label %bb38, label %bb80 349 350bb38: ; preds = %bb 351 %tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32> 352 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i6, <8 x i32> %tmp56, <4 x i32> %tmp28, i1 0, i32 0, i32 0) 353 br label %bb71 354 355bb80: ; preds = %bb 356 %tmp81 = bitcast float %p2.i to i32 357 %tmp82 = bitcast float %p2.i6 to i32 358 %tmp82.2 = add i32 %tmp82, 1 359 %tmp83 = bitcast i32 %tmp81 to float 360 %tmp84 = bitcast i32 %tmp82.2 to float 361 %tmp85 = bitcast <8 x i32> %tmp26 to <8 x i32> 362 %tmp3 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp83, float %tmp84, <8 x i32> %tmp85, <4 x i32> %tmp28, i1 0, i32 0, i32 0) 363 br label %bb71 364 365bb71: ; preds = %bb80, %bb38 366 %tmp72 = phi <4 x float> [ %tmp2, %bb38 ], [ %tmp3, %bb80 ] 367 %tmp88 = extractelement <4 x float> %tmp72, i32 0 368 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp88, float %tmp88, float %tmp88, float %tmp88, i1 true, i1 true) #0 369 ret void 370} 371 372; Check the resource descriptor is stored in an sgpr. 373; CHECK-LABEL: {{^}}mimg_srsrc_sgpr: 374; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 375define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(4)* inreg %arg) #0 { 376bb: 377 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 378 %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(4)* %arg, i32 0, i32 %tid 379 %tmp8 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp7, align 32, !tbaa !0 380 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> %tmp8, <4 x i32> undef, i1 0, i32 0, i32 0) 381 %tmp10 = extractelement <4 x float> %tmp, i32 0 382 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp10) 383 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 384 ret void 385} 386 387; Check the sampler is stored in an sgpr. 388; CHECK-LABEL: {{^}}mimg_ssamp_sgpr: 389; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 390define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(4)* inreg %arg) #0 { 391bb: 392 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 393 %tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i32 0, i32 %tid 394 %tmp8 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp7, align 16, !tbaa !0 395 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> undef, <4 x i32> %tmp8, i1 0, i32 0, i32 0) 396 %tmp10 = extractelement <4 x float> %tmp, i32 0 397 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef) 398 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 399 ret void 400} 401 402declare float @llvm.fabs.f32(float) #1 403declare float @llvm.amdgcn.rsq.f32(float) #1 404declare float @llvm.exp2.f32(float) #1 405declare float @llvm.pow.f32(float, float) #1 406declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 407declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1 408declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1 409declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 410declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0 411declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1 412declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2 413declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1 414 415attributes #0 = { nounwind } 416attributes #1 = { nounwind readnone } 417attributes #2 = { nounwind readonly } 418 419!0 = !{!1, !1, i64 0, i32 1} 420!1 = !{!"const", !2} 421!2 = !{!"tbaa root"} 422!3 = !{!1, !1, i64 0} 423