1;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
2
3;CHECK: TEX
4;CHECK-NEXT: ALU
5
6define amdgpu_vs void @test(<4 x float> inreg %reg0) {
7  %1 = extractelement <4 x float> %reg0, i32 0
8  %2 = extractelement <4 x float> %reg0, i32 1
9  %3 = extractelement <4 x float> %reg0, i32 2
10  %4 = extractelement <4 x float> %reg0, i32 3
11  %5 = insertelement <4 x float> undef, float %1, i32 0
12  %6 = insertelement <4 x float> %5, float %2, i32 1
13  %7 = insertelement <4 x float> %6, float %3, i32 2
14  %8 = insertelement <4 x float> %7, float %4, i32 3
15  %9 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
16  %10 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
17  %11 = fadd <4 x float> %9, %10
18  call void @llvm.r600.store.swizzle(<4 x float> %11, i32 0, i32 0)
19  ret void
20}
21
22declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
23declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
24