1; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
2
3; CHECK: [[REG0:(r[0-9]+)]] = add(r{{[0-9]+}},mpyi([[REG0]],r{{[0-9]+}})
4; CHECK: [[REG0:(r[0-9]+)]] = add(r{{[0-9]+}},mpyi([[REG0]],r{{[0-9]+}})
5
6target triple = "hexagon"
7
8@g0 = private unnamed_addr constant [50 x i8] c"%x :  Q6_R_add_mpyi_RRR(INT_MIN,INT_MIN,INT_MIN)\0A\00", align 1
9@g1 = private unnamed_addr constant [45 x i8] c"%x :  Q6_R_add_mpyi_RRR(-1,INT_MIN,INT_MIN)\0A\00", align 1
10
11; Function Attrs: nounwind
12declare i32 @f0(i8* nocapture readonly, ...) #0
13
14; Function Attrs: nounwind
15define i32 @f1() #0 {
16b0:
17  %v0 = tail call i32 @llvm.hexagon.M4.mpyrr.addr(i32 -2147483648, i32 -2147483648, i32 -2147483648)
18  %v1 = tail call i32 (i8*, ...) @f0(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @g0, i32 0, i32 0), i32 %v0) #2
19  %v2 = tail call i32 @llvm.hexagon.M4.mpyrr.addr(i32 -1, i32 -2147483648, i32 -2147483648)
20  %v3 = tail call i32 (i8*, ...) @f0(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @g1, i32 0, i32 0), i32 %v2) #2
21  ret i32 0
22}
23
24; Function Attrs: nounwind readnone
25declare i32 @llvm.hexagon.M4.mpyrr.addr(i32, i32, i32) #1
26
27attributes #0 = { nounwind "target-cpu"="hexagonv55" }
28attributes #1 = { nounwind readnone }
29attributes #2 = { nounwind }
30