1; RUN: llc -march=hexagon < %s | FileCheck %s
2; Check that we are able to predicate instructions.
3
4; CHECK: if ({{!?}}p{{[0-3]}}{{(.new)?}}) r{{[0-9]+}} = {{and|aslh}}
5; CHECK: if ({{!?}}p{{[0-3]}}{{(.new)?}}) r{{[0-9]+}} = {{and|aslh}}
6
7@g0 = external global i32
8@g1 = external global i32
9
10define i32 @f0(i8 zeroext %a0, i8 zeroext %a1) #0 {
11b0:
12  %v0 = icmp eq i8 %a0, %a1
13  br i1 %v0, label %b1, label %b2
14
15b1:                                               ; preds = %b0
16  %v1 = zext i8 %a0 to i32
17  %v2 = shl nuw nsw i32 %v1, 16
18  br label %b3
19
20b2:                                               ; preds = %b0
21  %v3 = and i8 %a1, %a0
22  %v4 = zext i8 %v3 to i32
23  br label %b3
24
25b3:                                               ; preds = %b2, %b1
26  %v5 = phi i32 [ %v4, %b2 ], [ %v2, %b1 ]
27  store i32 %v5, i32* @g0, align 4
28  %v6 = load i32, i32* @g1, align 4
29  ret i32 %v6
30}
31
32attributes #0 = { nounwind "target-cpu"="hexagonv5" }
33