1; RUN: llc -march=hexagon -enable-pipeliner -enable-pipeliner-opt-size \
2; RUN:     -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 \
3; RUN:     -enable-aa-sched-mi=false -hexagon-expand-condsets=0 \
4; RUN:     < %s -pipeliner-experimental-cg=true | FileCheck %s
5
6; Disable expand-condsets because it will assert on undefined registers.
7
8; Test that we change the CFG correctly for pipelined loops where the trip
9; count is a compile-time constant, and the trip count is the same as the
10; number of prolog blocks (i.e., stages).
11
12; CHECK: memb(r{{[0-9]+}}+#0) =
13; CHECK: memb(r{{[0-9]+}}+#0) =
14
15; Function Attrs: nounwind optsize
16define void @f0(i1 %x) #0 {
17b0:
18  br label %b1
19
20b1:                                               ; preds = %b5, %b0
21  %v0 = load i16, i16* undef, align 2, !tbaa !0
22  %v1 = sext i16 %v0 to i32
23  %v2 = load i16, i16* undef, align 2, !tbaa !0
24  %v3 = sext i16 %v2 to i32
25  %v4 = and i32 %v1, 7
26  %v5 = and i32 %v3, 7
27  br label %b2
28
29b2:                                               ; preds = %b4, %b1
30  br label %b3
31
32b3:                                               ; preds = %b3, %b2
33  %v6 = phi i32 [ 0, %b2 ], [ %v22, %b3 ]
34  %v7 = add i32 %v6, undef
35  %v8 = icmp slt i32 undef, %v7
36  %v9 = add nsw i32 %v7, 1
37  %v10 = select i1 %x, i32 1, i32 %v9
38  %v11 = add i32 %v10, 0
39  %v12 = getelementptr inbounds i8, i8* null, i32 %v11
40  %v13 = load i8, i8* %v12, align 1, !tbaa !4
41  %v14 = zext i8 %v13 to i32
42  %v15 = mul i32 %v14, %v4
43  %v16 = add i32 %v15, 0
44  %v17 = mul i32 %v16, %v5
45  %v18 = add i32 %v17, 32
46  %v19 = add i32 %v18, 0
47  %v20 = lshr i32 %v19, 6
48  %v21 = trunc i32 %v20 to i8
49  store i8 %v21, i8* undef, align 1, !tbaa !4
50  %v22 = add i32 %v6, 1
51  %v23 = icmp eq i32 %v22, 2
52  br i1 %v23, label %b4, label %b3
53
54b4:                                               ; preds = %b3
55  br i1 undef, label %b5, label %b2
56
57b5:                                               ; preds = %b4
58  br i1 undef, label %b1, label %b6
59
60b6:                                               ; preds = %b5
61  ret void
62}
63
64attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" }
65
66!0 = !{!1, !1, i64 0}
67!1 = !{!"short", !2}
68!2 = !{!"omnipotent char", !3}
69!3 = !{!"Simple C/C++ TBAA"}
70!4 = !{!2, !2, i64 0}
71