1; RUN: llc -march=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
2
3; Test that we fixup a pipelined loop correctly when the number of
4; stages is greater than the compile-time loop trip count. In this
5; test, there are two prolog stages, but the loop executes only once.
6; In the bug, the final CFG contains two iterations of the loop.
7
8; CHECK-NOT: loop0
9; CHECK: r{{[0-9]+}} = mpyi
10; CHECK-NOT: r{{[0-9]+}} = mpyi
11
12define i32 @f0(i32* %a0) {
13b0:
14  br label %b1
15
16b1:                                               ; preds = %b1, %b0
17  %v0 = phi i32 [ 0, %b0 ], [ %v9, %b1 ]
18  %v1 = phi i32 [ 0, %b0 ], [ %v8, %b1 ]
19  %v2 = load i32, i32* %a0, align 4
20  %v3 = add nsw i32 %v1, 1
21  %v4 = srem i32 %v2, 3
22  %v5 = icmp ne i32 %v4, 0
23  %v6 = sub nsw i32 0, %v2
24  %v7 = select i1 %v5, i32 %v6, i32 %v2
25  %v8 = mul nsw i32 %v3, %v7
26  %v9 = add nsw i32 %v0, 1
27  %v10 = icmp eq i32 %v9, 1
28  br i1 %v10, label %b2, label %b1
29
30b2:                                               ; preds = %b1
31  %v11 = phi i32 [ %v8, %b1 ]
32  br label %b3
33
34b3:                                               ; preds = %b3, %b2
35  ret i32 %v11
36}
37